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IB/ipath: Be more cautious about coming out of freeze mode
[net-next-2.6.git] / drivers / infiniband / hw / ipath / ipath_iba6120.c
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dc741bbd 1/*
87427da5 2 * Copyright (c) 2006, 2007 QLogic Corporation. All rights reserved.
dc741bbd
BS		 3 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33/*
34 * This file contains all of the code that is specific to the
525d0ca1 35 * InfiniPath PCIe chip.
dc741bbd
BS		 36 */
37
38#include <linux/interrupt.h>
39#include <linux/pci.h>
40#include <linux/delay.h>
41
42
43#include "ipath_kernel.h"
44#include "ipath_registers.h"
45
f5408ac7
BS		 46static void ipath_setup_pe_setextled(struct ipath_devdata *, u64, u64);
47
dc741bbd
BS		 48/*
49 * This file contains all the chip-specific register information and
525d0ca1 50 * access functions for the QLogic InfiniPath PCI-Express chip.
dc741bbd 51 *
525d0ca1 52 * This lists the InfiniPath registers, in the actual chip layout.
dc741bbd
BS		 53 * This structure should never be directly accessed.
54 */
55struct _infinipath_do_not_use_kernel_regs {
56 unsigned long long Revision;
57 unsigned long long Control;
58 unsigned long long PageAlign;
59 unsigned long long PortCnt;
60 unsigned long long DebugPortSelect;
61 unsigned long long Reserved0;
62 unsigned long long SendRegBase;
63 unsigned long long UserRegBase;
64 unsigned long long CounterRegBase;
65 unsigned long long Scratch;
66 unsigned long long Reserved1;
67 unsigned long long Reserved2;
68 unsigned long long IntBlocked;
69 unsigned long long IntMask;
70 unsigned long long IntStatus;
71 unsigned long long IntClear;
72 unsigned long long ErrorMask;
73 unsigned long long ErrorStatus;
74 unsigned long long ErrorClear;
75 unsigned long long HwErrMask;
76 unsigned long long HwErrStatus;
77 unsigned long long HwErrClear;
78 unsigned long long HwDiagCtrl;
79 unsigned long long MDIO;
80 unsigned long long IBCStatus;
81 unsigned long long IBCCtrl;
82 unsigned long long ExtStatus;
83 unsigned long long ExtCtrl;
84 unsigned long long GPIOOut;
85 unsigned long long GPIOMask;
86 unsigned long long GPIOStatus;
87 unsigned long long GPIOClear;
88 unsigned long long RcvCtrl;
89 unsigned long long RcvBTHQP;
90 unsigned long long RcvHdrSize;
91 unsigned long long RcvHdrCnt;
92 unsigned long long RcvHdrEntSize;
93 unsigned long long RcvTIDBase;
94 unsigned long long RcvTIDCnt;
95 unsigned long long RcvEgrBase;
96 unsigned long long RcvEgrCnt;
97 unsigned long long RcvBufBase;
98 unsigned long long RcvBufSize;
99 unsigned long long RxIntMemBase;
100 unsigned long long RxIntMemSize;
101 unsigned long long RcvPartitionKey;
102 unsigned long long Reserved3;
103 unsigned long long RcvPktLEDCnt;
104 unsigned long long Reserved4[8];
105 unsigned long long SendCtrl;
106 unsigned long long SendPIOBufBase;
107 unsigned long long SendPIOSize;
108 unsigned long long SendPIOBufCnt;
109 unsigned long long SendPIOAvailAddr;
110 unsigned long long TxIntMemBase;
111 unsigned long long TxIntMemSize;
112 unsigned long long Reserved5;
113 unsigned long long PCIeRBufTestReg0;
114 unsigned long long PCIeRBufTestReg1;
115 unsigned long long Reserved51[6];
116 unsigned long long SendBufferError;
117 unsigned long long SendBufferErrorCONT1;
118 unsigned long long Reserved6SBE[6];
119 unsigned long long RcvHdrAddr0;
120 unsigned long long RcvHdrAddr1;
121 unsigned long long RcvHdrAddr2;
122 unsigned long long RcvHdrAddr3;
123 unsigned long long RcvHdrAddr4;
124 unsigned long long Reserved7RHA[11];
125 unsigned long long RcvHdrTailAddr0;
126 unsigned long long RcvHdrTailAddr1;
127 unsigned long long RcvHdrTailAddr2;
128 unsigned long long RcvHdrTailAddr3;
129 unsigned long long RcvHdrTailAddr4;
130 unsigned long long Reserved8RHTA[11];
131 unsigned long long Reserved9SW[8];
132 unsigned long long SerdesConfig0;
133 unsigned long long SerdesConfig1;
134 unsigned long long SerdesStatus;
135 unsigned long long XGXSConfig;
136 unsigned long long IBPLLCfg;
137 unsigned long long Reserved10SW2[3];
138 unsigned long long PCIEQ0SerdesConfig0;
139 unsigned long long PCIEQ0SerdesConfig1;
140 unsigned long long PCIEQ0SerdesStatus;
141 unsigned long long Reserved11;
142 unsigned long long PCIEQ1SerdesConfig0;
143 unsigned long long PCIEQ1SerdesConfig1;
144 unsigned long long PCIEQ1SerdesStatus;
145 unsigned long long Reserved12;
146};
147
148#define IPATH_KREG_OFFSET(field) (offsetof(struct \
149 _infinipath_do_not_use_kernel_regs, field) / sizeof(u64))
150#define IPATH_CREG_OFFSET(field) (offsetof( \
151 struct infinipath_counters, field) / sizeof(u64))
152
153static const struct ipath_kregs ipath_pe_kregs = {
154 .kr_control = IPATH_KREG_OFFSET(Control),
155 .kr_counterregbase = IPATH_KREG_OFFSET(CounterRegBase),
156 .kr_debugportselect = IPATH_KREG_OFFSET(DebugPortSelect),
157 .kr_errorclear = IPATH_KREG_OFFSET(ErrorClear),
158 .kr_errormask = IPATH_KREG_OFFSET(ErrorMask),
159 .kr_errorstatus = IPATH_KREG_OFFSET(ErrorStatus),
160 .kr_extctrl = IPATH_KREG_OFFSET(ExtCtrl),
161 .kr_extstatus = IPATH_KREG_OFFSET(ExtStatus),
162 .kr_gpio_clear = IPATH_KREG_OFFSET(GPIOClear),
163 .kr_gpio_mask = IPATH_KREG_OFFSET(GPIOMask),
164 .kr_gpio_out = IPATH_KREG_OFFSET(GPIOOut),
165 .kr_gpio_status = IPATH_KREG_OFFSET(GPIOStatus),
166 .kr_hwdiagctrl = IPATH_KREG_OFFSET(HwDiagCtrl),
167 .kr_hwerrclear = IPATH_KREG_OFFSET(HwErrClear),
168 .kr_hwerrmask = IPATH_KREG_OFFSET(HwErrMask),
169 .kr_hwerrstatus = IPATH_KREG_OFFSET(HwErrStatus),
170 .kr_ibcctrl = IPATH_KREG_OFFSET(IBCCtrl),
171 .kr_ibcstatus = IPATH_KREG_OFFSET(IBCStatus),
172 .kr_intblocked = IPATH_KREG_OFFSET(IntBlocked),
173 .kr_intclear = IPATH_KREG_OFFSET(IntClear),
174 .kr_intmask = IPATH_KREG_OFFSET(IntMask),
175 .kr_intstatus = IPATH_KREG_OFFSET(IntStatus),
176 .kr_mdio = IPATH_KREG_OFFSET(MDIO),
177 .kr_pagealign = IPATH_KREG_OFFSET(PageAlign),
178 .kr_partitionkey = IPATH_KREG_OFFSET(RcvPartitionKey),
179 .kr_portcnt = IPATH_KREG_OFFSET(PortCnt),
180 .kr_rcvbthqp = IPATH_KREG_OFFSET(RcvBTHQP),
181 .kr_rcvbufbase = IPATH_KREG_OFFSET(RcvBufBase),
182 .kr_rcvbufsize = IPATH_KREG_OFFSET(RcvBufSize),
183 .kr_rcvctrl = IPATH_KREG_OFFSET(RcvCtrl),
184 .kr_rcvegrbase = IPATH_KREG_OFFSET(RcvEgrBase),
185 .kr_rcvegrcnt = IPATH_KREG_OFFSET(RcvEgrCnt),
186 .kr_rcvhdrcnt = IPATH_KREG_OFFSET(RcvHdrCnt),
187 .kr_rcvhdrentsize = IPATH_KREG_OFFSET(RcvHdrEntSize),
188 .kr_rcvhdrsize = IPATH_KREG_OFFSET(RcvHdrSize),
189 .kr_rcvintmembase = IPATH_KREG_OFFSET(RxIntMemBase),
190 .kr_rcvintmemsize = IPATH_KREG_OFFSET(RxIntMemSize),
191 .kr_rcvtidbase = IPATH_KREG_OFFSET(RcvTIDBase),
192 .kr_rcvtidcnt = IPATH_KREG_OFFSET(RcvTIDCnt),
193 .kr_revision = IPATH_KREG_OFFSET(Revision),
194 .kr_scratch = IPATH_KREG_OFFSET(Scratch),
195 .kr_sendbuffererror = IPATH_KREG_OFFSET(SendBufferError),
196 .kr_sendctrl = IPATH_KREG_OFFSET(SendCtrl),
197 .kr_sendpioavailaddr = IPATH_KREG_OFFSET(SendPIOAvailAddr),
198 .kr_sendpiobufbase = IPATH_KREG_OFFSET(SendPIOBufBase),
199 .kr_sendpiobufcnt = IPATH_KREG_OFFSET(SendPIOBufCnt),
200 .kr_sendpiosize = IPATH_KREG_OFFSET(SendPIOSize),
201 .kr_sendregbase = IPATH_KREG_OFFSET(SendRegBase),
202 .kr_txintmembase = IPATH_KREG_OFFSET(TxIntMemBase),
203 .kr_txintmemsize = IPATH_KREG_OFFSET(TxIntMemSize),
204 .kr_userregbase = IPATH_KREG_OFFSET(UserRegBase),
205 .kr_serdesconfig0 = IPATH_KREG_OFFSET(SerdesConfig0),
206 .kr_serdesconfig1 = IPATH_KREG_OFFSET(SerdesConfig1),
207 .kr_serdesstatus = IPATH_KREG_OFFSET(SerdesStatus),
208 .kr_xgxsconfig = IPATH_KREG_OFFSET(XGXSConfig),
209 .kr_ibpllcfg = IPATH_KREG_OFFSET(IBPLLCfg),
210
211 /*
c8c6f5d4
BS		 212 * These should not be used directly via ipath_write_kreg64(),
213 * use them with ipath_write_kreg64_port(),
dc741bbd
BS		 214 */
215 .kr_rcvhdraddr = IPATH_KREG_OFFSET(RcvHdrAddr0),
216 .kr_rcvhdrtailaddr = IPATH_KREG_OFFSET(RcvHdrTailAddr0),
217
dc741bbd
BS		 218 /* The rcvpktled register controls one of the debug port signals, so
219 * a packet activity LED can be connected to it. */
220 .kr_rcvpktledcnt = IPATH_KREG_OFFSET(RcvPktLEDCnt),
221 .kr_pcierbuftestreg0 = IPATH_KREG_OFFSET(PCIeRBufTestReg0),
222 .kr_pcierbuftestreg1 = IPATH_KREG_OFFSET(PCIeRBufTestReg1),
223 .kr_pcieq0serdesconfig0 = IPATH_KREG_OFFSET(PCIEQ0SerdesConfig0),
224 .kr_pcieq0serdesconfig1 = IPATH_KREG_OFFSET(PCIEQ0SerdesConfig1),
225 .kr_pcieq0serdesstatus = IPATH_KREG_OFFSET(PCIEQ0SerdesStatus),
226 .kr_pcieq1serdesconfig0 = IPATH_KREG_OFFSET(PCIEQ1SerdesConfig0),
227 .kr_pcieq1serdesconfig1 = IPATH_KREG_OFFSET(PCIEQ1SerdesConfig1),
228 .kr_pcieq1serdesstatus = IPATH_KREG_OFFSET(PCIEQ1SerdesStatus)
229};
230
231static const struct ipath_cregs ipath_pe_cregs = {
232 .cr_badformatcnt = IPATH_CREG_OFFSET(RxBadFormatCnt),
233 .cr_erricrccnt = IPATH_CREG_OFFSET(RxICRCErrCnt),
234 .cr_errlinkcnt = IPATH_CREG_OFFSET(RxLinkProblemCnt),
235 .cr_errlpcrccnt = IPATH_CREG_OFFSET(RxLPCRCErrCnt),
236 .cr_errpkey = IPATH_CREG_OFFSET(RxPKeyMismatchCnt),
237 .cr_errrcvflowctrlcnt = IPATH_CREG_OFFSET(RxFlowCtrlErrCnt),
238 .cr_err_rlencnt = IPATH_CREG_OFFSET(RxLenErrCnt),
239 .cr_errslencnt = IPATH_CREG_OFFSET(TxLenErrCnt),
240 .cr_errtidfull = IPATH_CREG_OFFSET(RxTIDFullErrCnt),
241 .cr_errtidvalid = IPATH_CREG_OFFSET(RxTIDValidErrCnt),
242 .cr_errvcrccnt = IPATH_CREG_OFFSET(RxVCRCErrCnt),
243 .cr_ibstatuschange = IPATH_CREG_OFFSET(IBStatusChangeCnt),
244 .cr_intcnt = IPATH_CREG_OFFSET(LBIntCnt),
245 .cr_invalidrlencnt = IPATH_CREG_OFFSET(RxMaxMinLenErrCnt),
246 .cr_invalidslencnt = IPATH_CREG_OFFSET(TxMaxMinLenErrCnt),
247 .cr_lbflowstallcnt = IPATH_CREG_OFFSET(LBFlowStallCnt),
248 .cr_pktrcvcnt = IPATH_CREG_OFFSET(RxDataPktCnt),
249 .cr_pktrcvflowctrlcnt = IPATH_CREG_OFFSET(RxFlowPktCnt),
250 .cr_pktsendcnt = IPATH_CREG_OFFSET(TxDataPktCnt),
251 .cr_pktsendflowcnt = IPATH_CREG_OFFSET(TxFlowPktCnt),
252 .cr_portovflcnt = IPATH_CREG_OFFSET(RxP0HdrEgrOvflCnt),
253 .cr_rcvebpcnt = IPATH_CREG_OFFSET(RxEBPCnt),
254 .cr_rcvovflcnt = IPATH_CREG_OFFSET(RxBufOvflCnt),
255 .cr_senddropped = IPATH_CREG_OFFSET(TxDroppedPktCnt),
256 .cr_sendstallcnt = IPATH_CREG_OFFSET(TxFlowStallCnt),
257 .cr_sendunderruncnt = IPATH_CREG_OFFSET(TxUnderrunCnt),
258 .cr_wordrcvcnt = IPATH_CREG_OFFSET(RxDwordCnt),
259 .cr_wordsendcnt = IPATH_CREG_OFFSET(TxDwordCnt),
260 .cr_unsupvlcnt = IPATH_CREG_OFFSET(TxUnsupVLErrCnt),
261 .cr_rxdroppktcnt = IPATH_CREG_OFFSET(RxDroppedPktCnt),
262 .cr_iblinkerrrecovcnt = IPATH_CREG_OFFSET(IBLinkErrRecoveryCnt),
263 .cr_iblinkdowncnt = IPATH_CREG_OFFSET(IBLinkDownedCnt),
264 .cr_ibsymbolerrcnt = IPATH_CREG_OFFSET(IBSymbolErrCnt)
265};
266
267/* kr_intstatus, kr_intclear, kr_intmask bits */
f62fe77a
BS		 268#define INFINIPATH_I_RCVURG_MASK ((1U<<5)-1)
269#define INFINIPATH_I_RCVAVAIL_MASK ((1U<<5)-1)
dc741bbd
BS		 270
271/* kr_hwerrclear, kr_hwerrmask, kr_hwerrstatus, bits */
272#define INFINIPATH_HWE_PCIEMEMPARITYERR_MASK 0x000000000000003fULL
273#define INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT 0
274#define INFINIPATH_HWE_PCIEPOISONEDTLP 0x0000000010000000ULL
275#define INFINIPATH_HWE_PCIECPLTIMEOUT 0x0000000020000000ULL
276#define INFINIPATH_HWE_PCIEBUSPARITYXTLH 0x0000000040000000ULL
277#define INFINIPATH_HWE_PCIEBUSPARITYXADM 0x0000000080000000ULL
278#define INFINIPATH_HWE_PCIEBUSPARITYRADM 0x0000000100000000ULL
279#define INFINIPATH_HWE_COREPLL_FBSLIP 0x0080000000000000ULL
280#define INFINIPATH_HWE_COREPLL_RFSLIP 0x0100000000000000ULL
281#define INFINIPATH_HWE_PCIE1PLLFAILED 0x0400000000000000ULL
282#define INFINIPATH_HWE_PCIE0PLLFAILED 0x0800000000000000ULL
283#define INFINIPATH_HWE_SERDESPLLFAILED 0x1000000000000000ULL
284
285/* kr_extstatus bits */
286#define INFINIPATH_EXTS_FREQSEL 0x2
287#define INFINIPATH_EXTS_SERDESSEL 0x4
288#define INFINIPATH_EXTS_MEMBIST_ENDTEST 0x0000000000004000
289#define INFINIPATH_EXTS_MEMBIST_FOUND 0x0000000000008000
290
291#define _IPATH_GPIO_SDA_NUM 1
292#define _IPATH_GPIO_SCL_NUM 0
293
294#define IPATH_GPIO_SDA (1ULL << \
295 (_IPATH_GPIO_SDA_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT))
296#define IPATH_GPIO_SCL (1ULL << \
297 (_IPATH_GPIO_SCL_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT))
298
8d588f8b
BS		 299/* 6120 specific hardware errors... */
300static const struct ipath_hwerror_msgs ipath_6120_hwerror_msgs[] = {
301 INFINIPATH_HWE_MSG(PCIEPOISONEDTLP, "PCIe Poisoned TLP"),
302 INFINIPATH_HWE_MSG(PCIECPLTIMEOUT, "PCIe completion timeout"),
303 /*
304 * In practice, it's unlikely wthat we'll see PCIe PLL, or bus
305 * parity or memory parity error failures, because most likely we
306 * won't be able to talk to the core of the chip. Nonetheless, we
307 * might see them, if they are in parts of the PCIe core that aren't
308 * essential.
309 */
310 INFINIPATH_HWE_MSG(PCIE1PLLFAILED, "PCIePLL1"),
311 INFINIPATH_HWE_MSG(PCIE0PLLFAILED, "PCIePLL0"),
312 INFINIPATH_HWE_MSG(PCIEBUSPARITYXTLH, "PCIe XTLH core parity"),
313 INFINIPATH_HWE_MSG(PCIEBUSPARITYXADM, "PCIe ADM TX core parity"),
314 INFINIPATH_HWE_MSG(PCIEBUSPARITYRADM, "PCIe ADM RX core parity"),
315 INFINIPATH_HWE_MSG(RXDSYNCMEMPARITYERR, "Rx Dsync"),
316 INFINIPATH_HWE_MSG(SERDESPLLFAILED, "SerDes PLL"),
317};
318
9783ab40
BS		 319#define TXE_PIO_PARITY ((INFINIPATH_HWE_TXEMEMPARITYERR_PIOBUF | \
320 INFINIPATH_HWE_TXEMEMPARITYERR_PIOPBC) \
321 << INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT)
322
323static int ipath_pe_txe_recover(struct ipath_devdata *);
324
dc741bbd
BS		 325/**
326 * ipath_pe_handle_hwerrors - display hardware errors.
327 * @dd: the infinipath device
328 * @msg: the output buffer
329 * @msgl: the size of the output buffer
330 *
331 * Use same msg buffer as regular errors to avoid excessive stack
332 * use. Most hardware errors are catastrophic, but for right now,
333 * we'll print them and continue. We reuse the same message buffer as
334 * ipath_handle_errors() to avoid excessive stack usage.
335 */
ac2ae4c9
RD		 336static void ipath_pe_handle_hwerrors(struct ipath_devdata *dd, char *msg,
337 size_t msgl)
dc741bbd
BS		 338{
339 ipath_err_t hwerrs;
340 u32 bits, ctrl;
341 int isfatal = 0;
342 char bitsmsg[64];
aecd3b5a 343 int log_idx;
dc741bbd
BS		 344
345 hwerrs = ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus);
346 if (!hwerrs) {
347 /*
348 * better than printing cofusing messages
349 * This seems to be related to clearing the crc error, or
350 * the pll error during init.
351 */
352 ipath_cdbg(VERBOSE, "Called but no hardware errors set\n");
353 return;
354 } else if (hwerrs == ~0ULL) {
355 ipath_dev_err(dd, "Read of hardware error status failed "
356 "(all bits set); ignoring\n");
357 return;
358 }
359 ipath_stats.sps_hwerrs++;
360
361 /* Always clear the error status register, except MEMBISTFAIL,
362 * regardless of whether we continue or stop using the chip.
363 * We want that set so we know it failed, even across driver reload.
364 * We'll still ignore it in the hwerrmask. We do this partly for
365 * diagnostics, but also for support */
366 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
367 hwerrs&~INFINIPATH_HWE_MEMBISTFAILED);
368
369 hwerrs &= dd->ipath_hwerrmask;
370
aecd3b5a
MA		 371 /* We log some errors to EEPROM, check if we have any of those. */
372 for (log_idx = 0; log_idx < IPATH_EEP_LOG_CNT; ++log_idx)
373 if (hwerrs & dd->ipath_eep_st_masks[log_idx].hwerrs_to_log)
374 ipath_inc_eeprom_err(dd, log_idx, 1);
375
dc741bbd
BS		 376 /*
377 * make sure we get this much out, unless told to be quiet,
378 * or it's occurred within the last 5 seconds
379 */
89d1e09b
BS		 380 if ((hwerrs & ~(dd->ipath_lasthwerror |
381 ((INFINIPATH_HWE_TXEMEMPARITYERR_PIOBUF |
382 INFINIPATH_HWE_TXEMEMPARITYERR_PIOPBC)
383 << INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT))) ||
dc741bbd
BS		 384 (ipath_debug & __IPATH_VERBDBG))
385 dev_info(&dd->pcidev->dev, "Hardware error: hwerr=0x%llx "
386 "(cleared)\n", (unsigned long long) hwerrs);
387 dd->ipath_lasthwerror |= hwerrs;
388
f62fe77a 389 if (hwerrs & ~dd->ipath_hwe_bitsextant)
dc741bbd
BS		 390 ipath_dev_err(dd, "hwerror interrupt with unknown errors "
391 "%llx set\n", (unsigned long long)
f62fe77a 392 (hwerrs & ~dd->ipath_hwe_bitsextant));
dc741bbd
BS		 393
394 ctrl = ipath_read_kreg32(dd, dd->ipath_kregs->kr_control);
395 if (ctrl & INFINIPATH_C_FREEZEMODE) {
89d1e09b
BS		 396 /*
397 * parity errors in send memory are recoverable,
398 * just cancel the send (if indicated in * sendbuffererror),
399 * count the occurrence, unfreeze (if no other handled
400 * hardware error bits are set), and continue. They can
401 * occur if a processor speculative read is done to the PIO
402 * buffer while we are sending a packet, for example.
403 */
9783ab40
BS		 404 if ((hwerrs & TXE_PIO_PARITY) && ipath_pe_txe_recover(dd))
405 hwerrs &= ~TXE_PIO_PARITY;
dc741bbd
BS		 406 if (hwerrs) {
407 /*
408 * if any set that we aren't ignoring only make the
409 * complaint once, in case it's stuck or recurring,
410 * and we get here multiple times
f5408ac7
BS		 411 * Force link down, so switch knows, and
412 * LEDs are turned off
dc741bbd
BS		 413 */
414 if (dd->ipath_flags & IPATH_INITTED) {
f5408ac7
BS		 415 ipath_set_linkstate(dd, IPATH_IB_LINKDOWN);
416 ipath_setup_pe_setextled(dd,
417 INFINIPATH_IBCS_L_STATE_DOWN,
418 INFINIPATH_IBCS_LT_STATE_DISABLED);
ff0b8597
BS		 419 ipath_dev_err(dd, "Fatal Hardware Error (freeze "
420 "mode), no longer usable, SN %.16s\n",
421 dd->ipath_serial);
dc741bbd
BS		 422 isfatal = 1;
423 }
424 /*
425 * Mark as having had an error for driver, and also
426 * for /sys and status word mapped to user programs.
427 * This marks unit as not usable, until reset
428 */
429 *dd->ipath_statusp &= ~IPATH_STATUS_IB_READY;
430 *dd->ipath_statusp |= IPATH_STATUS_HWERROR;
431 dd->ipath_flags &= ~IPATH_INITTED;
432 } else {
9380068f
DO		 433 static u32 freeze_cnt;
434
435 freeze_cnt++;
436 ipath_dbg("Clearing freezemode on ignored or recovered "
437 "hardware error (%u)\n", freeze_cnt);
0f4fc5eb 438 ipath_clear_freeze(dd);
dc741bbd
BS		 439 }
440 }
441
442 *msg = '\0';
443
444 if (hwerrs & INFINIPATH_HWE_MEMBISTFAILED) {
525d0ca1 445 strlcat(msg, "[Memory BIST test failed, InfiniPath hardware unusable]",
dc741bbd
BS		 446 msgl);
447 /* ignore from now on, so disable until driver reloaded */
448 *dd->ipath_statusp |= IPATH_STATUS_HWERROR;
449 dd->ipath_hwerrmask &= ~INFINIPATH_HWE_MEMBISTFAILED;
450 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
451 dd->ipath_hwerrmask);
452 }
8d588f8b
BS		 453
454 ipath_format_hwerrors(hwerrs,
455 ipath_6120_hwerror_msgs,
456 sizeof(ipath_6120_hwerror_msgs)/
457 sizeof(ipath_6120_hwerror_msgs[0]),
458 msg, msgl);
459
dc741bbd
BS		 460 if (hwerrs & (INFINIPATH_HWE_PCIEMEMPARITYERR_MASK
461 << INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT)) {
462 bits = (u32) ((hwerrs >>
463 INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT) &
464 INFINIPATH_HWE_PCIEMEMPARITYERR_MASK);
465 snprintf(bitsmsg, sizeof bitsmsg,
466 "[PCIe Mem Parity Errs %x] ", bits);
467 strlcat(msg, bitsmsg, msgl);
468 }
dc741bbd
BS		 469
470#define _IPATH_PLL_FAIL (INFINIPATH_HWE_COREPLL_FBSLIP | \
471 INFINIPATH_HWE_COREPLL_RFSLIP )
472
473 if (hwerrs & _IPATH_PLL_FAIL) {
474 snprintf(bitsmsg, sizeof bitsmsg,
525d0ca1 475 "[PLL failed (%llx), InfiniPath hardware unusable]",
dc741bbd
BS		 476 (unsigned long long) hwerrs & _IPATH_PLL_FAIL);
477 strlcat(msg, bitsmsg, msgl);
478 /* ignore from now on, so disable until driver reloaded */
479 dd->ipath_hwerrmask &= ~(hwerrs & _IPATH_PLL_FAIL);
480 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
481 dd->ipath_hwerrmask);
482 }
483
484 if (hwerrs & INFINIPATH_HWE_SERDESPLLFAILED) {
485 /*
486 * If it occurs, it is left masked since the eternal
487 * interface is unused
488 */
489 dd->ipath_hwerrmask &= ~INFINIPATH_HWE_SERDESPLLFAILED;
490 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
491 dd->ipath_hwerrmask);
492 }
493
f5408ac7
BS		 494 if (*msg)
495 ipath_dev_err(dd, "%s hardware error\n", msg);
dc741bbd
BS		 496 if (isfatal && !ipath_diag_inuse && dd->ipath_freezemsg) {
497 /*
498 * for /sys status file ; if no trailing } is copied, we'll
499 * know it was truncated.
500 */
501 snprintf(dd->ipath_freezemsg, dd->ipath_freezelen,
502 "{%s}", msg);
503 }
504}
505
506/**
507 * ipath_pe_boardname - fill in the board name
508 * @dd: the infinipath device
509 * @name: the output buffer
510 * @namelen: the size of the output buffer
511 *
512 * info is based on the board revision register
513 */
514static int ipath_pe_boardname(struct ipath_devdata *dd, char *name,
515 size_t namelen)
516{
517 char *n = NULL;
518 u8 boardrev = dd->ipath_boardrev;
519 int ret;
520
521 switch (boardrev) {
522 case 0:
523 n = "InfiniPath_Emulation";
524 break;
525 case 1:
525d0ca1 526 n = "InfiniPath_QLE7140-Bringup";
dc741bbd
BS		 527 break;
528 case 2:
525d0ca1 529 n = "InfiniPath_QLE7140";
dc741bbd
BS		 530 break;
531 case 3:
525d0ca1 532 n = "InfiniPath_QMI7140";
dc741bbd
BS		 533 break;
534 case 4:
525d0ca1
BS		 535 n = "InfiniPath_QEM7140";
536 break;
537 case 5:
538 n = "InfiniPath_QMH7140";
dc741bbd 539 break;
bf3258ec
BS		 540 case 6:
541 n = "InfiniPath_QLE7142";
542 break;
dc741bbd
BS		 543 default:
544 ipath_dev_err(dd,
545 "Don't yet know about board with ID %u\n",
546 boardrev);
525d0ca1 547 snprintf(name, namelen, "Unknown_InfiniPath_PCIe_%u",
dc741bbd
BS		 548 boardrev);
549 break;
550 }
551 if (n)
552 snprintf(name, namelen, "%s", n);
553
8307c28e 554 if (dd->ipath_majrev != 4 || !dd->ipath_minrev || dd->ipath_minrev>2) {
525d0ca1 555 ipath_dev_err(dd, "Unsupported InfiniPath hardware revision %u.%u!\n",
dc741bbd
BS		 556 dd->ipath_majrev, dd->ipath_minrev);
557 ret = 1;
558 } else
559 ret = 0;
560
561 return ret;
562}
563
564/**
565 * ipath_pe_init_hwerrors - enable hardware errors
566 * @dd: the infinipath device
567 *
568 * now that we have finished initializing everything that might reasonably
569 * cause a hardware error, and cleared those errors bits as they occur,
570 * we can enable hardware errors in the mask (potentially enabling
571 * freeze mode), and enable hardware errors as errors (along with
572 * everything else) in errormask
573 */
ac2ae4c9 574static void ipath_pe_init_hwerrors(struct ipath_devdata *dd)
dc741bbd
BS		 575{
576 ipath_err_t val;
577 u64 extsval;
578
579 extsval = ipath_read_kreg64(dd, dd->ipath_kregs->kr_extstatus);
580
581 if (!(extsval & INFINIPATH_EXTS_MEMBIST_ENDTEST))
582 ipath_dev_err(dd, "MemBIST did not complete!\n");
9783ab40
BS		 583 if (extsval & INFINIPATH_EXTS_MEMBIST_FOUND)
584 ipath_dbg("MemBIST corrected\n");
dc741bbd
BS		 585
586 val = ~0ULL; /* barring bugs, all hwerrors become interrupts, */
587
588 if (!dd->ipath_boardrev) // no PLL for Emulator
589 val &= ~INFINIPATH_HWE_SERDESPLLFAILED;
590
2c9446a1
BS		 591 if (dd->ipath_minrev < 2) {
592 /* workaround bug 9460 in internal interface bus parity
593 * checking. Fixed (HW bug 9490) in Rev2.
594 */
595 val &= ~INFINIPATH_HWE_PCIEBUSPARITYRADM;
596 }
dc741bbd
BS		 597 dd->ipath_hwerrmask = val;
598}
599
600/**
601 * ipath_pe_bringup_serdes - bring up the serdes
602 * @dd: the infinipath device
603 */
ac2ae4c9 604static int ipath_pe_bringup_serdes(struct ipath_devdata *dd)
dc741bbd 605{
44f8e3f3 606 u64 val, config1, prev_val;
2c9446a1 607 int ret = 0;
dc741bbd
BS		 608
609 ipath_dbg("Trying to bringup serdes\n");
610
611 if (ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus) &
612 INFINIPATH_HWE_SERDESPLLFAILED) {
613 ipath_dbg("At start, serdes PLL failed bit set "
614 "in hwerrstatus, clearing and continuing\n");
615 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
616 INFINIPATH_HWE_SERDESPLLFAILED);
617 }
618
619 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
620 config1 = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig1);
621
622 ipath_cdbg(VERBOSE, "SerDes status config0=%llx config1=%llx, "
623 "xgxsconfig %llx\n", (unsigned long long) val,
624 (unsigned long long) config1, (unsigned long long)
625 ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig));
626
627 /*
628 * Force reset on, also set rxdetect enable. Must do before reading
629 * serdesstatus at least for simulation, or some of the bits in
630 * serdes status will come back as undefined and cause simulation
631 * failures
632 */
633 val |= INFINIPATH_SERDC0_RESET_PLL | INFINIPATH_SERDC0_RXDETECT_EN
634 | INFINIPATH_SERDC0_L1PWR_DN;
635 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
636 /* be sure chip saw it */
44f8e3f3 637 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
dc741bbd
BS		 638 udelay(5); /* need pll reset set at least for a bit */
639 /*
640 * after PLL is reset, set the per-lane Resets and TxIdle and
641 * clear the PLL reset and rxdetect (to get falling edge).
642 * Leave L1PWR bits set (permanently)
643 */
644 val &= ~(INFINIPATH_SERDC0_RXDETECT_EN | INFINIPATH_SERDC0_RESET_PLL
645 | INFINIPATH_SERDC0_L1PWR_DN);
646 val |= INFINIPATH_SERDC0_RESET_MASK | INFINIPATH_SERDC0_TXIDLE;
647 ipath_cdbg(VERBOSE, "Clearing pll reset and setting lane resets "
648 "and txidle (%llx)\n", (unsigned long long) val);
649 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
650 /* be sure chip saw it */
44f8e3f3 651 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
dc741bbd
BS		 652 /* need PLL reset clear for at least 11 usec before lane
653 * resets cleared; give it a few more to be sure */
654 udelay(15);
655 val &= ~(INFINIPATH_SERDC0_RESET_MASK | INFINIPATH_SERDC0_TXIDLE);
656
657 ipath_cdbg(VERBOSE, "Clearing lane resets and txidle "
658 "(writing %llx)\n", (unsigned long long) val);
659 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
660 /* be sure chip saw it */
661 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
662
663 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig);
2c9446a1 664 prev_val = val;
dc741bbd
BS		 665 if (((val >> INFINIPATH_XGXS_MDIOADDR_SHIFT) &
666 INFINIPATH_XGXS_MDIOADDR_MASK) != 3) {
667 val &=
668 ~(INFINIPATH_XGXS_MDIOADDR_MASK <<
669 INFINIPATH_XGXS_MDIOADDR_SHIFT);
670 /* MDIO address 3 */
671 val |= 3ULL << INFINIPATH_XGXS_MDIOADDR_SHIFT;
dc741bbd
BS		 672 }
673 if (val & INFINIPATH_XGXS_RESET) {
674 val &= ~INFINIPATH_XGXS_RESET;
dc741bbd 675 }
30fc5c31
BS		 676 if (((val >> INFINIPATH_XGXS_RX_POL_SHIFT) &
677 INFINIPATH_XGXS_RX_POL_MASK) != dd->ipath_rx_pol_inv ) {
678 /* need to compensate for Tx inversion in partner */
679 val &= ~(INFINIPATH_XGXS_RX_POL_MASK <<
680 INFINIPATH_XGXS_RX_POL_SHIFT);
681 val |= dd->ipath_rx_pol_inv <<
682 INFINIPATH_XGXS_RX_POL_SHIFT;
30fc5c31 683 }
2c9446a1 684 if (val != prev_val)
dc741bbd
BS		 685 ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, val);
686
687 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
688
689 /* clear current and de-emphasis bits */
690 config1 &= ~0x0ffffffff00ULL;
691 /* set current to 20ma */
692 config1 |= 0x00000000000ULL;
693 /* set de-emphasis to -5.68dB */
694 config1 |= 0x0cccc000000ULL;
695 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig1, config1);
696
697 ipath_cdbg(VERBOSE, "done: SerDes status config0=%llx "
698 "config1=%llx, sstatus=%llx xgxs=%llx\n",
699 (unsigned long long) val, (unsigned long long) config1,
700 (unsigned long long)
701 ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesstatus),
702 (unsigned long long)
703 ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig));
704
705 if (!ipath_waitfor_mdio_cmdready(dd)) {
706 ipath_write_kreg(
707 dd, dd->ipath_kregs->kr_mdio,
708 ipath_mdio_req(IPATH_MDIO_CMD_READ, 31,
709 IPATH_MDIO_CTRL_XGXS_REG_8, 0));
710 if (ipath_waitfor_complete(dd, dd->ipath_kregs->kr_mdio,
711 IPATH_MDIO_DATAVALID, &val))
712 ipath_dbg("Never got MDIO data for XGXS "
713 "status read\n");
714 else
715 ipath_cdbg(VERBOSE, "MDIO Read reg8, "
716 "'bank' 31 %x\n", (u32) val);
717 } else
718 ipath_dbg("Never got MDIO cmdready for XGXS status read\n");
719
720 return ret;
721}
722
723/**
724 * ipath_pe_quiet_serdes - set serdes to txidle
725 * @dd: the infinipath device
726 * Called when driver is being unloaded
727 */
ac2ae4c9 728static void ipath_pe_quiet_serdes(struct ipath_devdata *dd)
dc741bbd
BS		 729{
730 u64 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
731
732 val |= INFINIPATH_SERDC0_TXIDLE;
733 ipath_dbg("Setting TxIdleEn on serdes (config0 = %llx)\n",
734 (unsigned long long) val);
735 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
736}
737
dc741bbd
BS		 738static int ipath_pe_intconfig(struct ipath_devdata *dd)
739{
2c9446a1
BS		 740 u32 chiprev;
741
742 /*
743 * If the chip supports added error indication via GPIO pins,
744 * enable interrupts on those bits so the interrupt routine
745 * can count the events. Also set flag so interrupt routine
746 * can know they are expected.
747 */
748 chiprev = dd->ipath_revision >> INFINIPATH_R_CHIPREVMINOR_SHIFT;
749 if ((chiprev & INFINIPATH_R_CHIPREVMINOR_MASK) > 1) {
750 /* Rev2+ reports extra errors via internal GPIO pins */
751 dd->ipath_flags |= IPATH_GPIO_ERRINTRS;
8f140b40
AJ		 752 dd->ipath_gpio_mask |= IPATH_GPIO_ERRINTR_MASK;
753 ipath_write_kreg(dd, dd->ipath_kregs->kr_gpio_mask,
754 dd->ipath_gpio_mask);
2c9446a1 755 }
dc741bbd
BS		 756 return 0;
757}
758
759/**
760 * ipath_setup_pe_setextled - set the state of the two external LEDs
761 * @dd: the infinipath device
762 * @lst: the L state
763 * @ltst: the LT state
764
765 * These LEDs indicate the physical and logical state of IB link.
766 * For this chip (at least with recommended board pinouts), LED1
767 * is Yellow (logical state) and LED2 is Green (physical state),
768 *
769 * Note: We try to match the Mellanox HCA LED behavior as best
770 * we can. Green indicates physical link state is OK (something is
771 * plugged in, and we can train).
772 * Amber indicates the link is logically up (ACTIVE).
773 * Mellanox further blinks the amber LED to indicate data packet
774 * activity, but we have no hardware support for that, so it would
775 * require waking up every 10-20 msecs and checking the counters
776 * on the chip, and then turning the LED off if appropriate. That's
777 * visible overhead, so not something we will do.
778 *
779 */
780static void ipath_setup_pe_setextled(struct ipath_devdata *dd, u64 lst,
781 u64 ltst)
782{
783 u64 extctl;
17b2eb9f 784 unsigned long flags = 0;
dc741bbd
BS		 785
786 /* the diags use the LED to indicate diag info, so we leave
787 * the external LED alone when the diags are running */
788 if (ipath_diag_inuse)
789 return;
790
82466f00
MA		 791 /* Allow override of LED display for, e.g. Locating system in rack */
792 if (dd->ipath_led_override) {
793 ltst = (dd->ipath_led_override & IPATH_LED_PHYS)
794 ? INFINIPATH_IBCS_LT_STATE_LINKUP
795 : INFINIPATH_IBCS_LT_STATE_DISABLED;
796 lst = (dd->ipath_led_override & IPATH_LED_LOG)
797 ? INFINIPATH_IBCS_L_STATE_ACTIVE
798 : INFINIPATH_IBCS_L_STATE_DOWN;
799 }
800
17b2eb9f 801 spin_lock_irqsave(&dd->ipath_gpio_lock, flags);
dc741bbd
BS		 802 extctl = dd->ipath_extctrl & ~(INFINIPATH_EXTC_LED1PRIPORT_ON |
803 INFINIPATH_EXTC_LED2PRIPORT_ON);
804
805 if (ltst & INFINIPATH_IBCS_LT_STATE_LINKUP)
806 extctl |= INFINIPATH_EXTC_LED2PRIPORT_ON;
807 if (lst == INFINIPATH_IBCS_L_STATE_ACTIVE)
808 extctl |= INFINIPATH_EXTC_LED1PRIPORT_ON;
809 dd->ipath_extctrl = extctl;
810 ipath_write_kreg(dd, dd->ipath_kregs->kr_extctrl, extctl);
17b2eb9f 811 spin_unlock_irqrestore(&dd->ipath_gpio_lock, flags);
dc741bbd
BS		 812}
813
814/**
815 * ipath_setup_pe_cleanup - clean up any per-chip chip-specific stuff
816 * @dd: the infinipath device
817 *
818 * This is called during driver unload.
819 * We do the pci_disable_msi here, not in generic code, because it
525d0ca1
BS		 820 * isn't used for the HT chips. If we do end up needing pci_enable_msi
821 * at some point in the future for HT, we'll move the call back
dc741bbd
BS		 822 * into the main init_one code.
823 */
824static void ipath_setup_pe_cleanup(struct ipath_devdata *dd)
825{
826 dd->ipath_msi_lo = 0; /* just in case unload fails */
827 pci_disable_msi(dd->pcidev);
828}
829
830/**
831 * ipath_setup_pe_config - setup PCIe config related stuff
832 * @dd: the infinipath device
833 * @pdev: the PCI device
834 *
835 * The pci_enable_msi() call will fail on systems with MSI quirks
836 * such as those with AMD8131, even if the device of interest is not
837 * attached to that device, (in the 2.6.13 - 2.6.15 kernels, at least, fixed
838 * late in 2.6.16).
839 * All that can be done is to edit the kernel source to remove the quirk
840 * check until that is fixed.
525d0ca1
BS		 841 * We do not need to call enable_msi() for our HyperTransport chip,
842 * even though it uses MSI, and we want to avoid the quirk warning, so
843 * So we call enable_msi only for PCIe. If we do end up needing
844 * pci_enable_msi at some point in the future for HT, we'll move the
dc741bbd
BS		 845 * call back into the main init_one code.
846 * We save the msi lo and hi values, so we can restore them after
847 * chip reset (the kernel PCI infrastructure doesn't yet handle that
848 * correctly).
849 */
850static int ipath_setup_pe_config(struct ipath_devdata *dd,
851 struct pci_dev *pdev)
852{
853 int pos, ret;
854
855 dd->ipath_msi_lo = 0; /* used as a flag during reset processing */
856 ret = pci_enable_msi(dd->pcidev);
857 if (ret)
858 ipath_dev_err(dd, "pci_enable_msi failed: %d, "
859 "interrupts may not work\n", ret);
860 /* continue even if it fails, we may still be OK... */
0a1336c8 861 dd->ipath_irq = pdev->irq;
dc741bbd
BS		 862
863 if ((pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_MSI))) {
864 u16 control;
865 pci_read_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_LO,
866 &dd->ipath_msi_lo);
867 pci_read_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_HI,
868 &dd->ipath_msi_hi);
869 pci_read_config_word(dd->pcidev, pos + PCI_MSI_FLAGS,
870 &control);
871 /* now save the data (vector) info */
872 pci_read_config_word(dd->pcidev,
873 pos + ((control & PCI_MSI_FLAGS_64BIT)
874 ? 12 : 8),
875 &dd->ipath_msi_data);
876 ipath_cdbg(VERBOSE, "Read msi data 0x%x from config offset "
877 "0x%x, control=0x%x\n", dd->ipath_msi_data,
878 pos + ((control & PCI_MSI_FLAGS_64BIT) ? 12 : 8),
879 control);
880 /* we save the cachelinesize also, although it doesn't
881 * really matter */
882 pci_read_config_byte(dd->pcidev, PCI_CACHE_LINE_SIZE,
883 &dd->ipath_pci_cacheline);
884 } else
885 ipath_dev_err(dd, "Can't find MSI capability, "
886 "can't save MSI settings for reset\n");
887 if ((pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_EXP))) {
888 u16 linkstat;
889 pci_read_config_word(dd->pcidev, pos + PCI_EXP_LNKSTA,
890 &linkstat);
891 linkstat >>= 4;
892 linkstat &= 0x1f;
893 if (linkstat != 8)
894 ipath_dev_err(dd, "PCIe width %u, "
895 "performance reduced\n", linkstat);
896 }
897 else
898 ipath_dev_err(dd, "Can't find PCI Express "
899 "capability!\n");
900 return 0;
901}
902
f62fe77a 903static void ipath_init_pe_variables(struct ipath_devdata *dd)
dc741bbd
BS		 904{
905 /*
906 * bits for selecting i2c direction and values,
907 * used for I2C serial flash
908 */
f62fe77a
BS		 909 dd->ipath_gpio_sda_num = _IPATH_GPIO_SDA_NUM;
910 dd->ipath_gpio_scl_num = _IPATH_GPIO_SCL_NUM;
911 dd->ipath_gpio_sda = IPATH_GPIO_SDA;
912 dd->ipath_gpio_scl = IPATH_GPIO_SCL;
dc741bbd
BS		 913
914 /* variables for sanity checking interrupt and errors */
f62fe77a 915 dd->ipath_hwe_bitsextant =
dc741bbd
BS		 916 (INFINIPATH_HWE_RXEMEMPARITYERR_MASK <<
917 INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT) |
89d1e09b
BS		 918 (INFINIPATH_HWE_TXEMEMPARITYERR_MASK <<
919 INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT) |
dc741bbd
BS		 920 (INFINIPATH_HWE_PCIEMEMPARITYERR_MASK <<
921 INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT) |
922 INFINIPATH_HWE_PCIE1PLLFAILED |
923 INFINIPATH_HWE_PCIE0PLLFAILED |
924 INFINIPATH_HWE_PCIEPOISONEDTLP |
925 INFINIPATH_HWE_PCIECPLTIMEOUT |
926 INFINIPATH_HWE_PCIEBUSPARITYXTLH |
927 INFINIPATH_HWE_PCIEBUSPARITYXADM |
928 INFINIPATH_HWE_PCIEBUSPARITYRADM |
929 INFINIPATH_HWE_MEMBISTFAILED |
930 INFINIPATH_HWE_COREPLL_FBSLIP |
931 INFINIPATH_HWE_COREPLL_RFSLIP |
932 INFINIPATH_HWE_SERDESPLLFAILED |
933 INFINIPATH_HWE_IBCBUSTOSPCPARITYERR |
934 INFINIPATH_HWE_IBCBUSFRSPCPARITYERR;
f62fe77a 935 dd->ipath_i_bitsextant =
dc741bbd
BS		 936 (INFINIPATH_I_RCVURG_MASK << INFINIPATH_I_RCVURG_SHIFT) |
937 (INFINIPATH_I_RCVAVAIL_MASK <<
938 INFINIPATH_I_RCVAVAIL_SHIFT) |
939 INFINIPATH_I_ERROR | INFINIPATH_I_SPIOSENT |
940 INFINIPATH_I_SPIOBUFAVAIL | INFINIPATH_I_GPIO;
f62fe77a 941 dd->ipath_e_bitsextant =
dc741bbd
BS		 942 INFINIPATH_E_RFORMATERR | INFINIPATH_E_RVCRC |
943 INFINIPATH_E_RICRC | INFINIPATH_E_RMINPKTLEN |
944 INFINIPATH_E_RMAXPKTLEN | INFINIPATH_E_RLONGPKTLEN |
945 INFINIPATH_E_RSHORTPKTLEN | INFINIPATH_E_RUNEXPCHAR |
946 INFINIPATH_E_RUNSUPVL | INFINIPATH_E_REBP |
947 INFINIPATH_E_RIBFLOW | INFINIPATH_E_RBADVERSION |
948 INFINIPATH_E_RRCVEGRFULL | INFINIPATH_E_RRCVHDRFULL |
949 INFINIPATH_E_RBADTID | INFINIPATH_E_RHDRLEN |
950 INFINIPATH_E_RHDR | INFINIPATH_E_RIBLOSTLINK |
951 INFINIPATH_E_SMINPKTLEN | INFINIPATH_E_SMAXPKTLEN |
952 INFINIPATH_E_SUNDERRUN | INFINIPATH_E_SPKTLEN |
953 INFINIPATH_E_SDROPPEDSMPPKT | INFINIPATH_E_SDROPPEDDATAPKT |
954 INFINIPATH_E_SPIOARMLAUNCH | INFINIPATH_E_SUNEXPERRPKTNUM |
955 INFINIPATH_E_SUNSUPVL | INFINIPATH_E_IBSTATUSCHANGED |
956 INFINIPATH_E_INVALIDADDR | INFINIPATH_E_RESET |
957 INFINIPATH_E_HARDWARE;
958
f62fe77a
BS		 959 dd->ipath_i_rcvavail_mask = INFINIPATH_I_RCVAVAIL_MASK;
960 dd->ipath_i_rcvurg_mask = INFINIPATH_I_RCVURG_MASK;
aecd3b5a
MA		 961
962 /*
963 * EEPROM error log 0 is TXE Parity errors. 1 is RXE Parity.
964 * 2 is Some Misc, 3 is reserved for future.
965 */
966 dd->ipath_eep_st_masks[0].hwerrs_to_log =
967 INFINIPATH_HWE_TXEMEMPARITYERR_MASK <<
968 INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT;
969
970 /* Ignore errors in PIO/PBC on systems with unordered write-combining */
971 if (ipath_unordered_wc())
972 dd->ipath_eep_st_masks[0].hwerrs_to_log &= ~TXE_PIO_PARITY;
973
974 dd->ipath_eep_st_masks[1].hwerrs_to_log =
975 INFINIPATH_HWE_RXEMEMPARITYERR_MASK <<
976 INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT;
977
978 dd->ipath_eep_st_masks[2].errs_to_log =
979 INFINIPATH_E_INVALIDADDR | INFINIPATH_E_RESET;
980
981
dc741bbd
BS		 982}
983
984/* setup the MSI stuff again after a reset. I'd like to just call
985 * pci_enable_msi() and request_irq() again, but when I do that,
986 * the MSI enable bit doesn't get set in the command word, and
987 * we switch to to a different interrupt vector, which is confusing,
988 * so I instead just do it all inline. Perhaps somehow can tie this
989 * into the PCIe hotplug support at some point
990 * Note, because I'm doing it all here, I don't call pci_disable_msi()
991 * or free_irq() at the start of ipath_setup_pe_reset().
992 */
993static int ipath_reinit_msi(struct ipath_devdata *dd)
994{
995 int pos;
996 u16 control;
997 int ret;
998
999 if (!dd->ipath_msi_lo) {
1000 dev_info(&dd->pcidev->dev, "Can't restore MSI config, "
1001 "initial setup failed?\n");
1002 ret = 0;
1003 goto bail;
1004 }
1005
1006 if (!(pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_MSI))) {
1007 ipath_dev_err(dd, "Can't find MSI capability, "
1008 "can't restore MSI settings\n");
1009 ret = 0;
1010 goto bail;
1011 }
1012 ipath_cdbg(VERBOSE, "Writing msi_lo 0x%x to config offset 0x%x\n",
1013 dd->ipath_msi_lo, pos + PCI_MSI_ADDRESS_LO);
1014 pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_LO,
1015 dd->ipath_msi_lo);
1016 ipath_cdbg(VERBOSE, "Writing msi_lo 0x%x to config offset 0x%x\n",
1017 dd->ipath_msi_hi, pos + PCI_MSI_ADDRESS_HI);
1018 pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_HI,
1019 dd->ipath_msi_hi);
1020 pci_read_config_word(dd->pcidev, pos + PCI_MSI_FLAGS, &control);
1021 if (!(control & PCI_MSI_FLAGS_ENABLE)) {
1022 ipath_cdbg(VERBOSE, "MSI control at off %x was %x, "
1023 "setting MSI enable (%x)\n", pos + PCI_MSI_FLAGS,
1024 control, control | PCI_MSI_FLAGS_ENABLE);
1025 control |= PCI_MSI_FLAGS_ENABLE;
1026 pci_write_config_word(dd->pcidev, pos + PCI_MSI_FLAGS,
1027 control);
1028 }
1029 /* now rewrite the data (vector) info */
1030 pci_write_config_word(dd->pcidev, pos +
1031 ((control & PCI_MSI_FLAGS_64BIT) ? 12 : 8),
1032 dd->ipath_msi_data);
1033 /* we restore the cachelinesize also, although it doesn't really
1034 * matter */
1035 pci_write_config_byte(dd->pcidev, PCI_CACHE_LINE_SIZE,
1036 dd->ipath_pci_cacheline);
1037 /* and now set the pci master bit again */
1038 pci_set_master(dd->pcidev);
1039 ret = 1;
1040
1041bail:
1042 return ret;
1043}
1044
1045/* This routine sleeps, so it can only be called from user context, not
1046 * from interrupt context. If we need interrupt context, we can split
1047 * it into two routines.
1048*/
1049static int ipath_setup_pe_reset(struct ipath_devdata *dd)
1050{
1051 u64 val;
1052 int i;
1053 int ret;
1054
1055 /* Use ERROR so it shows up in logs, etc. */
525d0ca1 1056 ipath_dev_err(dd, "Resetting InfiniPath unit %u\n", dd->ipath_unit);
c71c30dc
BS		 1057 /* keep chip from being accessed in a few places */
1058 dd->ipath_flags &= ~(IPATH_INITTED|IPATH_PRESENT);
dc741bbd
BS		 1059 val = dd->ipath_control | INFINIPATH_C_RESET;
1060 ipath_write_kreg(dd, dd->ipath_kregs->kr_control, val);
1061 mb();
1062
1063 for (i = 1; i <= 5; i++) {
1064 int r;
1065 /* allow MBIST, etc. to complete; longer on each retry.
1066 * We sometimes get machine checks from bus timeout if no
1067 * response, so for now, make it *really* long.
1068 */
1069 msleep(1000 + (1 + i) * 2000);
1070 if ((r =
1071 pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0,
1072 dd->ipath_pcibar0)))
1073 ipath_dev_err(dd, "rewrite of BAR0 failed: %d\n",
1074 r);
1075 if ((r =
1076 pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_1,
1077 dd->ipath_pcibar1)))
1078 ipath_dev_err(dd, "rewrite of BAR1 failed: %d\n",
1079 r);
1080 /* now re-enable memory access */
1081 if ((r = pci_enable_device(dd->pcidev)))
1082 ipath_dev_err(dd, "pci_enable_device failed after "
1083 "reset: %d\n", r);
c71c30dc
BS		 1084 /* whether it worked or not, mark as present, again */
1085 dd->ipath_flags |= IPATH_PRESENT;
dc741bbd
BS		 1086 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_revision);
1087 if (val == dd->ipath_revision) {
1088 ipath_cdbg(VERBOSE, "Got matching revision "
1089 "register %llx on try %d\n",
1090 (unsigned long long) val, i);
1091 ret = ipath_reinit_msi(dd);
1092 goto bail;
1093 }
1094 /* Probably getting -1 back */
1095 ipath_dbg("Didn't get expected revision register, "
1096 "got %llx, try %d\n", (unsigned long long) val,
1097 i + 1);
1098 }
1099 ret = 0; /* failed */
1100
1101bail:
1102 return ret;
1103}
1104
1105/**
1106 * ipath_pe_put_tid - write a TID in chip
1107 * @dd: the infinipath device
1108 * @tidptr: pointer to the expected TID (in chip) to udpate
f716cdfe 1109 * @tidtype: RCVHQ_RCV_TYPE_EAGER (1) for eager, RCVHQ_RCV_TYPE_EXPECTED (0) for expected
dc741bbd
BS		 1110 * @pa: physical address of in memory buffer; ipath_tidinvalid if freeing
1111 *
1112 * This exists as a separate routine to allow for special locking etc.
1113 * It's used for both the full cleanup on exit, as well as the normal
1114 * setup and teardown.
1115 */
1116static void ipath_pe_put_tid(struct ipath_devdata *dd, u64 __iomem *tidptr,
1117 u32 type, unsigned long pa)
1118{
1119 u32 __iomem *tidp32 = (u32 __iomem *)tidptr;
1120 unsigned long flags = 0; /* keep gcc quiet */
1121
1122 if (pa != dd->ipath_tidinvalid) {
1123 if (pa & ((1U << 11) - 1)) {
1124 dev_info(&dd->pcidev->dev, "BUG: physaddr %lx "
1125 "not 4KB aligned!\n", pa);
1126 return;
1127 }
1128 pa >>= 11;
1129 /* paranoia check */
1130 if (pa & (7<<29))
1131 ipath_dev_err(dd,
1132 "BUG: Physical page address 0x%lx "
1133 "has bits set in 31-29\n", pa);
1134
f716cdfe 1135 if (type == RCVHQ_RCV_TYPE_EAGER)
dc741bbd
BS		 1136 pa |= dd->ipath_tidtemplate;
1137 else /* for now, always full 4KB page */
1138 pa |= 2 << 29;
1139 }
1140
1141 /* workaround chip bug 9437 by writing each TID twice
1142 * and holding a spinlock around the writes, so they don't
1143 * intermix with other TID (eager or expected) writes
1144 * Unfortunately, this call can be done from interrupt level
1145 * for the port 0 eager TIDs, so we have to use irqsave
1146 */
1147 spin_lock_irqsave(&dd->ipath_tid_lock, flags);
1148 ipath_write_kreg(dd, dd->ipath_kregs->kr_scratch, 0xfeeddeaf);
1149 if (dd->ipath_kregbase)
1150 writel(pa, tidp32);
1151 ipath_write_kreg(dd, dd->ipath_kregs->kr_scratch, 0xdeadbeef);
1152 mmiowb();
1153 spin_unlock_irqrestore(&dd->ipath_tid_lock, flags);
1154}
2c9446a1
BS		 1155/**
1156 * ipath_pe_put_tid_2 - write a TID in chip, Revision 2 or higher
1157 * @dd: the infinipath device
1158 * @tidptr: pointer to the expected TID (in chip) to udpate
f716cdfe 1159 * @tidtype: RCVHQ_RCV_TYPE_EAGER (1) for eager, RCVHQ_RCV_TYPE_EXPECTED (0) for expected
2c9446a1
BS		 1160 * @pa: physical address of in memory buffer; ipath_tidinvalid if freeing
1161 *
1162 * This exists as a separate routine to allow for selection of the
1163 * appropriate "flavor". The static calls in cleanup just use the
1164 * revision-agnostic form, as they are not performance critical.
1165 */
1166static void ipath_pe_put_tid_2(struct ipath_devdata *dd, u64 __iomem *tidptr,
1167 u32 type, unsigned long pa)
1168{
1169 u32 __iomem *tidp32 = (u32 __iomem *)tidptr;
1170
1171 if (pa != dd->ipath_tidinvalid) {
1172 if (pa & ((1U << 11) - 1)) {
1173 dev_info(&dd->pcidev->dev, "BUG: physaddr %lx "
1fd3b40f 1174 "not 2KB aligned!\n", pa);
2c9446a1
BS		 1175 return;
1176 }
1177 pa >>= 11;
1178 /* paranoia check */
1179 if (pa & (7<<29))
1180 ipath_dev_err(dd,
1181 "BUG: Physical page address 0x%lx "
1182 "has bits set in 31-29\n", pa);
1183
f716cdfe 1184 if (type == RCVHQ_RCV_TYPE_EAGER)
2c9446a1
BS		 1185 pa |= dd->ipath_tidtemplate;
1186 else /* for now, always full 4KB page */
1187 pa |= 2 << 29;
1188 }
1189 if (dd->ipath_kregbase)
1190 writel(pa, tidp32);
1191 mmiowb();
1192}
1193
dc741bbd
BS		 1194
1195/**
1196 * ipath_pe_clear_tid - clear all TID entries for a port, expected and eager
1197 * @dd: the infinipath device
1198 * @port: the port
1199 *
1200 * clear all TID entries for a port, expected and eager.
525d0ca1 1201 * Used from ipath_close(). On this chip, TIDs are only 32 bits,
dc741bbd
BS		 1202 * not 64, but they are still on 64 bit boundaries, so tidbase
1203 * is declared as u64 * for the pointer math, even though we write 32 bits
1204 */
1205static void ipath_pe_clear_tids(struct ipath_devdata *dd, unsigned port)
1206{
1207 u64 __iomem *tidbase;
1208 unsigned long tidinv;
1209 int i;
1210
1211 if (!dd->ipath_kregbase)
1212 return;
1213
1214 ipath_cdbg(VERBOSE, "Invalidate TIDs for port %u\n", port);
1215
1216 tidinv = dd->ipath_tidinvalid;
1217 tidbase = (u64 __iomem *)
1218 ((char __iomem *)(dd->ipath_kregbase) +
1219 dd->ipath_rcvtidbase +
1220 port * dd->ipath_rcvtidcnt * sizeof(*tidbase));
1221
1222 for (i = 0; i < dd->ipath_rcvtidcnt; i++)
f716cdfe
JE		 1223 ipath_pe_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EXPECTED,
1224 tidinv);
dc741bbd
BS		 1225
1226 tidbase = (u64 __iomem *)
1227 ((char __iomem *)(dd->ipath_kregbase) +
1228 dd->ipath_rcvegrbase +
1229 port * dd->ipath_rcvegrcnt * sizeof(*tidbase));
1230
1231 for (i = 0; i < dd->ipath_rcvegrcnt; i++)
f716cdfe
JE		 1232 ipath_pe_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EAGER,
1233 tidinv);
dc741bbd
BS		 1234}
1235
1236/**
1237 * ipath_pe_tidtemplate - setup constants for TID updates
1238 * @dd: the infinipath device
1239 *
1240 * We setup stuff that we use a lot, to avoid calculating each time
1241 */
1242static void ipath_pe_tidtemplate(struct ipath_devdata *dd)
1243{
1244 u32 egrsize = dd->ipath_rcvegrbufsize;
1245
1246 /* For now, we always allocate 4KB buffers (at init) so we can
1247 * receive max size packets. We may want a module parameter to
1248 * specify 2KB or 4KB and/or make be per port instead of per device
1249 * for those who want to reduce memory footprint. Note that the
1250 * ipath_rcvhdrentsize size must be large enough to hold the largest
1251 * IB header (currently 96 bytes) that we expect to handle (plus of
1252 * course the 2 dwords of RHF).
1253 */
1254 if (egrsize == 2048)
1255 dd->ipath_tidtemplate = 1U << 29;
1256 else if (egrsize == 4096)
1257 dd->ipath_tidtemplate = 2U << 29;
1258 else {
1259 egrsize = 4096;
1260 dev_info(&dd->pcidev->dev, "BUG: unsupported egrbufsize "
1261 "%u, using %u\n", dd->ipath_rcvegrbufsize,
1262 egrsize);
1263 dd->ipath_tidtemplate = 2U << 29;
1264 }
1265 dd->ipath_tidinvalid = 0;
1266}
1267
1268static int ipath_pe_early_init(struct ipath_devdata *dd)
1269{
1270 dd->ipath_flags |= IPATH_4BYTE_TID;
1271
1272 /*
525d0ca1
BS		 1273 * For openfabrics, we need to be able to handle an IB header of
1274 * 24 dwords. HT chip has arbitrary sized receive buffers, so we
1275 * made them the same size as the PIO buffers. This chip does not
dc741bbd
BS		 1276 * handle arbitrary size buffers, so we need the header large enough
1277 * to handle largest IB header, but still have room for a 2KB MTU
1278 * standard IB packet.
1279 */
1280 dd->ipath_rcvhdrentsize = 24;
1281 dd->ipath_rcvhdrsize = IPATH_DFLT_RCVHDRSIZE;
1282
525d0ca1
BS		 1283 /*
1284 * To truly support a 4KB MTU (for usermode), we need to
1285 * bump this to a larger value. For now, we use them for
1286 * the kernel only.
dc741bbd
BS		 1287 */
1288 dd->ipath_rcvegrbufsize = 2048;
1289 /*
1290 * the min() check here is currently a nop, but it may not always
1291 * be, depending on just how we do ipath_rcvegrbufsize
1292 */
1293 dd->ipath_ibmaxlen = min(dd->ipath_piosize2k,
1294 dd->ipath_rcvegrbufsize +
1295 (dd->ipath_rcvhdrentsize << 2));
1296 dd->ipath_init_ibmaxlen = dd->ipath_ibmaxlen;
1297
1298 /*
525d0ca1 1299 * We can request a receive interrupt for 1 or
dc741bbd 1300 * more packets from current offset. For now, we set this
525d0ca1 1301 * up for a single packet.
dc741bbd
BS		 1302 */
1303 dd->ipath_rhdrhead_intr_off = 1ULL<<32;
1304
f2080fa3
BS		 1305 ipath_get_eeprom_info(dd);
1306
dc741bbd
BS		 1307 return 0;
1308}
1309
1310int __attribute__((weak)) ipath_unordered_wc(void)
1311{
1312 return 0;
1313}
1314
1315/**
1316 * ipath_init_pe_get_base_info - set chip-specific flags for user code
2c9446a1 1317 * @pd: the infinipath port
dc741bbd
BS		 1318 * @kbase: ipath_base_info pointer
1319 *
1320 * We set the PCIE flag because the lower bandwidth on PCIe vs
d08df601 1321 * HyperTransport can affect some user packet algorithms.
dc741bbd
BS		 1322 */
1323static int ipath_pe_get_base_info(struct ipath_portdata *pd, void *kbase)
1324{
1325 struct ipath_base_info *kinfo = kbase;
2c9446a1 1326 struct ipath_devdata *dd;
dc741bbd
BS		 1327
1328 if (ipath_unordered_wc()) {
1329 kinfo->spi_runtime_flags |= IPATH_RUNTIME_FORCE_WC_ORDER;
1330 ipath_cdbg(PROC, "Intel processor, forcing WC order\n");
1331 }
1332 else
1333 ipath_cdbg(PROC, "Not Intel processor, WC ordered\n");
1334
2c9446a1
BS		 1335 if (pd == NULL)
1336 goto done;
1337
1338 dd = pd->port_dd;
1339
2c9446a1
BS		 1340done:
1341 kinfo->spi_runtime_flags |= IPATH_RUNTIME_PCIE;
dc741bbd
BS		 1342 return 0;
1343}
1344
51f65ebc
BS		 1345static void ipath_pe_free_irq(struct ipath_devdata *dd)
1346{
1347 free_irq(dd->ipath_irq, dd);
1348 dd->ipath_irq = 0;
1349}
1350
9783ab40
BS		 1351/*
1352 * On platforms using this chip, and not having ordered WC stores, we
1353 * can get TXE parity errors due to speculative reads to the PIO buffers,
1354 * and this, due to a chip bug can result in (many) false parity error
1355 * reports. So it's a debug print on those, and an info print on systems
1356 * where the speculative reads don't occur.
1357 * Because we can get lots of false errors, we have no upper limit
1358 * on recovery attempts on those platforms.
1359 */
1360static int ipath_pe_txe_recover(struct ipath_devdata *dd)
1361{
1362 if (ipath_unordered_wc())
1363 ipath_dbg("Recovering from TXE PIO parity error\n");
1364 else {
1365 int cnt = ++ipath_stats.sps_txeparity;
1366 if (cnt >= IPATH_MAX_PARITY_ATTEMPTS) {
1367 if (cnt == IPATH_MAX_PARITY_ATTEMPTS)
1368 ipath_dev_err(dd,
1369 "Too many attempts to recover from "
1370 "TXE parity, giving up\n");
1371 return 0;
1372 }
1373 dev_info(&dd->pcidev->dev,
1374 "Recovering from TXE PIO parity error\n");
1375 }
9783ab40
BS		 1376 return 1;
1377}
1378
dc741bbd 1379/**
525d0ca1 1380 * ipath_init_iba6120_funcs - set up the chip-specific function pointers
dc741bbd
BS		 1381 * @dd: the infinipath device
1382 *
1383 * This is global, and is called directly at init to set up the
1384 * chip-specific function pointers for later use.
1385 */
525d0ca1 1386void ipath_init_iba6120_funcs(struct ipath_devdata *dd)
dc741bbd
BS		 1387{
1388 dd->ipath_f_intrsetup = ipath_pe_intconfig;
1389 dd->ipath_f_bus = ipath_setup_pe_config;
1390 dd->ipath_f_reset = ipath_setup_pe_reset;
1391 dd->ipath_f_get_boardname = ipath_pe_boardname;
1392 dd->ipath_f_init_hwerrors = ipath_pe_init_hwerrors;
1393 dd->ipath_f_early_init = ipath_pe_early_init;
1394 dd->ipath_f_handle_hwerrors = ipath_pe_handle_hwerrors;
1395 dd->ipath_f_quiet_serdes = ipath_pe_quiet_serdes;
1396 dd->ipath_f_bringup_serdes = ipath_pe_bringup_serdes;
1397 dd->ipath_f_clear_tids = ipath_pe_clear_tids;
2c9446a1
BS		 1398 if (dd->ipath_minrev >= 2)
1399 dd->ipath_f_put_tid = ipath_pe_put_tid_2;
1400 else
1401 dd->ipath_f_put_tid = ipath_pe_put_tid;
dc741bbd
BS		 1402 dd->ipath_f_cleanup = ipath_setup_pe_cleanup;
1403 dd->ipath_f_setextled = ipath_setup_pe_setextled;
1404 dd->ipath_f_get_base_info = ipath_pe_get_base_info;
51f65ebc 1405 dd->ipath_f_free_irq = ipath_pe_free_irq;
dc741bbd
BS		 1406
1407 /* initialize chip-specific variables */
1408 dd->ipath_f_tidtemplate = ipath_pe_tidtemplate;
1409
1410 /*
1411 * setup the register offsets, since they are different for each
1412 * chip
1413 */
1414 dd->ipath_kregs = &ipath_pe_kregs;
1415 dd->ipath_cregs = &ipath_pe_cregs;
1416
f62fe77a 1417 ipath_init_pe_variables(dd);
dc741bbd
BS		 1418}
1419
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