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au1xxx-ide: fix ->io_32bit handling
[net-next-2.6.git] / drivers / ide / pci / scc_pata.c
CommitLineData
bde18a2e
KI		 1/*
2 * Support for IDE interfaces on Celleb platform
3 *
4 * (C) Copyright 2006 TOSHIBA CORPORATION
5 *
6 * This code is based on drivers/ide/pci/siimage.c:
7 * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org>
8 * Copyright (C) 2003 Red Hat <alan@redhat.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, write to the Free Software Foundation, Inc.,
22 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
23 */
24
25#include <linux/types.h>
26#include <linux/module.h>
27#include <linux/pci.h>
28#include <linux/delay.h>
29#include <linux/hdreg.h>
30#include <linux/ide.h>
31#include <linux/init.h>
32
33#define PCI_DEVICE_ID_TOSHIBA_SCC_ATA 0x01b4
34
35#define SCC_PATA_NAME "scc IDE"
36
37#define TDVHSEL_MASTER 0x00000001
38#define TDVHSEL_SLAVE 0x00000004
39
40#define MODE_JCUSFEN 0x00000080
41
42#define CCKCTRL_ATARESET 0x00040000
43#define CCKCTRL_BUFCNT 0x00020000
44#define CCKCTRL_CRST 0x00010000
45#define CCKCTRL_OCLKEN 0x00000100
46#define CCKCTRL_ATACLKOEN 0x00000002
47#define CCKCTRL_LCLKEN 0x00000001
48
49#define QCHCD_IOS_SS 0x00000001
50
51#define QCHSD_STPDIAG 0x00020000
52
53#define INTMASK_MSK 0xD1000012
54#define INTSTS_SERROR 0x80000000
55#define INTSTS_PRERR 0x40000000
56#define INTSTS_RERR 0x10000000
57#define INTSTS_ICERR 0x01000000
58#define INTSTS_BMSINT 0x00000010
59#define INTSTS_BMHE 0x00000008
60#define INTSTS_IOIRQS 0x00000004
61#define INTSTS_INTRQ 0x00000002
62#define INTSTS_ACTEINT 0x00000001
63
64#define ECMODE_VALUE 0x01
65
66static struct scc_ports {
67 unsigned long ctl, dma;
68 unsigned char hwif_id; /* for removing hwif from system */
69} scc_ports[MAX_HWIFS];
70
71/* PIO transfer mode table */
72/* JCHST */
73static unsigned long JCHSTtbl[2][7] = {
74 {0x0E, 0x05, 0x02, 0x03, 0x02, 0x00, 0x00}, /* 100MHz */
75 {0x13, 0x07, 0x04, 0x04, 0x03, 0x00, 0x00} /* 133MHz */
76};
77
78/* JCHHT */
79static unsigned long JCHHTtbl[2][7] = {
80 {0x0E, 0x02, 0x02, 0x02, 0x02, 0x00, 0x00}, /* 100MHz */
81 {0x13, 0x03, 0x03, 0x03, 0x03, 0x00, 0x00} /* 133MHz */
82};
83
84/* JCHCT */
85static unsigned long JCHCTtbl[2][7] = {
86 {0x1D, 0x1D, 0x1C, 0x0B, 0x06, 0x00, 0x00}, /* 100MHz */
87 {0x27, 0x26, 0x26, 0x0E, 0x09, 0x00, 0x00} /* 133MHz */
88};
89
90
91/* DMA transfer mode table */
92/* JCHDCTM/JCHDCTS */
93static unsigned long JCHDCTxtbl[2][7] = {
94 {0x0A, 0x06, 0x04, 0x03, 0x01, 0x00, 0x00}, /* 100MHz */
95 {0x0E, 0x09, 0x06, 0x04, 0x02, 0x01, 0x00} /* 133MHz */
96};
97
98/* JCSTWTM/JCSTWTS */
99static unsigned long JCSTWTxtbl[2][7] = {
100 {0x06, 0x04, 0x03, 0x02, 0x02, 0x02, 0x00}, /* 100MHz */
101 {0x09, 0x06, 0x04, 0x02, 0x02, 0x02, 0x02} /* 133MHz */
102};
103
104/* JCTSS */
105static unsigned long JCTSStbl[2][7] = {
106 {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x00}, /* 100MHz */
107 {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05} /* 133MHz */
108};
109
110/* JCENVT */
111static unsigned long JCENVTtbl[2][7] = {
112 {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00}, /* 100MHz */
113 {0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02} /* 133MHz */
114};
115
116/* JCACTSELS/JCACTSELM */
117static unsigned long JCACTSELtbl[2][7] = {
118 {0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00}, /* 100MHz */
119 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01} /* 133MHz */
120};
121
122
123static u8 scc_ide_inb(unsigned long port)
124{
125 u32 data = in_be32((void*)port);
126 return (u8)data;
127}
128
129static u16 scc_ide_inw(unsigned long port)
130{
131 u32 data = in_be32((void*)port);
132 return (u16)data;
133}
134
bde18a2e
KI		 135static void scc_ide_insw(unsigned long port, void *addr, u32 count)
136{
137 u16 *ptr = (u16 *)addr;
138 while (count--) {
139 *ptr++ = le16_to_cpu(in_be32((void*)port));
140 }
141}
142
143static void scc_ide_insl(unsigned long port, void *addr, u32 count)
144{
145 u16 *ptr = (u16 *)addr;
146 while (count--) {
147 *ptr++ = le16_to_cpu(in_be32((void*)port));
148 *ptr++ = le16_to_cpu(in_be32((void*)port));
149 }
150}
151
152static void scc_ide_outb(u8 addr, unsigned long port)
153{
154 out_be32((void*)port, addr);
155}
156
157static void scc_ide_outw(u16 addr, unsigned long port)
158{
159 out_be32((void*)port, addr);
160}
161
bde18a2e
KI		 162static void
163scc_ide_outbsync(ide_drive_t * drive, u8 addr, unsigned long port)
164{
165 ide_hwif_t *hwif = HWIF(drive);
166
167 out_be32((void*)port, addr);
f644d47a 168 eieio();
bde18a2e 169 in_be32((void*)(hwif->dma_base + 0x01c));
f644d47a 170 eieio();
bde18a2e
KI		 171}
172
173static void
174scc_ide_outsw(unsigned long port, void *addr, u32 count)
175{
176 u16 *ptr = (u16 *)addr;
177 while (count--) {
178 out_be32((void*)port, cpu_to_le16(*ptr++));
179 }
180}
181
182static void
183scc_ide_outsl(unsigned long port, void *addr, u32 count)
184{
185 u16 *ptr = (u16 *)addr;
186 while (count--) {
187 out_be32((void*)port, cpu_to_le16(*ptr++));
188 out_be32((void*)port, cpu_to_le16(*ptr++));
189 }
190}
191
bde18a2e 192/**
88b2b32b
BZ		 193 * scc_set_pio_mode - set host controller for PIO mode
194 * @drive: drive
195 * @pio: PIO mode number
bde18a2e
KI		 196 *
197 * Load the timing settings for this device mode into the
198 * controller.
199 */
200
88b2b32b 201static void scc_set_pio_mode(ide_drive_t *drive, const u8 pio)
bde18a2e
KI		 202{
203 ide_hwif_t *hwif = HWIF(drive);
204 struct scc_ports *ports = ide_get_hwifdata(hwif);
205 unsigned long ctl_base = ports->ctl;
206 unsigned long cckctrl_port = ctl_base + 0xff0;
207 unsigned long piosht_port = ctl_base + 0x000;
208 unsigned long pioct_port = ctl_base + 0x004;
209 unsigned long reg;
bde18a2e
KI		 210 int offset;
211
0ecdca26 212 reg = in_be32((void __iomem *)cckctrl_port);
bde18a2e
KI		 213 if (reg & CCKCTRL_ATACLKOEN) {
214 offset = 1; /* 133MHz */
215 } else {
216 offset = 0; /* 100MHz */
217 }
3fcece66 218 reg = JCHSTtbl[offset][pio] << 16 | JCHHTtbl[offset][pio];
0ecdca26 219 out_be32((void __iomem *)piosht_port, reg);
3fcece66 220 reg = JCHCTtbl[offset][pio];
0ecdca26 221 out_be32((void __iomem *)pioct_port, reg);
3fcece66 222}
bde18a2e 223
bde18a2e 224/**
88b2b32b
BZ		 225 * scc_set_dma_mode - set host controller for DMA mode
226 * @drive: drive
227 * @speed: DMA mode
bde18a2e
KI		 228 *
229 * Load the timing settings for this device mode into the
230 * controller.
231 */
232
88b2b32b 233static void scc_set_dma_mode(ide_drive_t *drive, const u8 speed)
bde18a2e
KI		 234{
235 ide_hwif_t *hwif = HWIF(drive);
bde18a2e
KI		 236 struct scc_ports *ports = ide_get_hwifdata(hwif);
237 unsigned long ctl_base = ports->ctl;
238 unsigned long cckctrl_port = ctl_base + 0xff0;
239 unsigned long mdmact_port = ctl_base + 0x008;
240 unsigned long mcrcst_port = ctl_base + 0x00c;
241 unsigned long sdmact_port = ctl_base + 0x010;
242 unsigned long scrcst_port = ctl_base + 0x014;
243 unsigned long udenvt_port = ctl_base + 0x018;
244 unsigned long tdvhsel_port = ctl_base + 0x020;
245 int is_slave = (&hwif->drives[1] == drive);
246 int offset, idx;
247 unsigned long reg;
248 unsigned long jcactsel;
249
0ecdca26 250 reg = in_be32((void __iomem *)cckctrl_port);
bde18a2e
KI		 251 if (reg & CCKCTRL_ATACLKOEN) {
252 offset = 1; /* 133MHz */
253 } else {
254 offset = 0; /* 100MHz */
255 }
256
4db90a14 257 idx = speed - XFER_UDMA_0;
bde18a2e
KI		 258
259 jcactsel = JCACTSELtbl[offset][idx];
260 if (is_slave) {
0ecdca26
BZ		 261 out_be32((void __iomem *)sdmact_port, JCHDCTxtbl[offset][idx]);
262 out_be32((void __iomem *)scrcst_port, JCSTWTxtbl[offset][idx]);
263 jcactsel = jcactsel << 2;
264 out_be32((void __iomem *)tdvhsel_port, (in_be32((void __iomem *)tdvhsel_port) & ~TDVHSEL_SLAVE) | jcactsel);
bde18a2e 265 } else {
0ecdca26
BZ		 266 out_be32((void __iomem *)mdmact_port, JCHDCTxtbl[offset][idx]);
267 out_be32((void __iomem *)mcrcst_port, JCSTWTxtbl[offset][idx]);
268 out_be32((void __iomem *)tdvhsel_port, (in_be32((void __iomem *)tdvhsel_port) & ~TDVHSEL_MASTER) | jcactsel);
bde18a2e
KI		 269 }
270 reg = JCTSStbl[offset][idx] << 16 | JCENVTtbl[offset][idx];
0ecdca26 271 out_be32((void __iomem *)udenvt_port, reg);
bde18a2e
KI		 272}
273
0ecdca26
BZ		 274/**
275 * scc_ide_dma_setup - begin a DMA phase
276 * @drive: target device
277 *
278 * Build an IDE DMA PRD (IDE speak for scatter gather table)
279 * and then set up the DMA transfer registers.
280 *
281 * Returns 0 on success. If a PIO fallback is required then 1
282 * is returned.
283 */
284
285static int scc_dma_setup(ide_drive_t *drive)
286{
287 ide_hwif_t *hwif = drive->hwif;
288 struct request *rq = HWGROUP(drive)->rq;
289 unsigned int reading;
290 u8 dma_stat;
291
292 if (rq_data_dir(rq))
293 reading = 0;
294 else
295 reading = 1 << 3;
296
297 /* fall back to pio! */
298 if (!ide_build_dmatable(drive, rq)) {
299 ide_map_sg(drive, rq);
300 return 1;
301 }
302
303 /* PRD table */
304 out_be32((void __iomem *)hwif->dma_prdtable, hwif->dmatable_dma);
305
306 /* specify r/w */
307 out_be32((void __iomem *)hwif->dma_command, reading);
308
309 /* read dma_status for INTR & ERROR flags */
310 dma_stat = in_be32((void __iomem *)hwif->dma_status);
311
312 /* clear INTR & ERROR flags */
313 out_be32((void __iomem *)hwif->dma_status, dma_stat|6);
314 drive->waiting_for_dma = 1;
315 return 0;
316}
317
318
bde18a2e
KI		 319/**
320 * scc_ide_dma_end - Stop DMA
321 * @drive: IDE drive
322 *
323 * Check and clear INT Status register.
324 * Then call __ide_dma_end().
325 */
326
327static int scc_ide_dma_end(ide_drive_t * drive)
328{
329 ide_hwif_t *hwif = HWIF(drive);
330 unsigned long intsts_port = hwif->dma_base + 0x014;
331 u32 reg;
4ae41ff8
KI		 332 int dma_stat, data_loss = 0;
333 static int retry = 0;
334
335 /* errata A308 workaround: Step5 (check data loss) */
336 /* We don't check non ide_disk because it is limited to UDMA4 */
337 if (!(in_be32((void __iomem *)IDE_ALTSTATUS_REG) & ERR_STAT) &&
338 drive->media == ide_disk && drive->current_speed > XFER_UDMA_4) {
339 reg = in_be32((void __iomem *)intsts_port);
340 if (!(reg & INTSTS_ACTEINT)) {
341 printk(KERN_WARNING "%s: operation failed (transfer data loss)\n",
342 drive->name);
343 data_loss = 1;
344 if (retry++) {
345 struct request *rq = HWGROUP(drive)->rq;
346 int unit;
347 /* ERROR_RESET and drive->crc_count are needed
348 * to reduce DMA transfer mode in retry process.
349 */
350 if (rq)
351 rq->errors |= ERROR_RESET;
352 for (unit = 0; unit < MAX_DRIVES; unit++) {
353 ide_drive_t *drive = &hwif->drives[unit];
354 drive->crc_count++;
355 }
356 }
357 }
358 }
bde18a2e
KI		 359
360 while (1) {
0ecdca26 361 reg = in_be32((void __iomem *)intsts_port);
bde18a2e
KI		 362
363 if (reg & INTSTS_SERROR) {
364 printk(KERN_WARNING "%s: SERROR\n", SCC_PATA_NAME);
0ecdca26 365 out_be32((void __iomem *)intsts_port, INTSTS_SERROR|INTSTS_BMSINT);
bde18a2e 366
0ecdca26 367 out_be32((void __iomem *)hwif->dma_command, in_be32((void __iomem *)hwif->dma_command) & ~QCHCD_IOS_SS);
bde18a2e
KI		 368 continue;
369 }
370
371 if (reg & INTSTS_PRERR) {
372 u32 maea0, maec0;
373 unsigned long ctl_base = hwif->config_data;
374
0ecdca26
BZ		 375 maea0 = in_be32((void __iomem *)(ctl_base + 0xF50));
376 maec0 = in_be32((void __iomem *)(ctl_base + 0xF54));
bde18a2e
KI		 377
378 printk(KERN_WARNING "%s: PRERR [addr:%x cmd:%x]\n", SCC_PATA_NAME, maea0, maec0);
379
0ecdca26 380 out_be32((void __iomem *)intsts_port, INTSTS_PRERR|INTSTS_BMSINT);
bde18a2e 381
0ecdca26 382 out_be32((void __iomem *)hwif->dma_command, in_be32((void __iomem *)hwif->dma_command) & ~QCHCD_IOS_SS);
bde18a2e
KI		 383 continue;
384 }
385
386 if (reg & INTSTS_RERR) {
387 printk(KERN_WARNING "%s: Response Error\n", SCC_PATA_NAME);
0ecdca26 388 out_be32((void __iomem *)intsts_port, INTSTS_RERR|INTSTS_BMSINT);
bde18a2e 389
0ecdca26 390 out_be32((void __iomem *)hwif->dma_command, in_be32((void __iomem *)hwif->dma_command) & ~QCHCD_IOS_SS);
bde18a2e
KI		 391 continue;
392 }
393
394 if (reg & INTSTS_ICERR) {
0ecdca26 395 out_be32((void __iomem *)hwif->dma_command, in_be32((void __iomem *)hwif->dma_command) & ~QCHCD_IOS_SS);
bde18a2e
KI		 396
397 printk(KERN_WARNING "%s: Illegal Configuration\n", SCC_PATA_NAME);
0ecdca26 398 out_be32((void __iomem *)intsts_port, INTSTS_ICERR|INTSTS_BMSINT);
bde18a2e
KI		 399 continue;
400 }
401
402 if (reg & INTSTS_BMSINT) {
403 printk(KERN_WARNING "%s: Internal Bus Error\n", SCC_PATA_NAME);
0ecdca26 404 out_be32((void __iomem *)intsts_port, INTSTS_BMSINT);
bde18a2e
KI		 405
406 ide_do_reset(drive);
407 continue;
408 }
409
410 if (reg & INTSTS_BMHE) {
0ecdca26 411 out_be32((void __iomem *)intsts_port, INTSTS_BMHE);
bde18a2e
KI		 412 continue;
413 }
414
415 if (reg & INTSTS_ACTEINT) {
0ecdca26 416 out_be32((void __iomem *)intsts_port, INTSTS_ACTEINT);
bde18a2e
KI		 417 continue;
418 }
419
420 if (reg & INTSTS_IOIRQS) {
0ecdca26 421 out_be32((void __iomem *)intsts_port, INTSTS_IOIRQS);
bde18a2e
KI		 422 continue;
423 }
424 break;
425 }
426
4ae41ff8
KI		 427 dma_stat = __ide_dma_end(drive);
428 if (data_loss)
429 dma_stat |= 2; /* emulate DMA error (to retry command) */
430 return dma_stat;
bde18a2e
KI		 431}
432
06a9952b
AI		 433/* returns 1 if dma irq issued, 0 otherwise */
434static int scc_dma_test_irq(ide_drive_t *drive)
435{
4ae41ff8
KI		 436 ide_hwif_t *hwif = HWIF(drive);
437 u32 int_stat = in_be32((void __iomem *)hwif->dma_base + 0x014);
06a9952b 438
4ae41ff8
KI		 439 /* SCC errata A252,A308 workaround: Step4 */
440 if ((in_be32((void __iomem *)IDE_ALTSTATUS_REG) & ERR_STAT) &&
441 (int_stat & INTSTS_INTRQ))
06a9952b
AI		 442 return 1;
443
4ae41ff8
KI		 444 /* SCC errata A308 workaround: Step5 (polling IOIRQS) */
445 if (int_stat & INTSTS_IOIRQS)
06a9952b
AI		 446 return 1;
447
448 if (!drive->waiting_for_dma)
449 printk(KERN_WARNING "%s: (%s) called while not waiting\n",
450 drive->name, __FUNCTION__);
451 return 0;
452}
453
4ae41ff8
KI		 454static u8 scc_udma_filter(ide_drive_t *drive)
455{
456 ide_hwif_t *hwif = drive->hwif;
457 u8 mask = hwif->ultra_mask;
458
459 /* errata A308 workaround: limit non ide_disk drive to UDMA4 */
460 if ((drive->media != ide_disk) && (mask & 0xE0)) {
461 printk(KERN_INFO "%s: limit %s to UDMA4\n",
462 SCC_PATA_NAME, drive->name);
5f8b6c34 463 mask = ATA_UDMA4;
4ae41ff8
KI		 464 }
465
466 return mask;
467}
468
bde18a2e
KI		 469/**
470 * setup_mmio_scc - map CTRL/BMID region
471 * @dev: PCI device we are configuring
472 * @name: device name
473 *
474 */
475
476static int setup_mmio_scc (struct pci_dev *dev, const char *name)
477{
478 unsigned long ctl_base = pci_resource_start(dev, 0);
479 unsigned long dma_base = pci_resource_start(dev, 1);
480 unsigned long ctl_size = pci_resource_len(dev, 0);
481 unsigned long dma_size = pci_resource_len(dev, 1);
0bd8496b
AV		 482 void __iomem *ctl_addr;
483 void __iomem *dma_addr;
bde18a2e
KI		 484 int i;
485
486 for (i = 0; i < MAX_HWIFS; i++) {
487 if (scc_ports[i].ctl == 0)
488 break;
489 }
490 if (i >= MAX_HWIFS)
491 return -ENOMEM;
492
493 if (!request_mem_region(ctl_base, ctl_size, name)) {
494 printk(KERN_WARNING "%s: IDE controller MMIO ports not available.\n", SCC_PATA_NAME);
495 goto fail_0;
496 }
497
498 if (!request_mem_region(dma_base, dma_size, name)) {
499 printk(KERN_WARNING "%s: IDE controller MMIO ports not available.\n", SCC_PATA_NAME);
500 goto fail_1;
501 }
502
503 if ((ctl_addr = ioremap(ctl_base, ctl_size)) == NULL)
504 goto fail_2;
505
506 if ((dma_addr = ioremap(dma_base, dma_size)) == NULL)
507 goto fail_3;
508
509 pci_set_master(dev);
510 scc_ports[i].ctl = (unsigned long)ctl_addr;
511 scc_ports[i].dma = (unsigned long)dma_addr;
512 pci_set_drvdata(dev, (void *) &scc_ports[i]);
513
514 return 1;
515
516 fail_3:
517 iounmap(ctl_addr);
518 fail_2:
519 release_mem_region(dma_base, dma_size);
520 fail_1:
521 release_mem_region(ctl_base, ctl_size);
522 fail_0:
523 return -ENOMEM;
524}
525
526/**
527 * init_setup_scc - set up an SCC PATA Controller
528 * @dev: PCI device
039788e1 529 * @d: IDE port info
bde18a2e
KI		 530 *
531 * Perform the initial set up for this device.
532 */
533
039788e1 534static int __devinit init_setup_scc(struct pci_dev *dev,
85620436 535 const struct ide_port_info *d)
bde18a2e
KI		 536{
537 unsigned long ctl_base;
538 unsigned long dma_base;
539 unsigned long cckctrl_port;
540 unsigned long intmask_port;
541 unsigned long mode_port;
542 unsigned long ecmode_port;
543 unsigned long dma_status_port;
544 u32 reg = 0;
545 struct scc_ports *ports;
546 int rc;
547
548 rc = setup_mmio_scc(dev, d->name);
549 if (rc < 0) {
550 return rc;
551 }
552
553 ports = pci_get_drvdata(dev);
554 ctl_base = ports->ctl;
555 dma_base = ports->dma;
556 cckctrl_port = ctl_base + 0xff0;
557 intmask_port = dma_base + 0x010;
558 mode_port = ctl_base + 0x024;
559 ecmode_port = ctl_base + 0xf00;
560 dma_status_port = dma_base + 0x004;
561
562 /* controller initialization */
563 reg = 0;
564 out_be32((void*)cckctrl_port, reg);
565 reg |= CCKCTRL_ATACLKOEN;
566 out_be32((void*)cckctrl_port, reg);
567 reg |= CCKCTRL_LCLKEN | CCKCTRL_OCLKEN;
568 out_be32((void*)cckctrl_port, reg);
569 reg |= CCKCTRL_CRST;
570 out_be32((void*)cckctrl_port, reg);
571
572 for (;;) {
573 reg = in_be32((void*)cckctrl_port);
574 if (reg & CCKCTRL_CRST)
575 break;
576 udelay(5000);
577 }
578
579 reg |= CCKCTRL_ATARESET;
580 out_be32((void*)cckctrl_port, reg);
581
582 out_be32((void*)ecmode_port, ECMODE_VALUE);
583 out_be32((void*)mode_port, MODE_JCUSFEN);
584 out_be32((void*)intmask_port, INTMASK_MSK);
585
586 return ide_setup_pci_device(dev, d);
587}
588
589/**
590 * init_mmio_iops_scc - set up the iops for MMIO
591 * @hwif: interface to set up
592 *
593 */
594
595static void __devinit init_mmio_iops_scc(ide_hwif_t *hwif)
596{
36501650 597 struct pci_dev *dev = to_pci_dev(hwif->dev);
bde18a2e
KI		 598 struct scc_ports *ports = pci_get_drvdata(dev);
599 unsigned long dma_base = ports->dma;
600
601 ide_set_hwifdata(hwif, ports);
602
603 hwif->INB = scc_ide_inb;
604 hwif->INW = scc_ide_inw;
bde18a2e
KI		 605 hwif->INSW = scc_ide_insw;
606 hwif->INSL = scc_ide_insl;
607 hwif->OUTB = scc_ide_outb;
608 hwif->OUTBSYNC = scc_ide_outbsync;
609 hwif->OUTW = scc_ide_outw;
bde18a2e
KI		 610 hwif->OUTSW = scc_ide_outsw;
611 hwif->OUTSL = scc_ide_outsl;
612
613 hwif->io_ports[IDE_DATA_OFFSET] = dma_base + 0x20;
614 hwif->io_ports[IDE_ERROR_OFFSET] = dma_base + 0x24;
615 hwif->io_ports[IDE_NSECTOR_OFFSET] = dma_base + 0x28;
616 hwif->io_ports[IDE_SECTOR_OFFSET] = dma_base + 0x2c;
617 hwif->io_ports[IDE_LCYL_OFFSET] = dma_base + 0x30;
618 hwif->io_ports[IDE_HCYL_OFFSET] = dma_base + 0x34;
619 hwif->io_ports[IDE_SELECT_OFFSET] = dma_base + 0x38;
620 hwif->io_ports[IDE_STATUS_OFFSET] = dma_base + 0x3c;
621 hwif->io_ports[IDE_CONTROL_OFFSET] = dma_base + 0x40;
622
36501650 623 hwif->irq = dev->irq;
bde18a2e
KI		 624 hwif->dma_base = dma_base;
625 hwif->config_data = ports->ctl;
2ad1e558 626 hwif->mmio = 1;
bde18a2e
KI		 627}
628
629/**
630 * init_iops_scc - set up iops
631 * @hwif: interface to set up
632 *
633 * Do the basic setup for the SCC hardware interface
634 * and then do the MMIO setup.
635 */
636
637static void __devinit init_iops_scc(ide_hwif_t *hwif)
638{
36501650
BZ		 639 struct pci_dev *dev = to_pci_dev(hwif->dev);
640
bde18a2e
KI		 641 hwif->hwif_data = NULL;
642 if (pci_get_drvdata(dev) == NULL)
643 return;
644 init_mmio_iops_scc(hwif);
645}
646
647/**
648 * init_hwif_scc - set up hwif
649 * @hwif: interface to set up
650 *
651 * We do the basic set up of the interface structure. The SCC
652 * requires several custom handlers so we override the default
653 * ide DMA handlers appropriately.
654 */
655
656static void __devinit init_hwif_scc(ide_hwif_t *hwif)
657{
658 struct scc_ports *ports = ide_get_hwifdata(hwif);
659
660 ports->hwif_id = hwif->index;
661
662 hwif->dma_command = hwif->dma_base;
663 hwif->dma_status = hwif->dma_base + 0x04;
664 hwif->dma_prdtable = hwif->dma_base + 0x08;
665
0ecdca26
BZ		 666 /* PTERADD */
667 out_be32((void __iomem *)(hwif->dma_base + 0x018), hwif->dmatable_dma);
bde18a2e 668
0ecdca26 669 hwif->dma_setup = scc_dma_setup;
bde18a2e 670 hwif->ide_dma_end = scc_ide_dma_end;
26bcb879 671 hwif->set_pio_mode = scc_set_pio_mode;
88b2b32b 672 hwif->set_dma_mode = scc_set_dma_mode;
06a9952b 673 hwif->ide_dma_test_irq = scc_dma_test_irq;
4ae41ff8 674 hwif->udma_filter = scc_udma_filter;
bde18a2e 675
5f8b6c34
BZ		 676 if (in_be32((void __iomem *)(hwif->config_data + 0xff0)) & CCKCTRL_ATACLKOEN)
677 hwif->ultra_mask = ATA_UDMA6; /* 133MHz */
678 else
679 hwif->ultra_mask = ATA_UDMA5; /* 100MHz */
bde18a2e
KI		 680
681 /* we support 80c cable only. */
49521f97 682 hwif->cbl = ATA_CBL_PATA80;
bde18a2e
KI		 683}
684
685#define DECLARE_SCC_DEV(name_str) \
686 { \
687 .name = name_str, \
bde18a2e
KI		 688 .init_iops = init_iops_scc, \
689 .init_hwif = init_hwif_scc, \
7cab14a7
BZ		 690 .host_flags = IDE_HFLAG_SINGLE | \
691 IDE_HFLAG_BOOTABLE, \
4099d143 692 .pio_mask = ATA_PIO4, \
bde18a2e
KI		 693 }
694
85620436 695static const struct ide_port_info scc_chipsets[] __devinitdata = {
bde18a2e
KI		 696 /* 0 */ DECLARE_SCC_DEV("sccIDE"),
697};
698
699/**
700 * scc_init_one - pci layer discovery entry
701 * @dev: PCI device
702 * @id: ident table entry
703 *
704 * Called by the PCI code when it finds an SCC PATA controller.
705 * We then use the IDE PCI generic helper to do most of the work.
706 */
707
708static int __devinit scc_init_one(struct pci_dev *dev, const struct pci_device_id *id)
709{
039788e1 710 return init_setup_scc(dev, &scc_chipsets[id->driver_data]);
bde18a2e
KI		 711}
712
713/**
714 * scc_remove - pci layer remove entry
715 * @dev: PCI device
716 *
717 * Called by the PCI code when it removes an SCC PATA controller.
718 */
719
720static void __devexit scc_remove(struct pci_dev *dev)
721{
722 struct scc_ports *ports = pci_get_drvdata(dev);
723 ide_hwif_t *hwif = &ide_hwifs[ports->hwif_id];
724 unsigned long ctl_base = pci_resource_start(dev, 0);
725 unsigned long dma_base = pci_resource_start(dev, 1);
726 unsigned long ctl_size = pci_resource_len(dev, 0);
727 unsigned long dma_size = pci_resource_len(dev, 1);
728
729 if (hwif->dmatable_cpu) {
36501650
BZ		 730 pci_free_consistent(dev, PRD_ENTRIES * PRD_BYTES,
731 hwif->dmatable_cpu, hwif->dmatable_dma);
bde18a2e
KI		 732 hwif->dmatable_cpu = NULL;
733 }
734
735 ide_unregister(hwif->index);
736
737 hwif->chipset = ide_unknown;
738 iounmap((void*)ports->dma);
739 iounmap((void*)ports->ctl);
740 release_mem_region(dma_base, dma_size);
741 release_mem_region(ctl_base, ctl_size);
742 memset(ports, 0, sizeof(*ports));
743}
744
9cbcc5e3
BZ		 745static const struct pci_device_id scc_pci_tbl[] = {
746 { PCI_VDEVICE(TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_SCC_ATA), 0 },
bde18a2e
KI		 747 { 0, },
748};
749MODULE_DEVICE_TABLE(pci, scc_pci_tbl);
750
751static struct pci_driver driver = {
752 .name = "SCC IDE",
753 .id_table = scc_pci_tbl,
754 .probe = scc_init_one,
755 .remove = scc_remove,
756};
757
758static int scc_ide_init(void)
759{
760 return ide_pci_register_driver(&driver);
761}
762
763module_init(scc_ide_init);
764/* -- No exit code?
765static void scc_ide_exit(void)
766{
767 ide_pci_unregister_driver(&driver);
768}
769module_exit(scc_ide_exit);
770 */
771
772
773MODULE_DESCRIPTION("PCI driver module for Toshiba SCC IDE");
774MODULE_LICENSE("GPL");
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