[net-next-2.6.git] / drivers / ide / pci / sc1200.c

/*
 * linux/drivers/ide/pci/sc1200.c		Version 0.97	Aug 3 2007
 *
 * Copyright (C) 2000-2002		Mark Lord <mlord@pobox.com>
 * Copyright (C)      2007		Bartlomiej Zolnierkiewicz
 *
 * May be copied or modified under the terms of the GNU General Public License
 *
 * Development of this chipset driver was funded
 * by the nice folks at National Semiconductor.
 *
 * Documentation:
 *	Available from National Semiconductor
 */

#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/timer.h>
#include <linux/mm.h>
#include <linux/ioport.h>
#include <linux/blkdev.h>
#include <linux/hdreg.h>
#include <linux/interrupt.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/ide.h>
#include <linux/pm.h>
#include <asm/io.h>
#include <asm/irq.h>

#define SC1200_REV_A	0x00
#define SC1200_REV_B1	0x01
#define SC1200_REV_B3	0x02
#define SC1200_REV_C1	0x03
#define SC1200_REV_D1	0x04

#define PCI_CLK_33	0x00
#define PCI_CLK_48	0x01
#define PCI_CLK_66	0x02
#define PCI_CLK_33A	0x03

static unsigned short sc1200_get_pci_clock (void)
{
	unsigned char chip_id, silicon_revision;
	unsigned int pci_clock;
	/*
	 * Check the silicon revision, as not all versions of the chip
	 * have the register with the fast PCI bus timings.
	 */
	chip_id = inb (0x903c);
	silicon_revision = inb (0x903d);

	// Read the fast pci clock frequency
	if (chip_id == 0x04 && silicon_revision < SC1200_REV_B1) {
		pci_clock = PCI_CLK_33;
	} else {
		// check clock generator configuration (cfcc)
		// the clock is in bits 8 and 9 of this word

		pci_clock = inw (0x901e);
		pci_clock >>= 8;
		pci_clock &= 0x03;
		if (pci_clock == PCI_CLK_33A)
			pci_clock = PCI_CLK_33;
	}
	return pci_clock;
}

/*
 * Here are the standard PIO mode 0-4 timings for each "format".
 * Format-0 uses fast data reg timings, with slower command reg timings.
 * Format-1 uses fast timings for all registers, but won't work with all drives.
 */
static const unsigned int sc1200_pio_timings[4][5] =
	{{0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010},	// format0  33Mhz
	 {0xd1329172, 0x71212171, 0x30200080, 0x20102010, 0x00100010},	// format1, 33Mhz
	 {0xfaa3f4f3, 0xc23232b2, 0x513101c1, 0x31213121, 0x10211021},	// format1, 48Mhz
	 {0xfff4fff4, 0xf35353d3, 0x814102f1, 0x42314231, 0x11311131}};	// format1, 66Mhz

/*
 * After chip reset, the PIO timings are set to 0x00009172, which is not valid.
 */
//#define SC1200_BAD_PIO(timings) (((timings)&~0x80000000)==0x00009172)

static void sc1200_tunepio(ide_drive_t *drive, u8 pio)
{
	ide_hwif_t *hwif = drive->hwif;
	struct pci_dev *pdev = hwif->pci_dev;
	unsigned int basereg = hwif->channel ? 0x50 : 0x40, format = 0;

	pci_read_config_dword(pdev, basereg + 4, &format);
	format = (format >> 31) & 1;
	if (format)
		format += sc1200_get_pci_clock();
	pci_write_config_dword(pdev, basereg + ((drive->dn & 1) << 3),
			       sc1200_pio_timings[format][pio]);
}

/*
 *	The SC1200 specifies that two drives sharing a cable cannot mix
 *	UDMA/MDMA.  It has to be one or the other, for the pair, though
 *	different timings can still be chosen for each drive.  We could
 *	set the appropriate timing bits on the fly, but that might be
 *	a bit confusing.  So, for now we statically handle this requirement
 *	by looking at our mate drive to see what it is capable of, before
 *	choosing a mode for our own drive.
 */
static u8 sc1200_udma_filter(ide_drive_t *drive)
{
	ide_hwif_t *hwif = drive->hwif;
	ide_drive_t *mate = &hwif->drives[(drive->dn & 1) ^ 1];
	struct hd_driveid *mateid = mate->id;
	u8 mask = hwif->ultra_mask;

	if (mate->present == 0)
		goto out;

	if ((mateid->capability & 1) && __ide_dma_bad_drive(mate) == 0) {
		if ((mateid->field_valid & 4) && (mateid->dma_ultra & 7))
			goto out;
		if ((mateid->field_valid & 2) && (mateid->dma_mword & 7))
			mask = 0;
	}
out:
	return mask;
}

static void sc1200_set_dma_mode(ide_drive_t *drive, const u8 mode)
{
	ide_hwif_t		*hwif = HWIF(drive);
	int			unit = drive->select.b.unit;
	unsigned int		reg, timings;
	unsigned short		pci_clock;
	unsigned int		basereg = hwif->channel ? 0x50 : 0x40;

	pci_clock = sc1200_get_pci_clock();

	/*
	 * Note that each DMA mode has several timings associated with it.
	 * The correct timing depends on the fast PCI clock freq.
	 */
	timings = 0;
	switch (mode) {
		case XFER_UDMA_0:
			switch (pci_clock) {
				case PCI_CLK_33:	timings = 0x00921250;	break;
				case PCI_CLK_48:	timings = 0x00932470;	break;
				case PCI_CLK_66:	timings = 0x009436a1;	break;
			}
			break;
		case XFER_UDMA_1:
			switch (pci_clock) {
				case PCI_CLK_33:	timings = 0x00911140;	break;
				case PCI_CLK_48:	timings = 0x00922260;	break;
				case PCI_CLK_66:	timings = 0x00933481;	break;
			}
			break;
		case XFER_UDMA_2:
			switch (pci_clock) {
				case PCI_CLK_33:	timings = 0x00911030;	break;
				case PCI_CLK_48:	timings = 0x00922140;	break;
				case PCI_CLK_66:	timings = 0x00923261;	break;
			}
			break;
		case XFER_MW_DMA_0:
			switch (pci_clock) {
				case PCI_CLK_33:	timings = 0x00077771;	break;
				case PCI_CLK_48:	timings = 0x000bbbb2;	break;
				case PCI_CLK_66:	timings = 0x000ffff3;	break;
			}
			break;
		case XFER_MW_DMA_1:
			switch (pci_clock) {
				case PCI_CLK_33:	timings = 0x00012121;	break;
				case PCI_CLK_48:	timings = 0x00024241;	break;
				case PCI_CLK_66:	timings = 0x00035352;	break;
			}
			break;
		case XFER_MW_DMA_2:
			switch (pci_clock) {
				case PCI_CLK_33:	timings = 0x00002020;	break;
				case PCI_CLK_48:	timings = 0x00013131;	break;
				case PCI_CLK_66:	timings = 0x00015151;	break;
			}
			break;
		default:
			BUG();
			break;
	}

	if (unit == 0) {			/* are we configuring drive0? */
		pci_read_config_dword(hwif->pci_dev, basereg+4, &reg);
		timings |= reg & 0x80000000;	/* preserve PIO format bit */
		pci_write_config_dword(hwif->pci_dev, basereg+4, timings);
	} else {
		pci_write_config_dword(hwif->pci_dev, basereg+12, timings);
	}
}

/*  Replacement for the standard ide_dma_end action in
 *  dma_proc.
 *
 *  returns 1 on error, 0 otherwise
 */
static int sc1200_ide_dma_end (ide_drive_t *drive)
{
	ide_hwif_t *hwif = HWIF(drive);
	unsigned long dma_base = hwif->dma_base;
	byte dma_stat;

	dma_stat = inb(dma_base+2);		/* get DMA status */

	if (!(dma_stat & 4))
		printk(" ide_dma_end dma_stat=%0x err=%x newerr=%x\n",
		  dma_stat, ((dma_stat&7)!=4), ((dma_stat&2)==2));

	outb(dma_stat|0x1b, dma_base+2);	/* clear the INTR & ERROR bits */
	outb(inb(dma_base)&~1, dma_base);	/* !! DO THIS HERE !! stop DMA */

	drive->waiting_for_dma = 0;
	ide_destroy_dmatable(drive);		/* purge DMA mappings */

	return (dma_stat & 7) != 4;		/* verify good DMA status */
}

/*
 * sc1200_set_pio_mode() handles setting of PIO modes
 * for both the chipset and drive.
 *
 * All existing BIOSs for this chipset guarantee that all drives
 * will have valid default PIO timings set up before we get here.
 */

static void sc1200_set_pio_mode(ide_drive_t *drive, const u8 pio)
{
	ide_hwif_t	*hwif = HWIF(drive);
	int		mode = -1;

	/*
	 * bad abuse of ->set_pio_mode interface
	 */
	switch (pio) {
		case 200: mode = XFER_UDMA_0;	break;
		case 201: mode = XFER_UDMA_1;	break;
		case 202: mode = XFER_UDMA_2;	break;
		case 100: mode = XFER_MW_DMA_0;	break;
		case 101: mode = XFER_MW_DMA_1;	break;
		case 102: mode = XFER_MW_DMA_2;	break;
	}
	if (mode != -1) {
		printk("SC1200: %s: changing (U)DMA mode\n", drive->name);
		hwif->dma_off_quietly(drive);
		if (ide_set_dma_mode(drive, mode) == 0)
			hwif->dma_host_on(drive);
		return;
	}

	sc1200_tunepio(drive, pio);
}

#ifdef CONFIG_PM
static ide_hwif_t *lookup_pci_dev (ide_hwif_t *prev, struct pci_dev *dev)
{
	int	h;

	for (h = 0; h < MAX_HWIFS; h++) {
		ide_hwif_t *hwif = &ide_hwifs[h];
		if (prev) {
			if (hwif == prev)
				prev = NULL;	// found previous, now look for next match
		} else {
			if (hwif && hwif->pci_dev == dev)
				return hwif;	// found next match
		}
	}
	return NULL;	// not found
}

typedef struct sc1200_saved_state_s {
	__u32		regs[4];
} sc1200_saved_state_t;


static int sc1200_suspend (struct pci_dev *dev, pm_message_t state)
{
	ide_hwif_t		*hwif = NULL;

	printk("SC1200: suspend(%u)\n", state.event);

	if (state.event == PM_EVENT_ON) {
		// we only save state when going from full power to less

		//
		// Loop over all interfaces that are part of this PCI device:
		//
		while ((hwif = lookup_pci_dev(hwif, dev)) != NULL) {
			sc1200_saved_state_t	*ss;
			unsigned int		basereg, r;
			//
			// allocate a permanent save area, if not already allocated
			//
			ss = (sc1200_saved_state_t *)hwif->config_data;
			if (ss == NULL) {
				ss = kmalloc(sizeof(sc1200_saved_state_t), GFP_KERNEL);
				if (ss == NULL)
					return -ENOMEM;
				hwif->config_data = (unsigned long)ss;
			}
			ss = (sc1200_saved_state_t *)hwif->config_data;
			//
			// Save timing registers:  this may be unnecessary if 
			// BIOS also does it
			//
			basereg = hwif->channel ? 0x50 : 0x40;
			for (r = 0; r < 4; ++r) {
				pci_read_config_dword (hwif->pci_dev, basereg + (r<<2), &ss->regs[r]);
			}
		}
	}

	/* You don't need to iterate over disks -- sysfs should have done that for you already */ 

	pci_disable_device(dev);
	pci_set_power_state(dev, pci_choose_state(dev, state));
	dev->current_state = state.event;
	return 0;
}

static int sc1200_resume (struct pci_dev *dev)
{
	ide_hwif_t	*hwif = NULL;

	pci_set_power_state(dev, PCI_D0);	// bring chip back from sleep state
	dev->current_state = PM_EVENT_ON;
	pci_enable_device(dev);
	//
	// loop over all interfaces that are part of this pci device:
	//
	while ((hwif = lookup_pci_dev(hwif, dev)) != NULL) {
		unsigned int		basereg, r;
		sc1200_saved_state_t	*ss = (sc1200_saved_state_t *)hwif->config_data;

		//
		// Restore timing registers:  this may be unnecessary if BIOS also does it
		//
		basereg = hwif->channel ? 0x50 : 0x40;
		if (ss != NULL) {
			for (r = 0; r < 4; ++r) {
				pci_write_config_dword(hwif->pci_dev, basereg + (r<<2), ss->regs[r]);
			}
		}
	}
	return 0;
}
#endif

/*
 * This gets invoked by the IDE driver once for each channel,
 * and performs channel-specific pre-initialization before drive probing.
 */
static void __devinit init_hwif_sc1200 (ide_hwif_t *hwif)
{
	hwif->set_pio_mode = &sc1200_set_pio_mode;
	hwif->set_dma_mode = &sc1200_set_dma_mode;

	if (hwif->dma_base == 0)
		return;

	hwif->udma_filter = sc1200_udma_filter;
	hwif->ide_dma_end   = &sc1200_ide_dma_end;
}

static struct ide_port_info sc1200_chipset __devinitdata = {
	.name		= "SC1200",
	.init_hwif	= init_hwif_sc1200,
	.host_flags	= IDE_HFLAG_SERIALIZE |
			  IDE_HFLAG_POST_SET_MODE |
			  IDE_HFLAG_ABUSE_DMA_MODES |
			  IDE_HFLAG_BOOTABLE,
	.pio_mask	= ATA_PIO4,
	.mwdma_mask	= ATA_MWDMA2,
	.udma_mask	= ATA_UDMA2,
};

static int __devinit sc1200_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	return ide_setup_pci_device(dev, &sc1200_chipset);
}

static const struct pci_device_id sc1200_pci_tbl[] = {
	{ PCI_VDEVICE(NS, PCI_DEVICE_ID_NS_SCx200_IDE), 0},
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, sc1200_pci_tbl);

static struct pci_driver driver = {
	.name		= "SC1200_IDE",
	.id_table	= sc1200_pci_tbl,
	.probe		= sc1200_init_one,
#ifdef CONFIG_PM
	.suspend	= sc1200_suspend,
	.resume		= sc1200_resume,
#endif
};

static int __init sc1200_ide_init(void)
{
	return ide_pci_register_driver(&driver);
}

module_init(sc1200_ide_init);

MODULE_AUTHOR("Mark Lord");
MODULE_DESCRIPTION("PCI driver module for NS SC1200 IDE");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4	1	/*
3f019eea	2	* linux/drivers/ide/pci/sc1200.c Version 0.97 Aug 3 2007
1da177e4 LT	3	*
1da177e4 LT	4	* Copyright (C) 2000-2002 Mark Lord <mlord@pobox.com>
5fd216bb BZ	5	* Copyright (C) 2007 Bartlomiej Zolnierkiewicz
5fd216bb BZ	6	*
1da177e4 LT	7	* May be copied or modified under the terms of the GNU General Public License
	8	*
	9	* Development of this chipset driver was funded
	10	* by the nice folks at National Semiconductor.
	11	*
	12	* Documentation:
	13	* Available from National Semiconductor
	14	*/
	15
1da177e4 LT	16	#include <linux/module.h>
	17	#include <linux/types.h>
	18	#include <linux/kernel.h>
	19	#include <linux/delay.h>
	20	#include <linux/timer.h>
	21	#include <linux/mm.h>
	22	#include <linux/ioport.h>
	23	#include <linux/blkdev.h>
	24	#include <linux/hdreg.h>
	25	#include <linux/interrupt.h>
	26	#include <linux/pci.h>
	27	#include <linux/init.h>
	28	#include <linux/ide.h>
	29	#include <linux/pm.h>
	30	#include <asm/io.h>
	31	#include <asm/irq.h>
	32
	33	#define SC1200_REV_A 0x00
	34	#define SC1200_REV_B1 0x01
	35	#define SC1200_REV_B3 0x02
	36	#define SC1200_REV_C1 0x03
	37	#define SC1200_REV_D1 0x04
	38
	39	#define PCI_CLK_33 0x00
	40	#define PCI_CLK_48 0x01
	41	#define PCI_CLK_66 0x02
	42	#define PCI_CLK_33A 0x03
	43
	44	static unsigned short sc1200_get_pci_clock (void)
	45	{
	46	unsigned char chip_id, silicon_revision;
	47	unsigned int pci_clock;
	48	/*
	49	* Check the silicon revision, as not all versions of the chip
	50	* have the register with the fast PCI bus timings.
	51	*/
	52	chip_id = inb (0x903c);
	53	silicon_revision = inb (0x903d);
	54
	55	// Read the fast pci clock frequency
	56	if (chip_id == 0x04 && silicon_revision < SC1200_REV_B1) {
	57	pci_clock = PCI_CLK_33;
	58	} else {
	59	// check clock generator configuration (cfcc)
	60	// the clock is in bits 8 and 9 of this word
	61
	62	pci_clock = inw (0x901e);
	63	pci_clock >>= 8;
	64	pci_clock &= 0x03;
	65	if (pci_clock == PCI_CLK_33A)
	66	pci_clock = PCI_CLK_33;
	67	}
	68	return pci_clock;
	69	}
	70
1da177e4 LT	71	/*
	72	* Here are the standard PIO mode 0-4 timings for each "format".
	73	* Format-0 uses fast data reg timings, with slower command reg timings.
	74	* Format-1 uses fast timings for all registers, but won't work with all drives.
	75	*/
	76	static const unsigned int sc1200_pio_timings[4][5] =
	77	{{0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010}, // format0 33Mhz
	78	{0xd1329172, 0x71212171, 0x30200080, 0x20102010, 0x00100010}, // format1, 33Mhz
	79	{0xfaa3f4f3, 0xc23232b2, 0x513101c1, 0x31213121, 0x10211021}, // format1, 48Mhz
	80	{0xfff4fff4, 0xf35353d3, 0x814102f1, 0x42314231, 0x11311131}}; // format1, 66Mhz
	81
	82	/*
	83	* After chip reset, the PIO timings are set to 0x00009172, which is not valid.
	84	*/
	85	//#define SC1200_BAD_PIO(timings) (((timings)&~0x80000000)==0x00009172)
	86
3c3f5d2c BZ	87	static void sc1200_tunepio(ide_drive_t *drive, u8 pio)
	88	{
	89	ide_hwif_t *hwif = drive->hwif;
	90	struct pci_dev *pdev = hwif->pci_dev;
	91	unsigned int basereg = hwif->channel ? 0x50 : 0x40, format = 0;
	92
	93	pci_read_config_dword(pdev, basereg + 4, &format);
	94	format = (format >> 31) & 1;
	95	if (format)
	96	format += sc1200_get_pci_clock();
	97	pci_write_config_dword(pdev, basereg + ((drive->dn & 1) << 3),
	98	sc1200_pio_timings[format][pio]);
	99	}
	100
5fd216bb BZ	101	/*
	102	* The SC1200 specifies that two drives sharing a cable cannot mix
	103	* UDMA/MDMA. It has to be one or the other, for the pair, though
	104	* different timings can still be chosen for each drive. We could
	105	* set the appropriate timing bits on the fly, but that might be
	106	* a bit confusing. So, for now we statically handle this requirement
	107	* by looking at our mate drive to see what it is capable of, before
	108	* choosing a mode for our own drive.
	109	*/
	110	static u8 sc1200_udma_filter(ide_drive_t *drive)
1da177e4	111	{
5fd216bb BZ	112	ide_hwif_t *hwif = drive->hwif;
	113	ide_drive_t *mate = &hwif->drives[(drive->dn & 1) ^ 1];
	114	struct hd_driveid *mateid = mate->id;
	115	u8 mask = hwif->ultra_mask;
	116
	117	if (mate->present == 0)
	118	goto out;
	119
	120	if ((mateid->capability & 1) && __ide_dma_bad_drive(mate) == 0) {
	121	if ((mateid->field_valid & 4) && (mateid->dma_ultra & 7))
	122	goto out;
	123	if ((mateid->field_valid & 2) && (mateid->dma_mword & 7))
	124	mask = 0;
1da177e4	125	}
5fd216bb BZ	126	out:
5fd216bb BZ	127	return mask;
1da177e4 LT	128	}
1da177e4 LT	129
88b2b32b	130	static void sc1200_set_dma_mode(ide_drive_t *drive, const u8 mode)
1da177e4 LT	131	{
	132	ide_hwif_t *hwif = HWIF(drive);
	133	int unit = drive->select.b.unit;
	134	unsigned int reg, timings;
	135	unsigned short pci_clock;
	136	unsigned int basereg = hwif->channel ? 0x50 : 0x40;
	137
1da177e4 LT	138	pci_clock = sc1200_get_pci_clock();
	139
	140	/*
1da177e4 LT	141	* Note that each DMA mode has several timings associated with it.
	142	* The correct timing depends on the fast PCI clock freq.
	143	*/
	144	timings = 0;
	145	switch (mode) {
	146	case XFER_UDMA_0:
	147	switch (pci_clock) {
	148	case PCI_CLK_33: timings = 0x00921250; break;
	149	case PCI_CLK_48: timings = 0x00932470; break;
	150	case PCI_CLK_66: timings = 0x009436a1; break;
	151	}
	152	break;
	153	case XFER_UDMA_1:
	154	switch (pci_clock) {
	155	case PCI_CLK_33: timings = 0x00911140; break;
	156	case PCI_CLK_48: timings = 0x00922260; break;
	157	case PCI_CLK_66: timings = 0x00933481; break;
	158	}
	159	break;
	160	case XFER_UDMA_2:
	161	switch (pci_clock) {
	162	case PCI_CLK_33: timings = 0x00911030; break;
	163	case PCI_CLK_48: timings = 0x00922140; break;
	164	case PCI_CLK_66: timings = 0x00923261; break;
	165	}
	166	break;
	167	case XFER_MW_DMA_0:
	168	switch (pci_clock) {
	169	case PCI_CLK_33: timings = 0x00077771; break;
	170	case PCI_CLK_48: timings = 0x000bbbb2; break;
	171	case PCI_CLK_66: timings = 0x000ffff3; break;
	172	}
	173	break;
	174	case XFER_MW_DMA_1:
	175	switch (pci_clock) {
	176	case PCI_CLK_33: timings = 0x00012121; break;
	177	case PCI_CLK_48: timings = 0x00024241; break;
	178	case PCI_CLK_66: timings = 0x00035352; break;
	179	}
	180	break;
	181	case XFER_MW_DMA_2:
	182	switch (pci_clock) {
	183	case PCI_CLK_33: timings = 0x00002020; break;
	184	case PCI_CLK_48: timings = 0x00013131; break;
	185	case PCI_CLK_66: timings = 0x00015151; break;
	186	}
	187	break;
3c3f5d2c BZ	188	default:
	189	BUG();
	190	break;
1da177e4 LT	191	}
	192
	193	if (unit == 0) { /* are we configuring drive0? */
	194	pci_read_config_dword(hwif->pci_dev, basereg+4, &reg);
	195	timings \|= reg & 0x80000000; /* preserve PIO format bit */
	196	pci_write_config_dword(hwif->pci_dev, basereg+4, timings);
	197	} else {
	198	pci_write_config_dword(hwif->pci_dev, basereg+12, timings);
	199	}
1da177e4 LT	200	}
1da177e4 LT	201
1da177e4 LT	202	/* Replacement for the standard ide_dma_end action in
	203	* dma_proc.
	204	*
	205	* returns 1 on error, 0 otherwise
	206	*/
	207	static int sc1200_ide_dma_end (ide_drive_t *drive)
	208	{
	209	ide_hwif_t *hwif = HWIF(drive);
	210	unsigned long dma_base = hwif->dma_base;
	211	byte dma_stat;
	212
	213	dma_stat = inb(dma_base+2); /* get DMA status */
	214
	215	if (!(dma_stat & 4))
	216	printk(" ide_dma_end dma_stat=%0x err=%x newerr=%x\n",
	217	dma_stat, ((dma_stat&7)!=4), ((dma_stat&2)==2));
	218
	219	outb(dma_stat\|0x1b, dma_base+2); /* clear the INTR & ERROR bits */
	220	outb(inb(dma_base)&~1, dma_base); /* !! DO THIS HERE !! stop DMA */
	221
	222	drive->waiting_for_dma = 0;
	223	ide_destroy_dmatable(drive); /* purge DMA mappings */
	224
	225	return (dma_stat & 7) != 4; /* verify good DMA status */
	226	}
	227
	228	/*
26bcb879	229	* sc1200_set_pio_mode() handles setting of PIO modes
1da177e4 LT	230	* for both the chipset and drive.
	231	*
	232	* All existing BIOSs for this chipset guarantee that all drives
	233	* will have valid default PIO timings set up before we get here.
	234	*/
26bcb879 BZ	235
26bcb879 BZ	236	static void sc1200_set_pio_mode(ide_drive_t *drive, const u8 pio)
1da177e4 LT	237	{
1da177e4 LT	238	ide_hwif_t *hwif = HWIF(drive);
1da177e4 LT	239	int mode = -1;
1da177e4 LT	240
a01ba401	241	/*
26bcb879	242	* bad abuse of ->set_pio_mode interface
a01ba401	243	*/
1da177e4 LT	244	switch (pio) {
	245	case 200: mode = XFER_UDMA_0; break;
	246	case 201: mode = XFER_UDMA_1; break;
	247	case 202: mode = XFER_UDMA_2; break;
	248	case 100: mode = XFER_MW_DMA_0; break;
	249	case 101: mode = XFER_MW_DMA_1; break;
	250	case 102: mode = XFER_MW_DMA_2; break;
	251	}
	252	if (mode != -1) {
	253	printk("SC1200: %s: changing (U)DMA mode\n", drive->name);
a01ba401	254	hwif->dma_off_quietly(drive);
88b2b32b	255	if (ide_set_dma_mode(drive, mode) == 0)
a01ba401	256	hwif->dma_host_on(drive);
1da177e4 LT	257	return;
	258	}
	259
88b2b32b	260	sc1200_tunepio(drive, pio);
1da177e4 LT	261	}
1da177e4 LT	262
b86cc29d	263	#ifdef CONFIG_PM
1da177e4 LT	264	static ide_hwif_t lookup_pci_dev (ide_hwif_t prev, struct pci_dev *dev)
	265	{
	266	int h;
	267
	268	for (h = 0; h < MAX_HWIFS; h++) {
	269	ide_hwif_t *hwif = &ide_hwifs[h];
	270	if (prev) {
	271	if (hwif == prev)
	272	prev = NULL; // found previous, now look for next match
	273	} else {
	274	if (hwif && hwif->pci_dev == dev)
	275	return hwif; // found next match
	276	}
	277	}
	278	return NULL; // not found
	279	}
	280
	281	typedef struct sc1200_saved_state_s {
	282	__u32 regs[4];
	283	} sc1200_saved_state_t;
	284
	285
3bfffd97	286	static int sc1200_suspend (struct pci_dev *dev, pm_message_t state)
1da177e4 LT	287	{
	288	ide_hwif_t *hwif = NULL;
	289
ca078bae	290	printk("SC1200: suspend(%u)\n", state.event);
1da177e4	291
ca078bae	292	if (state.event == PM_EVENT_ON) {
1da177e4 LT	293	// we only save state when going from full power to less
	294
	295	//
	296	// Loop over all interfaces that are part of this PCI device:
	297	//
	298	while ((hwif = lookup_pci_dev(hwif, dev)) != NULL) {
	299	sc1200_saved_state_t *ss;
	300	unsigned int basereg, r;
	301	//
	302	// allocate a permanent save area, if not already allocated
	303	//
	304	ss = (sc1200_saved_state_t *)hwif->config_data;
	305	if (ss == NULL) {
	306	ss = kmalloc(sizeof(sc1200_saved_state_t), GFP_KERNEL);
	307	if (ss == NULL)
	308	return -ENOMEM;
	309	hwif->config_data = (unsigned long)ss;
	310	}
	311	ss = (sc1200_saved_state_t *)hwif->config_data;
	312	//
	313	// Save timing registers: this may be unnecessary if
	314	// BIOS also does it
	315	//
	316	basereg = hwif->channel ? 0x50 : 0x40;
	317	for (r = 0; r < 4; ++r) {
	318	pci_read_config_dword (hwif->pci_dev, basereg + (r<<2), &ss->regs[r]);
	319	}
	320	}
	321	}
	322
	323	/* You don't need to iterate over disks -- sysfs should have done that for you already */
	324
	325	pci_disable_device(dev);
ca078bae PM	326	pci_set_power_state(dev, pci_choose_state(dev, state));
ca078bae PM	327	dev->current_state = state.event;
1da177e4 LT	328	return 0;
	329	}
	330
	331	static int sc1200_resume (struct pci_dev *dev)
	332	{
	333	ide_hwif_t *hwif = NULL;
	334
ca078bae PM	335	pci_set_power_state(dev, PCI_D0); // bring chip back from sleep state
ca078bae PM	336	dev->current_state = PM_EVENT_ON;
1da177e4 LT	337	pci_enable_device(dev);
	338	//
	339	// loop over all interfaces that are part of this pci device:
	340	//
	341	while ((hwif = lookup_pci_dev(hwif, dev)) != NULL) {
31c4df44	342	unsigned int basereg, r;
1da177e4	343	sc1200_saved_state_t ss = (sc1200_saved_state_t )hwif->config_data;
1da177e4 LT	344
	345	//
	346	// Restore timing registers: this may be unnecessary if BIOS also does it
	347	//
	348	basereg = hwif->channel ? 0x50 : 0x40;
	349	if (ss != NULL) {
	350	for (r = 0; r < 4; ++r) {
	351	pci_write_config_dword(hwif->pci_dev, basereg + (r<<2), ss->regs[r]);
	352	}
	353	}
1da177e4 LT	354	}
	355	return 0;
	356	}
b86cc29d	357	#endif
1da177e4 LT	358
	359	/*
	360	* This gets invoked by the IDE driver once for each channel,
	361	* and performs channel-specific pre-initialization before drive probing.
	362	*/
6a6e1b1c	363	static void __devinit init_hwif_sc1200 (ide_hwif_t *hwif)
1da177e4	364	{
88ae4d8c BZ	365	hwif->set_pio_mode = &sc1200_set_pio_mode;
	366	hwif->set_dma_mode = &sc1200_set_dma_mode;
	367
	368	if (hwif->dma_base == 0)
	369	return;
	370
	371	hwif->udma_filter = sc1200_udma_filter;
88ae4d8c	372	hwif->ide_dma_end = &sc1200_ide_dma_end;
1da177e4 LT	373	}
1da177e4 LT	374
039788e1	375	static struct ide_port_info sc1200_chipset __devinitdata = {
1da177e4 LT	376	.name = "SC1200",
1da177e4 LT	377	.init_hwif = init_hwif_sc1200,
1c51361a BZ	378	.host_flags = IDE_HFLAG_SERIALIZE \|
	379	IDE_HFLAG_POST_SET_MODE \|
	380	IDE_HFLAG_ABUSE_DMA_MODES \|
7cab14a7	381	IDE_HFLAG_BOOTABLE,
4099d143	382	.pio_mask = ATA_PIO4,
5f8b6c34 BZ	383	.mwdma_mask = ATA_MWDMA2,
5f8b6c34 BZ	384	.udma_mask = ATA_UDMA2,
1da177e4 LT	385	};
	386
	387	static int __devinit sc1200_init_one(struct pci_dev dev, const struct pci_device_id id)
	388	{
	389	return ide_setup_pci_device(dev, &sc1200_chipset);
	390	}
	391
9cbcc5e3 BZ	392	static const struct pci_device_id sc1200_pci_tbl[] = {
9cbcc5e3 BZ	393	{ PCI_VDEVICE(NS, PCI_DEVICE_ID_NS_SCx200_IDE), 0},
1da177e4 LT	394	{ 0, },
	395	};
	396	MODULE_DEVICE_TABLE(pci, sc1200_pci_tbl);
	397
	398	static struct pci_driver driver = {
	399	.name = "SC1200_IDE",
	400	.id_table = sc1200_pci_tbl,
	401	.probe = sc1200_init_one,
b86cc29d	402	#ifdef CONFIG_PM
1da177e4 LT	403	.suspend = sc1200_suspend,
1da177e4 LT	404	.resume = sc1200_resume,
b86cc29d	405	#endif
1da177e4 LT	406	};
1da177e4 LT	407
82ab1eec	408	static int __init sc1200_ide_init(void)
1da177e4 LT	409	{
	410	return ide_pci_register_driver(&driver);
	411	}
	412
	413	module_init(sc1200_ide_init);
	414
	415	MODULE_AUTHOR("Mark Lord");
	416	MODULE_DESCRIPTION("PCI driver module for NS SC1200 IDE");
	417	MODULE_LICENSE("GPL");