[net-next-2.6.git] / drivers / ide / pci / pdc202xx_new.c

/*
 *  Promise TX2/TX4/TX2000/133 IDE driver
 *
 *  This program is free software; you can redistribute it and/or
 *  modify it under the terms of the GNU General Public License
 *  as published by the Free Software Foundation; either version
 *  2 of the License, or (at your option) any later version.
 *
 *  Split from:
 *  linux/drivers/ide/pdc202xx.c	Version 0.35	Mar. 30, 2002
 *  Copyright (C) 1998-2002		Andre Hedrick <andre@linux-ide.org>
 *  Copyright (C) 2005-2007		MontaVista Software, Inc.
 *  Portions Copyright (C) 1999 Promise Technology, Inc.
 *  Author: Frank Tiernan (frankt@promise.com)
 *  Released under terms of General Public License
 */

#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/hdreg.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/ide.h>

#include <asm/io.h>

#ifdef CONFIG_PPC_PMAC
#include <asm/prom.h>
#include <asm/pci-bridge.h>
#endif

#undef DEBUG

#ifdef DEBUG
#define DBG(fmt, args...) printk("%s: " fmt, __func__, ## args)
#else
#define DBG(fmt, args...)
#endif

static const char *pdc_quirk_drives[] = {
	"QUANTUM FIREBALLlct08 08",
	"QUANTUM FIREBALLP KA6.4",
	"QUANTUM FIREBALLP KA9.1",
	"QUANTUM FIREBALLP LM20.4",
	"QUANTUM FIREBALLP KX13.6",
	"QUANTUM FIREBALLP KX20.5",
	"QUANTUM FIREBALLP KX27.3",
	"QUANTUM FIREBALLP LM20.5",
	NULL
};

static u8 max_dma_rate(struct pci_dev *pdev)
{
	u8 mode;

	switch(pdev->device) {
		case PCI_DEVICE_ID_PROMISE_20277:
		case PCI_DEVICE_ID_PROMISE_20276:
		case PCI_DEVICE_ID_PROMISE_20275:
		case PCI_DEVICE_ID_PROMISE_20271:
		case PCI_DEVICE_ID_PROMISE_20269:
			mode = 4;
			break;
		case PCI_DEVICE_ID_PROMISE_20270:
		case PCI_DEVICE_ID_PROMISE_20268:
			mode = 3;
			break;
		default:
			return 0;
	}

	return mode;
}

/**
 * get_indexed_reg - Get indexed register
 * @hwif: for the port address
 * @index: index of the indexed register
 */
static u8 get_indexed_reg(ide_hwif_t *hwif, u8 index)
{
	u8 value;

	outb(index, hwif->dma_base + 1);
	value = inb(hwif->dma_base + 3);

	DBG("index[%02X] value[%02X]\n", index, value);
	return value;
}

/**
 * set_indexed_reg - Set indexed register
 * @hwif: for the port address
 * @index: index of the indexed register
 */
static void set_indexed_reg(ide_hwif_t *hwif, u8 index, u8 value)
{
	outb(index, hwif->dma_base + 1);
	outb(value, hwif->dma_base + 3);
	DBG("index[%02X] value[%02X]\n", index, value);
}

/*
 * ATA Timing Tables based on 133 MHz PLL output clock.
 *
 * If the PLL outputs 100 MHz clock, the ASIC hardware will set
 * the timing registers automatically when "set features" command is
 * issued to the device. However, if the PLL output clock is 133 MHz,
 * the following tables must be used.
 */
static struct pio_timing {
	u8 reg0c, reg0d, reg13;
} pio_timings [] = {
	{ 0xfb, 0x2b, 0xac },	/* PIO mode 0, IORDY off, Prefetch off */
	{ 0x46, 0x29, 0xa4 },	/* PIO mode 1, IORDY off, Prefetch off */
	{ 0x23, 0x26, 0x64 },	/* PIO mode 2, IORDY off, Prefetch off */
	{ 0x27, 0x0d, 0x35 },	/* PIO mode 3, IORDY on,  Prefetch off */
	{ 0x23, 0x09, 0x25 },	/* PIO mode 4, IORDY on,  Prefetch off */
};

static struct mwdma_timing {
	u8 reg0e, reg0f;
} mwdma_timings [] = {
	{ 0xdf, 0x5f }, 	/* MWDMA mode 0 */
	{ 0x6b, 0x27 }, 	/* MWDMA mode 1 */
	{ 0x69, 0x25 }, 	/* MWDMA mode 2 */
};

static struct udma_timing {
	u8 reg10, reg11, reg12;
} udma_timings [] = {
	{ 0x4a, 0x0f, 0xd5 },	/* UDMA mode 0 */
	{ 0x3a, 0x0a, 0xd0 },	/* UDMA mode 1 */
	{ 0x2a, 0x07, 0xcd },	/* UDMA mode 2 */
	{ 0x1a, 0x05, 0xcd },	/* UDMA mode 3 */
	{ 0x1a, 0x03, 0xcd },	/* UDMA mode 4 */
	{ 0x1a, 0x02, 0xcb },	/* UDMA mode 5 */
	{ 0x1a, 0x01, 0xcb },	/* UDMA mode 6 */
};

static void pdcnew_set_dma_mode(ide_drive_t *drive, const u8 speed)
{
	ide_hwif_t *hwif	= HWIF(drive);
	struct pci_dev *dev	= to_pci_dev(hwif->dev);
	u8 adj			= (drive->dn & 1) ? 0x08 : 0x00;

	/*
	 * IDE core issues SETFEATURES_XFER to the drive first (thanks to
	 * IDE_HFLAG_POST_SET_MODE in ->host_flags).  PDC202xx hardware will
	 * automatically set the timing registers based on 100 MHz PLL output.
	 *
	 * As we set up the PLL to output 133 MHz for UltraDMA/133 capable
	 * chips, we must override the default register settings...
	 */
	if (max_dma_rate(dev) == 4) {
		u8 mode = speed & 0x07;

		if (speed >= XFER_UDMA_0) {
			set_indexed_reg(hwif, 0x10 + adj,
					udma_timings[mode].reg10);
			set_indexed_reg(hwif, 0x11 + adj,
					udma_timings[mode].reg11);
			set_indexed_reg(hwif, 0x12 + adj,
					udma_timings[mode].reg12);
		} else {
			set_indexed_reg(hwif, 0x0e + adj,
					mwdma_timings[mode].reg0e);
			set_indexed_reg(hwif, 0x0f + adj,
					mwdma_timings[mode].reg0f);
		}
	} else if (speed == XFER_UDMA_2) {
		/* Set tHOLD bit to 0 if using UDMA mode 2 */
		u8 tmp = get_indexed_reg(hwif, 0x10 + adj);

		set_indexed_reg(hwif, 0x10 + adj, tmp & 0x7f);
 	}
}

static void pdcnew_set_pio_mode(ide_drive_t *drive, const u8 pio)
{
	ide_hwif_t *hwif = drive->hwif;
	struct pci_dev *dev = to_pci_dev(hwif->dev);
	u8 adj = (drive->dn & 1) ? 0x08 : 0x00;

	if (max_dma_rate(dev) == 4) {
		set_indexed_reg(hwif, 0x0c + adj, pio_timings[pio].reg0c);
		set_indexed_reg(hwif, 0x0d + adj, pio_timings[pio].reg0d);
		set_indexed_reg(hwif, 0x13 + adj, pio_timings[pio].reg13);
	}
}

static u8 __devinit pdcnew_cable_detect(ide_hwif_t *hwif)
{
	if (get_indexed_reg(hwif, 0x0b) & 0x04)
		return ATA_CBL_PATA40;
	else
		return ATA_CBL_PATA80;
}

static void pdcnew_quirkproc(ide_drive_t *drive)
{
	const char **list, *model = drive->id->model;

	for (list = pdc_quirk_drives; *list != NULL; list++)
		if (strstr(model, *list) != NULL) {
			drive->quirk_list = 2;
			return;
		}

	drive->quirk_list = 0;
}

static void pdcnew_reset(ide_drive_t *drive)
{
	/*
	 * Deleted this because it is redundant from the caller.
	 */
	printk(KERN_WARNING "pdc202xx_new: %s channel reset.\n",
		HWIF(drive)->channel ? "Secondary" : "Primary");
}

/**
 * read_counter - Read the byte count registers
 * @dma_base: for the port address
 */
static long __devinit read_counter(u32 dma_base)
{
	u32  pri_dma_base = dma_base, sec_dma_base = dma_base + 0x08;
	u8   cnt0, cnt1, cnt2, cnt3;
	long count = 0, last;
	int  retry = 3;

	do {
		last = count;

		/* Read the current count */
		outb(0x20, pri_dma_base + 0x01);
		cnt0 = inb(pri_dma_base + 0x03);
		outb(0x21, pri_dma_base + 0x01);
		cnt1 = inb(pri_dma_base + 0x03);
		outb(0x20, sec_dma_base + 0x01);
		cnt2 = inb(sec_dma_base + 0x03);
		outb(0x21, sec_dma_base + 0x01);
		cnt3 = inb(sec_dma_base + 0x03);

		count = (cnt3 << 23) | (cnt2 << 15) | (cnt1 << 8) | cnt0;

		/*
		 * The 30-bit decrementing counter is read in 4 pieces.
		 * Incorrect value may be read when the most significant bytes
		 * are changing...
		 */
	} while (retry-- && (((last ^ count) & 0x3fff8000) || last < count));

	DBG("cnt0[%02X] cnt1[%02X] cnt2[%02X] cnt3[%02X]\n",
		  cnt0, cnt1, cnt2, cnt3);

	return count;
}

/**
 * detect_pll_input_clock - Detect the PLL input clock in Hz.
 * @dma_base: for the port address
 * E.g. 16949000 on 33 MHz PCI bus, i.e. half of the PCI clock.
 */
static long __devinit detect_pll_input_clock(unsigned long dma_base)
{
	struct timeval start_time, end_time;
	long start_count, end_count;
	long pll_input, usec_elapsed;
	u8 scr1;

	start_count = read_counter(dma_base);
	do_gettimeofday(&start_time);

	/* Start the test mode */
	outb(0x01, dma_base + 0x01);
	scr1 = inb(dma_base + 0x03);
	DBG("scr1[%02X]\n", scr1);
	outb(scr1 | 0x40, dma_base + 0x03);

	/* Let the counter run for 10 ms. */
	mdelay(10);

	end_count = read_counter(dma_base);
	do_gettimeofday(&end_time);

	/* Stop the test mode */
	outb(0x01, dma_base + 0x01);
	scr1 = inb(dma_base + 0x03);
	DBG("scr1[%02X]\n", scr1);
	outb(scr1 & ~0x40, dma_base + 0x03);

	/*
	 * Calculate the input clock in Hz
	 * (the clock counter is 30 bit wide and counts down)
	 */
	usec_elapsed = (end_time.tv_sec - start_time.tv_sec) * 1000000 +
		(end_time.tv_usec - start_time.tv_usec);
	pll_input = ((start_count - end_count) & 0x3fffffff) / 10 *
		(10000000 / usec_elapsed);

	DBG("start[%ld] end[%ld]\n", start_count, end_count);

	return pll_input;
}

#ifdef CONFIG_PPC_PMAC
static void __devinit apple_kiwi_init(struct pci_dev *pdev)
{
	struct device_node *np = pci_device_to_OF_node(pdev);
	u8 conf;

	if (np == NULL || !of_device_is_compatible(np, "kiwi-root"))
		return;

	if (pdev->revision >= 0x03) {
		/* Setup chip magic config stuff (from darwin) */
		pci_read_config_byte (pdev, 0x40, &conf);
		pci_write_config_byte(pdev, 0x40, (conf | 0x01));
	}
}
#endif /* CONFIG_PPC_PMAC */

static unsigned int __devinit init_chipset_pdcnew(struct pci_dev *dev, const char *name)
{
	unsigned long dma_base = pci_resource_start(dev, 4);
	unsigned long sec_dma_base = dma_base + 0x08;
	long pll_input, pll_output, ratio;
	int f, r;
	u8 pll_ctl0, pll_ctl1;

	if (dma_base == 0)
		return -EFAULT;

#ifdef CONFIG_PPC_PMAC
	apple_kiwi_init(dev);
#endif

	/* Calculate the required PLL output frequency */
	switch(max_dma_rate(dev)) {
		case 4: /* it's 133 MHz for Ultra133 chips */
			pll_output = 133333333;
			break;
		case 3: /* and  100 MHz for Ultra100 chips */
		default:
			pll_output = 100000000;
			break;
	}

	/*
	 * Detect PLL input clock.
	 * On some systems, where PCI bus is running at non-standard clock rate
	 * (e.g. 25 or 40 MHz), we have to adjust the cycle time.
	 * PDC20268 and newer chips employ PLL circuit to help correct timing
	 * registers setting.
	 */
	pll_input = detect_pll_input_clock(dma_base);
	printk("%s: PLL input clock is %ld kHz\n", name, pll_input / 1000);

	/* Sanity check */
	if (unlikely(pll_input < 5000000L || pll_input > 70000000L)) {
		printk(KERN_ERR "%s: Bad PLL input clock %ld Hz, giving up!\n",
		       name, pll_input);
		goto out;
	}

#ifdef DEBUG
	DBG("pll_output is %ld Hz\n", pll_output);

	/* Show the current clock value of PLL control register
	 * (maybe already configured by the BIOS)
	 */
	outb(0x02, sec_dma_base + 0x01);
	pll_ctl0 = inb(sec_dma_base + 0x03);
	outb(0x03, sec_dma_base + 0x01);
	pll_ctl1 = inb(sec_dma_base + 0x03);

	DBG("pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
#endif

	/*
	 * Calculate the ratio of F, R and NO
	 * POUT = (F + 2) / (( R + 2) * NO)
	 */
	ratio = pll_output / (pll_input / 1000);
	if (ratio < 8600L) { /* 8.6x */
		/* Using NO = 0x01, R = 0x0d */
		r = 0x0d;
	} else if (ratio < 12900L) { /* 12.9x */
		/* Using NO = 0x01, R = 0x08 */
		r = 0x08;
	} else if (ratio < 16100L) { /* 16.1x */
		/* Using NO = 0x01, R = 0x06 */
		r = 0x06;
	} else if (ratio < 64000L) { /* 64x */
		r = 0x00;
	} else {
		/* Invalid ratio */
		printk(KERN_ERR "%s: Bad ratio %ld, giving up!\n", name, ratio);
		goto out;
	}

	f = (ratio * (r + 2)) / 1000 - 2;

	DBG("F[%d] R[%d] ratio*1000[%ld]\n", f, r, ratio);

	if (unlikely(f < 0 || f > 127)) {
		/* Invalid F */
		printk(KERN_ERR "%s: F[%d] invalid!\n", name, f);
		goto out;
	}

	pll_ctl0 = (u8) f;
	pll_ctl1 = (u8) r;

	DBG("Writing pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);

	outb(0x02,     sec_dma_base + 0x01);
	outb(pll_ctl0, sec_dma_base + 0x03);
	outb(0x03,     sec_dma_base + 0x01);
	outb(pll_ctl1, sec_dma_base + 0x03);

	/* Wait the PLL circuit to be stable */
	mdelay(30);

#ifdef DEBUG
	/*
	 *  Show the current clock value of PLL control register
	 */
	outb(0x02, sec_dma_base + 0x01);
	pll_ctl0 = inb(sec_dma_base + 0x03);
	outb(0x03, sec_dma_base + 0x01);
	pll_ctl1 = inb(sec_dma_base + 0x03);

	DBG("pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
#endif

 out:
	return dev->irq;
}

static struct pci_dev * __devinit pdc20270_get_dev2(struct pci_dev *dev)
{
	struct pci_dev *dev2;

	dev2 = pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn) + 1,
						PCI_FUNC(dev->devfn)));

	if (dev2 &&
	    dev2->vendor == dev->vendor &&
	    dev2->device == dev->device) {

		if (dev2->irq != dev->irq) {
			dev2->irq = dev->irq;
			printk(KERN_INFO "PDC20270: PCI config space "
					 "interrupt fixed\n");
		}

		return dev2;
	}

	return NULL;
}

static const struct ide_port_ops pdcnew_port_ops = {
	.set_pio_mode		= pdcnew_set_pio_mode,
	.set_dma_mode		= pdcnew_set_dma_mode,
	.quirkproc		= pdcnew_quirkproc,
	.resetproc		= pdcnew_reset,
	.cable_detect		= pdcnew_cable_detect,
};

#define DECLARE_PDCNEW_DEV(name_str, udma) \
	{ \
		.name		= name_str, \
		.init_chipset	= init_chipset_pdcnew, \
		.port_ops	= &pdcnew_port_ops, \
		.host_flags	= IDE_HFLAG_POST_SET_MODE | \
				  IDE_HFLAG_ERROR_STOPS_FIFO | \
				  IDE_HFLAG_OFF_BOARD, \
		.pio_mask	= ATA_PIO4, \
		.mwdma_mask	= ATA_MWDMA2, \
		.udma_mask	= udma, \
	}

static const struct ide_port_info pdcnew_chipsets[] __devinitdata = {
	/* 0 */ DECLARE_PDCNEW_DEV("PDC20268", ATA_UDMA5),
	/* 1 */ DECLARE_PDCNEW_DEV("PDC20269", ATA_UDMA6),
	/* 2 */ DECLARE_PDCNEW_DEV("PDC20270", ATA_UDMA5),
	/* 3 */ DECLARE_PDCNEW_DEV("PDC20271", ATA_UDMA6),
	/* 4 */ DECLARE_PDCNEW_DEV("PDC20275", ATA_UDMA6),
	/* 5 */ DECLARE_PDCNEW_DEV("PDC20276", ATA_UDMA6),
	/* 6 */ DECLARE_PDCNEW_DEV("PDC20277", ATA_UDMA6),
};

/**
 *	pdc202new_init_one	-	called when a pdc202xx is found
 *	@dev: the pdc202new device
 *	@id: the matching pci id
 *
 *	Called when the PCI registration layer (or the IDE initialization)
 *	finds a device matching our IDE device tables.
 */
 
static int __devinit pdc202new_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	const struct ide_port_info *d;
	struct pci_dev *bridge = dev->bus->self;
	u8 idx = id->driver_data;

	d = &pdcnew_chipsets[idx];

	if (idx == 2 && bridge &&
	    bridge->vendor == PCI_VENDOR_ID_DEC &&
	    bridge->device == PCI_DEVICE_ID_DEC_21150) {
		struct pci_dev *dev2;

		if (PCI_SLOT(dev->devfn) & 2)
			return -ENODEV;

		dev2 = pdc20270_get_dev2(dev);

		if (dev2) {
			int ret = ide_pci_init_two(dev, dev2, d, NULL);
			if (ret < 0)
				pci_dev_put(dev2);
			return ret;
		}
	}

	if (idx == 5 && bridge &&
	    bridge->vendor == PCI_VENDOR_ID_INTEL &&
	    (bridge->device == PCI_DEVICE_ID_INTEL_I960 ||
	     bridge->device == PCI_DEVICE_ID_INTEL_I960RM)) {
		printk(KERN_INFO "PDC20276: attached to I2O RAID controller, "
				 "skipping\n");
		return -ENODEV;
	}

	return ide_pci_init_one(dev, d, NULL);
}

static void __devexit pdc202new_remove(struct pci_dev *dev)
{
	struct ide_host *host = pci_get_drvdata(dev);
	struct pci_dev *dev2 = host->dev[1] ? to_pci_dev(host->dev[1]) : NULL;

	ide_pci_remove(dev);
	pci_dev_put(dev2);
}

static const struct pci_device_id pdc202new_pci_tbl[] = {
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20268), 0 },
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20269), 1 },
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20270), 2 },
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20271), 3 },
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20275), 4 },
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20276), 5 },
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20277), 6 },
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, pdc202new_pci_tbl);

static struct pci_driver driver = {
	.name		= "Promise_IDE",
	.id_table	= pdc202new_pci_tbl,
	.probe		= pdc202new_init_one,
	.remove		= pdc202new_remove,
};

static int __init pdc202new_ide_init(void)
{
	return ide_pci_register_driver(&driver);
}

static void __exit pdc202new_ide_exit(void)
{
	pci_unregister_driver(&driver);
}

module_init(pdc202new_ide_init);
module_exit(pdc202new_ide_exit);

MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
MODULE_DESCRIPTION("PCI driver module for Promise PDC20268 and higher");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Promise TX2/TX4/TX2000/133 IDE driver
	3	*
	4	* This program is free software; you can redistribute it and/or
	5	* modify it under the terms of the GNU General Public License
	6	* as published by the Free Software Foundation; either version
	7	* 2 of the License, or (at your option) any later version.
	8	*
	9	* Split from:
	10	* linux/drivers/ide/pdc202xx.c Version 0.35 Mar. 30, 2002
	11	* Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
35198234	12	* Copyright (C) 2005-2007 MontaVista Software, Inc.
1da177e4 LT	13	* Portions Copyright (C) 1999 Promise Technology, Inc.
	14	* Author: Frank Tiernan (frankt@promise.com)
	15	* Released under terms of General Public License
	16	*/
	17
1da177e4 LT	18	#include <linux/module.h>
	19	#include <linux/types.h>
	20	#include <linux/kernel.h>
	21	#include <linux/delay.h>
1da177e4	22	#include <linux/hdreg.h>
1da177e4 LT	23	#include <linux/pci.h>
	24	#include <linux/init.h>
	25	#include <linux/ide.h>
	26
	27	#include <asm/io.h>
1da177e4 LT	28
	29	#ifdef CONFIG_PPC_PMAC
	30	#include <asm/prom.h>
	31	#include <asm/pci-bridge.h>
	32	#endif
	33
47694bb8 SS	34	#undef DEBUG
	35
	36	#ifdef DEBUG
eb63963a	37	#define DBG(fmt, args...) printk("%s: " fmt, __func__, ## args)
47694bb8 SS	38	#else
	39	#define DBG(fmt, args...)
	40	#endif
	41
3c6bee1d	42	static const char *pdc_quirk_drives[] = {
1da177e4 LT	43	"QUANTUM FIREBALLlct08 08",
	44	"QUANTUM FIREBALLP KA6.4",
	45	"QUANTUM FIREBALLP KA9.1",
	46	"QUANTUM FIREBALLP LM20.4",
	47	"QUANTUM FIREBALLP KX13.6",
	48	"QUANTUM FIREBALLP KX20.5",
	49	"QUANTUM FIREBALLP KX27.3",
	50	"QUANTUM FIREBALLP LM20.5",
	51	NULL
	52	};
	53
47694bb8	54	static u8 max_dma_rate(struct pci_dev *pdev)
1da177e4 LT	55	{
	56	u8 mode;
	57
47694bb8	58	switch(pdev->device) {
1da177e4 LT	59	case PCI_DEVICE_ID_PROMISE_20277:
	60	case PCI_DEVICE_ID_PROMISE_20276:
	61	case PCI_DEVICE_ID_PROMISE_20275:
	62	case PCI_DEVICE_ID_PROMISE_20271:
	63	case PCI_DEVICE_ID_PROMISE_20269:
	64	mode = 4;
	65	break;
	66	case PCI_DEVICE_ID_PROMISE_20270:
	67	case PCI_DEVICE_ID_PROMISE_20268:
	68	mode = 3;
	69	break;
	70	default:
	71	return 0;
	72	}
47694bb8	73
1da177e4 LT	74	return mode;
	75	}
	76
47694bb8 SS	77	/**
	78	* get_indexed_reg - Get indexed register
	79	* @hwif: for the port address
	80	* @index: index of the indexed register
	81	*/
	82	static u8 get_indexed_reg(ide_hwif_t *hwif, u8 index)
	83	{
	84	u8 value;
	85
41051a14 BZ	86	outb(index, hwif->dma_base + 1);
41051a14 BZ	87	value = inb(hwif->dma_base + 3);
47694bb8 SS	88
	89	DBG("index[%02X] value[%02X]\n", index, value);
	90	return value;
	91	}
	92
	93	/**
	94	* set_indexed_reg - Set indexed register
	95	* @hwif: for the port address
	96	* @index: index of the indexed register
	97	*/
	98	static void set_indexed_reg(ide_hwif_t *hwif, u8 index, u8 value)
	99	{
41051a14 BZ	100	outb(index, hwif->dma_base + 1);
41051a14 BZ	101	outb(value, hwif->dma_base + 3);
47694bb8 SS	102	DBG("index[%02X] value[%02X]\n", index, value);
	103	}
	104
	105	/*
	106	* ATA Timing Tables based on 133 MHz PLL output clock.
	107	*
	108	* If the PLL outputs 100 MHz clock, the ASIC hardware will set
	109	* the timing registers automatically when "set features" command is
	110	* issued to the device. However, if the PLL output clock is 133 MHz,
	111	* the following tables must be used.
	112	*/
	113	static struct pio_timing {
	114	u8 reg0c, reg0d, reg13;
	115	} pio_timings [] = {
	116	{ 0xfb, 0x2b, 0xac }, /* PIO mode 0, IORDY off, Prefetch off */
	117	{ 0x46, 0x29, 0xa4 }, /* PIO mode 1, IORDY off, Prefetch off */
	118	{ 0x23, 0x26, 0x64 }, /* PIO mode 2, IORDY off, Prefetch off */
	119	{ 0x27, 0x0d, 0x35 }, /* PIO mode 3, IORDY on, Prefetch off */
	120	{ 0x23, 0x09, 0x25 }, /* PIO mode 4, IORDY on, Prefetch off */
	121	};
	122
	123	static struct mwdma_timing {
	124	u8 reg0e, reg0f;
	125	} mwdma_timings [] = {
	126	{ 0xdf, 0x5f }, /* MWDMA mode 0 */
	127	{ 0x6b, 0x27 }, /* MWDMA mode 1 */
	128	{ 0x69, 0x25 }, /* MWDMA mode 2 */
	129	};
	130
	131	static struct udma_timing {
	132	u8 reg10, reg11, reg12;
	133	} udma_timings [] = {
	134	{ 0x4a, 0x0f, 0xd5 }, /* UDMA mode 0 */
	135	{ 0x3a, 0x0a, 0xd0 }, /* UDMA mode 1 */
	136	{ 0x2a, 0x07, 0xcd }, /* UDMA mode 2 */
	137	{ 0x1a, 0x05, 0xcd }, /* UDMA mode 3 */
	138	{ 0x1a, 0x03, 0xcd }, /* UDMA mode 4 */
	139	{ 0x1a, 0x02, 0xcb }, /* UDMA mode 5 */
	140	{ 0x1a, 0x01, 0xcb }, /* UDMA mode 6 */
	141	};
	142
ad4ba7dc	143	static void pdcnew_set_dma_mode(ide_drive_t *drive, const u8 speed)
1da177e4 LT	144	{
1da177e4 LT	145	ide_hwif_t *hwif = HWIF(drive);
36501650	146	struct pci_dev *dev = to_pci_dev(hwif->dev);
47694bb8	147	u8 adj = (drive->dn & 1) ? 0x08 : 0x00;
1da177e4	148
47694bb8	149	/*
88b2b32b BZ	150	* IDE core issues SETFEATURES_XFER to the drive first (thanks to
88b2b32b BZ	151	* IDE_HFLAG_POST_SET_MODE in ->host_flags). PDC202xx hardware will
47694bb8	152	* automatically set the timing registers based on 100 MHz PLL output.
88b2b32b	153	*
47694bb8 SS	154	* As we set up the PLL to output 133 MHz for UltraDMA/133 capable
	155	* chips, we must override the default register settings...
	156	*/
36501650	157	if (max_dma_rate(dev) == 4) {
47694bb8 SS	158	u8 mode = speed & 0x07;
47694bb8 SS	159
4db90a14 BZ	160	if (speed >= XFER_UDMA_0) {
	161	set_indexed_reg(hwif, 0x10 + adj,
	162	udma_timings[mode].reg10);
	163	set_indexed_reg(hwif, 0x11 + adj,
	164	udma_timings[mode].reg11);
	165	set_indexed_reg(hwif, 0x12 + adj,
	166	udma_timings[mode].reg12);
	167	} else {
	168	set_indexed_reg(hwif, 0x0e + adj,
	169	mwdma_timings[mode].reg0e);
	170	set_indexed_reg(hwif, 0x0f + adj,
	171	mwdma_timings[mode].reg0f);
47694bb8 SS	172	}
	173	} else if (speed == XFER_UDMA_2) {
	174	/* Set tHOLD bit to 0 if using UDMA mode 2 */
	175	u8 tmp = get_indexed_reg(hwif, 0x10 + adj);
	176
	177	set_indexed_reg(hwif, 0x10 + adj, tmp & 0x7f);
	178	}
1da177e4 LT	179	}
1da177e4 LT	180
26bcb879	181	static void pdcnew_set_pio_mode(ide_drive_t *drive, const u8 pio)
1da177e4	182	{
ad4ba7dc	183	ide_hwif_t *hwif = drive->hwif;
36501650	184	struct pci_dev *dev = to_pci_dev(hwif->dev);
ad4ba7dc BZ	185	u8 adj = (drive->dn & 1) ? 0x08 : 0x00;
ad4ba7dc BZ	186
36501650	187	if (max_dma_rate(dev) == 4) {
ad4ba7dc BZ	188	set_indexed_reg(hwif, 0x0c + adj, pio_timings[pio].reg0c);
	189	set_indexed_reg(hwif, 0x0d + adj, pio_timings[pio].reg0d);
	190	set_indexed_reg(hwif, 0x13 + adj, pio_timings[pio].reg13);
	191	}
1da177e4 LT	192	}
1da177e4 LT	193
bfa14b42	194	static u8 __devinit pdcnew_cable_detect(ide_hwif_t *hwif)
1da177e4	195	{
49521f97 BZ	196	if (get_indexed_reg(hwif, 0x0b) & 0x04)
	197	return ATA_CBL_PATA40;
	198	else
	199	return ATA_CBL_PATA80;
1da177e4	200	}
47694bb8	201
f01393e4	202	static void pdcnew_quirkproc(ide_drive_t *drive)
1da177e4	203	{
d24ec426 SS	204	const char *list, model = drive->id->model;
	205
	206	for (list = pdc_quirk_drives; *list != NULL; list++)
f01393e4 BZ	207	if (strstr(model, *list) != NULL) {
	208	drive->quirk_list = 2;
	209	return;
	210	}
	211
	212	drive->quirk_list = 0;
1da177e4 LT	213	}
1da177e4 LT	214
47694bb8	215	static void pdcnew_reset(ide_drive_t *drive)
1da177e4 LT	216	{
	217	/*
	218	* Deleted this because it is redundant from the caller.
	219	*/
47694bb8	220	printk(KERN_WARNING "pdc202xx_new: %s channel reset.\n",
1da177e4 LT	221	HWIF(drive)->channel ? "Secondary" : "Primary");
	222	}
	223
47694bb8 SS	224	/**
	225	* read_counter - Read the byte count registers
	226	* @dma_base: for the port address
	227	*/
	228	static long __devinit read_counter(u32 dma_base)
	229	{
	230	u32 pri_dma_base = dma_base, sec_dma_base = dma_base + 0x08;
	231	u8 cnt0, cnt1, cnt2, cnt3;
	232	long count = 0, last;
	233	int retry = 3;
	234
	235	do {
	236	last = count;
	237
	238	/* Read the current count */
	239	outb(0x20, pri_dma_base + 0x01);
	240	cnt0 = inb(pri_dma_base + 0x03);
	241	outb(0x21, pri_dma_base + 0x01);
	242	cnt1 = inb(pri_dma_base + 0x03);
	243	outb(0x20, sec_dma_base + 0x01);
	244	cnt2 = inb(sec_dma_base + 0x03);
	245	outb(0x21, sec_dma_base + 0x01);
	246	cnt3 = inb(sec_dma_base + 0x03);
	247
	248	count = (cnt3 << 23) \| (cnt2 << 15) \| (cnt1 << 8) \| cnt0;
	249
	250	/*
	251	* The 30-bit decrementing counter is read in 4 pieces.
	252	* Incorrect value may be read when the most significant bytes
	253	* are changing...
	254	*/
	255	} while (retry-- && (((last ^ count) & 0x3fff8000) \|\| last < count));
	256
	257	DBG("cnt0[%02X] cnt1[%02X] cnt2[%02X] cnt3[%02X]\n",
	258	cnt0, cnt1, cnt2, cnt3);
	259
	260	return count;
	261	}
	262
	263	/**
	264	* detect_pll_input_clock - Detect the PLL input clock in Hz.
	265	* @dma_base: for the port address
	266	* E.g. 16949000 on 33 MHz PCI bus, i.e. half of the PCI clock.
	267	*/
	268	static long __devinit detect_pll_input_clock(unsigned long dma_base)
	269	{
8006bf56	270	struct timeval start_time, end_time;
47694bb8	271	long start_count, end_count;
8006bf56	272	long pll_input, usec_elapsed;
47694bb8 SS	273	u8 scr1;
	274
	275	start_count = read_counter(dma_base);
8006bf56	276	do_gettimeofday(&start_time);
47694bb8 SS	277
	278	/* Start the test mode */
	279	outb(0x01, dma_base + 0x01);
	280	scr1 = inb(dma_base + 0x03);
	281	DBG("scr1[%02X]\n", scr1);
	282	outb(scr1 \| 0x40, dma_base + 0x03);
	283
	284	/* Let the counter run for 10 ms. */
	285	mdelay(10);
	286
	287	end_count = read_counter(dma_base);
8006bf56	288	do_gettimeofday(&end_time);
47694bb8 SS	289
	290	/* Stop the test mode */
	291	outb(0x01, dma_base + 0x01);
	292	scr1 = inb(dma_base + 0x03);
	293	DBG("scr1[%02X]\n", scr1);
	294	outb(scr1 & ~0x40, dma_base + 0x03);
	295
	296	/*
	297	* Calculate the input clock in Hz
	298	* (the clock counter is 30 bit wide and counts down)
	299	*/
8006bf56 AL	300	usec_elapsed = (end_time.tv_sec - start_time.tv_sec) * 1000000 +
8006bf56 AL	301	(end_time.tv_usec - start_time.tv_usec);
56fe23d5	302	pll_input = ((start_count - end_count) & 0x3fffffff) / 10 *
8006bf56	303	(10000000 / usec_elapsed);
47694bb8 SS	304
	305	DBG("start[%ld] end[%ld]\n", start_count, end_count);
	306
	307	return pll_input;
	308	}
	309
1da177e4 LT	310	#ifdef CONFIG_PPC_PMAC
	311	static void __devinit apple_kiwi_init(struct pci_dev *pdev)
	312	{
	313	struct device_node *np = pci_device_to_OF_node(pdev);
1da177e4 LT	314	u8 conf;
1da177e4 LT	315
55b61fec	316	if (np == NULL \|\| !of_device_is_compatible(np, "kiwi-root"))
1da177e4 LT	317	return;
1da177e4 LT	318
fc212bb1	319	if (pdev->revision >= 0x03) {
1da177e4	320	/* Setup chip magic config stuff (from darwin) */
47694bb8 SS	321	pci_read_config_byte (pdev, 0x40, &conf);
47694bb8 SS	322	pci_write_config_byte(pdev, 0x40, (conf \| 0x01));
1da177e4	323	}
1da177e4 LT	324	}
	325	#endif /* CONFIG_PPC_PMAC */
	326
	327	static unsigned int __devinit init_chipset_pdcnew(struct pci_dev dev, const char name)
	328	{
47694bb8 SS	329	unsigned long dma_base = pci_resource_start(dev, 4);
	330	unsigned long sec_dma_base = dma_base + 0x08;
	331	long pll_input, pll_output, ratio;
	332	int f, r;
	333	u8 pll_ctl0, pll_ctl1;
	334
01cc643a BZ	335	if (dma_base == 0)
	336	return -EFAULT;
	337
1da177e4 LT	338	#ifdef CONFIG_PPC_PMAC
	339	apple_kiwi_init(dev);
	340	#endif
	341
47694bb8 SS	342	/* Calculate the required PLL output frequency */
	343	switch(max_dma_rate(dev)) {
	344	case 4: /* it's 133 MHz for Ultra133 chips */
	345	pll_output = 133333333;
	346	break;
	347	case 3: /* and 100 MHz for Ultra100 chips */
	348	default:
	349	pll_output = 100000000;
	350	break;
	351	}
	352
	353	/*
	354	* Detect PLL input clock.
	355	* On some systems, where PCI bus is running at non-standard clock rate
	356	* (e.g. 25 or 40 MHz), we have to adjust the cycle time.
	357	* PDC20268 and newer chips employ PLL circuit to help correct timing
	358	* registers setting.
	359	*/
	360	pll_input = detect_pll_input_clock(dma_base);
	361	printk("%s: PLL input clock is %ld kHz\n", name, pll_input / 1000);
	362
	363	/* Sanity check */
	364	if (unlikely(pll_input < 5000000L \|\| pll_input > 70000000L)) {
	365	printk(KERN_ERR "%s: Bad PLL input clock %ld Hz, giving up!\n",
	366	name, pll_input);
	367	goto out;
	368	}
	369
	370	#ifdef DEBUG
	371	DBG("pll_output is %ld Hz\n", pll_output);
	372
	373	/* Show the current clock value of PLL control register
	374	* (maybe already configured by the BIOS)
	375	*/
	376	outb(0x02, sec_dma_base + 0x01);
	377	pll_ctl0 = inb(sec_dma_base + 0x03);
	378	outb(0x03, sec_dma_base + 0x01);
	379	pll_ctl1 = inb(sec_dma_base + 0x03);
	380
	381	DBG("pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
	382	#endif
	383
	384	/*
	385	* Calculate the ratio of F, R and NO
	386	* POUT = (F + 2) / (( R + 2) * NO)
	387	*/
	388	ratio = pll_output / (pll_input / 1000);
	389	if (ratio < 8600L) { /* 8.6x */
	390	/* Using NO = 0x01, R = 0x0d */
	391	r = 0x0d;
	392	} else if (ratio < 12900L) { /* 12.9x */
	393	/* Using NO = 0x01, R = 0x08 */
	394	r = 0x08;
	395	} else if (ratio < 16100L) { /* 16.1x */
	396	/* Using NO = 0x01, R = 0x06 */
	397	r = 0x06;
	398	} else if (ratio < 64000L) { /* 64x */
	399	r = 0x00;
	400	} else {
	401	/* Invalid ratio */
	402	printk(KERN_ERR "%s: Bad ratio %ld, giving up!\n", name, ratio);
	403	goto out;
	404	}
	405
406	f = (ratio * (r + 2)) / 1000 - 2;
407
408	DBG("F[%d] R[%d] ratio*1000[%ld]\n", f, r, ratio);
409
410	if (unlikely(f < 0 \|\| f > 127)) {
411	/* Invalid F */
412	printk(KERN_ERR "%s: F[%d] invalid!\n", name, f);
413	goto out;
414	}
415
416	pll_ctl0 = (u8) f;
417	pll_ctl1 = (u8) r;
418
419	DBG("Writing pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
420
421	outb(0x02, sec_dma_base + 0x01);
422	outb(pll_ctl0, sec_dma_base + 0x03);
423	outb(0x03, sec_dma_base + 0x01);
424	outb(pll_ctl1, sec_dma_base + 0x03);
425
426	/* Wait the PLL circuit to be stable */
427	mdelay(30);
428
429	#ifdef DEBUG
430	/*
431	* Show the current clock value of PLL control register
432	*/
433	outb(0x02, sec_dma_base + 0x01);
434	pll_ctl0 = inb(sec_dma_base + 0x03);
435	outb(0x03, sec_dma_base + 0x01);
436	pll_ctl1 = inb(sec_dma_base + 0x03);
437
438	DBG("pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
439	#endif
440
441	out:
1da177e4 LT	442	return dev->irq;
	443	}
	444
099b1f42	445	static struct pci_dev * __devinit pdc20270_get_dev2(struct pci_dev *dev)
1da177e4	446	{
099b1f42 BZ	447	struct pci_dev *dev2;
099b1f42 BZ	448
eadb6ecf	449	dev2 = pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn) + 1,
099b1f42	450	PCI_FUNC(dev->devfn)));
eadb6ecf	451
099b1f42 BZ	452	if (dev2 &&
	453	dev2->vendor == dev->vendor &&
	454	dev2->device == dev->device) {
	455
	456	if (dev2->irq != dev->irq) {
	457	dev2->irq = dev->irq;
	458	printk(KERN_INFO "PDC20270: PCI config space "
	459	"interrupt fixed\n");
1da177e4	460	}
07047935	461
099b1f42	462	return dev2;
1da177e4	463	}
099b1f42 BZ	464
099b1f42 BZ	465	return NULL;
1da177e4 LT	466	}
1da177e4 LT	467
ac95beed BZ	468	static const struct ide_port_ops pdcnew_port_ops = {
	469	.set_pio_mode = pdcnew_set_pio_mode,
	470	.set_dma_mode = pdcnew_set_dma_mode,
	471	.quirkproc = pdcnew_quirkproc,
	472	.resetproc = pdcnew_reset,
	473	.cable_detect = pdcnew_cable_detect,
	474	};
	475
05d7e6cb BZ	476	#define DECLARE_PDCNEW_DEV(name_str, udma) \
	477	{ \
	478	.name = name_str, \
	479	.init_chipset = init_chipset_pdcnew, \
ac95beed	480	.port_ops = &pdcnew_port_ops, \
05d7e6cb	481	.host_flags = IDE_HFLAG_POST_SET_MODE \| \
ed67b923	482	IDE_HFLAG_ERROR_STOPS_FIFO \| \
05d7e6cb BZ	483	IDE_HFLAG_OFF_BOARD, \
	484	.pio_mask = ATA_PIO4, \
	485	.mwdma_mask = ATA_MWDMA2, \
	486	.udma_mask = udma, \
1da177e4	487	}
05d7e6cb	488
85620436	489	static const struct ide_port_info pdcnew_chipsets[] __devinitdata = {
05d7e6cb BZ	490	/* 0 */ DECLARE_PDCNEW_DEV("PDC20268", ATA_UDMA5),
	491	/* 1 */ DECLARE_PDCNEW_DEV("PDC20269", ATA_UDMA6),
	492	/* 2 */ DECLARE_PDCNEW_DEV("PDC20270", ATA_UDMA5),
	493	/* 3 */ DECLARE_PDCNEW_DEV("PDC20271", ATA_UDMA6),
	494	/* 4 */ DECLARE_PDCNEW_DEV("PDC20275", ATA_UDMA6),
	495	/* 5 */ DECLARE_PDCNEW_DEV("PDC20276", ATA_UDMA6),
	496	/* 6 */ DECLARE_PDCNEW_DEV("PDC20277", ATA_UDMA6),
1da177e4 LT	497	};
	498
	499	/**
	500	* pdc202new_init_one - called when a pdc202xx is found
	501	* @dev: the pdc202new device
	502	* @id: the matching pci id
	503	*
	504	* Called when the PCI registration layer (or the IDE initialization)
	505	* finds a device matching our IDE device tables.
	506	*/
	507
	508	static int __devinit pdc202new_init_one(struct pci_dev dev, const struct pci_device_id id)
	509	{
85620436	510	const struct ide_port_info *d;
099b1f42 BZ	511	struct pci_dev *bridge = dev->bus->self;
	512	u8 idx = id->driver_data;
	513
	514	d = &pdcnew_chipsets[idx];
	515
	516	if (idx == 2 && bridge &&
	517	bridge->vendor == PCI_VENDOR_ID_DEC &&
	518	bridge->device == PCI_DEVICE_ID_DEC_21150) {
	519	struct pci_dev *dev2;
	520
	521	if (PCI_SLOT(dev->devfn) & 2)
	522	return -ENODEV;
1da177e4	523
099b1f42 BZ	524	dev2 = pdc20270_get_dev2(dev);
	525
	526	if (dev2) {
6cdf6eb3	527	int ret = ide_pci_init_two(dev, dev2, d, NULL);
099b1f42 BZ	528	if (ret < 0)
	529	pci_dev_put(dev2);
	530	return ret;
	531	}
	532	}
	533
	534	if (idx == 5 && bridge &&
	535	bridge->vendor == PCI_VENDOR_ID_INTEL &&
	536	(bridge->device == PCI_DEVICE_ID_INTEL_I960 \|\|
	537	bridge->device == PCI_DEVICE_ID_INTEL_I960RM)) {
	538	printk(KERN_INFO "PDC20276: attached to I2O RAID controller, "
	539	"skipping\n");
	540	return -ENODEV;
	541	}
	542
6cdf6eb3	543	return ide_pci_init_one(dev, d, NULL);
1da177e4 LT	544	}
1da177e4 LT	545
d69c8f8c BZ	546	static void __devexit pdc202new_remove(struct pci_dev *dev)
	547	{
	548	struct ide_host *host = pci_get_drvdata(dev);
	549	struct pci_dev *dev2 = host->dev[1] ? to_pci_dev(host->dev[1]) : NULL;
	550
	551	ide_pci_remove(dev);
	552	pci_dev_put(dev2);
	553	}
	554
9cbcc5e3 BZ	555	static const struct pci_device_id pdc202new_pci_tbl[] = {
	556	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20268), 0 },
	557	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20269), 1 },
	558	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20270), 2 },
	559	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20271), 3 },
	560	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20275), 4 },
	561	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20276), 5 },
	562	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20277), 6 },
1da177e4 LT	563	{ 0, },
	564	};
	565	MODULE_DEVICE_TABLE(pci, pdc202new_pci_tbl);
	566
	567	static struct pci_driver driver = {
	568	.name = "Promise_IDE",
	569	.id_table = pdc202new_pci_tbl,
	570	.probe = pdc202new_init_one,
d69c8f8c	571	.remove = pdc202new_remove,
1da177e4 LT	572	};
1da177e4 LT	573
82ab1eec	574	static int __init pdc202new_ide_init(void)
1da177e4 LT	575	{
	576	return ide_pci_register_driver(&driver);
	577	}
	578
d69c8f8c BZ	579	static void __exit pdc202new_ide_exit(void)
	580	{
	581	pci_unregister_driver(&driver);
	582	}
	583
1da177e4	584	module_init(pdc202new_ide_init);
d69c8f8c	585	module_exit(pdc202new_ide_exit);
1da177e4 LT	586
	587	MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
	588	MODULE_DESCRIPTION("PCI driver module for Promise PDC20268 and higher");
	589	MODULE_LICENSE("GPL");