[net-next-2.6.git] / drivers / ide / pci / cs5530.c

/*
 * linux/drivers/ide/pci/cs5530.c		Version 0.76	Aug 3 2007
 *
 * Copyright (C) 2000			Andre Hedrick <andre@linux-ide.org>
 * Copyright (C) 2000			Mark Lord <mlord@pobox.com>
 * Copyright (C) 2007			Bartlomiej Zolnierkiewicz
 *
 * May be copied or modified under the terms of the GNU General Public License
 *
 * Development of this chipset driver was funded
 * by the nice folks at National Semiconductor.
 *
 * Documentation:
 *	CS5530 documentation available from National Semiconductor.
 */

#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/timer.h>
#include <linux/mm.h>
#include <linux/ioport.h>
#include <linux/blkdev.h>
#include <linux/hdreg.h>
#include <linux/interrupt.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/ide.h>
#include <asm/io.h>
#include <asm/irq.h>

/*
 * Here are the standard PIO mode 0-4 timings for each "format".
 * Format-0 uses fast data reg timings, with slower command reg timings.
 * Format-1 uses fast timings for all registers, but won't work with all drives.
 */
static unsigned int cs5530_pio_timings[2][5] = {
	{0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010},
	{0xd1329172, 0x71212171, 0x30200080, 0x20102010, 0x00100010}
};

/*
 * After chip reset, the PIO timings are set to 0x0000e132, which is not valid.
 */
#define CS5530_BAD_PIO(timings) (((timings)&~0x80000000)==0x0000e132)
#define CS5530_BASEREG(hwif)	(((hwif)->dma_base & ~0xf) + ((hwif)->channel ? 0x30 : 0x20))

/**
 *	cs5530_set_pio_mode	-	set host controller for PIO mode
 *	@drive: drive
 *	@pio: PIO mode number
 *
 *	Handles setting of PIO mode for the chipset.
 *
 *	The init_hwif_cs5530() routine guarantees that all drives
 *	will have valid default PIO timings set up before we get here.
 */

static void cs5530_set_pio_mode(ide_drive_t *drive, const u8 pio)
{
	unsigned long basereg = CS5530_BASEREG(drive->hwif);
	unsigned int format = (inl(basereg + 4) >> 31) & 1;

	outl(cs5530_pio_timings[format][pio], basereg + ((drive->dn & 1)<<3));
}

/**
 *	cs5530_udma_filter	-	UDMA filter
 *	@drive: drive
 *
 *	cs5530_udma_filter() does UDMA mask filtering for the given drive
 *	taking into the consideration capabilities of the mate device.
 *
 *	The CS5530 specifies that two drives sharing a cable cannot mix
 *	UDMA/MDMA.  It has to be one or the other, for the pair, though
 *	different timings can still be chosen for each drive.  We could
 *	set the appropriate timing bits on the fly, but that might be
 *	a bit confusing.  So, for now we statically handle this requirement
 *	by looking at our mate drive to see what it is capable of, before
 *	choosing a mode for our own drive.
 *
 *	Note: This relies on the fact we never fail from UDMA to MWDMA2
 *	but instead drop to PIO.
 */

static u8 cs5530_udma_filter(ide_drive_t *drive)
{
	ide_hwif_t *hwif = drive->hwif;
	ide_drive_t *mate = &hwif->drives[(drive->dn & 1) ^ 1];
	struct hd_driveid *mateid = mate->id;
	u8 mask = hwif->ultra_mask;

	if (mate->present == 0)
		goto out;

	if ((mateid->capability & 1) && __ide_dma_bad_drive(mate) == 0) {
		if ((mateid->field_valid & 4) && (mateid->dma_ultra & 7))
			goto out;
		if ((mateid->field_valid & 2) && (mateid->dma_mword & 7))
			mask = 0;
	}
out:
	return mask;
}

static void cs5530_set_dma_mode(ide_drive_t *drive, const u8 mode)
{
	unsigned long basereg;
	unsigned int reg, timings = 0;

	switch (mode) {
		case XFER_UDMA_0:	timings = 0x00921250; break;
		case XFER_UDMA_1:	timings = 0x00911140; break;
		case XFER_UDMA_2:	timings = 0x00911030; break;
		case XFER_MW_DMA_0:	timings = 0x00077771; break;
		case XFER_MW_DMA_1:	timings = 0x00012121; break;
		case XFER_MW_DMA_2:	timings = 0x00002020; break;
		default:
			BUG();
			break;
	}
	basereg = CS5530_BASEREG(drive->hwif);
	reg = inl(basereg + 4);			/* get drive0 config register */
	timings |= reg & 0x80000000;		/* preserve PIO format bit */
	if ((drive-> dn & 1) == 0) {		/* are we configuring drive0? */
		outl(timings, basereg + 4);	/* write drive0 config register */
	} else {
		if (timings & 0x00100000)
			reg |=  0x00100000;	/* enable UDMA timings for both drives */
		else
			reg &= ~0x00100000;	/* disable UDMA timings for both drives */
		outl(reg, basereg + 4);		/* write drive0 config register */
		outl(timings, basereg + 12);	/* write drive1 config register */
	}
}

/**
 *	init_chipset_5530	-	set up 5530 bridge
 *	@dev: PCI device
 *	@name: device name
 *
 *	Initialize the cs5530 bridge for reliable IDE DMA operation.
 */

static unsigned int __devinit init_chipset_cs5530 (struct pci_dev *dev, const char *name)
{
	struct pci_dev *master_0 = NULL, *cs5530_0 = NULL;
	unsigned long flags;

	if (pci_resource_start(dev, 4) == 0)
		return -EFAULT;

	dev = NULL;
	while ((dev = pci_get_device(PCI_VENDOR_ID_CYRIX, PCI_ANY_ID, dev)) != NULL) {
		switch (dev->device) {
			case PCI_DEVICE_ID_CYRIX_PCI_MASTER:
				master_0 = pci_dev_get(dev);
				break;
			case PCI_DEVICE_ID_CYRIX_5530_LEGACY:
				cs5530_0 = pci_dev_get(dev);
				break;
		}
	}
	if (!master_0) {
		printk(KERN_ERR "%s: unable to locate PCI MASTER function\n", name);
		goto out;
	}
	if (!cs5530_0) {
		printk(KERN_ERR "%s: unable to locate CS5530 LEGACY function\n", name);
		goto out;
	}

	spin_lock_irqsave(&ide_lock, flags);
		/* all CPUs (there should only be one CPU with this chipset) */

	/*
	 * Enable BusMaster and MemoryWriteAndInvalidate for the cs5530:
	 * -->  OR 0x14 into 16-bit PCI COMMAND reg of function 0 of the cs5530
	 */

	pci_set_master(cs5530_0);
	pci_try_set_mwi(cs5530_0);

	/*
	 * Set PCI CacheLineSize to 16-bytes:
	 * --> Write 0x04 into 8-bit PCI CACHELINESIZE reg of function 0 of the cs5530
	 */

	pci_write_config_byte(cs5530_0, PCI_CACHE_LINE_SIZE, 0x04);

	/*
	 * Disable trapping of UDMA register accesses (Win98 hack):
	 * --> Write 0x5006 into 16-bit reg at offset 0xd0 of function 0 of the cs5530
	 */

	pci_write_config_word(cs5530_0, 0xd0, 0x5006);

	/*
	 * Bit-1 at 0x40 enables MemoryWriteAndInvalidate on internal X-bus:
	 * The other settings are what is necessary to get the register
	 * into a sane state for IDE DMA operation.
	 */

	pci_write_config_byte(master_0, 0x40, 0x1e);

	/* 
	 * Set max PCI burst size (16-bytes seems to work best):
	 *	   16bytes: set bit-1 at 0x41 (reg value of 0x16)
	 *	all others: clear bit-1 at 0x41, and do:
	 *	  128bytes: OR 0x00 at 0x41
	 *	  256bytes: OR 0x04 at 0x41
	 *	  512bytes: OR 0x08 at 0x41
	 *	 1024bytes: OR 0x0c at 0x41
	 */

	pci_write_config_byte(master_0, 0x41, 0x14);

	/*
	 * These settings are necessary to get the chip
	 * into a sane state for IDE DMA operation.
	 */

	pci_write_config_byte(master_0, 0x42, 0x00);
	pci_write_config_byte(master_0, 0x43, 0xc1);

	spin_unlock_irqrestore(&ide_lock, flags);

out:
	pci_dev_put(master_0);
	pci_dev_put(cs5530_0);
	return 0;
}

/**
 *	init_hwif_cs5530	-	initialise an IDE channel
 *	@hwif: IDE to initialize
 *
 *	This gets invoked by the IDE driver once for each channel. It
 *	performs channel-specific pre-initialization before drive probing.
 */

static void __devinit init_hwif_cs5530 (ide_hwif_t *hwif)
{
	unsigned long basereg;
	u32 d0_timings;
	hwif->autodma = 0;

	if (hwif->mate)
		hwif->serialized = hwif->mate->serialized = 1;

	hwif->set_pio_mode = &cs5530_set_pio_mode;
	hwif->set_dma_mode = &cs5530_set_dma_mode;

	basereg = CS5530_BASEREG(hwif);
	d0_timings = inl(basereg + 0);
	if (CS5530_BAD_PIO(d0_timings))
		outl(cs5530_pio_timings[(d0_timings >> 31) & 1][0], basereg + 0);
	if (CS5530_BAD_PIO(inl(basereg + 8)))
		outl(cs5530_pio_timings[(d0_timings >> 31) & 1][0], basereg + 8);

	hwif->drives[0].autotune = 1;
	hwif->drives[1].autotune = 1;

	if (hwif->dma_base == 0)
		return;

	hwif->atapi_dma = 1;
	hwif->ultra_mask = 0x07;
	hwif->mwdma_mask = 0x07;

	hwif->udma_filter = cs5530_udma_filter;

	if (!noautodma)
		hwif->autodma = 1;
	hwif->drives[0].autodma = hwif->autodma;
	hwif->drives[1].autodma = hwif->autodma;
}

static ide_pci_device_t cs5530_chipset __devinitdata = {
	.name		= "CS5530",
	.init_chipset	= init_chipset_cs5530,
	.init_hwif	= init_hwif_cs5530,
	.autodma	= AUTODMA,
	.bootable	= ON_BOARD,
	.pio_mask	= ATA_PIO4,
	.host_flags	= IDE_HFLAG_POST_SET_MODE,
};

static int __devinit cs5530_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	return ide_setup_pci_device(dev, &cs5530_chipset);
}

static struct pci_device_id cs5530_pci_tbl[] = {
	{ PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, cs5530_pci_tbl);

static struct pci_driver driver = {
	.name		= "CS5530 IDE",
	.id_table	= cs5530_pci_tbl,
	.probe		= cs5530_init_one,
};

static int __init cs5530_ide_init(void)
{
	return ide_pci_register_driver(&driver);
}

module_init(cs5530_ide_init);

MODULE_AUTHOR("Mark Lord");
MODULE_DESCRIPTION("PCI driver module for Cyrix/NS 5530 IDE");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4	1	/*
3f019eea	2	* linux/drivers/ide/pci/cs5530.c Version 0.76 Aug 3 2007
1da177e4 LT	3	*
1da177e4 LT	4	* Copyright (C) 2000 Andre Hedrick <andre@linux-ide.org>
1da177e4	5	* Copyright (C) 2000 Mark Lord <mlord@pobox.com>
5fd216bb BZ	6	* Copyright (C) 2007 Bartlomiej Zolnierkiewicz
5fd216bb BZ	7	*
1da177e4 LT	8	* May be copied or modified under the terms of the GNU General Public License
	9	*
	10	* Development of this chipset driver was funded
	11	* by the nice folks at National Semiconductor.
	12	*
	13	* Documentation:
	14	* CS5530 documentation available from National Semiconductor.
	15	*/
	16
1da177e4 LT	17	#include <linux/module.h>
	18	#include <linux/types.h>
	19	#include <linux/kernel.h>
	20	#include <linux/delay.h>
	21	#include <linux/timer.h>
	22	#include <linux/mm.h>
	23	#include <linux/ioport.h>
	24	#include <linux/blkdev.h>
	25	#include <linux/hdreg.h>
	26	#include <linux/interrupt.h>
	27	#include <linux/pci.h>
	28	#include <linux/init.h>
	29	#include <linux/ide.h>
	30	#include <asm/io.h>
	31	#include <asm/irq.h>
	32
1da177e4 LT	33	/*
	34	* Here are the standard PIO mode 0-4 timings for each "format".
	35	* Format-0 uses fast data reg timings, with slower command reg timings.
	36	* Format-1 uses fast timings for all registers, but won't work with all drives.
	37	*/
	38	static unsigned int cs5530_pio_timings[2][5] = {
	39	{0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010},
	40	{0xd1329172, 0x71212171, 0x30200080, 0x20102010, 0x00100010}
	41	};
	42
	43	/*
	44	* After chip reset, the PIO timings are set to 0x0000e132, which is not valid.
	45	*/
	46	#define CS5530_BAD_PIO(timings) (((timings)&~0x80000000)==0x0000e132)
	47	#define CS5530_BASEREG(hwif) (((hwif)->dma_base & ~0xf) + ((hwif)->channel ? 0x30 : 0x20))
	48
	49	/**
88b2b32b	50	* cs5530_set_pio_mode - set host controller for PIO mode
26bcb879 BZ	51	* @drive: drive
26bcb879 BZ	52	* @pio: PIO mode number
1da177e4	53	*
88b2b32b	54	* Handles setting of PIO mode for the chipset.
1da177e4	55	*
26bcb879	56	* The init_hwif_cs5530() routine guarantees that all drives
1da177e4 LT	57	* will have valid default PIO timings set up before we get here.
	58	*/
	59
26bcb879	60	static void cs5530_set_pio_mode(ide_drive_t *drive, const u8 pio)
1da177e4	61	{
88b2b32b BZ	62	unsigned long basereg = CS5530_BASEREG(drive->hwif);
	63	unsigned int format = (inl(basereg + 4) >> 31) & 1;
	64
	65	outl(cs5530_pio_timings[format][pio], basereg + ((drive->dn & 1)<<3));
1da177e4 LT	66	}
	67
	68	/**
5fd216bb BZ	69	* cs5530_udma_filter - UDMA filter
	70	* @drive: drive
	71	*
	72	* cs5530_udma_filter() does UDMA mask filtering for the given drive
	73	* taking into the consideration capabilities of the mate device.
	74	*
	75	* The CS5530 specifies that two drives sharing a cable cannot mix
	76	* UDMA/MDMA. It has to be one or the other, for the pair, though
	77	* different timings can still be chosen for each drive. We could
	78	* set the appropriate timing bits on the fly, but that might be
	79	* a bit confusing. So, for now we statically handle this requirement
	80	* by looking at our mate drive to see what it is capable of, before
	81	* choosing a mode for our own drive.
	82	*
	83	* Note: This relies on the fact we never fail from UDMA to MWDMA2
	84	* but instead drop to PIO.
	85	*/
	86
	87	static u8 cs5530_udma_filter(ide_drive_t *drive)
	88	{
	89	ide_hwif_t *hwif = drive->hwif;
	90	ide_drive_t *mate = &hwif->drives[(drive->dn & 1) ^ 1];
	91	struct hd_driveid *mateid = mate->id;
	92	u8 mask = hwif->ultra_mask;
	93
	94	if (mate->present == 0)
	95	goto out;
	96
	97	if ((mateid->capability & 1) && __ide_dma_bad_drive(mate) == 0) {
	98	if ((mateid->field_valid & 4) && (mateid->dma_ultra & 7))
	99	goto out;
	100	if ((mateid->field_valid & 2) && (mateid->dma_mword & 7))
	101	mask = 0;
	102	}
	103	out:
	104	return mask;
	105	}
	106
88b2b32b	107	static void cs5530_set_dma_mode(ide_drive_t *drive, const u8 mode)
3c3f5d2c	108	{
5fd216bb	109	unsigned long basereg;
3c3f5d2c	110	unsigned int reg, timings = 0;
1da177e4	111
1da177e4 LT	112	switch (mode) {
	113	case XFER_UDMA_0: timings = 0x00921250; break;
	114	case XFER_UDMA_1: timings = 0x00911140; break;
	115	case XFER_UDMA_2: timings = 0x00911030; break;
	116	case XFER_MW_DMA_0: timings = 0x00077771; break;
	117	case XFER_MW_DMA_1: timings = 0x00012121; break;
	118	case XFER_MW_DMA_2: timings = 0x00002020; break;
	119	default:
15b85485 BZ	120	BUG();
15b85485 BZ	121	break;
1da177e4	122	}
3c3f5d2c	123	basereg = CS5530_BASEREG(drive->hwif);
0ecdca26	124	reg = inl(basereg + 4); /* get drive0 config register */
1da177e4	125	timings \|= reg & 0x80000000; /* preserve PIO format bit */
3c3f5d2c	126	if ((drive-> dn & 1) == 0) { /* are we configuring drive0? */
0ecdca26	127	outl(timings, basereg + 4); /* write drive0 config register */
1da177e4 LT	128	} else {
	129	if (timings & 0x00100000)
	130	reg \|= 0x00100000; /* enable UDMA timings for both drives */
	131	else
	132	reg &= ~0x00100000; /* disable UDMA timings for both drives */
0ecdca26 BZ	133	outl(reg, basereg + 4); /* write drive0 config register */
0ecdca26 BZ	134	outl(timings, basereg + 12); /* write drive1 config register */
1da177e4	135	}
1da177e4 LT	136	}
	137
	138	/**
	139	* init_chipset_5530 - set up 5530 bridge
	140	* @dev: PCI device
	141	* @name: device name
	142	*
	143	* Initialize the cs5530 bridge for reliable IDE DMA operation.
	144	*/
	145
88de8e99	146	static unsigned int __devinit init_chipset_cs5530 (struct pci_dev dev, const char name)
1da177e4 LT	147	{
	148	struct pci_dev master_0 = NULL, cs5530_0 = NULL;
	149	unsigned long flags;
	150
f7b0d2df BZ	151	if (pci_resource_start(dev, 4) == 0)
	152	return -EFAULT;
	153
1da177e4	154	dev = NULL;
652aa162	155	while ((dev = pci_get_device(PCI_VENDOR_ID_CYRIX, PCI_ANY_ID, dev)) != NULL) {
1da177e4 LT	156	switch (dev->device) {
1da177e4 LT	157	case PCI_DEVICE_ID_CYRIX_PCI_MASTER:
652aa162	158	master_0 = pci_dev_get(dev);
1da177e4 LT	159	break;
1da177e4 LT	160	case PCI_DEVICE_ID_CYRIX_5530_LEGACY:
652aa162	161	cs5530_0 = pci_dev_get(dev);
1da177e4 LT	162	break;
	163	}
	164	}
	165	if (!master_0) {
	166	printk(KERN_ERR "%s: unable to locate PCI MASTER function\n", name);
652aa162	167	goto out;
1da177e4 LT	168	}
	169	if (!cs5530_0) {
	170	printk(KERN_ERR "%s: unable to locate CS5530 LEGACY function\n", name);
652aa162	171	goto out;
1da177e4 LT	172	}
	173
	174	spin_lock_irqsave(&ide_lock, flags);
	175	/* all CPUs (there should only be one CPU with this chipset) */
	176
	177	/*
	178	* Enable BusMaster and MemoryWriteAndInvalidate for the cs5530:
	179	* --> OR 0x14 into 16-bit PCI COMMAND reg of function 0 of the cs5530
	180	*/
	181
	182	pci_set_master(cs5530_0);
694625c0	183	pci_try_set_mwi(cs5530_0);
1da177e4 LT	184
	185	/*
	186	* Set PCI CacheLineSize to 16-bytes:
	187	* --> Write 0x04 into 8-bit PCI CACHELINESIZE reg of function 0 of the cs5530
	188	*/
	189
	190	pci_write_config_byte(cs5530_0, PCI_CACHE_LINE_SIZE, 0x04);
	191
	192	/*
	193	* Disable trapping of UDMA register accesses (Win98 hack):
	194	* --> Write 0x5006 into 16-bit reg at offset 0xd0 of function 0 of the cs5530
	195	*/
	196
	197	pci_write_config_word(cs5530_0, 0xd0, 0x5006);
	198
	199	/*
	200	* Bit-1 at 0x40 enables MemoryWriteAndInvalidate on internal X-bus:
	201	* The other settings are what is necessary to get the register
	202	* into a sane state for IDE DMA operation.
	203	*/
	204
	205	pci_write_config_byte(master_0, 0x40, 0x1e);
	206
	207	/*
	208	* Set max PCI burst size (16-bytes seems to work best):
	209	* 16bytes: set bit-1 at 0x41 (reg value of 0x16)
	210	* all others: clear bit-1 at 0x41, and do:
	211	* 128bytes: OR 0x00 at 0x41
	212	* 256bytes: OR 0x04 at 0x41
	213	* 512bytes: OR 0x08 at 0x41
	214	* 1024bytes: OR 0x0c at 0x41
	215	*/
	216
	217	pci_write_config_byte(master_0, 0x41, 0x14);
	218
	219	/*
	220	* These settings are necessary to get the chip
	221	* into a sane state for IDE DMA operation.
	222	*/
	223
	224	pci_write_config_byte(master_0, 0x42, 0x00);
	225	pci_write_config_byte(master_0, 0x43, 0xc1);
	226
	227	spin_unlock_irqrestore(&ide_lock, flags);
	228
652aa162 AC	229	out:
	230	pci_dev_put(master_0);
	231	pci_dev_put(cs5530_0);
1da177e4 LT	232	return 0;
	233	}
	234
	235	/**
	236	* init_hwif_cs5530 - initialise an IDE channel
	237	* @hwif: IDE to initialize
	238	*
	239	* This gets invoked by the IDE driver once for each channel. It
	240	* performs channel-specific pre-initialization before drive probing.
	241	*/
	242
88de8e99	243	static void __devinit init_hwif_cs5530 (ide_hwif_t *hwif)
1da177e4 LT	244	{
	245	unsigned long basereg;
	246	u32 d0_timings;
	247	hwif->autodma = 0;
	248
	249	if (hwif->mate)
	250	hwif->serialized = hwif->mate->serialized = 1;
	251
26bcb879	252	hwif->set_pio_mode = &cs5530_set_pio_mode;
88b2b32b	253	hwif->set_dma_mode = &cs5530_set_dma_mode;
3c3f5d2c	254
1da177e4	255	basereg = CS5530_BASEREG(hwif);
0ecdca26	256	d0_timings = inl(basereg + 0);
93104654	257	if (CS5530_BAD_PIO(d0_timings))
0ecdca26	258	outl(cs5530_pio_timings[(d0_timings >> 31) & 1][0], basereg + 0);
93104654	259	if (CS5530_BAD_PIO(inl(basereg + 8)))
0ecdca26	260	outl(cs5530_pio_timings[(d0_timings >> 31) & 1][0], basereg + 8);
93104654 BZ	261
	262	hwif->drives[0].autotune = 1;
	263	hwif->drives[1].autotune = 1;
1da177e4	264
f7b0d2df BZ	265	if (hwif->dma_base == 0)
	266	return;
	267
1da177e4 LT	268	hwif->atapi_dma = 1;
	269	hwif->ultra_mask = 0x07;
	270	hwif->mwdma_mask = 0x07;
	271
5fd216bb	272	hwif->udma_filter = cs5530_udma_filter;
0ae2e178	273
1da177e4 LT	274	if (!noautodma)
	275	hwif->autodma = 1;
	276	hwif->drives[0].autodma = hwif->autodma;
	277	hwif->drives[1].autodma = hwif->autodma;
	278	}
	279
	280	static ide_pci_device_t cs5530_chipset __devinitdata = {
	281	.name = "CS5530",
	282	.init_chipset = init_chipset_cs5530,
	283	.init_hwif = init_hwif_cs5530,
1da177e4 LT	284	.autodma = AUTODMA,
1da177e4 LT	285	.bootable = ON_BOARD,
4099d143	286	.pio_mask = ATA_PIO4,
88b2b32b	287	.host_flags = IDE_HFLAG_POST_SET_MODE,
1da177e4 LT	288	};
	289
	290	static int __devinit cs5530_init_one(struct pci_dev dev, const struct pci_device_id id)
	291	{
	292	return ide_setup_pci_device(dev, &cs5530_chipset);
	293	}
	294
	295	static struct pci_device_id cs5530_pci_tbl[] = {
	296	{ PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
	297	{ 0, },
	298	};
	299	MODULE_DEVICE_TABLE(pci, cs5530_pci_tbl);
	300
	301	static struct pci_driver driver = {
	302	.name = "CS5530 IDE",
	303	.id_table = cs5530_pci_tbl,
	304	.probe = cs5530_init_one,
	305	};
	306
82ab1eec	307	static int __init cs5530_ide_init(void)
1da177e4 LT	308	{
	309	return ide_pci_register_driver(&driver);
	310	}
	311
	312	module_init(cs5530_ide_init);
	313
	314	MODULE_AUTHOR("Mark Lord");
	315	MODULE_DESCRIPTION("PCI driver module for Cyrix/NS 5530 IDE");
	316	MODULE_LICENSE("GPL");