[net-next-2.6.git] / drivers / ide / pci / cs5530.c

/*
 * linux/drivers/ide/pci/cs5530.c		Version 0.73	Mar 10 2007
 *
 * Copyright (C) 2000			Andre Hedrick <andre@linux-ide.org>
 * Copyright (C) 2000			Mark Lord <mlord@pobox.com>
 * Copyright (C) 2007			Bartlomiej Zolnierkiewicz
 *
 * May be copied or modified under the terms of the GNU General Public License
 *
 * Development of this chipset driver was funded
 * by the nice folks at National Semiconductor.
 *
 * Documentation:
 *	CS5530 documentation available from National Semiconductor.
 */

#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/timer.h>
#include <linux/mm.h>
#include <linux/ioport.h>
#include <linux/blkdev.h>
#include <linux/hdreg.h>
#include <linux/interrupt.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/ide.h>
#include <asm/io.h>
#include <asm/irq.h>

/**
 *	cs5530_xfer_set_mode	-	set a new transfer mode at the drive
 *	@drive: drive to tune
 *	@mode: new mode
 *
 *	Logging wrapper to the IDE driver speed configuration. This can
 *	probably go away now.
 */
 
static int cs5530_set_xfer_mode (ide_drive_t *drive, u8 mode)
{
	printk(KERN_DEBUG "%s: cs5530_set_xfer_mode(%s)\n",
		drive->name, ide_xfer_verbose(mode));
	return (ide_config_drive_speed(drive, mode));
}

/*
 * Here are the standard PIO mode 0-4 timings for each "format".
 * Format-0 uses fast data reg timings, with slower command reg timings.
 * Format-1 uses fast timings for all registers, but won't work with all drives.
 */
static unsigned int cs5530_pio_timings[2][5] = {
	{0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010},
	{0xd1329172, 0x71212171, 0x30200080, 0x20102010, 0x00100010}
};

/*
 * After chip reset, the PIO timings are set to 0x0000e132, which is not valid.
 */
#define CS5530_BAD_PIO(timings) (((timings)&~0x80000000)==0x0000e132)
#define CS5530_BASEREG(hwif)	(((hwif)->dma_base & ~0xf) + ((hwif)->channel ? 0x30 : 0x20))

static void cs5530_tunepio(ide_drive_t *drive, u8 pio)
{
	unsigned long basereg = CS5530_BASEREG(drive->hwif);
	unsigned int format = (inl(basereg + 4) >> 31) & 1;

	outl(cs5530_pio_timings[format][pio], basereg + ((drive->dn & 1)<<3));
}

/**
 *	cs5530_tuneproc		-	select/set PIO modes
 *
 *	cs5530_tuneproc() handles selection/setting of PIO modes
 *	for both the chipset and drive.
 *
 *	The ide_init_cs5530() routine guarantees that all drives
 *	will have valid default PIO timings set up before we get here.
 */

static void cs5530_tuneproc (ide_drive_t *drive, u8 pio)	/* pio=255 means "autotune" */
{
	pio = ide_get_best_pio_mode(drive, pio, 4);

	if (cs5530_set_xfer_mode(drive, XFER_PIO_0 + pio) == 0)
		cs5530_tunepio(drive, pio);
}

/**
 *	cs5530_udma_filter	-	UDMA filter
 *	@drive: drive
 *
 *	cs5530_udma_filter() does UDMA mask filtering for the given drive
 *	taking into the consideration capabilities of the mate device.
 *
 *	The CS5530 specifies that two drives sharing a cable cannot mix
 *	UDMA/MDMA.  It has to be one or the other, for the pair, though
 *	different timings can still be chosen for each drive.  We could
 *	set the appropriate timing bits on the fly, but that might be
 *	a bit confusing.  So, for now we statically handle this requirement
 *	by looking at our mate drive to see what it is capable of, before
 *	choosing a mode for our own drive.
 *
 *	Note: This relies on the fact we never fail from UDMA to MWDMA2
 *	but instead drop to PIO.
 */

static u8 cs5530_udma_filter(ide_drive_t *drive)
{
	ide_hwif_t *hwif = drive->hwif;
	ide_drive_t *mate = &hwif->drives[(drive->dn & 1) ^ 1];
	struct hd_driveid *mateid = mate->id;
	u8 mask = hwif->ultra_mask;

	if (mate->present == 0)
		goto out;

	if ((mateid->capability & 1) && __ide_dma_bad_drive(mate) == 0) {
		if ((mateid->field_valid & 4) && (mateid->dma_ultra & 7))
			goto out;
		if ((mateid->field_valid & 2) && (mateid->dma_mword & 7))
			mask = 0;
	}
out:
	return mask;
}

/**
 *	cs5530_config_dma	-	set DMA/UDMA mode
 *	@drive: drive to tune
 *
 *	cs5530_config_dma() handles setting of DMA/UDMA mode
 *	for both the chipset and drive.
 */

static int cs5530_config_dma(ide_drive_t *drive)
{
	if (ide_tune_dma(drive))
		return 0;

	return 1;
}

static int cs5530_tune_chipset(ide_drive_t *drive, u8 mode)
{
	unsigned long basereg;
	unsigned int reg, timings = 0;

	mode = ide_rate_filter(drive, mode);

	/*
	 * Tell the drive to switch to the new mode; abort on failure.
	 */
	if (cs5530_set_xfer_mode(drive, mode))
		return 1;	/* failure */

	/*
	 * Now tune the chipset to match the drive:
	 */
	switch (mode) {
		case XFER_UDMA_0:	timings = 0x00921250; break;
		case XFER_UDMA_1:	timings = 0x00911140; break;
		case XFER_UDMA_2:	timings = 0x00911030; break;
		case XFER_MW_DMA_0:	timings = 0x00077771; break;
		case XFER_MW_DMA_1:	timings = 0x00012121; break;
		case XFER_MW_DMA_2:	timings = 0x00002020; break;
		case XFER_PIO_4:
		case XFER_PIO_3:
		case XFER_PIO_2:
		case XFER_PIO_1:
		case XFER_PIO_0:
			cs5530_tunepio(drive, mode - XFER_PIO_0);
			return 0;
		default:
			BUG();
			break;
	}
	basereg = CS5530_BASEREG(drive->hwif);
	reg = inl(basereg + 4);			/* get drive0 config register */
	timings |= reg & 0x80000000;		/* preserve PIO format bit */
	if ((drive-> dn & 1) == 0) {		/* are we configuring drive0? */
		outl(timings, basereg + 4);	/* write drive0 config register */
	} else {
		if (timings & 0x00100000)
			reg |=  0x00100000;	/* enable UDMA timings for both drives */
		else
			reg &= ~0x00100000;	/* disable UDMA timings for both drives */
		outl(reg, basereg + 4);		/* write drive0 config register */
		outl(timings, basereg + 12);	/* write drive1 config register */
	}

	return 0;	/* success */
}

/**
 *	init_chipset_5530	-	set up 5530 bridge
 *	@dev: PCI device
 *	@name: device name
 *
 *	Initialize the cs5530 bridge for reliable IDE DMA operation.
 */

static unsigned int __devinit init_chipset_cs5530 (struct pci_dev *dev, const char *name)
{
	struct pci_dev *master_0 = NULL, *cs5530_0 = NULL;
	unsigned long flags;

	dev = NULL;
	while ((dev = pci_get_device(PCI_VENDOR_ID_CYRIX, PCI_ANY_ID, dev)) != NULL) {
		switch (dev->device) {
			case PCI_DEVICE_ID_CYRIX_PCI_MASTER:
				master_0 = pci_dev_get(dev);
				break;
			case PCI_DEVICE_ID_CYRIX_5530_LEGACY:
				cs5530_0 = pci_dev_get(dev);
				break;
		}
	}
	if (!master_0) {
		printk(KERN_ERR "%s: unable to locate PCI MASTER function\n", name);
		goto out;
	}
	if (!cs5530_0) {
		printk(KERN_ERR "%s: unable to locate CS5530 LEGACY function\n", name);
		goto out;
	}

	spin_lock_irqsave(&ide_lock, flags);
		/* all CPUs (there should only be one CPU with this chipset) */

	/*
	 * Enable BusMaster and MemoryWriteAndInvalidate for the cs5530:
	 * -->  OR 0x14 into 16-bit PCI COMMAND reg of function 0 of the cs5530
	 */

	pci_set_master(cs5530_0);
	pci_try_set_mwi(cs5530_0);

	/*
	 * Set PCI CacheLineSize to 16-bytes:
	 * --> Write 0x04 into 8-bit PCI CACHELINESIZE reg of function 0 of the cs5530
	 */

	pci_write_config_byte(cs5530_0, PCI_CACHE_LINE_SIZE, 0x04);

	/*
	 * Disable trapping of UDMA register accesses (Win98 hack):
	 * --> Write 0x5006 into 16-bit reg at offset 0xd0 of function 0 of the cs5530
	 */

	pci_write_config_word(cs5530_0, 0xd0, 0x5006);

	/*
	 * Bit-1 at 0x40 enables MemoryWriteAndInvalidate on internal X-bus:
	 * The other settings are what is necessary to get the register
	 * into a sane state for IDE DMA operation.
	 */

	pci_write_config_byte(master_0, 0x40, 0x1e);

	/* 
	 * Set max PCI burst size (16-bytes seems to work best):
	 *	   16bytes: set bit-1 at 0x41 (reg value of 0x16)
	 *	all others: clear bit-1 at 0x41, and do:
	 *	  128bytes: OR 0x00 at 0x41
	 *	  256bytes: OR 0x04 at 0x41
	 *	  512bytes: OR 0x08 at 0x41
	 *	 1024bytes: OR 0x0c at 0x41
	 */

	pci_write_config_byte(master_0, 0x41, 0x14);

	/*
	 * These settings are necessary to get the chip
	 * into a sane state for IDE DMA operation.
	 */

	pci_write_config_byte(master_0, 0x42, 0x00);
	pci_write_config_byte(master_0, 0x43, 0xc1);

	spin_unlock_irqrestore(&ide_lock, flags);

out:
	pci_dev_put(master_0);
	pci_dev_put(cs5530_0);
	return 0;
}

/**
 *	init_hwif_cs5530	-	initialise an IDE channel
 *	@hwif: IDE to initialize
 *
 *	This gets invoked by the IDE driver once for each channel. It
 *	performs channel-specific pre-initialization before drive probing.
 */

static void __devinit init_hwif_cs5530 (ide_hwif_t *hwif)
{
	unsigned long basereg;
	u32 d0_timings;
	hwif->autodma = 0;

	if (hwif->mate)
		hwif->serialized = hwif->mate->serialized = 1;

	hwif->tuneproc = &cs5530_tuneproc;
	hwif->speedproc = &cs5530_tune_chipset;

	basereg = CS5530_BASEREG(hwif);
	d0_timings = inl(basereg + 0);
	if (CS5530_BAD_PIO(d0_timings)) {
		/* PIO timings not initialized? */
		outl(cs5530_pio_timings[(d0_timings >> 31) & 1][0], basereg + 0);
		if (!hwif->drives[0].autotune)
			hwif->drives[0].autotune = 1;
			/* needs autotuning later */
	}
	if (CS5530_BAD_PIO(inl(basereg + 8))) {
		/* PIO timings not initialized? */
		outl(cs5530_pio_timings[(d0_timings >> 31) & 1][0], basereg + 8);
		if (!hwif->drives[1].autotune)
			hwif->drives[1].autotune = 1;
			/* needs autotuning later */
	}

	hwif->atapi_dma = 1;
	hwif->ultra_mask = 0x07;
	hwif->mwdma_mask = 0x07;

	hwif->udma_filter = cs5530_udma_filter;
	hwif->ide_dma_check = &cs5530_config_dma;
	if (!noautodma)
		hwif->autodma = 1;
	hwif->drives[0].autodma = hwif->autodma;
	hwif->drives[1].autodma = hwif->autodma;
}

static ide_pci_device_t cs5530_chipset __devinitdata = {
	.name		= "CS5530",
	.init_chipset	= init_chipset_cs5530,
	.init_hwif	= init_hwif_cs5530,
	.autodma	= AUTODMA,
	.bootable	= ON_BOARD,
};

static int __devinit cs5530_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	return ide_setup_pci_device(dev, &cs5530_chipset);
}

static struct pci_device_id cs5530_pci_tbl[] = {
	{ PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, cs5530_pci_tbl);

static struct pci_driver driver = {
	.name		= "CS5530 IDE",
	.id_table	= cs5530_pci_tbl,
	.probe		= cs5530_init_one,
};

static int __init cs5530_ide_init(void)
{
	return ide_pci_register_driver(&driver);
}

module_init(cs5530_ide_init);

MODULE_AUTHOR("Mark Lord");
MODULE_DESCRIPTION("PCI driver module for Cyrix/NS 5530 IDE");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4	1	/*
3c3f5d2c	2	* linux/drivers/ide/pci/cs5530.c Version 0.73 Mar 10 2007
1da177e4 LT	3	*
1da177e4 LT	4	* Copyright (C) 2000 Andre Hedrick <andre@linux-ide.org>
1da177e4	5	* Copyright (C) 2000 Mark Lord <mlord@pobox.com>
5fd216bb BZ	6	* Copyright (C) 2007 Bartlomiej Zolnierkiewicz
5fd216bb BZ	7	*
1da177e4 LT	8	* May be copied or modified under the terms of the GNU General Public License
	9	*
	10	* Development of this chipset driver was funded
	11	* by the nice folks at National Semiconductor.
	12	*
	13	* Documentation:
	14	* CS5530 documentation available from National Semiconductor.
	15	*/
	16
1da177e4 LT	17	#include <linux/module.h>
	18	#include <linux/types.h>
	19	#include <linux/kernel.h>
	20	#include <linux/delay.h>
	21	#include <linux/timer.h>
	22	#include <linux/mm.h>
	23	#include <linux/ioport.h>
	24	#include <linux/blkdev.h>
	25	#include <linux/hdreg.h>
	26	#include <linux/interrupt.h>
	27	#include <linux/pci.h>
	28	#include <linux/init.h>
	29	#include <linux/ide.h>
	30	#include <asm/io.h>
	31	#include <asm/irq.h>
	32
	33	/**
	34	* cs5530_xfer_set_mode - set a new transfer mode at the drive
	35	* @drive: drive to tune
	36	* @mode: new mode
	37	*
	38	* Logging wrapper to the IDE driver speed configuration. This can
	39	* probably go away now.
	40	*/
	41
	42	static int cs5530_set_xfer_mode (ide_drive_t *drive, u8 mode)
	43	{
	44	printk(KERN_DEBUG "%s: cs5530_set_xfer_mode(%s)\n",
	45	drive->name, ide_xfer_verbose(mode));
	46	return (ide_config_drive_speed(drive, mode));
	47	}
	48
	49	/*
	50	* Here are the standard PIO mode 0-4 timings for each "format".
	51	* Format-0 uses fast data reg timings, with slower command reg timings.
	52	* Format-1 uses fast timings for all registers, but won't work with all drives.
	53	*/
	54	static unsigned int cs5530_pio_timings[2][5] = {
	55	{0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010},
	56	{0xd1329172, 0x71212171, 0x30200080, 0x20102010, 0x00100010}
	57	};
	58
	59	/*
	60	* After chip reset, the PIO timings are set to 0x0000e132, which is not valid.
	61	*/
	62	#define CS5530_BAD_PIO(timings) (((timings)&~0x80000000)==0x0000e132)
	63	#define CS5530_BASEREG(hwif) (((hwif)->dma_base & ~0xf) + ((hwif)->channel ? 0x30 : 0x20))
	64
3c3f5d2c BZ	65	static void cs5530_tunepio(ide_drive_t *drive, u8 pio)
	66	{
	67	unsigned long basereg = CS5530_BASEREG(drive->hwif);
	68	unsigned int format = (inl(basereg + 4) >> 31) & 1;
	69
	70	outl(cs5530_pio_timings[format][pio], basereg + ((drive->dn & 1)<<3));
	71	}
	72
1da177e4 LT	73	/**
	74	* cs5530_tuneproc - select/set PIO modes
	75	*
	76	* cs5530_tuneproc() handles selection/setting of PIO modes
	77	* for both the chipset and drive.
	78	*
	79	* The ide_init_cs5530() routine guarantees that all drives
	80	* will have valid default PIO timings set up before we get here.
	81	*/
	82
	83	static void cs5530_tuneproc (ide_drive_t drive, u8 pio) / pio=255 means "autotune" */
	84	{
2134758d	85	pio = ide_get_best_pio_mode(drive, pio, 4);
3c3f5d2c BZ	86
	87	if (cs5530_set_xfer_mode(drive, XFER_PIO_0 + pio) == 0)
	88	cs5530_tunepio(drive, pio);
1da177e4 LT	89	}
	90
	91	/**
5fd216bb BZ	92	* cs5530_udma_filter - UDMA filter
	93	* @drive: drive
	94	*
	95	* cs5530_udma_filter() does UDMA mask filtering for the given drive
	96	* taking into the consideration capabilities of the mate device.
	97	*
	98	* The CS5530 specifies that two drives sharing a cable cannot mix
	99	* UDMA/MDMA. It has to be one or the other, for the pair, though
	100	* different timings can still be chosen for each drive. We could
	101	* set the appropriate timing bits on the fly, but that might be
	102	* a bit confusing. So, for now we statically handle this requirement
	103	* by looking at our mate drive to see what it is capable of, before
	104	* choosing a mode for our own drive.
	105	*
	106	* Note: This relies on the fact we never fail from UDMA to MWDMA2
	107	* but instead drop to PIO.
	108	*/
	109
	110	static u8 cs5530_udma_filter(ide_drive_t *drive)
	111	{
	112	ide_hwif_t *hwif = drive->hwif;
	113	ide_drive_t *mate = &hwif->drives[(drive->dn & 1) ^ 1];
	114	struct hd_driveid *mateid = mate->id;
	115	u8 mask = hwif->ultra_mask;
	116
	117	if (mate->present == 0)
	118	goto out;
	119
	120	if ((mateid->capability & 1) && __ide_dma_bad_drive(mate) == 0) {
	121	if ((mateid->field_valid & 4) && (mateid->dma_ultra & 7))
	122	goto out;
	123	if ((mateid->field_valid & 2) && (mateid->dma_mword & 7))
	124	mask = 0;
	125	}
	126	out:
	127	return mask;
	128	}
	129
	130	/**
	131	* cs5530_config_dma - set DMA/UDMA mode
1da177e4 LT	132	* @drive: drive to tune
1da177e4 LT	133	*
5fd216bb BZ	134	* cs5530_config_dma() handles setting of DMA/UDMA mode
5fd216bb BZ	135	* for both the chipset and drive.
1da177e4	136	*/
5fd216bb BZ	137
5fd216bb BZ	138	static int cs5530_config_dma(ide_drive_t *drive)
1da177e4	139	{
4728d546 BZ	140	if (ide_tune_dma(drive))
4728d546 BZ	141	return 0;
3c3f5d2c BZ	142
	143	return 1;
	144	}
	145
	146	static int cs5530_tune_chipset(ide_drive_t *drive, u8 mode)
	147	{
5fd216bb	148	unsigned long basereg;
3c3f5d2c	149	unsigned int reg, timings = 0;
1da177e4	150
3c3f5d2c	151	mode = ide_rate_filter(drive, mode);
1da177e4 LT	152
	153	/*
	154	* Tell the drive to switch to the new mode; abort on failure.
	155	*/
3c3f5d2c	156	if (cs5530_set_xfer_mode(drive, mode))
1da177e4 LT	157	return 1; /* failure */
	158
	159	/*
	160	* Now tune the chipset to match the drive:
	161	*/
	162	switch (mode) {
	163	case XFER_UDMA_0: timings = 0x00921250; break;
	164	case XFER_UDMA_1: timings = 0x00911140; break;
	165	case XFER_UDMA_2: timings = 0x00911030; break;
	166	case XFER_MW_DMA_0: timings = 0x00077771; break;
	167	case XFER_MW_DMA_1: timings = 0x00012121; break;
	168	case XFER_MW_DMA_2: timings = 0x00002020; break;
3c3f5d2c BZ	169	case XFER_PIO_4:
	170	case XFER_PIO_3:
	171	case XFER_PIO_2:
	172	case XFER_PIO_1:
	173	case XFER_PIO_0:
	174	cs5530_tunepio(drive, mode - XFER_PIO_0);
	175	return 0;
1da177e4	176	default:
15b85485 BZ	177	BUG();
15b85485 BZ	178	break;
1da177e4	179	}
3c3f5d2c	180	basereg = CS5530_BASEREG(drive->hwif);
0ecdca26	181	reg = inl(basereg + 4); /* get drive0 config register */
1da177e4	182	timings \|= reg & 0x80000000; /* preserve PIO format bit */
3c3f5d2c	183	if ((drive-> dn & 1) == 0) { /* are we configuring drive0? */
0ecdca26	184	outl(timings, basereg + 4); /* write drive0 config register */
1da177e4 LT	185	} else {
	186	if (timings & 0x00100000)
	187	reg \|= 0x00100000; /* enable UDMA timings for both drives */
	188	else
	189	reg &= ~0x00100000; /* disable UDMA timings for both drives */
0ecdca26 BZ	190	outl(reg, basereg + 4); /* write drive0 config register */
0ecdca26 BZ	191	outl(timings, basereg + 12); /* write drive1 config register */
1da177e4	192	}
1da177e4	193
3608b5d7	194	return 0; /* success */
1da177e4 LT	195	}
	196
	197	/**
	198	* init_chipset_5530 - set up 5530 bridge
	199	* @dev: PCI device
	200	* @name: device name
	201	*
	202	* Initialize the cs5530 bridge for reliable IDE DMA operation.
	203	*/
	204
88de8e99	205	static unsigned int __devinit init_chipset_cs5530 (struct pci_dev dev, const char name)
1da177e4 LT	206	{
	207	struct pci_dev master_0 = NULL, cs5530_0 = NULL;
	208	unsigned long flags;
	209
	210	dev = NULL;
652aa162	211	while ((dev = pci_get_device(PCI_VENDOR_ID_CYRIX, PCI_ANY_ID, dev)) != NULL) {
1da177e4 LT	212	switch (dev->device) {
1da177e4 LT	213	case PCI_DEVICE_ID_CYRIX_PCI_MASTER:
652aa162	214	master_0 = pci_dev_get(dev);
1da177e4 LT	215	break;
1da177e4 LT	216	case PCI_DEVICE_ID_CYRIX_5530_LEGACY:
652aa162	217	cs5530_0 = pci_dev_get(dev);
1da177e4 LT	218	break;
	219	}
	220	}
	221	if (!master_0) {
	222	printk(KERN_ERR "%s: unable to locate PCI MASTER function\n", name);
652aa162	223	goto out;
1da177e4 LT	224	}
	225	if (!cs5530_0) {
	226	printk(KERN_ERR "%s: unable to locate CS5530 LEGACY function\n", name);
652aa162	227	goto out;
1da177e4 LT	228	}
	229
	230	spin_lock_irqsave(&ide_lock, flags);
	231	/* all CPUs (there should only be one CPU with this chipset) */
	232
	233	/*
	234	* Enable BusMaster and MemoryWriteAndInvalidate for the cs5530:
	235	* --> OR 0x14 into 16-bit PCI COMMAND reg of function 0 of the cs5530
	236	*/
	237
	238	pci_set_master(cs5530_0);
694625c0	239	pci_try_set_mwi(cs5530_0);
1da177e4 LT	240
	241	/*
	242	* Set PCI CacheLineSize to 16-bytes:
	243	* --> Write 0x04 into 8-bit PCI CACHELINESIZE reg of function 0 of the cs5530
	244	*/
	245
	246	pci_write_config_byte(cs5530_0, PCI_CACHE_LINE_SIZE, 0x04);
	247
	248	/*
	249	* Disable trapping of UDMA register accesses (Win98 hack):
	250	* --> Write 0x5006 into 16-bit reg at offset 0xd0 of function 0 of the cs5530
	251	*/
	252
	253	pci_write_config_word(cs5530_0, 0xd0, 0x5006);
	254
	255	/*
	256	* Bit-1 at 0x40 enables MemoryWriteAndInvalidate on internal X-bus:
	257	* The other settings are what is necessary to get the register
	258	* into a sane state for IDE DMA operation.
	259	*/
	260
	261	pci_write_config_byte(master_0, 0x40, 0x1e);
	262
	263	/*
	264	* Set max PCI burst size (16-bytes seems to work best):
	265	* 16bytes: set bit-1 at 0x41 (reg value of 0x16)
	266	* all others: clear bit-1 at 0x41, and do:
	267	* 128bytes: OR 0x00 at 0x41
	268	* 256bytes: OR 0x04 at 0x41
	269	* 512bytes: OR 0x08 at 0x41
	270	* 1024bytes: OR 0x0c at 0x41
	271	*/
	272
	273	pci_write_config_byte(master_0, 0x41, 0x14);
	274
	275	/*
	276	* These settings are necessary to get the chip
	277	* into a sane state for IDE DMA operation.
	278	*/
	279
	280	pci_write_config_byte(master_0, 0x42, 0x00);
	281	pci_write_config_byte(master_0, 0x43, 0xc1);
	282
	283	spin_unlock_irqrestore(&ide_lock, flags);
	284
652aa162 AC	285	out:
	286	pci_dev_put(master_0);
	287	pci_dev_put(cs5530_0);
1da177e4 LT	288	return 0;
	289	}
	290
	291	/**
	292	* init_hwif_cs5530 - initialise an IDE channel
	293	* @hwif: IDE to initialize
	294	*
	295	* This gets invoked by the IDE driver once for each channel. It
	296	* performs channel-specific pre-initialization before drive probing.
	297	*/
	298
88de8e99	299	static void __devinit init_hwif_cs5530 (ide_hwif_t *hwif)
1da177e4 LT	300	{
	301	unsigned long basereg;
	302	u32 d0_timings;
	303	hwif->autodma = 0;
	304
	305	if (hwif->mate)
	306	hwif->serialized = hwif->mate->serialized = 1;
	307
	308	hwif->tuneproc = &cs5530_tuneproc;
3c3f5d2c BZ	309	hwif->speedproc = &cs5530_tune_chipset;
3c3f5d2c BZ	310
1da177e4	311	basereg = CS5530_BASEREG(hwif);
0ecdca26	312	d0_timings = inl(basereg + 0);
1da177e4 LT	313	if (CS5530_BAD_PIO(d0_timings)) {
1da177e4 LT	314	/* PIO timings not initialized? */
0ecdca26	315	outl(cs5530_pio_timings[(d0_timings >> 31) & 1][0], basereg + 0);
1da177e4 LT	316	if (!hwif->drives[0].autotune)
	317	hwif->drives[0].autotune = 1;
	318	/* needs autotuning later */
	319	}
0ecdca26 BZ	320	if (CS5530_BAD_PIO(inl(basereg + 8))) {
	321	/* PIO timings not initialized? */
	322	outl(cs5530_pio_timings[(d0_timings >> 31) & 1][0], basereg + 8);
1da177e4 LT	323	if (!hwif->drives[1].autotune)
	324	hwif->drives[1].autotune = 1;
	325	/* needs autotuning later */
	326	}
	327
	328	hwif->atapi_dma = 1;
	329	hwif->ultra_mask = 0x07;
	330	hwif->mwdma_mask = 0x07;
	331
5fd216bb	332	hwif->udma_filter = cs5530_udma_filter;
1da177e4 LT	333	hwif->ide_dma_check = &cs5530_config_dma;
	334	if (!noautodma)
	335	hwif->autodma = 1;
	336	hwif->drives[0].autodma = hwif->autodma;
	337	hwif->drives[1].autodma = hwif->autodma;
	338	}
	339
	340	static ide_pci_device_t cs5530_chipset __devinitdata = {
	341	.name = "CS5530",
	342	.init_chipset = init_chipset_cs5530,
	343	.init_hwif = init_hwif_cs5530,
1da177e4 LT	344	.autodma = AUTODMA,
	345	.bootable = ON_BOARD,
	346	};
	347
	348	static int __devinit cs5530_init_one(struct pci_dev dev, const struct pci_device_id id)
	349	{
	350	return ide_setup_pci_device(dev, &cs5530_chipset);
	351	}
	352
	353	static struct pci_device_id cs5530_pci_tbl[] = {
	354	{ PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
	355	{ 0, },
	356	};
	357	MODULE_DEVICE_TABLE(pci, cs5530_pci_tbl);
	358
	359	static struct pci_driver driver = {
	360	.name = "CS5530 IDE",
	361	.id_table = cs5530_pci_tbl,
	362	.probe = cs5530_init_one,
	363	};
	364
82ab1eec	365	static int __init cs5530_ide_init(void)
1da177e4 LT	366	{
	367	return ide_pci_register_driver(&driver);
	368	}
	369
	370	module_init(cs5530_ide_init);
	371
	372	MODULE_AUTHOR("Mark Lord");
	373	MODULE_DESCRIPTION("PCI driver module for Cyrix/NS 5530 IDE");
	374	MODULE_LICENSE("GPL");