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Commit | Line | Data |
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7c7e92a9 AS |
1 | /* |
2 | * Palmchip bk3710 IDE controller | |
3 | * | |
4 | * Copyright (C) 2006 Texas Instruments. | |
5 | * Copyright (C) 2007 MontaVista Software, Inc., <source@mvista.com> | |
6 | * | |
7 | * ---------------------------------------------------------------------------- | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; either version 2 of the License, or | |
12 | * (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
22 | * ---------------------------------------------------------------------------- | |
23 | * | |
24 | */ | |
25 | ||
26 | #include <linux/types.h> | |
27 | #include <linux/module.h> | |
28 | #include <linux/kernel.h> | |
29 | #include <linux/ioport.h> | |
7c7e92a9 AS |
30 | #include <linux/ide.h> |
31 | #include <linux/delay.h> | |
32 | #include <linux/init.h> | |
33 | #include <linux/clk.h> | |
34 | #include <linux/platform_device.h> | |
35 | ||
36 | /* Offset of the primary interface registers */ | |
37 | #define IDE_PALM_ATA_PRI_REG_OFFSET 0x1F0 | |
38 | ||
39 | /* Primary Control Offset */ | |
40 | #define IDE_PALM_ATA_PRI_CTL_OFFSET 0x3F6 | |
41 | ||
7c7e92a9 AS |
42 | #define BK3710_BMICP 0x00 |
43 | #define BK3710_BMISP 0x02 | |
44 | #define BK3710_BMIDTP 0x04 | |
45 | #define BK3710_BMICS 0x08 | |
46 | #define BK3710_BMISS 0x0A | |
47 | #define BK3710_BMIDTS 0x0C | |
48 | #define BK3710_IDETIMP 0x40 | |
49 | #define BK3710_IDETIMS 0x42 | |
50 | #define BK3710_SIDETIM 0x44 | |
51 | #define BK3710_SLEWCTL 0x45 | |
52 | #define BK3710_IDESTATUS 0x47 | |
53 | #define BK3710_UDMACTL 0x48 | |
54 | #define BK3710_UDMATIM 0x4A | |
55 | #define BK3710_MISCCTL 0x50 | |
56 | #define BK3710_REGSTB 0x54 | |
57 | #define BK3710_REGRCVR 0x58 | |
58 | #define BK3710_DATSTB 0x5C | |
59 | #define BK3710_DATRCVR 0x60 | |
60 | #define BK3710_DMASTB 0x64 | |
61 | #define BK3710_DMARCVR 0x68 | |
62 | #define BK3710_UDMASTB 0x6C | |
63 | #define BK3710_UDMATRP 0x70 | |
64 | #define BK3710_UDMAENV 0x74 | |
65 | #define BK3710_IORDYTMP 0x78 | |
66 | #define BK3710_IORDYTMS 0x7C | |
67 | ||
ffab6cf4 | 68 | static unsigned ideclk_period; /* in nanoseconds */ |
7c7e92a9 | 69 | |
db2f38c2 DB |
70 | struct palm_bk3710_udmatiming { |
71 | unsigned int rptime; /* tRP -- Ready to pause time (nsec) */ | |
72 | unsigned int cycletime; /* tCYCTYP2/2 -- avg Cycle Time (nsec) */ | |
73 | /* tENV is always a minimum of 20 nsec */ | |
74 | }; | |
75 | ||
7c7e92a9 | 76 | static const struct palm_bk3710_udmatiming palm_bk3710_udmatimings[6] = { |
db2f38c2 DB |
77 | {160, 240 / 2,}, /* UDMA Mode 0 */ |
78 | {125, 160 / 2,}, /* UDMA Mode 1 */ | |
79 | {100, 120 / 2,}, /* UDMA Mode 2 */ | |
80 | {100, 90 / 2,}, /* UDMA Mode 3 */ | |
81 | {100, 60 / 2,}, /* UDMA Mode 4 */ | |
82 | {85, 40 / 2,}, /* UDMA Mode 5 */ | |
7c7e92a9 AS |
83 | }; |
84 | ||
7c7e92a9 AS |
85 | static void palm_bk3710_setudmamode(void __iomem *base, unsigned int dev, |
86 | unsigned int mode) | |
87 | { | |
88 | u8 tenv, trp, t0; | |
89 | u32 val32; | |
90 | u16 val16; | |
91 | ||
92 | /* DMA Data Setup */ | |
00fe8b7a | 93 | t0 = DIV_ROUND_UP(palm_bk3710_udmatimings[mode].cycletime, |
ffab6cf4 SS |
94 | ideclk_period) - 1; |
95 | tenv = DIV_ROUND_UP(20, ideclk_period) - 1; | |
00fe8b7a | 96 | trp = DIV_ROUND_UP(palm_bk3710_udmatimings[mode].rptime, |
ffab6cf4 | 97 | ideclk_period) - 1; |
7c7e92a9 AS |
98 | |
99 | /* udmatim Register */ | |
100 | val16 = readw(base + BK3710_UDMATIM) & (dev ? 0xFF0F : 0xFFF0); | |
101 | val16 |= (mode << (dev ? 4 : 0)); | |
102 | writew(val16, base + BK3710_UDMATIM); | |
103 | ||
104 | /* udmastb Ultra DMA Access Strobe Width */ | |
105 | val32 = readl(base + BK3710_UDMASTB) & (0xFF << (dev ? 0 : 8)); | |
106 | val32 |= (t0 << (dev ? 8 : 0)); | |
107 | writel(val32, base + BK3710_UDMASTB); | |
108 | ||
109 | /* udmatrp Ultra DMA Ready to Pause Time */ | |
110 | val32 = readl(base + BK3710_UDMATRP) & (0xFF << (dev ? 0 : 8)); | |
111 | val32 |= (trp << (dev ? 8 : 0)); | |
112 | writel(val32, base + BK3710_UDMATRP); | |
113 | ||
114 | /* udmaenv Ultra DMA envelop Time */ | |
115 | val32 = readl(base + BK3710_UDMAENV) & (0xFF << (dev ? 0 : 8)); | |
116 | val32 |= (tenv << (dev ? 8 : 0)); | |
117 | writel(val32, base + BK3710_UDMAENV); | |
118 | ||
119 | /* Enable UDMA for Device */ | |
120 | val16 = readw(base + BK3710_UDMACTL) | (1 << dev); | |
121 | writew(val16, base + BK3710_UDMACTL); | |
122 | } | |
123 | ||
124 | static void palm_bk3710_setdmamode(void __iomem *base, unsigned int dev, | |
125 | unsigned short min_cycle, | |
126 | unsigned int mode) | |
127 | { | |
128 | u8 td, tkw, t0; | |
129 | u32 val32; | |
130 | u16 val16; | |
131 | struct ide_timing *t; | |
132 | int cycletime; | |
133 | ||
134 | t = ide_timing_find_mode(mode); | |
135 | cycletime = max_t(int, t->cycle, min_cycle); | |
136 | ||
137 | /* DMA Data Setup */ | |
ffab6cf4 SS |
138 | t0 = DIV_ROUND_UP(cycletime, ideclk_period); |
139 | td = DIV_ROUND_UP(t->active, ideclk_period); | |
7c7e92a9 AS |
140 | tkw = t0 - td - 1; |
141 | td -= 1; | |
142 | ||
143 | val32 = readl(base + BK3710_DMASTB) & (0xFF << (dev ? 0 : 8)); | |
144 | val32 |= (td << (dev ? 8 : 0)); | |
145 | writel(val32, base + BK3710_DMASTB); | |
146 | ||
147 | val32 = readl(base + BK3710_DMARCVR) & (0xFF << (dev ? 0 : 8)); | |
148 | val32 |= (tkw << (dev ? 8 : 0)); | |
149 | writel(val32, base + BK3710_DMARCVR); | |
150 | ||
151 | /* Disable UDMA for Device */ | |
152 | val16 = readw(base + BK3710_UDMACTL) & ~(1 << dev); | |
153 | writew(val16, base + BK3710_UDMACTL); | |
154 | } | |
155 | ||
156 | static void palm_bk3710_setpiomode(void __iomem *base, ide_drive_t *mate, | |
157 | unsigned int dev, unsigned int cycletime, | |
158 | unsigned int mode) | |
159 | { | |
160 | u8 t2, t2i, t0; | |
161 | u32 val32; | |
162 | struct ide_timing *t; | |
163 | ||
164 | /* PIO Data Setup */ | |
ffab6cf4 | 165 | t0 = DIV_ROUND_UP(cycletime, ideclk_period); |
00fe8b7a | 166 | t2 = DIV_ROUND_UP(ide_timing_find_mode(XFER_PIO_0 + mode)->active, |
ffab6cf4 | 167 | ideclk_period); |
7c7e92a9 AS |
168 | |
169 | t2i = t0 - t2 - 1; | |
170 | t2 -= 1; | |
171 | ||
172 | val32 = readl(base + BK3710_DATSTB) & (0xFF << (dev ? 0 : 8)); | |
173 | val32 |= (t2 << (dev ? 8 : 0)); | |
174 | writel(val32, base + BK3710_DATSTB); | |
175 | ||
176 | val32 = readl(base + BK3710_DATRCVR) & (0xFF << (dev ? 0 : 8)); | |
177 | val32 |= (t2i << (dev ? 8 : 0)); | |
178 | writel(val32, base + BK3710_DATRCVR); | |
179 | ||
7e59ea21 | 180 | if (mate) { |
7c7e92a9 AS |
181 | u8 mode2 = ide_get_best_pio_mode(mate, 255, 4); |
182 | ||
183 | if (mode2 < mode) | |
184 | mode = mode2; | |
185 | } | |
186 | ||
187 | /* TASKFILE Setup */ | |
188 | t = ide_timing_find_mode(XFER_PIO_0 + mode); | |
ffab6cf4 SS |
189 | t0 = DIV_ROUND_UP(t->cyc8b, ideclk_period); |
190 | t2 = DIV_ROUND_UP(t->act8b, ideclk_period); | |
7c7e92a9 AS |
191 | |
192 | t2i = t0 - t2 - 1; | |
193 | t2 -= 1; | |
194 | ||
195 | val32 = readl(base + BK3710_REGSTB) & (0xFF << (dev ? 0 : 8)); | |
196 | val32 |= (t2 << (dev ? 8 : 0)); | |
197 | writel(val32, base + BK3710_REGSTB); | |
198 | ||
199 | val32 = readl(base + BK3710_REGRCVR) & (0xFF << (dev ? 0 : 8)); | |
200 | val32 |= (t2i << (dev ? 8 : 0)); | |
201 | writel(val32, base + BK3710_REGRCVR); | |
202 | } | |
203 | ||
204 | static void palm_bk3710_set_dma_mode(ide_drive_t *drive, u8 xferspeed) | |
205 | { | |
206 | int is_slave = drive->dn & 1; | |
207 | void __iomem *base = (void *)drive->hwif->dma_base; | |
208 | ||
209 | if (xferspeed >= XFER_UDMA_0) { | |
210 | palm_bk3710_setudmamode(base, is_slave, | |
211 | xferspeed - XFER_UDMA_0); | |
212 | } else { | |
4dde4492 BZ |
213 | palm_bk3710_setdmamode(base, is_slave, |
214 | drive->id[ATA_ID_EIDE_DMA_MIN], | |
7c7e92a9 AS |
215 | xferspeed); |
216 | } | |
217 | } | |
218 | ||
219 | static void palm_bk3710_set_pio_mode(ide_drive_t *drive, u8 pio) | |
220 | { | |
221 | unsigned int cycle_time; | |
222 | int is_slave = drive->dn & 1; | |
223 | ide_drive_t *mate; | |
224 | void __iomem *base = (void *)drive->hwif->dma_base; | |
225 | ||
226 | /* | |
227 | * Obtain the drive PIO data for tuning the Palm Chip registers | |
228 | */ | |
229 | cycle_time = ide_pio_cycle_time(drive, pio); | |
7e59ea21 | 230 | mate = ide_get_pair_dev(drive); |
7c7e92a9 AS |
231 | palm_bk3710_setpiomode(base, mate, is_slave, cycle_time, pio); |
232 | } | |
233 | ||
234 | static void __devinit palm_bk3710_chipinit(void __iomem *base) | |
235 | { | |
236 | /* | |
237 | * enable the reset_en of ATA controller so that when ata signals | |
238 | * are brought out, by writing into device config. at that | |
239 | * time por_n signal should not be 'Z' and have a stable value. | |
240 | */ | |
241 | writel(0x0300, base + BK3710_MISCCTL); | |
242 | ||
243 | /* wait for some time and deassert the reset of ATA Device. */ | |
244 | mdelay(100); | |
245 | ||
246 | /* Deassert the Reset */ | |
247 | writel(0x0200, base + BK3710_MISCCTL); | |
248 | ||
249 | /* | |
250 | * Program the IDETIMP Register Value based on the following assumptions | |
251 | * | |
252 | * (ATA_IDETIMP_IDEEN , ENABLE ) | | |
253 | * (ATA_IDETIMP_SLVTIMEN , DISABLE) | | |
254 | * (ATA_IDETIMP_RDYSMPL , 70NS) | | |
255 | * (ATA_IDETIMP_RDYRCVRY , 50NS) | | |
256 | * (ATA_IDETIMP_DMAFTIM1 , PIOCOMP) | | |
257 | * (ATA_IDETIMP_PREPOST1 , DISABLE) | | |
258 | * (ATA_IDETIMP_RDYSEN1 , DISABLE) | | |
259 | * (ATA_IDETIMP_PIOFTIM1 , DISABLE) | | |
260 | * (ATA_IDETIMP_DMAFTIM0 , PIOCOMP) | | |
261 | * (ATA_IDETIMP_PREPOST0 , DISABLE) | | |
262 | * (ATA_IDETIMP_RDYSEN0 , DISABLE) | | |
263 | * (ATA_IDETIMP_PIOFTIM0 , DISABLE) | |
264 | */ | |
265 | writew(0xB388, base + BK3710_IDETIMP); | |
266 | ||
267 | /* | |
268 | * Configure SIDETIM Register | |
269 | * (ATA_SIDETIM_RDYSMPS1 ,120NS ) | | |
270 | * (ATA_SIDETIM_RDYRCYS1 ,120NS ) | |
271 | */ | |
272 | writeb(0, base + BK3710_SIDETIM); | |
273 | ||
274 | /* | |
275 | * UDMACTL Ultra-ATA DMA Control | |
276 | * (ATA_UDMACTL_UDMAP1 , 0 ) | | |
277 | * (ATA_UDMACTL_UDMAP0 , 0 ) | |
278 | * | |
279 | */ | |
280 | writew(0, base + BK3710_UDMACTL); | |
281 | ||
282 | /* | |
283 | * MISCCTL Miscellaneous Conrol Register | |
284 | * (ATA_MISCCTL_RSTMODEP , 1) | | |
285 | * (ATA_MISCCTL_RESETP , 0) | | |
286 | * (ATA_MISCCTL_TIMORIDE , 1) | |
287 | */ | |
288 | writel(0x201, base + BK3710_MISCCTL); | |
289 | ||
290 | /* | |
291 | * IORDYTMP IORDY Timer for Primary Register | |
292 | * (ATA_IORDYTMP_IORDYTMP , 0xffff ) | |
293 | */ | |
294 | writel(0xFFFF, base + BK3710_IORDYTMP); | |
295 | ||
296 | /* | |
297 | * Configure BMISP Register | |
298 | * (ATA_BMISP_DMAEN1 , DISABLE ) | | |
299 | * (ATA_BMISP_DMAEN0 , DISABLE ) | | |
300 | * (ATA_BMISP_IORDYINT , CLEAR) | | |
301 | * (ATA_BMISP_INTRSTAT , CLEAR) | | |
302 | * (ATA_BMISP_DMAERROR , CLEAR) | |
303 | */ | |
304 | writew(0, base + BK3710_BMISP); | |
305 | ||
306 | palm_bk3710_setpiomode(base, NULL, 0, 600, 0); | |
307 | palm_bk3710_setpiomode(base, NULL, 1, 600, 0); | |
308 | } | |
c79b60dd | 309 | |
f454cbe8 | 310 | static u8 palm_bk3710_cable_detect(ide_hwif_t *hwif) |
c79b60dd BZ |
311 | { |
312 | return ATA_CBL_PATA80; | |
313 | } | |
314 | ||
b552a2c1 BZ |
315 | static int __devinit palm_bk3710_init_dma(ide_hwif_t *hwif, |
316 | const struct ide_port_info *d) | |
317 | { | |
b552a2c1 BZ |
318 | printk(KERN_INFO " %s: MMIO-DMA\n", hwif->name); |
319 | ||
320 | if (ide_allocate_dma_engine(hwif)) | |
321 | return -1; | |
322 | ||
81e8d5a3 BZ |
323 | hwif->dma_base = hwif->io_ports.data_addr - IDE_PALM_ATA_PRI_REG_OFFSET; |
324 | ||
b552a2c1 BZ |
325 | return 0; |
326 | } | |
327 | ||
ac95beed BZ |
328 | static const struct ide_port_ops palm_bk3710_ports_ops = { |
329 | .set_pio_mode = palm_bk3710_set_pio_mode, | |
330 | .set_dma_mode = palm_bk3710_set_dma_mode, | |
331 | .cable_detect = palm_bk3710_cable_detect, | |
332 | }; | |
c79b60dd | 333 | |
a0f403bc | 334 | static struct ide_port_info __devinitdata palm_bk3710_port_info = { |
b552a2c1 | 335 | .init_dma = palm_bk3710_init_dma, |
ac95beed | 336 | .port_ops = &palm_bk3710_ports_ops, |
3f023b01 | 337 | .dma_ops = &sff_dma_ops, |
c5dd43ec | 338 | .host_flags = IDE_HFLAG_MMIO, |
c79b60dd | 339 | .pio_mask = ATA_PIO4, |
c79b60dd BZ |
340 | .mwdma_mask = ATA_MWDMA2, |
341 | }; | |
342 | ||
bfc2f01f | 343 | static int __init palm_bk3710_probe(struct platform_device *pdev) |
7c7e92a9 | 344 | { |
ffab6cf4 | 345 | struct clk *clk; |
7c7e92a9 | 346 | struct resource *mem, *irq; |
ef183f6b | 347 | void __iomem *base; |
13b8860d | 348 | unsigned long rate, mem_size; |
6f904d01 | 349 | int i, rc; |
c97c6aca | 350 | hw_regs_t hw, *hws[] = { &hw, NULL, NULL, NULL }; |
7c7e92a9 | 351 | |
a0f403bc | 352 | clk = clk_get(&pdev->dev, "IDECLK"); |
ffab6cf4 | 353 | if (IS_ERR(clk)) |
7c7e92a9 AS |
354 | return -ENODEV; |
355 | ||
ffab6cf4 SS |
356 | clk_enable(clk); |
357 | rate = clk_get_rate(clk); | |
358 | ideclk_period = 1000000000UL / rate; | |
359 | ||
7c7e92a9 | 360 | /* Register the IDE interface with Linux ATA Interface */ |
7824bc6b | 361 | memset(&hw, 0, sizeof(hw)); |
7c7e92a9 AS |
362 | |
363 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
364 | if (mem == NULL) { | |
365 | printk(KERN_ERR "failed to get memory region resource\n"); | |
366 | return -ENODEV; | |
367 | } | |
ce42a549 | 368 | |
7c7e92a9 AS |
369 | irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
370 | if (irq == NULL) { | |
371 | printk(KERN_ERR "failed to get IRQ resource\n"); | |
372 | return -ENODEV; | |
373 | } | |
374 | ||
13b8860d KH |
375 | mem_size = mem->end - mem->start + 1; |
376 | if (request_mem_region(mem->start, mem_size, "palm_bk3710") == NULL) { | |
ce42a549 SS |
377 | printk(KERN_ERR "failed to request memory region\n"); |
378 | return -EBUSY; | |
379 | } | |
380 | ||
13b8860d KH |
381 | base = ioremap(mem->start, mem_size); |
382 | if (!base) { | |
383 | printk(KERN_ERR "failed to map IO memory\n"); | |
384 | release_mem_region(mem->start, mem_size); | |
385 | return -ENOMEM; | |
386 | } | |
7c7e92a9 AS |
387 | |
388 | /* Configure the Palm Chip controller */ | |
ef183f6b | 389 | palm_bk3710_chipinit(base); |
7c7e92a9 | 390 | |
7824bc6b | 391 | for (i = 0; i < IDE_NR_PORTS - 2; i++) |
ef183f6b DB |
392 | hw.io_ports_array[i] = (unsigned long) |
393 | (base + IDE_PALM_ATA_PRI_REG_OFFSET + i); | |
394 | hw.io_ports.ctl_addr = (unsigned long) | |
395 | (base + IDE_PALM_ATA_PRI_CTL_OFFSET); | |
7824bc6b | 396 | hw.irq = irq->start; |
bfc2f01f | 397 | hw.dev = &pdev->dev; |
7824bc6b | 398 | hw.chipset = ide_palm3710; |
7c7e92a9 | 399 | |
a0f403bc SS |
400 | palm_bk3710_port_info.udma_mask = rate < 100000000 ? ATA_UDMA4 : |
401 | ATA_UDMA5; | |
402 | ||
6f904d01 BZ |
403 | rc = ide_host_add(&palm_bk3710_port_info, hws, NULL); |
404 | if (rc) | |
7824bc6b BZ |
405 | goto out; |
406 | ||
7c7e92a9 | 407 | return 0; |
7824bc6b BZ |
408 | out: |
409 | printk(KERN_WARNING "Palm Chip BK3710 IDE Register Fail\n"); | |
6f904d01 | 410 | return rc; |
7c7e92a9 AS |
411 | } |
412 | ||
458622fc KS |
413 | /* work with hotplug and coldplug */ |
414 | MODULE_ALIAS("platform:palm_bk3710"); | |
415 | ||
7c7e92a9 AS |
416 | static struct platform_driver platform_bk_driver = { |
417 | .driver = { | |
418 | .name = "palm_bk3710", | |
458622fc | 419 | .owner = THIS_MODULE, |
7c7e92a9 | 420 | }, |
7c7e92a9 AS |
421 | }; |
422 | ||
423 | static int __init palm_bk3710_init(void) | |
424 | { | |
bfc2f01f | 425 | return platform_driver_probe(&platform_bk_driver, palm_bk3710_probe); |
7c7e92a9 AS |
426 | } |
427 | ||
428 | module_init(palm_bk3710_init); | |
429 | MODULE_LICENSE("GPL"); |