[net-next-2.6.git] / drivers / ide / ns87415.c

/*
 * Copyright (C) 1997-1998	Mark Lord <mlord@pobox.com>
 * Copyright (C) 1998		Eddie C. Dost <ecd@skynet.be>
 * Copyright (C) 1999-2000	Andre Hedrick <andre@linux-ide.org>
 * Copyright (C) 2004		Grant Grundler <grundler at parisc-linux.org>
 *
 * Inspired by an earlier effort from David S. Miller <davem@redhat.com>
 */

#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/pci.h>
#include <linux/delay.h>
#include <linux/ide.h>
#include <linux/init.h>

#include <asm/io.h>

#define DRV_NAME "ns87415"

#ifdef CONFIG_SUPERIO
/* SUPERIO 87560 is a PoS chip that NatSem denies exists.
 * Unfortunately, it's built-in on all Astro-based PA-RISC workstations
 * which use the integrated NS87514 cell for CD-ROM support.
 * i.e we have to support for CD-ROM installs.
 * See drivers/parisc/superio.c for more gory details.
 */
#include <asm/superio.h>

#define SUPERIO_IDE_MAX_RETRIES 25

/* Because of a defect in Super I/O, all reads of the PCI DMA status 
 * registers, IDE status register and the IDE select register need to be 
 * retried
 */
static u8 superio_ide_inb (unsigned long port)
{
	u8 tmp;
	int retries = SUPERIO_IDE_MAX_RETRIES;

	/* printk(" [ reading port 0x%x with retry ] ", port); */

	do {
		tmp = inb(port);
		if (tmp == 0)
			udelay(50);
	} while (tmp == 0 && retries-- > 0);

	return tmp;
}

static u8 superio_read_status(ide_hwif_t *hwif)
{
	return superio_ide_inb(hwif->io_ports.status_addr);
}

static u8 superio_dma_sff_read_status(ide_hwif_t *hwif)
{
	return superio_ide_inb(hwif->dma_base + ATA_DMA_STATUS);
}

static void superio_tf_read(ide_drive_t *drive, struct ide_cmd *cmd)
{
	struct ide_io_ports *io_ports = &drive->hwif->io_ports;
	struct ide_taskfile *tf = &cmd->tf;

	/* be sure we're looking at the low order bits */
	outb(ATA_DEVCTL_OBS, io_ports->ctl_addr);

	if (cmd->tf_flags & IDE_TFLAG_IN_ERROR)
		tf->error  = inb(io_ports->feature_addr);
	if (cmd->tf_flags & IDE_TFLAG_IN_NSECT)
		tf->nsect  = inb(io_ports->nsect_addr);
	if (cmd->tf_flags & IDE_TFLAG_IN_LBAL)
		tf->lbal   = inb(io_ports->lbal_addr);
	if (cmd->tf_flags & IDE_TFLAG_IN_LBAM)
		tf->lbam   = inb(io_ports->lbam_addr);
	if (cmd->tf_flags & IDE_TFLAG_IN_LBAH)
		tf->lbah   = inb(io_ports->lbah_addr);
	if (cmd->tf_flags & IDE_TFLAG_IN_DEVICE)
		tf->device = superio_ide_inb(io_ports->device_addr);

	if (cmd->tf_flags & IDE_TFLAG_LBA48) {
		outb(ATA_HOB | ATA_DEVCTL_OBS, io_ports->ctl_addr);

		if (cmd->tf_flags & IDE_TFLAG_IN_HOB_ERROR)
			tf->hob_error = inb(io_ports->feature_addr);
		if (cmd->tf_flags & IDE_TFLAG_IN_HOB_NSECT)
			tf->hob_nsect = inb(io_ports->nsect_addr);
		if (cmd->tf_flags & IDE_TFLAG_IN_HOB_LBAL)
			tf->hob_lbal  = inb(io_ports->lbal_addr);
		if (cmd->tf_flags & IDE_TFLAG_IN_HOB_LBAM)
			tf->hob_lbam  = inb(io_ports->lbam_addr);
		if (cmd->tf_flags & IDE_TFLAG_IN_HOB_LBAH)
			tf->hob_lbah  = inb(io_ports->lbah_addr);
	}
}

static const struct ide_tp_ops superio_tp_ops = {
	.exec_command		= ide_exec_command,
	.read_status		= superio_read_status,
	.read_altstatus		= ide_read_altstatus,
	.write_devctl		= ide_write_devctl,

	.tf_load		= ide_tf_load,
	.tf_read		= superio_tf_read,

	.input_data		= ide_input_data,
	.output_data		= ide_output_data,
};

static void __devinit superio_init_iops(struct hwif_s *hwif)
{
	struct pci_dev *pdev = to_pci_dev(hwif->dev);
	u32 dma_stat;
	u8 port = hwif->channel, tmp;

	dma_stat = (pci_resource_start(pdev, 4) & ~3) + (!port ? 2 : 0xa);

	/* Clear error/interrupt, enable dma */
	tmp = superio_ide_inb(dma_stat);
	outb(tmp | 0x66, dma_stat);
}
#else
#define superio_dma_sff_read_status ide_dma_sff_read_status
#endif

static unsigned int ns87415_count = 0, ns87415_control[MAX_HWIFS] = { 0 };

/*
 * This routine either enables/disables (according to IDE_DFLAG_PRESENT)
 * the IRQ associated with the port,
 * and selects either PIO or DMA handshaking for the next I/O operation.
 */
static void ns87415_prepare_drive (ide_drive_t *drive, unsigned int use_dma)
{
	ide_hwif_t *hwif = drive->hwif;
	struct pci_dev *dev = to_pci_dev(hwif->dev);
	unsigned int bit, other, new, *old = (unsigned int *) hwif->select_data;
	unsigned long flags;

	local_irq_save(flags);
	new = *old;

	/* Adjust IRQ enable bit */
	bit = 1 << (8 + hwif->channel);

	if (drive->dev_flags & IDE_DFLAG_PRESENT)
		new &= ~bit;
	else
		new |= bit;

	/* Select PIO or DMA, DMA may only be selected for one drive/channel. */
	bit   = 1 << (20 + (drive->dn & 1) + (hwif->channel << 1));
	other = 1 << (20 + (1 - (drive->dn & 1)) + (hwif->channel << 1));
	new = use_dma ? ((new & ~other) | bit) : (new & ~bit);

	if (new != *old) {
		unsigned char stat;

		/*
		 * Don't change DMA engine settings while Write Buffers
		 * are busy.
		 */
		(void) pci_read_config_byte(dev, 0x43, &stat);
		while (stat & 0x03) {
			udelay(1);
			(void) pci_read_config_byte(dev, 0x43, &stat);
		}

		*old = new;
		(void) pci_write_config_dword(dev, 0x40, new);

		/*
		 * And let things settle...
		 */
		udelay(10);
	}

	local_irq_restore(flags);
}

static void ns87415_selectproc (ide_drive_t *drive)
{
	ns87415_prepare_drive(drive,
			      !!(drive->dev_flags & IDE_DFLAG_USING_DMA));
}

static void ns87415_dma_start(ide_drive_t *drive)
{
	ns87415_prepare_drive(drive, 1);
	ide_dma_start(drive);
}

static int ns87415_dma_end(ide_drive_t *drive)
{
	ide_hwif_t *hwif = drive->hwif;
	u8 dma_stat = 0, dma_cmd = 0;

	dma_stat = hwif->dma_ops->dma_sff_read_status(hwif);
	/* get DMA command mode */
	dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
	/* stop DMA */
	outb(dma_cmd & ~1, hwif->dma_base + ATA_DMA_CMD);
	/* from ERRATA: clear the INTR & ERROR bits */
	dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
	outb(dma_cmd | 6, hwif->dma_base + ATA_DMA_CMD);

	ns87415_prepare_drive(drive, 0);

	/* verify good DMA status */
	return (dma_stat & 7) != 4;
}

static void __devinit init_hwif_ns87415 (ide_hwif_t *hwif)
{
	struct pci_dev *dev = to_pci_dev(hwif->dev);
	unsigned int ctrl, using_inta;
	u8 progif;
#ifdef __sparc_v9__
	int timeout;
	u8 stat;
#endif

	/*
	 * We cannot probe for IRQ: both ports share common IRQ on INTA.
	 * Also, leave IRQ masked during drive probing, to prevent infinite
	 * interrupts from a potentially floating INTA..
	 *
	 * IRQs get unmasked in selectproc when drive is first used.
	 */
	(void) pci_read_config_dword(dev, 0x40, &ctrl);
	(void) pci_read_config_byte(dev, 0x09, &progif);
	/* is irq in "native" mode? */
	using_inta = progif & (1 << (hwif->channel << 1));
	if (!using_inta)
		using_inta = ctrl & (1 << (4 + hwif->channel));
	if (hwif->mate) {
		hwif->select_data = hwif->mate->select_data;
	} else {
		hwif->select_data = (unsigned long)
					&ns87415_control[ns87415_count++];
		ctrl |= (1 << 8) | (1 << 9);	/* mask both IRQs */
		if (using_inta)
			ctrl &= ~(1 << 6);	/* unmask INTA */
		*((unsigned int *)hwif->select_data) = ctrl;
		(void) pci_write_config_dword(dev, 0x40, ctrl);

		/*
		 * Set prefetch size to 512 bytes for both ports,
		 * but don't turn on/off prefetching here.
		 */
		pci_write_config_byte(dev, 0x55, 0xee);

#ifdef __sparc_v9__
		/*
		 * XXX: Reset the device, if we don't it will not respond to
		 *      SELECT_DRIVE() properly during first ide_probe_port().
		 */
		timeout = 10000;
		outb(12, hwif->io_ports.ctl_addr);
		udelay(10);
		outb(8, hwif->io_ports.ctl_addr);
		do {
			udelay(50);
			stat = hwif->tp_ops->read_status(hwif);
			if (stat == 0xff)
				break;
		} while ((stat & ATA_BUSY) && --timeout);
#endif
	}

	if (!using_inta)
		hwif->irq = pci_get_legacy_ide_irq(dev, hwif->channel);

	if (!hwif->dma_base)
		return;

	outb(0x60, hwif->dma_base + ATA_DMA_STATUS);
}

static const struct ide_port_ops ns87415_port_ops = {
	.selectproc		= ns87415_selectproc,
};

static const struct ide_dma_ops ns87415_dma_ops = {
	.dma_host_set		= ide_dma_host_set,
	.dma_setup		= ide_dma_setup,
	.dma_start		= ns87415_dma_start,
	.dma_end		= ns87415_dma_end,
	.dma_test_irq		= ide_dma_test_irq,
	.dma_lost_irq		= ide_dma_lost_irq,
	.dma_timer_expiry	= ide_dma_sff_timer_expiry,
	.dma_sff_read_status	= superio_dma_sff_read_status,
};

static const struct ide_port_info ns87415_chipset __devinitdata = {
	.name		= DRV_NAME,
	.init_hwif	= init_hwif_ns87415,
	.port_ops	= &ns87415_port_ops,
	.dma_ops	= &ns87415_dma_ops,
	.host_flags	= IDE_HFLAG_TRUST_BIOS_FOR_DMA |
			  IDE_HFLAG_NO_ATAPI_DMA,
};

static int __devinit ns87415_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	struct ide_port_info d = ns87415_chipset;

#ifdef CONFIG_SUPERIO
	if (PCI_SLOT(dev->devfn) == 0xE) {
		/* Built-in - assume it's under superio. */
		d.init_iops = superio_init_iops;
		d.tp_ops = &superio_tp_ops;
	}
#endif
	return ide_pci_init_one(dev, &d, NULL);
}

static const struct pci_device_id ns87415_pci_tbl[] = {
	{ PCI_VDEVICE(NS, PCI_DEVICE_ID_NS_87415), 0 },
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, ns87415_pci_tbl);

static struct pci_driver ns87415_pci_driver = {
	.name		= "NS87415_IDE",
	.id_table	= ns87415_pci_tbl,
	.probe		= ns87415_init_one,
	.remove		= ide_pci_remove,
	.suspend	= ide_pci_suspend,
	.resume		= ide_pci_resume,
};

static int __init ns87415_ide_init(void)
{
	return ide_pci_register_driver(&ns87415_pci_driver);
}

static void __exit ns87415_ide_exit(void)
{
	pci_unregister_driver(&ns87415_pci_driver);
}

module_init(ns87415_ide_init);
module_exit(ns87415_ide_exit);

MODULE_AUTHOR("Mark Lord, Eddie Dost, Andre Hedrick");
MODULE_DESCRIPTION("PCI driver module for NS87415 IDE");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4	1	/*
1da177e4 LT	2	* Copyright (C) 1997-1998 Mark Lord <mlord@pobox.com>
	3	* Copyright (C) 1998 Eddie C. Dost <ecd@skynet.be>
	4	* Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org>
	5	* Copyright (C) 2004 Grant Grundler <grundler at parisc-linux.org>
	6	*
	7	* Inspired by an earlier effort from David S. Miller <davem@redhat.com>
	8	*/
	9
1da177e4 LT	10	#include <linux/module.h>
	11	#include <linux/types.h>
	12	#include <linux/kernel.h>
1da177e4	13	#include <linux/interrupt.h>
1da177e4 LT	14	#include <linux/pci.h>
	15	#include <linux/delay.h>
	16	#include <linux/ide.h>
	17	#include <linux/init.h>
	18
	19	#include <asm/io.h>
	20
ced3ec8a BZ	21	#define DRV_NAME "ns87415"
ced3ec8a BZ	22
1da177e4 LT	23	#ifdef CONFIG_SUPERIO
	24	/* SUPERIO 87560 is a PoS chip that NatSem denies exists.
	25	* Unfortunately, it's built-in on all Astro-based PA-RISC workstations
	26	* which use the integrated NS87514 cell for CD-ROM support.
	27	* i.e we have to support for CD-ROM installs.
	28	* See drivers/parisc/superio.c for more gory details.
	29	*/
	30	#include <asm/superio.h>
	31
1da177e4 LT	32	#define SUPERIO_IDE_MAX_RETRIES 25
	33
	34	/* Because of a defect in Super I/O, all reads of the PCI DMA status
	35	* registers, IDE status register and the IDE select register need to be
	36	* retried
	37	*/
	38	static u8 superio_ide_inb (unsigned long port)
	39	{
761052e6 BZ	40	u8 tmp;
	41	int retries = SUPERIO_IDE_MAX_RETRIES;
	42
	43	/* printk(" [ reading port 0x%x with retry ] ", port); */
1da177e4	44
761052e6 BZ	45	do {
	46	tmp = inb(port);
	47	if (tmp == 0)
	48	udelay(50);
	49	} while (tmp == 0 && retries-- > 0);
	50
	51	return tmp;
1da177e4 LT	52	}
1da177e4 LT	53
b73c7ee2 BZ	54	static u8 superio_read_status(ide_hwif_t *hwif)
	55	{
	56	return superio_ide_inb(hwif->io_ports.status_addr);
	57	}
	58
592b5315	59	static u8 superio_dma_sff_read_status(ide_hwif_t *hwif)
b2f951aa	60	{
cab7f8ed	61	return superio_ide_inb(hwif->dma_base + ATA_DMA_STATUS);
b2f951aa BZ	62	}
b2f951aa BZ	63
22aa4b32	64	static void superio_tf_read(ide_drive_t drive, struct ide_cmd cmd)
ea23b8ba BZ	65	{
ea23b8ba BZ	66	struct ide_io_ports *io_ports = &drive->hwif->io_ports;
22aa4b32	67	struct ide_taskfile *tf = &cmd->tf;
ea23b8ba	68
ea23b8ba	69	/* be sure we're looking at the low order bits */
4d74c3fc	70	outb(ATA_DEVCTL_OBS, io_ports->ctl_addr);
ea23b8ba	71
67625119 SS	72	if (cmd->tf_flags & IDE_TFLAG_IN_ERROR)
67625119 SS	73	tf->error = inb(io_ports->feature_addr);
22aa4b32	74	if (cmd->tf_flags & IDE_TFLAG_IN_NSECT)
ea23b8ba	75	tf->nsect = inb(io_ports->nsect_addr);
22aa4b32	76	if (cmd->tf_flags & IDE_TFLAG_IN_LBAL)
ea23b8ba	77	tf->lbal = inb(io_ports->lbal_addr);
22aa4b32	78	if (cmd->tf_flags & IDE_TFLAG_IN_LBAM)
ea23b8ba	79	tf->lbam = inb(io_ports->lbam_addr);
22aa4b32	80	if (cmd->tf_flags & IDE_TFLAG_IN_LBAH)
ea23b8ba	81	tf->lbah = inb(io_ports->lbah_addr);
22aa4b32	82	if (cmd->tf_flags & IDE_TFLAG_IN_DEVICE)
ea23b8ba BZ	83	tf->device = superio_ide_inb(io_ports->device_addr);
ea23b8ba BZ	84
22aa4b32	85	if (cmd->tf_flags & IDE_TFLAG_LBA48) {
4d74c3fc	86	outb(ATA_HOB \| ATA_DEVCTL_OBS, io_ports->ctl_addr);
ea23b8ba	87
67625119 SS	88	if (cmd->tf_flags & IDE_TFLAG_IN_HOB_ERROR)
67625119 SS	89	tf->hob_error = inb(io_ports->feature_addr);
22aa4b32	90	if (cmd->tf_flags & IDE_TFLAG_IN_HOB_NSECT)
67625119	91	tf->hob_nsect = inb(io_ports->nsect_addr);
22aa4b32	92	if (cmd->tf_flags & IDE_TFLAG_IN_HOB_LBAL)
67625119	93	tf->hob_lbal = inb(io_ports->lbal_addr);
22aa4b32	94	if (cmd->tf_flags & IDE_TFLAG_IN_HOB_LBAM)
67625119	95	tf->hob_lbam = inb(io_ports->lbam_addr);
22aa4b32	96	if (cmd->tf_flags & IDE_TFLAG_IN_HOB_LBAH)
67625119	97	tf->hob_lbah = inb(io_ports->lbah_addr);
ea23b8ba BZ	98	}
	99	}
	100
374e042c BZ	101	static const struct ide_tp_ops superio_tp_ops = {
	102	.exec_command = ide_exec_command,
	103	.read_status = superio_read_status,
	104	.read_altstatus = ide_read_altstatus,
ecf3a31d	105	.write_devctl = ide_write_devctl,
374e042c BZ	106
	107	.tf_load = ide_tf_load,
	108	.tf_read = superio_tf_read,
	109
	110	.input_data = ide_input_data,
	111	.output_data = ide_output_data,
	112	};
	113
	114	static void __devinit superio_init_iops(struct hwif_s *hwif)
1da177e4	115	{
36501650	116	struct pci_dev *pdev = to_pci_dev(hwif->dev);
761052e6	117	u32 dma_stat;
36501650	118	u8 port = hwif->channel, tmp;
1da177e4	119
761052e6	120	dma_stat = (pci_resource_start(pdev, 4) & ~3) + (!port ? 2 : 0xa);
1da177e4 LT	121
1da177e4 LT	122	/* Clear error/interrupt, enable dma */
761052e6 BZ	123	tmp = superio_ide_inb(dma_stat);
761052e6 BZ	124	outb(tmp \| 0x66, dma_stat);
1da177e4	125	}
592b5315 SS	126	#else
592b5315 SS	127	#define superio_dma_sff_read_status ide_dma_sff_read_status
1da177e4 LT	128	#endif
	129
	130	static unsigned int ns87415_count = 0, ns87415_control[MAX_HWIFS] = { 0 };
	131
	132	/*
97100fc8	133	* This routine either enables/disables (according to IDE_DFLAG_PRESENT)
898ec223	134	* the IRQ associated with the port,
1da177e4 LT	135	* and selects either PIO or DMA handshaking for the next I/O operation.
	136	*/
	137	static void ns87415_prepare_drive (ide_drive_t *drive, unsigned int use_dma)
	138	{
898ec223	139	ide_hwif_t *hwif = drive->hwif;
36501650	140	struct pci_dev *dev = to_pci_dev(hwif->dev);
1da177e4	141	unsigned int bit, other, new, old = (unsigned int ) hwif->select_data;
1da177e4 LT	142	unsigned long flags;
	143
	144	local_irq_save(flags);
	145	new = *old;
	146
	147	/* Adjust IRQ enable bit */
	148	bit = 1 << (8 + hwif->channel);
97100fc8 BZ	149
	150	if (drive->dev_flags & IDE_DFLAG_PRESENT)
	151	new &= ~bit;
	152	else
	153	new \|= bit;
1da177e4 LT	154
1da177e4 LT	155	/* Select PIO or DMA, DMA may only be selected for one drive/channel. */
123995b9 BZ	156	bit = 1 << (20 + (drive->dn & 1) + (hwif->channel << 1));
123995b9 BZ	157	other = 1 << (20 + (1 - (drive->dn & 1)) + (hwif->channel << 1));
1da177e4 LT	158	new = use_dma ? ((new & ~other) \| bit) : (new & ~bit);
	159
	160	if (new != *old) {
	161	unsigned char stat;
	162
	163	/*
	164	* Don't change DMA engine settings while Write Buffers
	165	* are busy.
	166	*/
	167	(void) pci_read_config_byte(dev, 0x43, &stat);
	168	while (stat & 0x03) {
	169	udelay(1);
	170	(void) pci_read_config_byte(dev, 0x43, &stat);
	171	}
	172
	173	*old = new;
	174	(void) pci_write_config_dword(dev, 0x40, new);
	175
	176	/*
	177	* And let things settle...
	178	*/
	179	udelay(10);
	180	}
	181
	182	local_irq_restore(flags);
	183	}
	184
	185	static void ns87415_selectproc (ide_drive_t *drive)
	186	{
97100fc8 BZ	187	ns87415_prepare_drive(drive,
97100fc8 BZ	188	!!(drive->dev_flags & IDE_DFLAG_USING_DMA));
1da177e4 LT	189	}
1da177e4 LT	190
a6d67ffa BZ	191	static void ns87415_dma_start(ide_drive_t *drive)
	192	{
	193	ns87415_prepare_drive(drive, 1);
	194	ide_dma_start(drive);
	195	}
	196
5e37bdc0	197	static int ns87415_dma_end(ide_drive_t *drive)
1da177e4	198	{
898ec223	199	ide_hwif_t *hwif = drive->hwif;
1da177e4 LT	200	u8 dma_stat = 0, dma_cmd = 0;
1da177e4 LT	201
592b5315	202	dma_stat = hwif->dma_ops->dma_sff_read_status(hwif);
cab7f8ed BZ	203	/* get DMA command mode */
cab7f8ed BZ	204	dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
1da177e4	205	/* stop DMA */
cab7f8ed	206	outb(dma_cmd & ~1, hwif->dma_base + ATA_DMA_CMD);
1da177e4	207	/* from ERRATA: clear the INTR & ERROR bits */
cab7f8ed BZ	208	dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
cab7f8ed BZ	209	outb(dma_cmd \| 6, hwif->dma_base + ATA_DMA_CMD);
1da177e4	210
1da177e4	211	ns87415_prepare_drive(drive, 0);
a6d67ffa BZ	212
	213	/* verify good DMA status */
	214	return (dma_stat & 7) != 4;
1da177e4 LT	215	}
1da177e4 LT	216
c20530ed	217	static void __devinit init_hwif_ns87415 (ide_hwif_t *hwif)
1da177e4	218	{
36501650	219	struct pci_dev *dev = to_pci_dev(hwif->dev);
1da177e4 LT	220	unsigned int ctrl, using_inta;
	221	u8 progif;
	222	#ifdef __sparc_v9__
	223	int timeout;
	224	u8 stat;
	225	#endif
	226
1da177e4 LT	227	/*
	228	* We cannot probe for IRQ: both ports share common IRQ on INTA.
	229	* Also, leave IRQ masked during drive probing, to prevent infinite
	230	* interrupts from a potentially floating INTA..
	231	*
	232	* IRQs get unmasked in selectproc when drive is first used.
	233	*/
	234	(void) pci_read_config_dword(dev, 0x40, &ctrl);
	235	(void) pci_read_config_byte(dev, 0x09, &progif);
	236	/* is irq in "native" mode? */
	237	using_inta = progif & (1 << (hwif->channel << 1));
	238	if (!using_inta)
	239	using_inta = ctrl & (1 << (4 + hwif->channel));
	240	if (hwif->mate) {
	241	hwif->select_data = hwif->mate->select_data;
	242	} else {
	243	hwif->select_data = (unsigned long)
	244	&ns87415_control[ns87415_count++];
	245	ctrl \|= (1 << 8) \| (1 << 9); /* mask both IRQs */
	246	if (using_inta)
	247	ctrl &= ~(1 << 6); /* unmask INTA */
	248	((unsigned int )hwif->select_data) = ctrl;
	249	(void) pci_write_config_dword(dev, 0x40, ctrl);
	250
	251	/*
	252	* Set prefetch size to 512 bytes for both ports,
	253	* but don't turn on/off prefetching here.
	254	*/
	255	pci_write_config_byte(dev, 0x55, 0xee);
	256
	257	#ifdef __sparc_v9__
	258	/*
9d501529 BZ	259	* XXX: Reset the device, if we don't it will not respond to
9d501529 BZ	260	* SELECT_DRIVE() properly during first ide_probe_port().
1da177e4 LT	261	*/
1da177e4 LT	262	timeout = 10000;
4c3032d8	263	outb(12, hwif->io_ports.ctl_addr);
1da177e4	264	udelay(10);
4c3032d8	265	outb(8, hwif->io_ports.ctl_addr);
1da177e4 LT	266	do {
1da177e4 LT	267	udelay(50);
374e042c	268	stat = hwif->tp_ops->read_status(hwif);
3a7d2484 BZ	269	if (stat == 0xff)
	270	break;
	271	} while ((stat & ATA_BUSY) && --timeout);
1da177e4 LT	272	#endif
	273	}
	274
	275	if (!using_inta)
973d9e74	276	hwif->irq = pci_get_legacy_ide_irq(dev, hwif->channel);
1da177e4 LT	277
	278	if (!hwif->dma_base)
	279	return;
	280
cab7f8ed	281	outb(0x60, hwif->dma_base + ATA_DMA_STATUS);
1da177e4 LT	282	}
1da177e4 LT	283
ac95beed BZ	284	static const struct ide_port_ops ns87415_port_ops = {
	285	.selectproc = ns87415_selectproc,
	286	};
	287
f37afdac BZ	288	static const struct ide_dma_ops ns87415_dma_ops = {
f37afdac BZ	289	.dma_host_set = ide_dma_host_set,
a6d67ffa BZ	290	.dma_setup = ide_dma_setup,
a6d67ffa BZ	291	.dma_start = ns87415_dma_start,
5e37bdc0	292	.dma_end = ns87415_dma_end,
f37afdac BZ	293	.dma_test_irq = ide_dma_test_irq,
f37afdac BZ	294	.dma_lost_irq = ide_dma_lost_irq,
22117d6e	295	.dma_timer_expiry = ide_dma_sff_timer_expiry,
592b5315	296	.dma_sff_read_status = superio_dma_sff_read_status,
5e37bdc0 BZ	297	};
5e37bdc0 BZ	298
85620436	299	static const struct ide_port_info ns87415_chipset __devinitdata = {
ced3ec8a	300	.name = DRV_NAME,
1da177e4	301	.init_hwif = init_hwif_ns87415,
ac95beed	302	.port_ops = &ns87415_port_ops,
5e37bdc0	303	.dma_ops = &ns87415_dma_ops,
33c1002e	304	.host_flags = IDE_HFLAG_TRUST_BIOS_FOR_DMA \|
5e71d9c5	305	IDE_HFLAG_NO_ATAPI_DMA,
1da177e4 LT	306	};
	307
	308	static int __devinit ns87415_init_one(struct pci_dev dev, const struct pci_device_id id)
	309	{
374e042c BZ	310	struct ide_port_info d = ns87415_chipset;
	311
	312	#ifdef CONFIG_SUPERIO
	313	if (PCI_SLOT(dev->devfn) == 0xE) {
	314	/* Built-in - assume it's under superio. */
	315	d.init_iops = superio_init_iops;
	316	d.tp_ops = &superio_tp_ops;
	317	}
	318	#endif
6cdf6eb3	319	return ide_pci_init_one(dev, &d, NULL);
1da177e4 LT	320	}
1da177e4 LT	321
9cbcc5e3 BZ	322	static const struct pci_device_id ns87415_pci_tbl[] = {
9cbcc5e3 BZ	323	{ PCI_VDEVICE(NS, PCI_DEVICE_ID_NS_87415), 0 },
1da177e4 LT	324	{ 0, },
	325	};
	326	MODULE_DEVICE_TABLE(pci, ns87415_pci_tbl);
	327
a9ab09e2	328	static struct pci_driver ns87415_pci_driver = {
1da177e4 LT	329	.name = "NS87415_IDE",
	330	.id_table = ns87415_pci_tbl,
	331	.probe = ns87415_init_one,
aa6e518d	332	.remove = ide_pci_remove,
feb22b7f BZ	333	.suspend = ide_pci_suspend,
feb22b7f BZ	334	.resume = ide_pci_resume,
1da177e4 LT	335	};
1da177e4 LT	336
82ab1eec	337	static int __init ns87415_ide_init(void)
1da177e4	338	{
a9ab09e2	339	return ide_pci_register_driver(&ns87415_pci_driver);
1da177e4 LT	340	}
1da177e4 LT	341
aa6e518d BZ	342	static void __exit ns87415_ide_exit(void)
aa6e518d BZ	343	{
a9ab09e2	344	pci_unregister_driver(&ns87415_pci_driver);
aa6e518d BZ	345	}
aa6e518d BZ	346
1da177e4	347	module_init(ns87415_ide_init);
aa6e518d	348	module_exit(ns87415_ide_exit);
1da177e4 LT	349
	350	MODULE_AUTHOR("Mark Lord, Eddie Dost, Andre Hedrick");
	351	MODULE_DESCRIPTION("PCI driver module for NS87415 IDE");
	352	MODULE_LICENSE("GPL");