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[net-next-2.6.git] / drivers / ide / ide-dma.c
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1da177e4 1/*
204f47c5
BZ
2 * IDE DMA support (including IDE PCI BM-DMA).
3 *
59bca8cc
BZ
4 * Copyright (C) 1995-1998 Mark Lord
5 * Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org>
6 * Copyright (C) 2004, 2007 Bartlomiej Zolnierkiewicz
58f189fc 7 *
1da177e4 8 * May be copied or modified under the terms of the GNU General Public License
204f47c5
BZ
9 *
10 * DMA is supported for all IDE devices (disk drives, cdroms, tapes, floppies).
1da177e4
LT
11 */
12
13/*
14 * Special Thanks to Mark for his Six years of work.
1da177e4
LT
15 */
16
17/*
1da177e4
LT
18 * Thanks to "Christopher J. Reimer" <reimer@doe.carleton.ca> for
19 * fixing the problem with the BIOS on some Acer motherboards.
20 *
21 * Thanks to "Benoit Poulot-Cazajous" <poulot@chorus.fr> for testing
22 * "TX" chipset compatibility and for providing patches for the "TX" chipset.
23 *
24 * Thanks to Christian Brunner <chb@muc.de> for taking a good first crack
25 * at generic DMA -- his patches were referred to when preparing this code.
26 *
27 * Most importantly, thanks to Robert Bringman <rob@mars.trion.com>
28 * for supplying a Promise UDMA board & WD UDMA drive for this work!
1da177e4
LT
29 */
30
1da177e4
LT
31#include <linux/types.h>
32#include <linux/kernel.h>
1da177e4 33#include <linux/ide.h>
1da177e4 34#include <linux/scatterlist.h>
5c05ff68 35#include <linux/dma-mapping.h>
1da177e4 36
db3f99ef 37static const struct drive_list_entry drive_whitelist[] = {
c2d3ce8c
JH
38 { "Micropolis 2112A" , NULL },
39 { "CONNER CTMA 4000" , NULL },
40 { "CONNER CTT8000-A" , NULL },
41 { "ST34342A" , NULL },
1da177e4
LT
42 { NULL , NULL }
43};
44
db3f99ef 45static const struct drive_list_entry drive_blacklist[] = {
c2d3ce8c
JH
46 { "WDC AC11000H" , NULL },
47 { "WDC AC22100H" , NULL },
48 { "WDC AC32500H" , NULL },
49 { "WDC AC33100H" , NULL },
50 { "WDC AC31600H" , NULL },
1da177e4
LT
51 { "WDC AC32100H" , "24.09P07" },
52 { "WDC AC23200L" , "21.10N21" },
c2d3ce8c
JH
53 { "Compaq CRD-8241B" , NULL },
54 { "CRD-8400B" , NULL },
55 { "CRD-8480B", NULL },
56 { "CRD-8482B", NULL },
57 { "CRD-84" , NULL },
58 { "SanDisk SDP3B" , NULL },
59 { "SanDisk SDP3B-64" , NULL },
60 { "SANYO CD-ROM CRD" , NULL },
61 { "HITACHI CDR-8" , NULL },
62 { "HITACHI CDR-8335" , NULL },
63 { "HITACHI CDR-8435" , NULL },
64 { "Toshiba CD-ROM XM-6202B" , NULL },
65 { "TOSHIBA CD-ROM XM-1702BC", NULL },
66 { "CD-532E-A" , NULL },
67 { "E-IDE CD-ROM CR-840", NULL },
68 { "CD-ROM Drive/F5A", NULL },
69 { "WPI CDD-820", NULL },
70 { "SAMSUNG CD-ROM SC-148C", NULL },
71 { "SAMSUNG CD-ROM SC", NULL },
72 { "ATAPI CD-ROM DRIVE 40X MAXIMUM", NULL },
73 { "_NEC DV5800A", NULL },
5a6248ca 74 { "SAMSUNG CD-ROM SN-124", "N001" },
c2d3ce8c 75 { "Seagate STT20000A", NULL },
b0bc65b9 76 { "CD-ROM CDR_U200", "1.09" },
1da177e4
LT
77 { NULL , NULL }
78
79};
80
1da177e4
LT
81/**
82 * ide_dma_intr - IDE DMA interrupt handler
83 * @drive: the drive the interrupt is for
84 *
db3f99ef 85 * Handle an interrupt completing a read/write DMA transfer on an
1da177e4
LT
86 * IDE device
87 */
db3f99ef
BZ
88
89ide_startstop_t ide_dma_intr(ide_drive_t *drive)
1da177e4 90{
b73c7ee2 91 ide_hwif_t *hwif = drive->hwif;
1da177e4
LT
92 u8 stat = 0, dma_stat = 0;
93
b73c7ee2 94 dma_stat = hwif->dma_ops->dma_end(drive);
374e042c 95 stat = hwif->tp_ops->read_status(hwif);
c47137a9 96
3a7d2484 97 if (OK_STAT(stat, DRIVE_READY, drive->bad_wstat | ATA_DRQ)) {
1da177e4 98 if (!dma_stat) {
b65fac32 99 struct request *rq = hwif->rq;
1da177e4 100
4d7a984b 101 task_end_request(drive, rq, stat);
1da177e4
LT
102 return ide_stopped;
103 }
db3f99ef
BZ
104 printk(KERN_ERR "%s: %s: bad DMA status (0x%02x)\n",
105 drive->name, __func__, dma_stat);
1da177e4
LT
106 }
107 return ide_error(drive, "dma_intr", stat);
108}
1da177e4
LT
109EXPORT_SYMBOL_GPL(ide_dma_intr);
110
2dbe7e91 111int ide_dma_good_drive(ide_drive_t *drive)
75d7d963
BZ
112{
113 return ide_in_drive_list(drive->id, drive_whitelist);
114}
115
1da177e4
LT
116/**
117 * ide_build_sglist - map IDE scatter gather for DMA I/O
118 * @drive: the drive to build the DMA table for
119 * @rq: the request holding the sg list
120 *
5c05ff68
BZ
121 * Perform the DMA mapping magic necessary to access the source or
122 * target buffers of a request via DMA. The lower layers of the
1da177e4 123 * kernel provide the necessary cache management so that we can
5c05ff68 124 * operate in a portable fashion.
1da177e4
LT
125 */
126
127int ide_build_sglist(ide_drive_t *drive, struct request *rq)
128{
db3f99ef 129 ide_hwif_t *hwif = drive->hwif;
1da177e4 130 struct scatterlist *sg = hwif->sg_table;
5d82720a 131 int i;
1da177e4 132
1da177e4
LT
133 ide_map_sg(drive, rq);
134
135 if (rq_data_dir(rq) == READ)
5c05ff68 136 hwif->sg_dma_direction = DMA_FROM_DEVICE;
1da177e4 137 else
5c05ff68 138 hwif->sg_dma_direction = DMA_TO_DEVICE;
1da177e4 139
5d82720a
FT
140 i = dma_map_sg(hwif->dev, sg, hwif->sg_nents, hwif->sg_dma_direction);
141 if (i) {
142 hwif->orig_sg_nents = hwif->sg_nents;
143 hwif->sg_nents = i;
144 }
145
146 return i;
1da177e4 147}
1da177e4
LT
148EXPORT_SYMBOL_GPL(ide_build_sglist);
149
1da177e4
LT
150/**
151 * ide_destroy_dmatable - clean up DMA mapping
152 * @drive: The drive to unmap
153 *
154 * Teardown mappings after DMA has completed. This must be called
155 * after the completion of each use of ide_build_dmatable and before
156 * the next use of ide_build_dmatable. Failure to do so will cause
157 * an oops as only one mapping can be live for each target at a given
158 * time.
159 */
db3f99ef
BZ
160
161void ide_destroy_dmatable(ide_drive_t *drive)
1da177e4 162{
36501650 163 ide_hwif_t *hwif = drive->hwif;
1da177e4 164
5d82720a 165 dma_unmap_sg(hwif->dev, hwif->sg_table, hwif->orig_sg_nents,
36501650 166 hwif->sg_dma_direction);
1da177e4 167}
1da177e4
LT
168EXPORT_SYMBOL_GPL(ide_destroy_dmatable);
169
1da177e4 170/**
7469aaf6 171 * ide_dma_off_quietly - Generic DMA kill
1da177e4
LT
172 * @drive: drive to control
173 *
db3f99ef 174 * Turn off the current DMA on this IDE controller.
1da177e4
LT
175 */
176
7469aaf6 177void ide_dma_off_quietly(ide_drive_t *drive)
1da177e4 178{
97100fc8 179 drive->dev_flags &= ~IDE_DFLAG_USING_DMA;
1da177e4
LT
180 ide_toggle_bounce(drive, 0);
181
5e37bdc0 182 drive->hwif->dma_ops->dma_host_set(drive, 0);
1da177e4 183}
7469aaf6 184EXPORT_SYMBOL(ide_dma_off_quietly);
1da177e4
LT
185
186/**
7469aaf6 187 * ide_dma_off - disable DMA on a device
1da177e4
LT
188 * @drive: drive to disable DMA on
189 *
190 * Disable IDE DMA for a device on this IDE controller.
191 * Inform the user that DMA has been disabled.
192 */
193
7469aaf6 194void ide_dma_off(ide_drive_t *drive)
1da177e4
LT
195{
196 printk(KERN_INFO "%s: DMA disabled\n", drive->name);
4a546e04 197 ide_dma_off_quietly(drive);
1da177e4 198}
7469aaf6 199EXPORT_SYMBOL(ide_dma_off);
1da177e4 200
1da177e4 201/**
4a546e04 202 * ide_dma_on - Enable DMA on a device
1da177e4
LT
203 * @drive: drive to enable DMA on
204 *
205 * Enable IDE DMA for a device on this IDE controller.
206 */
4a546e04
BZ
207
208void ide_dma_on(ide_drive_t *drive)
1da177e4 209{
97100fc8 210 drive->dev_flags |= IDE_DFLAG_USING_DMA;
1da177e4
LT
211 ide_toggle_bounce(drive, 1);
212
5e37bdc0 213 drive->hwif->dma_ops->dma_host_set(drive, 1);
1da177e4
LT
214}
215
db3f99ef 216int __ide_dma_bad_drive(ide_drive_t *drive)
1da177e4 217{
4dde4492 218 u16 *id = drive->id;
1da177e4 219
65e5f2e3 220 int blacklist = ide_in_drive_list(id, drive_blacklist);
1da177e4
LT
221 if (blacklist) {
222 printk(KERN_WARNING "%s: Disabling (U)DMA for %s (blacklisted)\n",
4dde4492 223 drive->name, (char *)&id[ATA_ID_PROD]);
1da177e4
LT
224 return blacklist;
225 }
226 return 0;
227}
1da177e4
LT
228EXPORT_SYMBOL(__ide_dma_bad_drive);
229
2d5eaa6d
BZ
230static const u8 xfer_mode_bases[] = {
231 XFER_UDMA_0,
232 XFER_MW_DMA_0,
233 XFER_SW_DMA_0,
234};
235
7670df73 236static unsigned int ide_get_mode_mask(ide_drive_t *drive, u8 base, u8 req_mode)
2d5eaa6d 237{
4dde4492 238 u16 *id = drive->id;
2d5eaa6d 239 ide_hwif_t *hwif = drive->hwif;
ac95beed 240 const struct ide_port_ops *port_ops = hwif->port_ops;
2d5eaa6d
BZ
241 unsigned int mask = 0;
242
db3f99ef 243 switch (base) {
2d5eaa6d 244 case XFER_UDMA_0:
4dde4492 245 if ((id[ATA_ID_FIELD_VALID] & 4) == 0)
2d5eaa6d
BZ
246 break;
247
ac95beed
BZ
248 if (port_ops && port_ops->udma_filter)
249 mask = port_ops->udma_filter(drive);
851dd33b
SS
250 else
251 mask = hwif->ultra_mask;
4dde4492 252 mask &= id[ATA_ID_UDMA_MODES];
2d5eaa6d 253
7670df73
BZ
254 /*
255 * avoid false cable warning from eighty_ninty_three()
256 */
257 if (req_mode > XFER_UDMA_2) {
258 if ((mask & 0x78) && (eighty_ninty_three(drive) == 0))
259 mask &= 0x07;
260 }
2d5eaa6d
BZ
261 break;
262 case XFER_MW_DMA_0:
4dde4492 263 if ((id[ATA_ID_FIELD_VALID] & 2) == 0)
b4e44369 264 break;
ac95beed
BZ
265 if (port_ops && port_ops->mdma_filter)
266 mask = port_ops->mdma_filter(drive);
b4e44369
SS
267 else
268 mask = hwif->mwdma_mask;
4dde4492 269 mask &= id[ATA_ID_MWDMA_MODES];
2d5eaa6d
BZ
270 break;
271 case XFER_SW_DMA_0:
4dde4492
BZ
272 if (id[ATA_ID_FIELD_VALID] & 2) {
273 mask = id[ATA_ID_SWDMA_MODES] & hwif->swdma_mask;
48fb2688
BZ
274 } else if (id[ATA_ID_OLD_DMA_MODES] >> 8) {
275 u8 mode = id[ATA_ID_OLD_DMA_MODES] >> 8;
15a4f943
BZ
276
277 /*
278 * if the mode is valid convert it to the mask
279 * (the maximum allowed mode is XFER_SW_DMA_2)
280 */
281 if (mode <= 2)
282 mask = ((2 << mode) - 1) & hwif->swdma_mask;
283 }
2d5eaa6d
BZ
284 break;
285 default:
286 BUG();
287 break;
288 }
289
290 return mask;
291}
292
293/**
7670df73 294 * ide_find_dma_mode - compute DMA speed
2d5eaa6d 295 * @drive: IDE device
7670df73
BZ
296 * @req_mode: requested mode
297 *
298 * Checks the drive/host capabilities and finds the speed to use for
299 * the DMA transfer. The speed is then limited by the requested mode.
2d5eaa6d 300 *
7670df73
BZ
301 * Returns 0 if the drive/host combination is incapable of DMA transfers
302 * or if the requested mode is not a DMA mode.
2d5eaa6d
BZ
303 */
304
7670df73 305u8 ide_find_dma_mode(ide_drive_t *drive, u8 req_mode)
2d5eaa6d
BZ
306{
307 ide_hwif_t *hwif = drive->hwif;
308 unsigned int mask;
309 int x, i;
310 u8 mode = 0;
311
33c1002e
BZ
312 if (drive->media != ide_disk) {
313 if (hwif->host_flags & IDE_HFLAG_NO_ATAPI_DMA)
314 return 0;
315 }
2d5eaa6d
BZ
316
317 for (i = 0; i < ARRAY_SIZE(xfer_mode_bases); i++) {
7670df73
BZ
318 if (req_mode < xfer_mode_bases[i])
319 continue;
320 mask = ide_get_mode_mask(drive, xfer_mode_bases[i], req_mode);
2d5eaa6d
BZ
321 x = fls(mask) - 1;
322 if (x >= 0) {
323 mode = xfer_mode_bases[i] + x;
324 break;
325 }
326 }
327
75d7d963
BZ
328 if (hwif->chipset == ide_acorn && mode == 0) {
329 /*
330 * is this correct?
331 */
4dde4492
BZ
332 if (ide_dma_good_drive(drive) &&
333 drive->id[ATA_ID_EIDE_DMA_TIME] < 150)
75d7d963
BZ
334 mode = XFER_MW_DMA_1;
335 }
336
3ab7efe8
BZ
337 mode = min(mode, req_mode);
338
339 printk(KERN_INFO "%s: %s mode selected\n", drive->name,
d34887da 340 mode ? ide_xfer_verbose(mode) : "no DMA");
2d5eaa6d 341
3ab7efe8 342 return mode;
2d5eaa6d 343}
7670df73 344EXPORT_SYMBOL_GPL(ide_find_dma_mode);
2d5eaa6d 345
0ae2e178 346static int ide_tune_dma(ide_drive_t *drive)
29e744d0 347{
8704de8f 348 ide_hwif_t *hwif = drive->hwif;
29e744d0
BZ
349 u8 speed;
350
97100fc8
BZ
351 if (ata_id_has_dma(drive->id) == 0 ||
352 (drive->dev_flags & IDE_DFLAG_NODMA))
122ab088
BZ
353 return 0;
354
355 /* consult the list of known "bad" drives */
356 if (__ide_dma_bad_drive(drive))
29e744d0
BZ
357 return 0;
358
3ab7efe8
BZ
359 if (ide_id_dma_bug(drive))
360 return 0;
361
8704de8f 362 if (hwif->host_flags & IDE_HFLAG_TRUST_BIOS_FOR_DMA)
0ae2e178
BZ
363 return config_drive_for_dma(drive);
364
29e744d0
BZ
365 speed = ide_max_dma_mode(drive);
366
951784b6
BZ
367 if (!speed)
368 return 0;
29e744d0 369
88b2b32b 370 if (ide_set_dma_mode(drive, speed))
4728d546 371 return 0;
29e744d0 372
4728d546 373 return 1;
29e744d0
BZ
374}
375
0ae2e178
BZ
376static int ide_dma_check(ide_drive_t *drive)
377{
378 ide_hwif_t *hwif = drive->hwif;
0ae2e178 379
ba4b2e60 380 if (ide_tune_dma(drive))
0ae2e178
BZ
381 return 0;
382
383 /* TODO: always do PIO fallback */
384 if (hwif->host_flags & IDE_HFLAG_TRUST_BIOS_FOR_DMA)
385 return -1;
386
387 ide_set_max_pio(drive);
388
ba4b2e60 389 return -1;
0ae2e178
BZ
390}
391
3ab7efe8 392int ide_id_dma_bug(ide_drive_t *drive)
1da177e4 393{
4dde4492 394 u16 *id = drive->id;
1da177e4 395
4dde4492
BZ
396 if (id[ATA_ID_FIELD_VALID] & 4) {
397 if ((id[ATA_ID_UDMA_MODES] >> 8) &&
398 (id[ATA_ID_MWDMA_MODES] >> 8))
3ab7efe8 399 goto err_out;
4dde4492
BZ
400 } else if (id[ATA_ID_FIELD_VALID] & 2) {
401 if ((id[ATA_ID_MWDMA_MODES] >> 8) &&
402 (id[ATA_ID_SWDMA_MODES] >> 8))
3ab7efe8 403 goto err_out;
1da177e4 404 }
3ab7efe8
BZ
405 return 0;
406err_out:
407 printk(KERN_ERR "%s: bad DMA info in identify block\n", drive->name);
408 return 1;
1da177e4
LT
409}
410
3608b5d7
BZ
411int ide_set_dma(ide_drive_t *drive)
412{
3608b5d7
BZ
413 int rc;
414
7b905994
BZ
415 /*
416 * Force DMAing for the beginning of the check.
417 * Some chipsets appear to do interesting
418 * things, if not checked and cleared.
419 * PARANOIA!!!
420 */
4a546e04 421 ide_dma_off_quietly(drive);
3608b5d7 422
7b905994
BZ
423 rc = ide_dma_check(drive);
424 if (rc)
425 return rc;
3608b5d7 426
4a546e04
BZ
427 ide_dma_on(drive);
428
429 return 0;
3608b5d7
BZ
430}
431
578cfa0d
BZ
432void ide_check_dma_crc(ide_drive_t *drive)
433{
434 u8 mode;
435
436 ide_dma_off_quietly(drive);
437 drive->crc_count = 0;
438 mode = drive->current_speed;
439 /*
440 * Don't try non Ultra-DMA modes without iCRC's. Force the
441 * device to PIO and make the user enable SWDMA/MWDMA modes.
442 */
443 if (mode > XFER_UDMA_0 && mode <= XFER_UDMA_7)
444 mode--;
445 else
446 mode = XFER_PIO_4;
447 ide_set_xfer_rate(drive, mode);
448 if (drive->current_speed >= XFER_SW_DMA_0)
449 ide_dma_on(drive);
450}
451
de23ec9c 452void ide_dma_lost_irq(ide_drive_t *drive)
1da177e4 453{
de23ec9c 454 printk(KERN_ERR "%s: DMA interrupt recovery\n", drive->name);
1da177e4 455}
de23ec9c 456EXPORT_SYMBOL_GPL(ide_dma_lost_irq);
1da177e4 457
ffa15a69 458void ide_dma_timeout(ide_drive_t *drive)
1da177e4 459{
db3f99ef 460 ide_hwif_t *hwif = drive->hwif;
c283f5db 461
1da177e4 462 printk(KERN_ERR "%s: timeout waiting for DMA\n", drive->name);
1da177e4 463
5e37bdc0 464 if (hwif->dma_ops->dma_test_irq(drive))
c283f5db
SS
465 return;
466
ffa15a69
BZ
467 ide_dump_status(drive, "DMA timeout", hwif->tp_ops->read_status(hwif));
468
5e37bdc0 469 hwif->dma_ops->dma_end(drive);
1da177e4 470}
ffa15a69 471EXPORT_SYMBOL_GPL(ide_dma_timeout);
1da177e4 472
0d1bad21 473void ide_release_dma_engine(ide_hwif_t *hwif)
1da177e4
LT
474{
475 if (hwif->dmatable_cpu) {
2bbd57ca 476 int prd_size = hwif->prd_max_nents * hwif->prd_ent_size;
36501650 477
2bbd57ca
BZ
478 dma_free_coherent(hwif->dev, prd_size,
479 hwif->dmatable_cpu, hwif->dmatable_dma);
1da177e4
LT
480 hwif->dmatable_cpu = NULL;
481 }
1da177e4 482}
2bbd57ca 483EXPORT_SYMBOL_GPL(ide_release_dma_engine);
1da177e4 484
b8e73fba 485int ide_allocate_dma_engine(ide_hwif_t *hwif)
1da177e4 486{
2bbd57ca 487 int prd_size;
36501650 488
2bbd57ca
BZ
489 if (hwif->prd_max_nents == 0)
490 hwif->prd_max_nents = PRD_ENTRIES;
491 if (hwif->prd_ent_size == 0)
492 hwif->prd_ent_size = PRD_BYTES;
1da177e4 493
2bbd57ca 494 prd_size = hwif->prd_max_nents * hwif->prd_ent_size;
1da177e4 495
2bbd57ca
BZ
496 hwif->dmatable_cpu = dma_alloc_coherent(hwif->dev, prd_size,
497 &hwif->dmatable_dma,
498 GFP_ATOMIC);
499 if (hwif->dmatable_cpu == NULL) {
500 printk(KERN_ERR "%s: unable to allocate PRD table\n",
5e59c236 501 hwif->name);
2bbd57ca
BZ
502 return -ENOMEM;
503 }
1da177e4 504
2bbd57ca 505 return 0;
1da177e4 506}
b8e73fba 507EXPORT_SYMBOL_GPL(ide_allocate_dma_engine);