[net-next-2.6.git] / drivers / ide / cmd64x.c

/*
 * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines.
 *           Due to massive hardware bugs, UltraDMA is only supported
 *           on the 646U2 and not on the 646U.
 *
 * Copyright (C) 1998		Eddie C. Dost  (ecd@skynet.be)
 * Copyright (C) 1998		David S. Miller (davem@redhat.com)
 *
 * Copyright (C) 1999-2002	Andre Hedrick <andre@linux-ide.org>
 * Copyright (C) 2007,2009	MontaVista Software, Inc. <source@mvista.com>
 */

#include <linux/module.h>
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/ide.h>
#include <linux/init.h>

#include <asm/io.h>

#define DRV_NAME "cmd64x"

/*
 * CMD64x specific registers definition.
 */
#define CFR		0x50
#define   CFR_INTR_CH0		0x04

#define	CMDTIM		0x52
#define	ARTTIM0		0x53
#define	DRWTIM0		0x54
#define ARTTIM1 	0x55
#define DRWTIM1		0x56
#define ARTTIM23	0x57
#define   ARTTIM23_DIS_RA2	0x04
#define   ARTTIM23_DIS_RA3	0x08
#define   ARTTIM23_INTR_CH1	0x10
#define DRWTIM2		0x58
#define BRST		0x59
#define DRWTIM3		0x5b

#define BMIDECR0	0x70
#define MRDMODE		0x71
#define   MRDMODE_INTR_CH0	0x04
#define   MRDMODE_INTR_CH1	0x08
#define UDIDETCR0	0x73
#define DTPR0		0x74
#define BMIDECR1	0x78
#define BMIDECSR	0x79
#define UDIDETCR1	0x7B
#define DTPR1		0x7C

static u8 quantize_timing(int timing, int quant)
{
	return (timing + quant - 1) / quant;
}

/*
 * This routine calculates active/recovery counts and then writes them into
 * the chipset registers.
 */
static void program_cycle_times (ide_drive_t *drive, int cycle_time, int active_time)
{
	struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
	int clock_time = 1000 / (ide_pci_clk ? ide_pci_clk : 33);
	u8  cycle_count, active_count, recovery_count, drwtim;
	static const u8 recovery_values[] =
		{15, 15, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0};
	static const u8 drwtim_regs[4] = {DRWTIM0, DRWTIM1, DRWTIM2, DRWTIM3};

	cycle_count	= quantize_timing( cycle_time, clock_time);
	active_count	= quantize_timing(active_time, clock_time);
	recovery_count	= cycle_count - active_count;

	/*
	 * In case we've got too long recovery phase, try to lengthen
	 * the active phase
	 */
	if (recovery_count > 16) {
		active_count += recovery_count - 16;
		recovery_count = 16;
	}
	if (active_count > 16)		/* shouldn't actually happen... */
	 	active_count = 16;

	/*
	 * Convert values to internal chipset representation
	 */
	recovery_count = recovery_values[recovery_count];
 	active_count  &= 0x0f;

	/* Program the active/recovery counts into the DRWTIM register */
	drwtim = (active_count << 4) | recovery_count;
	(void) pci_write_config_byte(dev, drwtim_regs[drive->dn], drwtim);
}

/*
 * This routine writes into the chipset registers
 * PIO setup/active/recovery timings.
 */
static void cmd64x_tune_pio(ide_drive_t *drive, const u8 pio)
{
	ide_hwif_t *hwif	= drive->hwif;
	struct pci_dev *dev	= to_pci_dev(hwif->dev);
	struct ide_timing *t	= ide_timing_find_mode(XFER_PIO_0 + pio);
	unsigned long setup_count;
	unsigned int cycle_time;
	u8 arttim = 0;

	static const u8 setup_values[] = {0x40, 0x40, 0x40, 0x80, 0, 0xc0};
	static const u8 arttim_regs[4] = {ARTTIM0, ARTTIM1, ARTTIM23, ARTTIM23};

	cycle_time = ide_pio_cycle_time(drive, pio);

	program_cycle_times(drive, cycle_time, t->active);

	setup_count = quantize_timing(t->setup,
			1000 / (ide_pci_clk ? ide_pci_clk : 33));

	/*
	 * The primary channel has individual address setup timing registers
	 * for each drive and the hardware selects the slowest timing itself.
	 * The secondary channel has one common register and we have to select
	 * the slowest address setup timing ourselves.
	 */
	if (hwif->channel) {
		ide_drive_t *pair = ide_get_pair_dev(drive);

		ide_set_drivedata(drive, (void *)setup_count);

		if (pair)
			setup_count = max_t(u8, setup_count,
					(unsigned long)ide_get_drivedata(pair));
	}

	if (setup_count > 5)		/* shouldn't actually happen... */
		setup_count = 5;

	/*
	 * Program the address setup clocks into the ARTTIM registers.
	 * Avoid clearing the secondary channel's interrupt bit.
	 */
	(void) pci_read_config_byte (dev, arttim_regs[drive->dn], &arttim);
	if (hwif->channel)
		arttim &= ~ARTTIM23_INTR_CH1;
	arttim &= ~0xc0;
	arttim |= setup_values[setup_count];
	(void) pci_write_config_byte(dev, arttim_regs[drive->dn], arttim);
}

/*
 * Attempts to set drive's PIO mode.
 * Special cases are 8: prefetch off, 9: prefetch on (both never worked)
 */

static void cmd64x_set_pio_mode(ide_drive_t *drive, const u8 pio)
{
	/*
	 * Filter out the prefetch control values
	 * to prevent PIO5 from being programmed
	 */
	if (pio == 8 || pio == 9)
		return;

	cmd64x_tune_pio(drive, pio);
}

static void cmd64x_set_dma_mode(ide_drive_t *drive, const u8 speed)
{
	ide_hwif_t *hwif	= drive->hwif;
	struct pci_dev *dev	= to_pci_dev(hwif->dev);
	u8 unit			= drive->dn & 0x01;
	u8 regU = 0, pciU	= hwif->channel ? UDIDETCR1 : UDIDETCR0;

	if (speed >= XFER_SW_DMA_0) {
		(void) pci_read_config_byte(dev, pciU, &regU);
		regU &= ~(unit ? 0xCA : 0x35);
	}

	switch(speed) {
	case XFER_UDMA_5:
		regU |= unit ? 0x0A : 0x05;
		break;
	case XFER_UDMA_4:
		regU |= unit ? 0x4A : 0x15;
		break;
	case XFER_UDMA_3:
		regU |= unit ? 0x8A : 0x25;
		break;
	case XFER_UDMA_2:
		regU |= unit ? 0x42 : 0x11;
		break;
	case XFER_UDMA_1:
		regU |= unit ? 0x82 : 0x21;
		break;
	case XFER_UDMA_0:
		regU |= unit ? 0xC2 : 0x31;
		break;
	case XFER_MW_DMA_2:
		program_cycle_times(drive, 120, 70);
		break;
	case XFER_MW_DMA_1:
		program_cycle_times(drive, 150, 80);
		break;
	case XFER_MW_DMA_0:
		program_cycle_times(drive, 480, 215);
		break;
	}

	if (speed >= XFER_SW_DMA_0)
		(void) pci_write_config_byte(dev, pciU, regU);
}

static void cmd648_clear_irq(ide_drive_t *drive)
{
	ide_hwif_t *hwif	= drive->hwif;
	struct pci_dev *dev	= to_pci_dev(hwif->dev);
	unsigned long base	= pci_resource_start(dev, 4);
	u8  irq_mask		= hwif->channel ? MRDMODE_INTR_CH1 :
						  MRDMODE_INTR_CH0;
	u8  mrdmode		= inb(base + 1);

	/* clear the interrupt bit */
	outb((mrdmode & ~(MRDMODE_INTR_CH0 | MRDMODE_INTR_CH1)) | irq_mask,
	     base + 1);
}

static void cmd64x_clear_irq(ide_drive_t *drive)
{
	ide_hwif_t *hwif	= drive->hwif;
	struct pci_dev *dev	= to_pci_dev(hwif->dev);
	int irq_reg		= hwif->channel ? ARTTIM23 : CFR;
	u8  irq_mask		= hwif->channel ? ARTTIM23_INTR_CH1 :
						  CFR_INTR_CH0;
	u8  irq_stat		= 0;

	(void) pci_read_config_byte(dev, irq_reg, &irq_stat);
	/* clear the interrupt bit */
	(void) pci_write_config_byte(dev, irq_reg, irq_stat | irq_mask);
}

static int cmd648_test_irq(ide_hwif_t *hwif)
{
	struct pci_dev *dev	= to_pci_dev(hwif->dev);
	unsigned long base	= pci_resource_start(dev, 4);
	u8 irq_mask		= hwif->channel ? MRDMODE_INTR_CH1 :
						  MRDMODE_INTR_CH0;
	u8 mrdmode		= inb(base + 1);

	pr_debug("%s: mrdmode: 0x%02x irq_mask: 0x%02x\n",
		 hwif->name, mrdmode, irq_mask);

	return (mrdmode & irq_mask) ? 1 : 0;
}

static int cmd64x_test_irq(ide_hwif_t *hwif)
{
	struct pci_dev *dev	= to_pci_dev(hwif->dev);
	int irq_reg		= hwif->channel ? ARTTIM23 : CFR;
	u8  irq_mask		= hwif->channel ? ARTTIM23_INTR_CH1 :
						  CFR_INTR_CH0;
	u8  irq_stat		= 0;

	(void) pci_read_config_byte(dev, irq_reg, &irq_stat);

	pr_debug("%s: irq_stat: 0x%02x irq_mask: 0x%02x\n",
		 hwif->name, irq_stat, irq_mask);

	return (irq_stat & irq_mask) ? 1 : 0;
}

/*
 * ASUS P55T2P4D with CMD646 chipset revision 0x01 requires the old
 * event order for DMA transfers.
 */

static int cmd646_1_dma_end(ide_drive_t *drive)
{
	ide_hwif_t *hwif = drive->hwif;
	u8 dma_stat = 0, dma_cmd = 0;

	/* get DMA status */
	dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
	/* read DMA command state */
	dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
	/* stop DMA */
	outb(dma_cmd & ~1, hwif->dma_base + ATA_DMA_CMD);
	/* clear the INTR & ERROR bits */
	outb(dma_stat | 6, hwif->dma_base + ATA_DMA_STATUS);
	/* verify good DMA status */
	return (dma_stat & 7) != 4;
}

static int init_chipset_cmd64x(struct pci_dev *dev)
{
	u8 mrdmode = 0;

	/* Set a good latency timer and cache line size value. */
	(void) pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
	/* FIXME: pci_set_master() to ensure a good latency timer value */

	/*
	 * Enable interrupts, select MEMORY READ LINE for reads.
	 *
	 * NOTE: although not mentioned in the PCI0646U specs,
	 * bits 0-1 are write only and won't be read back as
	 * set or not -- PCI0646U2 specs clarify this point.
	 */
	(void) pci_read_config_byte (dev, MRDMODE, &mrdmode);
	mrdmode &= ~0x30;
	(void) pci_write_config_byte(dev, MRDMODE, (mrdmode | 0x02));

	return 0;
}

static u8 cmd64x_cable_detect(ide_hwif_t *hwif)
{
	struct pci_dev  *dev	= to_pci_dev(hwif->dev);
	u8 bmidecsr = 0, mask	= hwif->channel ? 0x02 : 0x01;

	switch (dev->device) {
	case PCI_DEVICE_ID_CMD_648:
	case PCI_DEVICE_ID_CMD_649:
 		pci_read_config_byte(dev, BMIDECSR, &bmidecsr);
		return (bmidecsr & mask) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
	default:
		return ATA_CBL_PATA40;
	}
}

static const struct ide_port_ops cmd64x_port_ops = {
	.set_pio_mode		= cmd64x_set_pio_mode,
	.set_dma_mode		= cmd64x_set_dma_mode,
	.clear_irq		= cmd64x_clear_irq,
	.test_irq		= cmd64x_test_irq,
	.cable_detect		= cmd64x_cable_detect,
};

static const struct ide_port_ops cmd648_port_ops = {
	.set_pio_mode		= cmd64x_set_pio_mode,
	.set_dma_mode		= cmd64x_set_dma_mode,
	.clear_irq		= cmd648_clear_irq,
	.test_irq		= cmd648_test_irq,
	.cable_detect		= cmd64x_cable_detect,
};

static const struct ide_dma_ops cmd646_rev1_dma_ops = {
	.dma_host_set		= ide_dma_host_set,
	.dma_setup		= ide_dma_setup,
	.dma_start		= ide_dma_start,
	.dma_end		= cmd646_1_dma_end,
	.dma_test_irq		= ide_dma_test_irq,
	.dma_lost_irq		= ide_dma_lost_irq,
	.dma_timer_expiry	= ide_dma_sff_timer_expiry,
	.dma_sff_read_status	= ide_dma_sff_read_status,
};

static const struct ide_port_info cmd64x_chipsets[] __devinitdata = {
	{	/* 0: CMD643 */
		.name		= DRV_NAME,
		.init_chipset	= init_chipset_cmd64x,
		.enablebits	= {{0x00,0x00,0x00}, {0x51,0x08,0x08}},
		.port_ops	= &cmd64x_port_ops,
		.host_flags	= IDE_HFLAG_CLEAR_SIMPLEX |
				  IDE_HFLAG_ABUSE_PREFETCH |
				  IDE_HFLAG_SERIALIZE,
		.pio_mask	= ATA_PIO5,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= 0x00, /* no udma */
	},
	{	/* 1: CMD646 */
		.name		= DRV_NAME,
		.init_chipset	= init_chipset_cmd64x,
		.enablebits	= {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
		.port_ops	= &cmd648_port_ops,
		.host_flags	= IDE_HFLAG_ABUSE_PREFETCH |
				  IDE_HFLAG_SERIALIZE,
		.pio_mask	= ATA_PIO5,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA2,
	},
	{	/* 2: CMD648 */
		.name		= DRV_NAME,
		.init_chipset	= init_chipset_cmd64x,
		.enablebits	= {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
		.port_ops	= &cmd648_port_ops,
		.host_flags	= IDE_HFLAG_ABUSE_PREFETCH,
		.pio_mask	= ATA_PIO5,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA4,
	},
	{	/* 3: CMD649 */
		.name		= DRV_NAME,
		.init_chipset	= init_chipset_cmd64x,
		.enablebits	= {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
		.port_ops	= &cmd648_port_ops,
		.host_flags	= IDE_HFLAG_ABUSE_PREFETCH,
		.pio_mask	= ATA_PIO5,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA5,
	}
};

static int __devinit cmd64x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	struct ide_port_info d;
	u8 idx = id->driver_data;

	d = cmd64x_chipsets[idx];

	if (idx == 1) {
		/*
		 * UltraDMA only supported on PCI646U and PCI646U2, which
		 * correspond to revisions 0x03, 0x05 and 0x07 respectively.
		 * Actually, although the CMD tech support people won't
		 * tell me the details, the 0x03 revision cannot support
		 * UDMA correctly without hardware modifications, and even
		 * then it only works with Quantum disks due to some
		 * hold time assumptions in the 646U part which are fixed
		 * in the 646U2.
		 *
		 * So we only do UltraDMA on revision 0x05 and 0x07 chipsets.
		 */
		if (dev->revision < 5) {
			d.udma_mask = 0x00;
			/*
			 * The original PCI0646 didn't have the primary
			 * channel enable bit, it appeared starting with
			 * PCI0646U (i.e. revision ID 3).
			 */
			if (dev->revision < 3) {
				d.enablebits[0].reg = 0;
				d.port_ops = &cmd64x_port_ops;
				if (dev->revision == 1)
					d.dma_ops = &cmd646_rev1_dma_ops;
			}
		}
	}

	return ide_pci_init_one(dev, &d, NULL);
}

static const struct pci_device_id cmd64x_pci_tbl[] = {
	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_643), 0 },
	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_646), 1 },
	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_648), 2 },
	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_649), 3 },
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, cmd64x_pci_tbl);

static struct pci_driver cmd64x_pci_driver = {
	.name		= "CMD64x_IDE",
	.id_table	= cmd64x_pci_tbl,
	.probe		= cmd64x_init_one,
	.remove		= ide_pci_remove,
	.suspend	= ide_pci_suspend,
	.resume		= ide_pci_resume,
};

static int __init cmd64x_ide_init(void)
{
	return ide_pci_register_driver(&cmd64x_pci_driver);
}

static void __exit cmd64x_ide_exit(void)
{
	pci_unregister_driver(&cmd64x_pci_driver);
}

module_init(cmd64x_ide_init);
module_exit(cmd64x_ide_exit);

MODULE_AUTHOR("Eddie Dost, David Miller, Andre Hedrick");
MODULE_DESCRIPTION("PCI driver module for CMD64x IDE");
MODULE_LICENSE("GPL");
Commit	Line	Data
60e7a82f	1	/*
1da177e4	2	* cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines.
1da177e4 LT	3	* Due to massive hardware bugs, UltraDMA is only supported
	4	* on the 646U2 and not on the 646U.
	5	*
	6	* Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
	7	* Copyright (C) 1998 David S. Miller (davem@redhat.com)
	8	*
	9	* Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>
30e5ffc3	10	* Copyright (C) 2007,2009 MontaVista Software, Inc. <source@mvista.com>
1da177e4 LT	11	*/
1da177e4 LT	12
1da177e4 LT	13	#include <linux/module.h>
	14	#include <linux/types.h>
	15	#include <linux/pci.h>
1da177e4 LT	16	#include <linux/ide.h>
	17	#include <linux/init.h>
	18
	19	#include <asm/io.h>
	20
ced3ec8a BZ	21	#define DRV_NAME "cmd64x"
ced3ec8a BZ	22
1da177e4 LT	23	/*
	24	* CMD64x specific registers definition.
	25	*/
	26	#define CFR 0x50
e51e2528	27	#define CFR_INTR_CH0 0x04
1da177e4 LT	28
	29	#define CMDTIM 0x52
	30	#define ARTTIM0 0x53
	31	#define DRWTIM0 0x54
	32	#define ARTTIM1 0x55
	33	#define DRWTIM1 0x56
	34	#define ARTTIM23 0x57
	35	#define ARTTIM23_DIS_RA2 0x04
	36	#define ARTTIM23_DIS_RA3 0x08
	37	#define ARTTIM23_INTR_CH1 0x10
1da177e4 LT	38	#define DRWTIM2 0x58
	39	#define BRST 0x59
	40	#define DRWTIM3 0x5b
	41
	42	#define BMIDECR0 0x70
	43	#define MRDMODE 0x71
	44	#define MRDMODE_INTR_CH0 0x04
	45	#define MRDMODE_INTR_CH1 0x08
1da177e4 LT	46	#define UDIDETCR0 0x73
	47	#define DTPR0 0x74
	48	#define BMIDECR1 0x78
	49	#define BMIDECSR 0x79
1da177e4 LT	50	#define UDIDETCR1 0x7B
	51	#define DTPR1 0x7C
	52
e277a1aa SS	53	static u8 quantize_timing(int timing, int quant)
	54	{
	55	return (timing + quant - 1) / quant;
	56	}
	57
1da177e4	58	/*
60e7a82f SS	59	* This routine calculates active/recovery counts and then writes them into
60e7a82f SS	60	* the chipset registers.
1da177e4	61	*/
60e7a82f	62	static void program_cycle_times (ide_drive_t *drive, int cycle_time, int active_time)
1da177e4	63	{
ebae41a5	64	struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
30e5ee4d	65	int clock_time = 1000 / (ide_pci_clk ? ide_pci_clk : 33);
60e7a82f SS	66	u8 cycle_count, active_count, recovery_count, drwtim;
60e7a82f SS	67	static const u8 recovery_values[] =
1da177e4	68	{15, 15, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0};
60e7a82f SS	69	static const u8 drwtim_regs[4] = {DRWTIM0, DRWTIM1, DRWTIM2, DRWTIM3};
60e7a82f SS	70
60e7a82f SS	71	cycle_count = quantize_timing( cycle_time, clock_time);
	72	active_count = quantize_timing(active_time, clock_time);
	73	recovery_count = cycle_count - active_count;
	74
1da177e4	75	/*
60e7a82f SS	76	* In case we've got too long recovery phase, try to lengthen
60e7a82f SS	77	* the active phase
1da177e4	78	*/
60e7a82f SS	79	if (recovery_count > 16) {
	80	active_count += recovery_count - 16;
	81	recovery_count = 16;
1da177e4	82	}
60e7a82f SS	83	if (active_count > 16) /* shouldn't actually happen... */
	84	active_count = 16;
	85
1da177e4 LT	86	/*
	87	* Convert values to internal chipset representation
	88	*/
60e7a82f SS	89	recovery_count = recovery_values[recovery_count];
60e7a82f SS	90	active_count &= 0x0f;
1da177e4	91
60e7a82f SS	92	/* Program the active/recovery counts into the DRWTIM register */
	93	drwtim = (active_count << 4) \| recovery_count;
	94	(void) pci_write_config_byte(dev, drwtim_regs[drive->dn], drwtim);
1da177e4 LT	95	}
	96
	97	/*
26bcb879 BZ	98	* This routine writes into the chipset registers
26bcb879 BZ	99	* PIO setup/active/recovery timings.
1da177e4	100	*/
26bcb879	101	static void cmd64x_tune_pio(ide_drive_t *drive, const u8 pio)
1da177e4	102	{
898ec223	103	ide_hwif_t *hwif = drive->hwif;
36501650	104	struct pci_dev *dev = to_pci_dev(hwif->dev);
86a0e12f	105	struct ide_timing *t = ide_timing_find_mode(XFER_PIO_0 + pio);
5bfb151f	106	unsigned long setup_count;
7dd00083	107	unsigned int cycle_time;
5bfb151f	108	u8 arttim = 0;
26bcb879	109
60e7a82f SS	110	static const u8 setup_values[] = {0x40, 0x40, 0x40, 0x80, 0, 0xc0};
60e7a82f SS	111	static const u8 arttim_regs[4] = {ARTTIM0, ARTTIM1, ARTTIM23, ARTTIM23};
7dd00083	112
26bcb879	113	cycle_time = ide_pio_cycle_time(drive, pio);
1da177e4	114
86a0e12f	115	program_cycle_times(drive, cycle_time, t->active);
1da177e4	116
86a0e12f	117	setup_count = quantize_timing(t->setup,
30e5ee4d	118	1000 / (ide_pci_clk ? ide_pci_clk : 33));
60e7a82f SS	119
	120	/*
	121	* The primary channel has individual address setup timing registers
	122	* for each drive and the hardware selects the slowest timing itself.
	123	* The secondary channel has one common register and we have to select
	124	* the slowest address setup timing ourselves.
	125	*/
	126	if (hwif->channel) {
5d44a150	127	ide_drive_t *pair = ide_get_pair_dev(drive);
60e7a82f	128
5bfb151f	129	ide_set_drivedata(drive, (void *)setup_count);
5d44a150 BZ	130
5d44a150 BZ	131	if (pair)
5bfb151f JR	132	setup_count = max_t(u8, setup_count,
5bfb151f JR	133	(unsigned long)ide_get_drivedata(pair));
1da177e4	134	}
1da177e4	135
60e7a82f SS	136	if (setup_count > 5) /* shouldn't actually happen... */
60e7a82f SS	137	setup_count = 5;
1da177e4	138
60e7a82f SS	139	/*
	140	* Program the address setup clocks into the ARTTIM registers.
	141	* Avoid clearing the secondary channel's interrupt bit.
	142	*/
	143	(void) pci_read_config_byte (dev, arttim_regs[drive->dn], &arttim);
	144	if (hwif->channel)
	145	arttim &= ~ARTTIM23_INTR_CH1;
	146	arttim &= ~0xc0;
	147	arttim \|= setup_values[setup_count];
	148	(void) pci_write_config_byte(dev, arttim_regs[drive->dn], arttim);
f92d50e6 SS	149	}
	150
	151	/*
	152	* Attempts to set drive's PIO mode.
26bcb879	153	* Special cases are 8: prefetch off, 9: prefetch on (both never worked)
f92d50e6	154	*/
26bcb879 BZ	155
26bcb879 BZ	156	static void cmd64x_set_pio_mode(ide_drive_t *drive, const u8 pio)
f92d50e6 SS	157	{
	158	/*
	159	* Filter out the prefetch control values
	160	* to prevent PIO5 from being programmed
	161	*/
	162	if (pio == 8 \|\| pio == 9)
	163	return;
	164
26bcb879	165	cmd64x_tune_pio(drive, pio);
1da177e4 LT	166	}
1da177e4 LT	167
88b2b32b	168	static void cmd64x_set_dma_mode(ide_drive_t *drive, const u8 speed)
1da177e4	169	{
898ec223	170	ide_hwif_t *hwif = drive->hwif;
36501650	171	struct pci_dev *dev = to_pci_dev(hwif->dev);
60e7a82f SS	172	u8 unit = drive->dn & 0x01;
60e7a82f SS	173	u8 regU = 0, pciU = hwif->channel ? UDIDETCR1 : UDIDETCR0;
1da177e4	174
f92d50e6	175	if (speed >= XFER_SW_DMA_0) {
1da177e4	176	(void) pci_read_config_byte(dev, pciU, &regU);
1da177e4	177	regU &= ~(unit ? 0xCA : 0x35);
1da177e4 LT	178	}
	179
	180	switch(speed) {
60e7a82f SS	181	case XFER_UDMA_5:
	182	regU \|= unit ? 0x0A : 0x05;
	183	break;
	184	case XFER_UDMA_4:
	185	regU \|= unit ? 0x4A : 0x15;
	186	break;
	187	case XFER_UDMA_3:
	188	regU \|= unit ? 0x8A : 0x25;
	189	break;
	190	case XFER_UDMA_2:
	191	regU \|= unit ? 0x42 : 0x11;
	192	break;
	193	case XFER_UDMA_1:
	194	regU \|= unit ? 0x82 : 0x21;
	195	break;
	196	case XFER_UDMA_0:
	197	regU \|= unit ? 0xC2 : 0x31;
	198	break;
	199	case XFER_MW_DMA_2:
	200	program_cycle_times(drive, 120, 70);
	201	break;
	202	case XFER_MW_DMA_1:
	203	program_cycle_times(drive, 150, 80);
	204	break;
	205	case XFER_MW_DMA_0:
	206	program_cycle_times(drive, 480, 215);
	207	break;
1da177e4 LT	208	}
1da177e4 LT	209
60e7a82f	210	if (speed >= XFER_SW_DMA_0)
1da177e4	211	(void) pci_write_config_byte(dev, pciU, regU);
1da177e4 LT	212	}
1da177e4 LT	213
30e5ffc3	214	static void cmd648_clear_irq(ide_drive_t *drive)
1da177e4	215	{
898ec223	216	ide_hwif_t *hwif = drive->hwif;
30e5ffc3 SS	217	struct pci_dev *dev = to_pci_dev(hwif->dev);
30e5ffc3 SS	218	unsigned long base = pci_resource_start(dev, 4);
66602c83 SS	219	u8 irq_mask = hwif->channel ? MRDMODE_INTR_CH1 :
66602c83 SS	220	MRDMODE_INTR_CH0;
1c029fd6	221	u8 mrdmode = inb(base + 1);
66602c83 SS	222
66602c83 SS	223	/* clear the interrupt bit */
6183289c	224	outb((mrdmode & ~(MRDMODE_INTR_CH0 \| MRDMODE_INTR_CH1)) \| irq_mask,
1c029fd6	225	base + 1);
1da177e4 LT	226	}
1da177e4 LT	227
30e5ffc3	228	static void cmd64x_clear_irq(ide_drive_t *drive)
1da177e4	229	{
898ec223	230	ide_hwif_t *hwif = drive->hwif;
36501650	231	struct pci_dev *dev = to_pci_dev(hwif->dev);
66602c83 SS	232	int irq_reg = hwif->channel ? ARTTIM23 : CFR;
	233	u8 irq_mask = hwif->channel ? ARTTIM23_INTR_CH1 :
	234	CFR_INTR_CH0;
	235	u8 irq_stat = 0;
1da177e4	236
66602c83 SS	237	(void) pci_read_config_byte(dev, irq_reg, &irq_stat);
	238	/* clear the interrupt bit */
	239	(void) pci_write_config_byte(dev, irq_reg, irq_stat \| irq_mask);
66602c83 SS	240	}
66602c83 SS	241
628df2f3	242	static int cmd648_test_irq(ide_hwif_t *hwif)
66602c83	243	{
628df2f3 SS	244	struct pci_dev *dev = to_pci_dev(hwif->dev);
628df2f3 SS	245	unsigned long base = pci_resource_start(dev, 4);
66602c83 SS	246	u8 irq_mask = hwif->channel ? MRDMODE_INTR_CH1 :
66602c83 SS	247	MRDMODE_INTR_CH0;
1c029fd6	248	u8 mrdmode = inb(base + 1);
66602c83	249
628df2f3 SS	250	pr_debug("%s: mrdmode: 0x%02x irq_mask: 0x%02x\n",
628df2f3 SS	251	hwif->name, mrdmode, irq_mask);
66602c83	252
628df2f3	253	return (mrdmode & irq_mask) ? 1 : 0;
1da177e4 LT	254	}
1da177e4 LT	255
628df2f3	256	static int cmd64x_test_irq(ide_hwif_t *hwif)
1da177e4	257	{
36501650	258	struct pci_dev *dev = to_pci_dev(hwif->dev);
66602c83 SS	259	int irq_reg = hwif->channel ? ARTTIM23 : CFR;
	260	u8 irq_mask = hwif->channel ? ARTTIM23_INTR_CH1 :
	261	CFR_INTR_CH0;
66602c83	262	u8 irq_stat = 0;
e51e2528 SS	263
e51e2528 SS	264	(void) pci_read_config_byte(dev, irq_reg, &irq_stat);
1da177e4	265
628df2f3 SS	266	pr_debug("%s: irq_stat: 0x%02x irq_mask: 0x%02x\n",
628df2f3 SS	267	hwif->name, irq_stat, irq_mask);
1da177e4	268
628df2f3	269	return (irq_stat & irq_mask) ? 1 : 0;
1da177e4 LT	270	}
	271
	272	/*
	273	* ASUS P55T2P4D with CMD646 chipset revision 0x01 requires the old
	274	* event order for DMA transfers.
	275	*/
	276
5e37bdc0	277	static int cmd646_1_dma_end(ide_drive_t *drive)
1da177e4	278	{
898ec223	279	ide_hwif_t *hwif = drive->hwif;
1da177e4 LT	280	u8 dma_stat = 0, dma_cmd = 0;
1da177e4 LT	281
1da177e4	282	/* get DMA status */
cab7f8ed	283	dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
1da177e4	284	/* read DMA command state */
cab7f8ed	285	dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
1da177e4	286	/* stop DMA */
cab7f8ed	287	outb(dma_cmd & ~1, hwif->dma_base + ATA_DMA_CMD);
1da177e4	288	/* clear the INTR & ERROR bits */
cab7f8ed	289	outb(dma_stat \| 6, hwif->dma_base + ATA_DMA_STATUS);
1da177e4 LT	290	/* verify good DMA status */
	291	return (dma_stat & 7) != 4;
	292	}
	293
2ed0ef54	294	static int init_chipset_cmd64x(struct pci_dev *dev)
1da177e4	295	{
1da177e4 LT	296	u8 mrdmode = 0;
1da177e4 LT	297
1da177e4 LT	298	/* Set a good latency timer and cache line size value. */
	299	(void) pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
	300	/* FIXME: pci_set_master() to ensure a good latency timer value */
	301
83a6d4ab SS	302	/*
	303	* Enable interrupts, select MEMORY READ LINE for reads.
	304	*
	305	* NOTE: although not mentioned in the PCI0646U specs,
	306	* bits 0-1 are write only and won't be read back as
	307	* set or not -- PCI0646U2 specs clarify this point.
1da177e4	308	*/
83a6d4ab SS	309	(void) pci_read_config_byte (dev, MRDMODE, &mrdmode);
	310	mrdmode &= ~0x30;
	311	(void) pci_write_config_byte(dev, MRDMODE, (mrdmode \| 0x02));
1da177e4	312
1da177e4 LT	313	return 0;
	314	}
	315
f454cbe8	316	static u8 cmd64x_cable_detect(ide_hwif_t *hwif)
1da177e4	317	{
36501650	318	struct pci_dev *dev = to_pci_dev(hwif->dev);
83a6d4ab	319	u8 bmidecsr = 0, mask = hwif->channel ? 0x02 : 0x01;
1da177e4	320
83a6d4ab SS	321	switch (dev->device) {
	322	case PCI_DEVICE_ID_CMD_648:
	323	case PCI_DEVICE_ID_CMD_649:
	324	pci_read_config_byte(dev, BMIDECSR, &bmidecsr);
49521f97	325	return (bmidecsr & mask) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
83a6d4ab	326	default:
49521f97	327	return ATA_CBL_PATA40;
1da177e4	328	}
1da177e4 LT	329	}
1da177e4 LT	330
ac95beed BZ	331	static const struct ide_port_ops cmd64x_port_ops = {
	332	.set_pio_mode = cmd64x_set_pio_mode,
	333	.set_dma_mode = cmd64x_set_dma_mode,
30e5ffc3	334	.clear_irq = cmd64x_clear_irq,
628df2f3	335	.test_irq = cmd64x_test_irq,
30e5ffc3 SS	336	.cable_detect = cmd64x_cable_detect,
	337	};
	338
	339	static const struct ide_port_ops cmd648_port_ops = {
	340	.set_pio_mode = cmd64x_set_pio_mode,
	341	.set_dma_mode = cmd64x_set_dma_mode,
	342	.clear_irq = cmd648_clear_irq,
628df2f3	343	.test_irq = cmd648_test_irq,
ac95beed BZ	344	.cable_detect = cmd64x_cable_detect,
	345	};
	346
f37afdac BZ	347	static const struct ide_dma_ops cmd646_rev1_dma_ops = {
	348	.dma_host_set = ide_dma_host_set,
	349	.dma_setup = ide_dma_setup,
f37afdac	350	.dma_start = ide_dma_start,
5e37bdc0	351	.dma_end = cmd646_1_dma_end,
f37afdac BZ	352	.dma_test_irq = ide_dma_test_irq,
f37afdac BZ	353	.dma_lost_irq = ide_dma_lost_irq,
22117d6e	354	.dma_timer_expiry = ide_dma_sff_timer_expiry,
592b5315	355	.dma_sff_read_status = ide_dma_sff_read_status,
5e37bdc0 BZ	356	};
5e37bdc0 BZ	357
85620436	358	static const struct ide_port_info cmd64x_chipsets[] __devinitdata = {
ced3ec8a BZ	359	{ /* 0: CMD643 */
ced3ec8a BZ	360	.name = DRV_NAME,
1da177e4	361	.init_chipset = init_chipset_cmd64x,
7accbffd	362	.enablebits = {{0x00,0x00,0x00}, {0x51,0x08,0x08}},
ac95beed	363	.port_ops = &cmd64x_port_ops,
8ac2b42a	364	.host_flags = IDE_HFLAG_CLEAR_SIMPLEX \|
9bd7496f MP	365	IDE_HFLAG_ABUSE_PREFETCH \|
9bd7496f MP	366	IDE_HFLAG_SERIALIZE,
4099d143	367	.pio_mask = ATA_PIO5,
5f8b6c34	368	.mwdma_mask = ATA_MWDMA2,
18137207	369	.udma_mask = 0x00, /* no udma */
ced3ec8a BZ	370	},
	371	{ /* 1: CMD646 */
	372	.name = DRV_NAME,
1da177e4	373	.init_chipset = init_chipset_cmd64x,
7accbffd	374	.enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
30e5ffc3	375	.port_ops = &cmd648_port_ops,
9bd7496f MP	376	.host_flags = IDE_HFLAG_ABUSE_PREFETCH \|
9bd7496f MP	377	IDE_HFLAG_SERIALIZE,
4099d143	378	.pio_mask = ATA_PIO5,
5f8b6c34 BZ	379	.mwdma_mask = ATA_MWDMA2,
5f8b6c34 BZ	380	.udma_mask = ATA_UDMA2,
ced3ec8a BZ	381	},
	382	{ /* 2: CMD648 */
	383	.name = DRV_NAME,
1da177e4	384	.init_chipset = init_chipset_cmd64x,
7accbffd	385	.enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
30e5ffc3	386	.port_ops = &cmd648_port_ops,
5e71d9c5	387	.host_flags = IDE_HFLAG_ABUSE_PREFETCH,
4099d143	388	.pio_mask = ATA_PIO5,
5f8b6c34 BZ	389	.mwdma_mask = ATA_MWDMA2,
5f8b6c34 BZ	390	.udma_mask = ATA_UDMA4,
ced3ec8a BZ	391	},
	392	{ /* 3: CMD649 */
	393	.name = DRV_NAME,
1da177e4	394	.init_chipset = init_chipset_cmd64x,
7accbffd	395	.enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
30e5ffc3	396	.port_ops = &cmd648_port_ops,
5e71d9c5	397	.host_flags = IDE_HFLAG_ABUSE_PREFETCH,
4099d143	398	.pio_mask = ATA_PIO5,
5f8b6c34 BZ	399	.mwdma_mask = ATA_MWDMA2,
5f8b6c34 BZ	400	.udma_mask = ATA_UDMA5,
1da177e4 LT	401	}
	402	};
	403
	404	static int __devinit cmd64x_init_one(struct pci_dev dev, const struct pci_device_id id)
	405	{
039788e1	406	struct ide_port_info d;
bfd314a3 BZ	407	u8 idx = id->driver_data;
	408
	409	d = cmd64x_chipsets[idx];
	410
5e37bdc0 BZ	411	if (idx == 1) {
	412	/*
	413	* UltraDMA only supported on PCI646U and PCI646U2, which
	414	* correspond to revisions 0x03, 0x05 and 0x07 respectively.
	415	* Actually, although the CMD tech support people won't
	416	* tell me the details, the 0x03 revision cannot support
	417	* UDMA correctly without hardware modifications, and even
	418	* then it only works with Quantum disks due to some
	419	* hold time assumptions in the 646U part which are fixed
	420	* in the 646U2.
	421	*
	422	* So we only do UltraDMA on revision 0x05 and 0x07 chipsets.
	423	*/
	424	if (dev->revision < 5) {
	425	d.udma_mask = 0x00;
	426	/*
	427	* The original PCI0646 didn't have the primary
	428	* channel enable bit, it appeared starting with
	429	* PCI0646U (i.e. revision ID 3).
	430	*/
	431	if (dev->revision < 3) {
	432	d.enablebits[0].reg = 0;
30e5ffc3	433	d.port_ops = &cmd64x_port_ops;
5e37bdc0 BZ	434	if (dev->revision == 1)
5e37bdc0 BZ	435	d.dma_ops = &cmd646_rev1_dma_ops;
5e37bdc0 BZ	436	}
	437	}
	438	}
7accbffd	439
6cdf6eb3	440	return ide_pci_init_one(dev, &d, NULL);
1da177e4 LT	441	}
1da177e4 LT	442
9cbcc5e3 BZ	443	static const struct pci_device_id cmd64x_pci_tbl[] = {
	444	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_643), 0 },
	445	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_646), 1 },
	446	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_648), 2 },
	447	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_649), 3 },
1da177e4 LT	448	{ 0, },
	449	};
	450	MODULE_DEVICE_TABLE(pci, cmd64x_pci_tbl);
	451
a9ab09e2	452	static struct pci_driver cmd64x_pci_driver = {
1da177e4 LT	453	.name = "CMD64x_IDE",
	454	.id_table = cmd64x_pci_tbl,
	455	.probe = cmd64x_init_one,
e2b15b47	456	.remove = ide_pci_remove,
feb22b7f BZ	457	.suspend = ide_pci_suspend,
feb22b7f BZ	458	.resume = ide_pci_resume,
1da177e4 LT	459	};
1da177e4 LT	460
82ab1eec	461	static int __init cmd64x_ide_init(void)
1da177e4	462	{
a9ab09e2	463	return ide_pci_register_driver(&cmd64x_pci_driver);
1da177e4 LT	464	}
1da177e4 LT	465
e2b15b47 BZ	466	static void __exit cmd64x_ide_exit(void)
e2b15b47 BZ	467	{
a9ab09e2	468	pci_unregister_driver(&cmd64x_pci_driver);
e2b15b47 BZ	469	}
e2b15b47 BZ	470
1da177e4	471	module_init(cmd64x_ide_init);
e2b15b47	472	module_exit(cmd64x_ide_exit);
1da177e4 LT	473
	474	MODULE_AUTHOR("Eddie Dost, David Miller, Andre Hedrick");
	475	MODULE_DESCRIPTION("PCI driver module for CMD64x IDE");
	476	MODULE_LICENSE("GPL");