[net-next-2.6.git] / drivers / ide / at91_ide.c

/*
 * IDE host driver for AT91 (SAM9, CAP9, AT572D940HF) Static Memory Controller
 * with Compact Flash True IDE logic
 *
 * Copyright (c) 2008, 2009 Kelvatek Ltd.
 *
 *  This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 *
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/ide.h>
#include <linux/platform_device.h>

#include <mach/board.h>
#include <mach/gpio.h>
#include <mach/at91sam9_smc.h>

#define DRV_NAME "at91_ide"

#define perr(fmt, args...) pr_err(DRV_NAME ": " fmt, ##args)
#define pdbg(fmt, args...) pr_debug("%s " fmt, __func__, ##args)

/*
 * Access to IDE device is possible through EBI Static Memory Controller
 * with Compact Flash logic. For details see EBI and SMC datasheet sections
 * of any microcontroller from AT91SAM9 family.
 *
 * Within SMC chip select address space, lines A[23:21] distinguish Compact
 * Flash modes (I/O, common memory, attribute memory, True IDE). IDE modes are:
 *   0x00c0000 - True IDE
 *   0x00e0000 - Alternate True IDE (Alt Status Register)
 *
 * On True IDE mode Task File and Data Register are mapped at the same address.
 * To distinguish access between these two different bus data width is used:
 * 8Bit for Task File, 16Bit for Data I/O.
 *
 * After initialization we do 8/16 bit flipping (changes in SMC MODE register)
 * only inside IDE callback routines which are serialized by IDE layer,
 * so no additional locking needed.
 */

#define TASK_FILE	0x00c00000
#define ALT_MODE	0x00e00000
#define REGS_SIZE	8

#define enter_16bit(cs, mode) do {					\
	mode = at91_sys_read(AT91_SMC_MODE(cs));			\
	at91_sys_write(AT91_SMC_MODE(cs), mode | AT91_SMC_DBW_16);	\
} while (0)

#define leave_16bit(cs, mode) at91_sys_write(AT91_SMC_MODE(cs), mode);

static void set_smc_timings(const u8 chipselect, const u16 cycle,
			    const u16 setup, const u16 pulse,
			    const u16 data_float, int use_iordy)
{
	unsigned long mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
			     AT91_SMC_BAT_SELECT;

	/* disable or enable waiting for IORDY signal */
	if (use_iordy)
		mode |= AT91_SMC_EXNWMODE_READY;

	/* add data float cycles if needed */
	if (data_float)
		mode |= AT91_SMC_TDF_(data_float);

	at91_sys_write(AT91_SMC_MODE(chipselect), mode);

	/* setup timings in SMC */
	at91_sys_write(AT91_SMC_SETUP(chipselect), AT91_SMC_NWESETUP_(setup) |
						   AT91_SMC_NCS_WRSETUP_(0) |
						   AT91_SMC_NRDSETUP_(setup) |
						   AT91_SMC_NCS_RDSETUP_(0));
	at91_sys_write(AT91_SMC_PULSE(chipselect), AT91_SMC_NWEPULSE_(pulse) |
						   AT91_SMC_NCS_WRPULSE_(cycle) |
						   AT91_SMC_NRDPULSE_(pulse) |
						   AT91_SMC_NCS_RDPULSE_(cycle));
	at91_sys_write(AT91_SMC_CYCLE(chipselect), AT91_SMC_NWECYCLE_(cycle) |
						   AT91_SMC_NRDCYCLE_(cycle));
}

static unsigned int calc_mck_cycles(unsigned int ns, unsigned int mck_hz)
{
	u64 tmp = ns;

	tmp *= mck_hz;
	tmp += 1000*1000*1000 - 1; /* round up */
	do_div(tmp, 1000*1000*1000);
	return (unsigned int) tmp;
}

static void apply_timings(const u8 chipselect, const u8 pio,
			  const struct ide_timing *timing, int use_iordy)
{
	unsigned int t0, t1, t2, t6z;
	unsigned int cycle, setup, pulse, data_float;
	unsigned int mck_hz;
	struct clk *mck;

	/* see table 22 of Compact Flash standard 4.1 for the meaning,
	 * we do not stretch active (t2) time, so setup (t1) + hold time (th)
	 * assure at least minimal recovery (t2i) time */
	t0 = timing->cyc8b;
	t1 = timing->setup;
	t2 = timing->act8b;
	t6z = (pio < 5) ? 30 : 20;

	pdbg("t0=%u t1=%u t2=%u t6z=%u\n", t0, t1, t2, t6z);

	mck = clk_get(NULL, "mck");
	BUG_ON(IS_ERR(mck));
	mck_hz = clk_get_rate(mck);
	pdbg("mck_hz=%u\n", mck_hz);

	cycle = calc_mck_cycles(t0, mck_hz);
	setup = calc_mck_cycles(t1, mck_hz);
	pulse = calc_mck_cycles(t2, mck_hz);
	data_float = calc_mck_cycles(t6z, mck_hz);

	pdbg("cycle=%u setup=%u pulse=%u data_float=%u\n",
	     cycle, setup, pulse, data_float);

	set_smc_timings(chipselect, cycle, setup, pulse, data_float, use_iordy);
}

static void at91_ide_input_data(ide_drive_t *drive, struct ide_cmd *cmd,
				void *buf, unsigned int len)
{
	ide_hwif_t *hwif = drive->hwif;
	struct ide_io_ports *io_ports = &hwif->io_ports;
	u8 chipselect = hwif->select_data;
	unsigned long mode;

	pdbg("cs %u buf %p len %d\n", chipselect, buf, len);

	len++;

	enter_16bit(chipselect, mode);
	readsw((void __iomem *)io_ports->data_addr, buf, len / 2);
	leave_16bit(chipselect, mode);
}

static void at91_ide_output_data(ide_drive_t *drive, struct ide_cmd *cmd,
				 void *buf, unsigned int len)
{
	ide_hwif_t *hwif = drive->hwif;
	struct ide_io_ports *io_ports = &hwif->io_ports;
	u8 chipselect = hwif->select_data;
	unsigned long mode;

	pdbg("cs %u buf %p len %d\n", chipselect,  buf, len);

	enter_16bit(chipselect, mode);
	writesw((void __iomem *)io_ports->data_addr, buf, len / 2);
	leave_16bit(chipselect, mode);
}

static void at91_ide_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
{
	struct ide_timing *timing;
	u8 chipselect = hwif->select_data;
	int use_iordy = 0;
	const u8 pio = drive->pio_mode - XFER_PIO_0;

	pdbg("chipselect %u pio %u\n", chipselect, pio);

	timing = ide_timing_find_mode(XFER_PIO_0 + pio);
	BUG_ON(!timing);

	if (ide_pio_need_iordy(drive, pio))
		use_iordy = 1;

	apply_timings(chipselect, pio, timing, use_iordy);
}

static const struct ide_tp_ops at91_ide_tp_ops = {
	.exec_command	= ide_exec_command,
	.read_status	= ide_read_status,
	.read_altstatus	= ide_read_altstatus,
	.write_devctl	= ide_write_devctl,

	.dev_select	= ide_dev_select,
	.tf_load	= ide_tf_load,
	.tf_read	= ide_tf_read,

	.input_data	= at91_ide_input_data,
	.output_data	= at91_ide_output_data,
};

static const struct ide_port_ops at91_ide_port_ops = {
	.set_pio_mode	= at91_ide_set_pio_mode,
};

static const struct ide_port_info at91_ide_port_info __initdata = {
	.port_ops	= &at91_ide_port_ops,
	.tp_ops		= &at91_ide_tp_ops,
	.host_flags 	= IDE_HFLAG_MMIO | IDE_HFLAG_NO_DMA | IDE_HFLAG_SINGLE |
			  IDE_HFLAG_NO_IO_32BIT | IDE_HFLAG_UNMASK_IRQS,
	.pio_mask 	= ATA_PIO6,
	.chipset	= ide_generic,
};

/*
 * If interrupt is delivered through GPIO, IRQ are triggered on falling
 * and rising edge of signal. Whereas IDE device request interrupt on high
 * level (rising edge in our case). This mean we have fake interrupts, so
 * we need to check interrupt pin and exit instantly from ISR when line
 * is on low level.
 */

irqreturn_t at91_irq_handler(int irq, void *dev_id)
{
	int ntries = 8;
	int pin_val1, pin_val2;

	/* additional deglitch, line can be noisy in badly designed PCB */
	do {
		pin_val1 = at91_get_gpio_value(irq);
		pin_val2 = at91_get_gpio_value(irq);
	} while (pin_val1 != pin_val2 && --ntries > 0);

	if (pin_val1 == 0 || ntries <= 0)
		return IRQ_HANDLED;

	return ide_intr(irq, dev_id);
}

static int __init at91_ide_probe(struct platform_device *pdev)
{
	int ret;
	struct ide_hw hw, *hws[] = { &hw };
	struct ide_host *host;
	struct resource *res;
	unsigned long tf_base = 0, ctl_base = 0;
	struct at91_cf_data *board = pdev->dev.platform_data;

	if (!board)
		return -ENODEV;

	if (board->det_pin && at91_get_gpio_value(board->det_pin) != 0) {
		perr("no device detected\n");
		return -ENODEV;
	}

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res) {
		perr("can't get memory resource\n");
		return -ENODEV;
	}

	if (!devm_request_mem_region(&pdev->dev, res->start + TASK_FILE,
				     REGS_SIZE, "ide") ||
	    !devm_request_mem_region(&pdev->dev, res->start + ALT_MODE,
				     REGS_SIZE, "alt")) {
		perr("memory resources in use\n");
		return -EBUSY;
	}

	pdbg("chipselect %u irq %u res %08lx\n", board->chipselect,
	     board->irq_pin, (unsigned long) res->start);

	tf_base = (unsigned long) devm_ioremap(&pdev->dev, res->start + TASK_FILE,
					       REGS_SIZE);
	ctl_base = (unsigned long) devm_ioremap(&pdev->dev, res->start + ALT_MODE,
						REGS_SIZE);
	if (!tf_base || !ctl_base) {
		perr("can't map memory regions\n");
		return -EBUSY;
	}

	memset(&hw, 0, sizeof(hw));

	if (board->flags & AT91_IDE_SWAP_A0_A2) {
		/* workaround for stupid hardware bug */
		hw.io_ports.data_addr	= tf_base + 0;
		hw.io_ports.error_addr	= tf_base + 4;
		hw.io_ports.nsect_addr	= tf_base + 2;
		hw.io_ports.lbal_addr	= tf_base + 6;
		hw.io_ports.lbam_addr	= tf_base + 1;
		hw.io_ports.lbah_addr	= tf_base + 5;
		hw.io_ports.device_addr = tf_base + 3;
		hw.io_ports.command_addr = tf_base + 7;
		hw.io_ports.ctl_addr	= ctl_base + 3;
	} else
		ide_std_init_ports(&hw, tf_base, ctl_base + 6);

	hw.irq = board->irq_pin;
	hw.dev = &pdev->dev;

	host = ide_host_alloc(&at91_ide_port_info, hws, 1);
	if (!host) {
		perr("failed to allocate ide host\n");
		return -ENOMEM;
	}

	/* setup Static Memory Controller - PIO 0 as default */
	apply_timings(board->chipselect, 0, ide_timing_find_mode(XFER_PIO_0), 0);

	/* with GPIO interrupt we have to do quirks in handler */
	if (board->irq_pin >= PIN_BASE)
		host->irq_handler = at91_irq_handler;

	host->ports[0]->select_data = board->chipselect;

	ret = ide_host_register(host, &at91_ide_port_info, hws);
	if (ret) {
		perr("failed to register ide host\n");
		goto err_free_host;
	}
	platform_set_drvdata(pdev, host);
	return 0;

err_free_host:
	ide_host_free(host);
	return ret;
}

static int __exit at91_ide_remove(struct platform_device *pdev)
{
	struct ide_host *host = platform_get_drvdata(pdev);

	ide_host_remove(host);
	return 0;
}

static struct platform_driver at91_ide_driver = {
	.driver	= {
		.name = DRV_NAME,
		.owner = THIS_MODULE,
	},
	.remove	= __exit_p(at91_ide_remove),
};

static int __init at91_ide_init(void)
{
	return platform_driver_probe(&at91_ide_driver, at91_ide_probe);
}

static void __exit at91_ide_exit(void)
{
	platform_driver_unregister(&at91_ide_driver);
}

module_init(at91_ide_init);
module_exit(at91_ide_exit);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Stanislaw Gruszka <stf_xl@wp.pl>");
Commit	Line	Data
6e5f1e11 SG	1	/*
	2	* IDE host driver for AT91 (SAM9, CAP9, AT572D940HF) Static Memory Controller
	3	* with Compact Flash True IDE logic
	4	*
	5	* Copyright (c) 2008, 2009 Kelvatek Ltd.
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	20	*
	21	*/
	22
6e5f1e11 SG	23	#include <linux/kernel.h>
	24	#include <linux/module.h>
	25	#include <linux/clk.h>
	26	#include <linux/err.h>
	27	#include <linux/ide.h>
	28	#include <linux/platform_device.h>
	29
	30	#include <mach/board.h>
	31	#include <mach/gpio.h>
6e5f1e11	32	#include <mach/at91sam9_smc.h>
6e5f1e11 SG	33
	34	#define DRV_NAME "at91_ide"
	35
	36	#define perr(fmt, args...) pr_err(DRV_NAME ": " fmt, ##args)
	37	#define pdbg(fmt, args...) pr_debug("%s " fmt, __func__, ##args)
	38
	39	/*
	40	* Access to IDE device is possible through EBI Static Memory Controller
	41	* with Compact Flash logic. For details see EBI and SMC datasheet sections
	42	* of any microcontroller from AT91SAM9 family.
	43	*
	44	* Within SMC chip select address space, lines A[23:21] distinguish Compact
	45	* Flash modes (I/O, common memory, attribute memory, True IDE). IDE modes are:
	46	* 0x00c0000 - True IDE
	47	* 0x00e0000 - Alternate True IDE (Alt Status Register)
	48	*
	49	* On True IDE mode Task File and Data Register are mapped at the same address.
	50	* To distinguish access between these two different bus data width is used:
	51	* 8Bit for Task File, 16Bit for Data I/O.
	52	*
	53	* After initialization we do 8/16 bit flipping (changes in SMC MODE register)
	54	* only inside IDE callback routines which are serialized by IDE layer,
	55	* so no additional locking needed.
	56	*/
	57
	58	#define TASK_FILE 0x00c00000
	59	#define ALT_MODE 0x00e00000
	60	#define REGS_SIZE 8
	61
	62	#define enter_16bit(cs, mode) do { \
	63	mode = at91_sys_read(AT91_SMC_MODE(cs)); \
	64	at91_sys_write(AT91_SMC_MODE(cs), mode \| AT91_SMC_DBW_16); \
	65	} while (0)
	66
	67	#define leave_16bit(cs, mode) at91_sys_write(AT91_SMC_MODE(cs), mode);
	68
	69	static void set_smc_timings(const u8 chipselect, const u16 cycle,
	70	const u16 setup, const u16 pulse,
	71	const u16 data_float, int use_iordy)
	72	{
	73	unsigned long mode = AT91_SMC_READMODE \| AT91_SMC_WRITEMODE \|
	74	AT91_SMC_BAT_SELECT;
	75
	76	/* disable or enable waiting for IORDY signal */
	77	if (use_iordy)
	78	mode \|= AT91_SMC_EXNWMODE_READY;
	79
	80	/* add data float cycles if needed */
	81	if (data_float)
	82	mode \|= AT91_SMC_TDF_(data_float);
	83
	84	at91_sys_write(AT91_SMC_MODE(chipselect), mode);
	85
	86	/* setup timings in SMC */
	87	at91_sys_write(AT91_SMC_SETUP(chipselect), AT91_SMC_NWESETUP_(setup) \|
	88	AT91_SMC_NCS_WRSETUP_(0) \|
	89	AT91_SMC_NRDSETUP_(setup) \|
	90	AT91_SMC_NCS_RDSETUP_(0));
	91	at91_sys_write(AT91_SMC_PULSE(chipselect), AT91_SMC_NWEPULSE_(pulse) \|
	92	AT91_SMC_NCS_WRPULSE_(cycle) \|
	93	AT91_SMC_NRDPULSE_(pulse) \|
	94	AT91_SMC_NCS_RDPULSE_(cycle));
	95	at91_sys_write(AT91_SMC_CYCLE(chipselect), AT91_SMC_NWECYCLE_(cycle) \|
	96	AT91_SMC_NRDCYCLE_(cycle));
97	}
98
99	static unsigned int calc_mck_cycles(unsigned int ns, unsigned int mck_hz)
100	{
101	u64 tmp = ns;
102
103	tmp *= mck_hz;
104	tmp += 100010001000 - 1; /* round up */
105	do_div(tmp, 100010001000);
106	return (unsigned int) tmp;
107	}
108
109	static void apply_timings(const u8 chipselect, const u8 pio,
110	const struct ide_timing *timing, int use_iordy)
111	{
112	unsigned int t0, t1, t2, t6z;
113	unsigned int cycle, setup, pulse, data_float;
114	unsigned int mck_hz;
115	struct clk *mck;
116
117	/* see table 22 of Compact Flash standard 4.1 for the meaning,
118	* we do not stretch active (t2) time, so setup (t1) + hold time (th)
119	* assure at least minimal recovery (t2i) time */
120	t0 = timing->cyc8b;
121	t1 = timing->setup;
122	t2 = timing->act8b;
123	t6z = (pio < 5) ? 30 : 20;
124
125	pdbg("t0=%u t1=%u t2=%u t6z=%u\n", t0, t1, t2, t6z);
126
127	mck = clk_get(NULL, "mck");
128	BUG_ON(IS_ERR(mck));
129	mck_hz = clk_get_rate(mck);
130	pdbg("mck_hz=%u\n", mck_hz);
131
132	cycle = calc_mck_cycles(t0, mck_hz);
133	setup = calc_mck_cycles(t1, mck_hz);
134	pulse = calc_mck_cycles(t2, mck_hz);
135	data_float = calc_mck_cycles(t6z, mck_hz);
136
137	pdbg("cycle=%u setup=%u pulse=%u data_float=%u\n",
138	cycle, setup, pulse, data_float);
139
140	set_smc_timings(chipselect, cycle, setup, pulse, data_float, use_iordy);
141	}
142
adb1af98	143	static void at91_ide_input_data(ide_drive_t drive, struct ide_cmd cmd,
6e5f1e11 SG	144	void *buf, unsigned int len)
	145	{
	146	ide_hwif_t *hwif = drive->hwif;
	147	struct ide_io_ports *io_ports = &hwif->io_ports;
	148	u8 chipselect = hwif->select_data;
	149	unsigned long mode;
	150
	151	pdbg("cs %u buf %p len %d\n", chipselect, buf, len);
	152
	153	len++;
	154
	155	enter_16bit(chipselect, mode);
443d18c8	156	readsw((void __iomem *)io_ports->data_addr, buf, len / 2);
6e5f1e11 SG	157	leave_16bit(chipselect, mode);
	158	}
	159
adb1af98	160	static void at91_ide_output_data(ide_drive_t drive, struct ide_cmd cmd,
6e5f1e11 SG	161	void *buf, unsigned int len)
	162	{
	163	ide_hwif_t *hwif = drive->hwif;
	164	struct ide_io_ports *io_ports = &hwif->io_ports;
	165	u8 chipselect = hwif->select_data;
	166	unsigned long mode;
	167
	168	pdbg("cs %u buf %p len %d\n", chipselect, buf, len);
	169
	170	enter_16bit(chipselect, mode);
443d18c8	171	writesw((void __iomem *)io_ports->data_addr, buf, len / 2);
6e5f1e11 SG	172	leave_16bit(chipselect, mode);
	173	}
	174
e085b3ca	175	static void at91_ide_set_pio_mode(ide_hwif_t hwif, ide_drive_t drive)
6e5f1e11 SG	176	{
6e5f1e11 SG	177	struct ide_timing *timing;
e085b3ca	178	u8 chipselect = hwif->select_data;
6e5f1e11	179	int use_iordy = 0;
e085b3ca	180	const u8 pio = drive->pio_mode - XFER_PIO_0;
6e5f1e11 SG	181
	182	pdbg("chipselect %u pio %u\n", chipselect, pio);
	183
	184	timing = ide_timing_find_mode(XFER_PIO_0 + pio);
	185	BUG_ON(!timing);
	186
c9ef59ff	187	if (ide_pio_need_iordy(drive, pio))
6e5f1e11 SG	188	use_iordy = 1;
	189
	190	apply_timings(chipselect, pio, timing, use_iordy);
	191	}
	192
	193	static const struct ide_tp_ops at91_ide_tp_ops = {
	194	.exec_command = ide_exec_command,
	195	.read_status = ide_read_status,
	196	.read_altstatus = ide_read_altstatus,
ecf3a31d	197	.write_devctl = ide_write_devctl,
6e5f1e11	198
abb596b2	199	.dev_select = ide_dev_select,
7636e455 SS	200	.tf_load = ide_tf_load,
7636e455 SS	201	.tf_read = ide_tf_read,
6e5f1e11 SG	202
	203	.input_data = at91_ide_input_data,
	204	.output_data = at91_ide_output_data,
	205	};
	206
	207	static const struct ide_port_ops at91_ide_port_ops = {
	208	.set_pio_mode = at91_ide_set_pio_mode,
	209	};
	210
	211	static const struct ide_port_info at91_ide_port_info __initdata = {
	212	.port_ops = &at91_ide_port_ops,
	213	.tp_ops = &at91_ide_tp_ops,
	214	.host_flags = IDE_HFLAG_MMIO \| IDE_HFLAG_NO_DMA \| IDE_HFLAG_SINGLE \|
	215	IDE_HFLAG_NO_IO_32BIT \| IDE_HFLAG_UNMASK_IRQS,
fb4252e5	216	.pio_mask = ATA_PIO6,
29e52cf7	217	.chipset = ide_generic,
6e5f1e11 SG	218	};
	219
	220	/*
	221	* If interrupt is delivered through GPIO, IRQ are triggered on falling
	222	* and rising edge of signal. Whereas IDE device request interrupt on high
	223	* level (rising edge in our case). This mean we have fake interrupts, so
	224	* we need to check interrupt pin and exit instantly from ISR when line
	225	* is on low level.
	226	*/
	227
	228	irqreturn_t at91_irq_handler(int irq, void *dev_id)
	229	{
	230	int ntries = 8;
	231	int pin_val1, pin_val2;
	232
	233	/* additional deglitch, line can be noisy in badly designed PCB */
	234	do {
	235	pin_val1 = at91_get_gpio_value(irq);
	236	pin_val2 = at91_get_gpio_value(irq);
	237	} while (pin_val1 != pin_val2 && --ntries > 0);
	238
	239	if (pin_val1 == 0 \|\| ntries <= 0)
	240	return IRQ_HANDLED;
	241
	242	return ide_intr(irq, dev_id);
	243	}
	244
	245	static int __init at91_ide_probe(struct platform_device *pdev)
	246	{
	247	int ret;
9f36d314	248	struct ide_hw hw, *hws[] = { &hw };
6e5f1e11 SG	249	struct ide_host *host;
	250	struct resource *res;
	251	unsigned long tf_base = 0, ctl_base = 0;
	252	struct at91_cf_data *board = pdev->dev.platform_data;
	253
	254	if (!board)
	255	return -ENODEV;
	256
	257	if (board->det_pin && at91_get_gpio_value(board->det_pin) != 0) {
	258	perr("no device detected\n");
	259	return -ENODEV;
	260	}
	261
	262	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	263	if (!res) {
	264	perr("can't get memory resource\n");
	265	return -ENODEV;
	266	}
	267
	268	if (!devm_request_mem_region(&pdev->dev, res->start + TASK_FILE,
	269	REGS_SIZE, "ide") \|\|
	270	!devm_request_mem_region(&pdev->dev, res->start + ALT_MODE,
	271	REGS_SIZE, "alt")) {
	272	perr("memory resources in use\n");
	273	return -EBUSY;
	274	}
	275
	276	pdbg("chipselect %u irq %u res %08lx\n", board->chipselect,
	277	board->irq_pin, (unsigned long) res->start);
	278
	279	tf_base = (unsigned long) devm_ioremap(&pdev->dev, res->start + TASK_FILE,
	280	REGS_SIZE);
	281	ctl_base = (unsigned long) devm_ioremap(&pdev->dev, res->start + ALT_MODE,
	282	REGS_SIZE);
	283	if (!tf_base \|\| !ctl_base) {
	284	perr("can't map memory regions\n");
	285	return -EBUSY;
	286	}
	287
	288	memset(&hw, 0, sizeof(hw));
	289
	290	if (board->flags & AT91_IDE_SWAP_A0_A2) {
	291	/* workaround for stupid hardware bug */
	292	hw.io_ports.data_addr = tf_base + 0;
	293	hw.io_ports.error_addr = tf_base + 4;
	294	hw.io_ports.nsect_addr = tf_base + 2;
	295	hw.io_ports.lbal_addr = tf_base + 6;
	296	hw.io_ports.lbam_addr = tf_base + 1;
	297	hw.io_ports.lbah_addr = tf_base + 5;
	298	hw.io_ports.device_addr = tf_base + 3;
	299	hw.io_ports.command_addr = tf_base + 7;
	300	hw.io_ports.ctl_addr = ctl_base + 3;
	301	} else
	302	ide_std_init_ports(&hw, tf_base, ctl_base + 6);
	303
	304	hw.irq = board->irq_pin;
6e5f1e11 SG	305	hw.dev = &pdev->dev;
6e5f1e11 SG	306
dca39830	307	host = ide_host_alloc(&at91_ide_port_info, hws, 1);
6e5f1e11 SG	308	if (!host) {
	309	perr("failed to allocate ide host\n");
	310	return -ENOMEM;
	311	}
	312
	313	/* setup Static Memory Controller - PIO 0 as default */
	314	apply_timings(board->chipselect, 0, ide_timing_find_mode(XFER_PIO_0), 0);
	315
	316	/* with GPIO interrupt we have to do quirks in handler */
	317	if (board->irq_pin >= PIN_BASE)
	318	host->irq_handler = at91_irq_handler;
	319
	320	host->ports[0]->select_data = board->chipselect;
	321
	322	ret = ide_host_register(host, &at91_ide_port_info, hws);
	323	if (ret) {
	324	perr("failed to register ide host\n");
	325	goto err_free_host;
	326	}
	327	platform_set_drvdata(pdev, host);
	328	return 0;
	329
	330	err_free_host:
	331	ide_host_free(host);
	332	return ret;
	333	}
	334
	335	static int __exit at91_ide_remove(struct platform_device *pdev)
	336	{
	337	struct ide_host *host = platform_get_drvdata(pdev);
	338
	339	ide_host_remove(host);
	340	return 0;
	341	}
	342
	343	static struct platform_driver at91_ide_driver = {
	344	.driver = {
	345	.name = DRV_NAME,
	346	.owner = THIS_MODULE,
	347	},
	348	.remove = __exit_p(at91_ide_remove),
	349	};
	350
	351	static int __init at91_ide_init(void)
	352	{
	353	return platform_driver_probe(&at91_ide_driver, at91_ide_probe);
	354	}
	355
	356	static void __exit at91_ide_exit(void)
	357	{
	358	platform_driver_unregister(&at91_ide_driver);
	359	}
	360
	361	module_init(at91_ide_init);
	362	module_exit(at91_ide_exit);
	363
	364	MODULE_LICENSE("GPL");
	365	MODULE_AUTHOR("Stanislaw Gruszka <stf_xl@wp.pl>");
	366