[net-next-2.6.git] / drivers / i2c / busses / i2c-sh_mobile.c

/*
 * SuperH Mobile I2C Controller
 *
 * Copyright (C) 2008 Magnus Damm
 *
 * Portions of the code based on out-of-tree driver i2c-sh7343.c
 * Copyright (c) 2006 Carlos Munoz <carlos@kenati.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/i2c.h>
#include <linux/err.h>
#include <linux/pm_runtime.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/slab.h>

/* Transmit operation:                                                      */
/*                                                                          */
/* 0 byte transmit                                                          */
/* BUS:     S     A8     ACK   P                                            */
/* IRQ:       DTE   WAIT                                                    */
/* ICIC:                                                                    */
/* ICCR: 0x94 0x90                                                          */
/* ICDR:      A8                                                            */
/*                                                                          */
/* 1 byte transmit                                                          */
/* BUS:     S     A8     ACK   D8(1)   ACK   P                              */
/* IRQ:       DTE   WAIT         WAIT                                       */
/* ICIC:      -DTE                                                          */
/* ICCR: 0x94       0x90                                                    */
/* ICDR:      A8    D8(1)                                                   */
/*                                                                          */
/* 2 byte transmit                                                          */
/* BUS:     S     A8     ACK   D8(1)   ACK   D8(2)   ACK   P                */
/* IRQ:       DTE   WAIT         WAIT          WAIT                         */
/* ICIC:      -DTE                                                          */
/* ICCR: 0x94                    0x90                                       */
/* ICDR:      A8    D8(1)        D8(2)                                      */
/*                                                                          */
/* 3 bytes or more, +---------+ gets repeated                               */
/*                                                                          */
/*                                                                          */
/* Receive operation:                                                       */
/*                                                                          */
/* 0 byte receive - not supported since slave may hold SDA low              */
/*                                                                          */
/* 1 byte receive       [TX] | [RX]                                         */
/* BUS:     S     A8     ACK | D8(1)   ACK   P                              */
/* IRQ:       DTE   WAIT     |   WAIT     DTE                               */
/* ICIC:      -DTE           |   +DTE                                       */
/* ICCR: 0x94       0x81     |   0xc0                                       */
/* ICDR:      A8             |            D8(1)                             */
/*                                                                          */
/* 2 byte receive        [TX]| [RX]                                         */
/* BUS:     S     A8     ACK | D8(1)   ACK   D8(2)   ACK   P                */
/* IRQ:       DTE   WAIT     |   WAIT          WAIT     DTE                 */
/* ICIC:      -DTE           |                 +DTE                         */
/* ICCR: 0x94       0x81     |                 0xc0                         */
/* ICDR:      A8             |                 D8(1)    D8(2)               */
/*                                                                          */
/* 3 byte receive       [TX] | [RX]                                         */
/* BUS:     S     A8     ACK | D8(1)   ACK   D8(2)   ACK   D8(3)   ACK    P */
/* IRQ:       DTE   WAIT     |   WAIT          WAIT         WAIT      DTE   */
/* ICIC:      -DTE           |                              +DTE            */
/* ICCR: 0x94       0x81     |                              0xc0            */
/* ICDR:      A8             |                 D8(1)        D8(2)     D8(3) */
/*                                                                          */
/* 4 bytes or more, this part is repeated    +---------+                    */
/*                                                                          */
/*                                                                          */
/* Interrupt order and BUSY flag                                            */
/*     ___                                                 _                */
/* SDA ___\___XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXAAAAAAAAA___/                 */
/* SCL      \_/1\_/2\_/3\_/4\_/5\_/6\_/7\_/8\___/9\_____/                   */
/*                                                                          */
/*        S   D7  D6  D5  D4  D3  D2  D1  D0              P                 */
/*                                           ___                            */
/* WAIT IRQ ________________________________/   \___________                */
/* TACK IRQ ____________________________________/   \_______                */
/* DTE  IRQ __________________________________________/   \_                */
/* AL   IRQ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX                */
/*         _______________________________________________                  */
/* BUSY __/                                               \_                */
/*                                                                          */

enum sh_mobile_i2c_op {
	OP_START = 0,
	OP_TX_FIRST,
	OP_TX,
	OP_TX_STOP,
	OP_TX_TO_RX,
	OP_RX,
	OP_RX_STOP,
	OP_RX_STOP_DATA,
};

struct sh_mobile_i2c_data {
	struct device *dev;
	void __iomem *reg;
	struct i2c_adapter adap;

	struct clk *clk;
	u_int8_t iccl;
	u_int8_t icch;

	spinlock_t lock;
	wait_queue_head_t wait;
	struct i2c_msg *msg;
	int pos;
	int sr;
};

#define NORMAL_SPEED		100000 /* FAST_SPEED 400000 */

/* Register offsets */
#define ICDR(pd)		(pd->reg + 0x00)
#define ICCR(pd)		(pd->reg + 0x04)
#define ICSR(pd)		(pd->reg + 0x08)
#define ICIC(pd)		(pd->reg + 0x0c)
#define ICCL(pd)		(pd->reg + 0x10)
#define ICCH(pd)		(pd->reg + 0x14)

/* Register bits */
#define ICCR_ICE		0x80
#define ICCR_RACK		0x40
#define ICCR_TRS		0x10
#define ICCR_BBSY		0x04
#define ICCR_SCP		0x01

#define ICSR_SCLM		0x80
#define ICSR_SDAM		0x40
#define SW_DONE			0x20
#define ICSR_BUSY		0x10
#define ICSR_AL			0x08
#define ICSR_TACK		0x04
#define ICSR_WAIT		0x02
#define ICSR_DTE		0x01

#define ICIC_ALE		0x08
#define ICIC_TACKE		0x04
#define ICIC_WAITE		0x02
#define ICIC_DTEE		0x01

static void activate_ch(struct sh_mobile_i2c_data *pd)
{
	unsigned long i2c_clk;
	u_int32_t num;
	u_int32_t denom;
	u_int32_t tmp;

	/* Wake up device and enable clock */
	pm_runtime_get_sync(pd->dev);
	clk_enable(pd->clk);

	/* Get clock rate after clock is enabled */
	i2c_clk = clk_get_rate(pd->clk);

	/* Calculate the value for iccl. From the data sheet:
	 * iccl = (p clock / transfer rate) * (L / (L + H))
	 * where L and H are the SCL low/high ratio (5/4 in this case).
	 * We also round off the result.
	 */
	num = i2c_clk * 5;
	denom = NORMAL_SPEED * 9;
	tmp = num * 10 / denom;
	if (tmp % 10 >= 5)
		pd->iccl = (u_int8_t)((num/denom) + 1);
	else
		pd->iccl = (u_int8_t)(num/denom);

	/* Calculate the value for icch. From the data sheet:
	   icch = (p clock / transfer rate) * (H / (L + H)) */
	num = i2c_clk * 4;
	tmp = num * 10 / denom;
	if (tmp % 10 >= 5)
		pd->icch = (u_int8_t)((num/denom) + 1);
	else
		pd->icch = (u_int8_t)(num/denom);

	/* Enable channel and configure rx ack */
	iowrite8(ioread8(ICCR(pd)) | ICCR_ICE, ICCR(pd));

	/* Mask all interrupts */
	iowrite8(0, ICIC(pd));

	/* Set the clock */
	iowrite8(pd->iccl, ICCL(pd));
	iowrite8(pd->icch, ICCH(pd));
}

static void deactivate_ch(struct sh_mobile_i2c_data *pd)
{
	/* Clear/disable interrupts */
	iowrite8(0, ICSR(pd));
	iowrite8(0, ICIC(pd));

	/* Disable channel */
	iowrite8(ioread8(ICCR(pd)) & ~ICCR_ICE, ICCR(pd));

	/* Disable clock and mark device as idle */
	clk_disable(pd->clk);
	pm_runtime_put_sync(pd->dev);
}

static unsigned char i2c_op(struct sh_mobile_i2c_data *pd,
			    enum sh_mobile_i2c_op op, unsigned char data)
{
	unsigned char ret = 0;
	unsigned long flags;

	dev_dbg(pd->dev, "op %d, data in 0x%02x\n", op, data);

	spin_lock_irqsave(&pd->lock, flags);

	switch (op) {
	case OP_START: /* issue start and trigger DTE interrupt */
		iowrite8(0x94, ICCR(pd));
		break;
	case OP_TX_FIRST: /* disable DTE interrupt and write data */
		iowrite8(ICIC_WAITE | ICIC_ALE | ICIC_TACKE, ICIC(pd));
		iowrite8(data, ICDR(pd));
		break;
	case OP_TX: /* write data */
		iowrite8(data, ICDR(pd));
		break;
	case OP_TX_STOP: /* write data and issue a stop afterwards */
		iowrite8(data, ICDR(pd));
		iowrite8(0x90, ICCR(pd));
		break;
	case OP_TX_TO_RX: /* select read mode */
		iowrite8(0x81, ICCR(pd));
		break;
	case OP_RX: /* just read data */
		ret = ioread8(ICDR(pd));
		break;
	case OP_RX_STOP: /* enable DTE interrupt, issue stop */
		iowrite8(ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE,
			 ICIC(pd));
		iowrite8(0xc0, ICCR(pd));
		break;
	case OP_RX_STOP_DATA: /* enable DTE interrupt, read data, issue stop */
		iowrite8(ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE,
			 ICIC(pd));
		ret = ioread8(ICDR(pd));
		iowrite8(0xc0, ICCR(pd));
		break;
	}

	spin_unlock_irqrestore(&pd->lock, flags);

	dev_dbg(pd->dev, "op %d, data out 0x%02x\n", op, ret);
	return ret;
}

static int sh_mobile_i2c_is_first_byte(struct sh_mobile_i2c_data *pd)
{
	if (pd->pos == -1)
		return 1;

	return 0;
}

static int sh_mobile_i2c_is_last_byte(struct sh_mobile_i2c_data *pd)
{
	if (pd->pos == (pd->msg->len - 1))
		return 1;

	return 0;
}

static void sh_mobile_i2c_get_data(struct sh_mobile_i2c_data *pd,
				   unsigned char *buf)
{
	switch (pd->pos) {
	case -1:
		*buf = (pd->msg->addr & 0x7f) << 1;
		*buf |= (pd->msg->flags & I2C_M_RD) ? 1 : 0;
		break;
	default:
		*buf = pd->msg->buf[pd->pos];
	}
}

static int sh_mobile_i2c_isr_tx(struct sh_mobile_i2c_data *pd)
{
	unsigned char data;

	if (pd->pos == pd->msg->len)
		return 1;

	sh_mobile_i2c_get_data(pd, &data);

	if (sh_mobile_i2c_is_last_byte(pd))
		i2c_op(pd, OP_TX_STOP, data);
	else if (sh_mobile_i2c_is_first_byte(pd))
		i2c_op(pd, OP_TX_FIRST, data);
	else
		i2c_op(pd, OP_TX, data);

	pd->pos++;
	return 0;
}

static int sh_mobile_i2c_isr_rx(struct sh_mobile_i2c_data *pd)
{
	unsigned char data;
	int real_pos;

	do {
		if (pd->pos <= -1) {
			sh_mobile_i2c_get_data(pd, &data);

			if (sh_mobile_i2c_is_first_byte(pd))
				i2c_op(pd, OP_TX_FIRST, data);
			else
				i2c_op(pd, OP_TX, data);
			break;
		}

		if (pd->pos == 0) {
			i2c_op(pd, OP_TX_TO_RX, 0);
			break;
		}

		real_pos = pd->pos - 2;

		if (pd->pos == pd->msg->len) {
			if (real_pos < 0) {
				i2c_op(pd, OP_RX_STOP, 0);
				break;
			}
			data = i2c_op(pd, OP_RX_STOP_DATA, 0);
		} else
			data = i2c_op(pd, OP_RX, 0);

		if (real_pos >= 0)
			pd->msg->buf[real_pos] = data;
	} while (0);

	pd->pos++;
	return pd->pos == (pd->msg->len + 2);
}

static irqreturn_t sh_mobile_i2c_isr(int irq, void *dev_id)
{
	struct platform_device *dev = dev_id;
	struct sh_mobile_i2c_data *pd = platform_get_drvdata(dev);
	unsigned char sr;
	int wakeup;

	sr = ioread8(ICSR(pd));
	pd->sr |= sr; /* remember state */

	dev_dbg(pd->dev, "i2c_isr 0x%02x 0x%02x %s %d %d!\n", sr, pd->sr,
	       (pd->msg->flags & I2C_M_RD) ? "read" : "write",
	       pd->pos, pd->msg->len);

	if (sr & (ICSR_AL | ICSR_TACK)) {
		/* don't interrupt transaction - continue to issue stop */
		iowrite8(sr & ~(ICSR_AL | ICSR_TACK), ICSR(pd));
		wakeup = 0;
	} else if (pd->msg->flags & I2C_M_RD)
		wakeup = sh_mobile_i2c_isr_rx(pd);
	else
		wakeup = sh_mobile_i2c_isr_tx(pd);

	if (sr & ICSR_WAIT) /* TODO: add delay here to support slow acks */
		iowrite8(sr & ~ICSR_WAIT, ICSR(pd));

	if (wakeup) {
		pd->sr |= SW_DONE;
		wake_up(&pd->wait);
	}

	return IRQ_HANDLED;
}

static int start_ch(struct sh_mobile_i2c_data *pd, struct i2c_msg *usr_msg)
{
	if (usr_msg->len == 0 && (usr_msg->flags & I2C_M_RD)) {
		dev_err(pd->dev, "Unsupported zero length i2c read\n");
		return -EIO;
	}

	/* Initialize channel registers */
	iowrite8(ioread8(ICCR(pd)) & ~ICCR_ICE, ICCR(pd));

	/* Enable channel and configure rx ack */
	iowrite8(ioread8(ICCR(pd)) | ICCR_ICE, ICCR(pd));

	/* Set the clock */
	iowrite8(pd->iccl, ICCL(pd));
	iowrite8(pd->icch, ICCH(pd));

	pd->msg = usr_msg;
	pd->pos = -1;
	pd->sr = 0;

	/* Enable all interrupts to begin with */
	iowrite8(ICIC_WAITE | ICIC_ALE | ICIC_TACKE | ICIC_DTEE, ICIC(pd));
	return 0;
}

static int sh_mobile_i2c_xfer(struct i2c_adapter *adapter,
			      struct i2c_msg *msgs,
			      int num)
{
	struct sh_mobile_i2c_data *pd = i2c_get_adapdata(adapter);
	struct i2c_msg	*msg;
	int err = 0;
	u_int8_t val;
	int i, k, retry_count;

	activate_ch(pd);

	/* Process all messages */
	for (i = 0; i < num; i++) {
		msg = &msgs[i];

		err = start_ch(pd, msg);
		if (err)
			break;

		i2c_op(pd, OP_START, 0);

		/* The interrupt handler takes care of the rest... */
		k = wait_event_timeout(pd->wait,
				       pd->sr & (ICSR_TACK | SW_DONE),
				       5 * HZ);
		if (!k)
			dev_err(pd->dev, "Transfer request timed out\n");

		retry_count = 1000;
again:
		val = ioread8(ICSR(pd));

		dev_dbg(pd->dev, "val 0x%02x pd->sr 0x%02x\n", val, pd->sr);

		/* the interrupt handler may wake us up before the
		 * transfer is finished, so poll the hardware
		 * until we're done.
		 */
		if (val & ICSR_BUSY) {
			udelay(10);
			if (retry_count--)
				goto again;

			err = -EIO;
			dev_err(pd->dev, "Polling timed out\n");
			break;
		}

		/* handle missing acknowledge and arbitration lost */
		if ((val | pd->sr) & (ICSR_TACK | ICSR_AL)) {
			err = -EIO;
			break;
		}
	}

	deactivate_ch(pd);

	if (!err)
		err = num;
	return err;
}

static u32 sh_mobile_i2c_func(struct i2c_adapter *adapter)
{
	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
}

static struct i2c_algorithm sh_mobile_i2c_algorithm = {
	.functionality	= sh_mobile_i2c_func,
	.master_xfer	= sh_mobile_i2c_xfer,
};

static int sh_mobile_i2c_hook_irqs(struct platform_device *dev, int hook)
{
	struct resource *res;
	int ret = -ENXIO;
	int q, m;
	int k = 0;
	int n = 0;

	while ((res = platform_get_resource(dev, IORESOURCE_IRQ, k))) {
		for (n = res->start; hook && n <= res->end; n++) {
			if (request_irq(n, sh_mobile_i2c_isr, IRQF_DISABLED,
					dev_name(&dev->dev), dev))
				goto rollback;
		}
		k++;
	}

	if (hook)
		return k > 0 ? 0 : -ENOENT;

	k--;
	ret = 0;

 rollback:
	for (q = k; k >= 0; k--) {
		for (m = n; m >= res->start; m--)
			free_irq(m, dev);

		res = platform_get_resource(dev, IORESOURCE_IRQ, k - 1);
		m = res->end;
	}

	return ret;
}

static int sh_mobile_i2c_probe(struct platform_device *dev)
{
	struct sh_mobile_i2c_data *pd;
	struct i2c_adapter *adap;
	struct resource *res;
	char clk_name[8];
	int size;
	int ret;

	pd = kzalloc(sizeof(struct sh_mobile_i2c_data), GFP_KERNEL);
	if (pd == NULL) {
		dev_err(&dev->dev, "cannot allocate private data\n");
		return -ENOMEM;
	}

	snprintf(clk_name, sizeof(clk_name), "i2c%d", dev->id);
	pd->clk = clk_get(&dev->dev, clk_name);
	if (IS_ERR(pd->clk)) {
		dev_err(&dev->dev, "cannot get clock \"%s\"\n", clk_name);
		ret = PTR_ERR(pd->clk);
		goto err;
	}

	ret = sh_mobile_i2c_hook_irqs(dev, 1);
	if (ret) {
		dev_err(&dev->dev, "cannot request IRQ\n");
		goto err_clk;
	}

	pd->dev = &dev->dev;
	platform_set_drvdata(dev, pd);

	res = platform_get_resource(dev, IORESOURCE_MEM, 0);
	if (res == NULL) {
		dev_err(&dev->dev, "cannot find IO resource\n");
		ret = -ENOENT;
		goto err_irq;
	}

	size = resource_size(res);

	pd->reg = ioremap(res->start, size);
	if (pd->reg == NULL) {
		dev_err(&dev->dev, "cannot map IO\n");
		ret = -ENXIO;
		goto err_irq;
	}

	/* Enable Runtime PM for this device.
	 *
	 * Also tell the Runtime PM core to ignore children
	 * for this device since it is valid for us to suspend
	 * this I2C master driver even though the slave devices
	 * on the I2C bus may not be suspended.
	 *
	 * The state of the I2C hardware bus is unaffected by
	 * the Runtime PM state.
	 */
	pm_suspend_ignore_children(&dev->dev, true);
	pm_runtime_enable(&dev->dev);

	/* setup the private data */
	adap = &pd->adap;
	i2c_set_adapdata(adap, pd);

	adap->owner = THIS_MODULE;
	adap->algo = &sh_mobile_i2c_algorithm;
	adap->dev.parent = &dev->dev;
	adap->retries = 5;
	adap->nr = dev->id;

	strlcpy(adap->name, dev->name, sizeof(adap->name));

	spin_lock_init(&pd->lock);
	init_waitqueue_head(&pd->wait);

	ret = i2c_add_numbered_adapter(adap);
	if (ret < 0) {
		dev_err(&dev->dev, "cannot add numbered adapter\n");
		goto err_all;
	}

	return 0;

 err_all:
	iounmap(pd->reg);
 err_irq:
	sh_mobile_i2c_hook_irqs(dev, 0);
 err_clk:
	clk_put(pd->clk);
 err:
	kfree(pd);
	return ret;
}

static int sh_mobile_i2c_remove(struct platform_device *dev)
{
	struct sh_mobile_i2c_data *pd = platform_get_drvdata(dev);

	i2c_del_adapter(&pd->adap);
	iounmap(pd->reg);
	sh_mobile_i2c_hook_irqs(dev, 0);
	clk_put(pd->clk);
	pm_runtime_disable(&dev->dev);
	kfree(pd);
	return 0;
}

static int sh_mobile_i2c_runtime_nop(struct device *dev)
{
	/* Runtime PM callback shared between ->runtime_suspend()
	 * and ->runtime_resume(). Simply returns success.
	 *
	 * This driver re-initializes all registers after
	 * pm_runtime_get_sync() anyway so there is no need
	 * to save and restore registers here.
	 */
	return 0;
}

static const struct dev_pm_ops sh_mobile_i2c_dev_pm_ops = {
	.runtime_suspend = sh_mobile_i2c_runtime_nop,
	.runtime_resume = sh_mobile_i2c_runtime_nop,
};

static struct platform_driver sh_mobile_i2c_driver = {
	.driver		= {
		.name		= "i2c-sh_mobile",
		.owner		= THIS_MODULE,
		.pm		= &sh_mobile_i2c_dev_pm_ops,
	},
	.probe		= sh_mobile_i2c_probe,
	.remove		= sh_mobile_i2c_remove,
};

static int __init sh_mobile_i2c_adap_init(void)
{
	return platform_driver_register(&sh_mobile_i2c_driver);
}

static void __exit sh_mobile_i2c_adap_exit(void)
{
	platform_driver_unregister(&sh_mobile_i2c_driver);
}

subsys_initcall(sh_mobile_i2c_adap_init);
module_exit(sh_mobile_i2c_adap_exit);

MODULE_DESCRIPTION("SuperH Mobile I2C Bus Controller driver");
MODULE_AUTHOR("Magnus Damm");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
da672773 MD	1	/*
	2	* SuperH Mobile I2C Controller
	3	*
	4	* Copyright (C) 2008 Magnus Damm
	5	*
	6	* Portions of the code based on out-of-tree driver i2c-sh7343.c
	7	* Copyright (c) 2006 Carlos Munoz <carlos@kenati.com>
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License as published by
	11	* the Free Software Foundation; either version 2 of the License
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	21	*/
	22
	23	#include <linux/kernel.h>
	24	#include <linux/module.h>
	25	#include <linux/init.h>
	26	#include <linux/delay.h>
	27	#include <linux/platform_device.h>
	28	#include <linux/interrupt.h>
	29	#include <linux/i2c.h>
	30	#include <linux/err.h>
f1a3b994	31	#include <linux/pm_runtime.h>
da672773 MD	32	#include <linux/clk.h>
da672773 MD	33	#include <linux/io.h>
5a0e3ad6	34	#include <linux/slab.h>
da672773	35
4eb00c9f MD	36	/* Transmit operation: */
	37	/* */
	38	/* 0 byte transmit */
	39	/* BUS: S A8 ACK P */
	40	/* IRQ: DTE WAIT */
	41	/* ICIC: */
	42	/* ICCR: 0x94 0x90 */
	43	/* ICDR: A8 */
	44	/* */
	45	/* 1 byte transmit */
	46	/* BUS: S A8 ACK D8(1) ACK P */
	47	/* IRQ: DTE WAIT WAIT */
	48	/* ICIC: -DTE */
	49	/* ICCR: 0x94 0x90 */
	50	/* ICDR: A8 D8(1) */
	51	/* */
	52	/* 2 byte transmit */
	53	/* BUS: S A8 ACK D8(1) ACK D8(2) ACK P */
	54	/* IRQ: DTE WAIT WAIT WAIT */
	55	/* ICIC: -DTE */
	56	/* ICCR: 0x94 0x90 */
	57	/* ICDR: A8 D8(1) D8(2) */
	58	/* */
	59	/* 3 bytes or more, +---------+ gets repeated */
	60	/* */
	61	/* */
	62	/* Receive operation: */
	63	/* */
	64	/* 0 byte receive - not supported since slave may hold SDA low */
	65	/* */
	66	/* 1 byte receive [TX] \| [RX] */
	67	/* BUS: S A8 ACK \| D8(1) ACK P */
	68	/* IRQ: DTE WAIT \| WAIT DTE */
	69	/* ICIC: -DTE \| +DTE */
	70	/* ICCR: 0x94 0x81 \| 0xc0 */
	71	/* ICDR: A8 \| D8(1) */
	72	/* */
	73	/* 2 byte receive [TX]\| [RX] */
	74	/* BUS: S A8 ACK \| D8(1) ACK D8(2) ACK P */
	75	/* IRQ: DTE WAIT \| WAIT WAIT DTE */
	76	/* ICIC: -DTE \| +DTE */
	77	/* ICCR: 0x94 0x81 \| 0xc0 */
	78	/* ICDR: A8 \| D8(1) D8(2) */
	79	/* */
	80	/* 3 byte receive [TX] \| [RX] */
	81	/* BUS: S A8 ACK \| D8(1) ACK D8(2) ACK D8(3) ACK P */
	82	/* IRQ: DTE WAIT \| WAIT WAIT WAIT DTE */
	83	/* ICIC: -DTE \| +DTE */
	84	/* ICCR: 0x94 0x81 \| 0xc0 */
	85	/* ICDR: A8 \| D8(1) D8(2) D8(3) */
	86	/* */
	87	/* 4 bytes or more, this part is repeated +---------+ */
	88	/* */
	89	/* */
	90	/* Interrupt order and BUSY flag */
	91	/* ___ _ */
	92	/* SDA ___\___XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXAAAAAAAAA___/ */
	93	/* SCL \_/1\_/2\_/3\_/4\_/5\_/6\_/7\_/8\___/9\_____/ */
	94	/* */
	95	/* S D7 D6 D5 D4 D3 D2 D1 D0 P */
	96	/* ___ */
	97	/* WAIT IRQ ________________________________/ \___________ */
	98	/* TACK IRQ ____________________________________/ \_______ */
	99	/* DTE IRQ __________________________________________/ \_ */
100	/* AL IRQ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX */
101	/* _______________________________________________ */
102	/* BUSY __/ \_ */
103	/* */
104
da672773 MD	105	enum sh_mobile_i2c_op {
da672773 MD	106	OP_START = 0,
4eb00c9f MD	107	OP_TX_FIRST,
4eb00c9f MD	108	OP_TX,
da672773 MD	109	OP_TX_STOP,
da672773 MD	110	OP_TX_TO_RX,
4eb00c9f	111	OP_RX,
da672773	112	OP_RX_STOP,
4eb00c9f	113	OP_RX_STOP_DATA,
da672773 MD	114	};
	115
	116	struct sh_mobile_i2c_data {
	117	struct device *dev;
	118	void __iomem *reg;
	119	struct i2c_adapter adap;
	120
	121	struct clk *clk;
	122	u_int8_t iccl;
	123	u_int8_t icch;
	124
	125	spinlock_t lock;
	126	wait_queue_head_t wait;
	127	struct i2c_msg *msg;
	128	int pos;
	129	int sr;
	130	};
	131
	132	#define NORMAL_SPEED 100000 /* FAST_SPEED 400000 */
	133
	134	/* Register offsets */
	135	#define ICDR(pd) (pd->reg + 0x00)
	136	#define ICCR(pd) (pd->reg + 0x04)
	137	#define ICSR(pd) (pd->reg + 0x08)
	138	#define ICIC(pd) (pd->reg + 0x0c)
	139	#define ICCL(pd) (pd->reg + 0x10)
	140	#define ICCH(pd) (pd->reg + 0x14)
	141
	142	/* Register bits */
	143	#define ICCR_ICE 0x80
	144	#define ICCR_RACK 0x40
	145	#define ICCR_TRS 0x10
	146	#define ICCR_BBSY 0x04
	147	#define ICCR_SCP 0x01
	148
	149	#define ICSR_SCLM 0x80
	150	#define ICSR_SDAM 0x40
	151	#define SW_DONE 0x20
	152	#define ICSR_BUSY 0x10
	153	#define ICSR_AL 0x08
	154	#define ICSR_TACK 0x04
	155	#define ICSR_WAIT 0x02
	156	#define ICSR_DTE 0x01
	157
	158	#define ICIC_ALE 0x08
	159	#define ICIC_TACKE 0x04
	160	#define ICIC_WAITE 0x02
	161	#define ICIC_DTEE 0x01
	162
	163	static void activate_ch(struct sh_mobile_i2c_data *pd)
	164	{
a5616bd0 MD	165	unsigned long i2c_clk;
	166	u_int32_t num;
	167	u_int32_t denom;
	168	u_int32_t tmp;
	169
f1a3b994 MD	170	/* Wake up device and enable clock */
f1a3b994 MD	171	pm_runtime_get_sync(pd->dev);
da672773 MD	172	clk_enable(pd->clk);
da672773 MD	173
a5616bd0 MD	174	/* Get clock rate after clock is enabled */
	175	i2c_clk = clk_get_rate(pd->clk);
	176
	177	/* Calculate the value for iccl. From the data sheet:
	178	* iccl = (p clock / transfer rate) * (L / (L + H))
	179	* where L and H are the SCL low/high ratio (5/4 in this case).
	180	* We also round off the result.
	181	*/
	182	num = i2c_clk * 5;
	183	denom = NORMAL_SPEED * 9;
	184	tmp = num * 10 / denom;
	185	if (tmp % 10 >= 5)
	186	pd->iccl = (u_int8_t)((num/denom) + 1);
	187	else
	188	pd->iccl = (u_int8_t)(num/denom);
	189
	190	/* Calculate the value for icch. From the data sheet:
	191	icch = (p clock / transfer rate) * (H / (L + H)) */
	192	num = i2c_clk * 4;
	193	tmp = num * 10 / denom;
	194	if (tmp % 10 >= 5)
	195	pd->icch = (u_int8_t)((num/denom) + 1);
	196	else
	197	pd->icch = (u_int8_t)(num/denom);
	198
da672773 MD	199	/* Enable channel and configure rx ack */
	200	iowrite8(ioread8(ICCR(pd)) \| ICCR_ICE, ICCR(pd));
	201
	202	/* Mask all interrupts */
	203	iowrite8(0, ICIC(pd));
	204
	205	/* Set the clock */
	206	iowrite8(pd->iccl, ICCL(pd));
	207	iowrite8(pd->icch, ICCH(pd));
	208	}
	209
	210	static void deactivate_ch(struct sh_mobile_i2c_data *pd)
	211	{
	212	/* Clear/disable interrupts */
	213	iowrite8(0, ICSR(pd));
	214	iowrite8(0, ICIC(pd));
	215
	216	/* Disable channel */
	217	iowrite8(ioread8(ICCR(pd)) & ~ICCR_ICE, ICCR(pd));
	218
f1a3b994	219	/* Disable clock and mark device as idle */
da672773	220	clk_disable(pd->clk);
f1a3b994	221	pm_runtime_put_sync(pd->dev);
da672773 MD	222	}
	223
	224	static unsigned char i2c_op(struct sh_mobile_i2c_data *pd,
	225	enum sh_mobile_i2c_op op, unsigned char data)
	226	{
	227	unsigned char ret = 0;
	228	unsigned long flags;
	229
	230	dev_dbg(pd->dev, "op %d, data in 0x%02x\n", op, data);
	231
	232	spin_lock_irqsave(&pd->lock, flags);
	233
	234	switch (op) {
4eb00c9f	235	case OP_START: /* issue start and trigger DTE interrupt */
da672773 MD	236	iowrite8(0x94, ICCR(pd));
da672773 MD	237	break;
4eb00c9f MD	238	case OP_TX_FIRST: /* disable DTE interrupt and write data */
4eb00c9f MD	239	iowrite8(ICIC_WAITE \| ICIC_ALE \| ICIC_TACKE, ICIC(pd));
da672773 MD	240	iowrite8(data, ICDR(pd));
da672773 MD	241	break;
4eb00c9f	242	case OP_TX: /* write data */
da672773	243	iowrite8(data, ICDR(pd));
da672773	244	break;
4eb00c9f	245	case OP_TX_STOP: /* write data and issue a stop afterwards */
da672773	246	iowrite8(data, ICDR(pd));
4eb00c9f MD	247	iowrite8(0x90, ICCR(pd));
	248	break;
	249	case OP_TX_TO_RX: /* select read mode */
da672773 MD	250	iowrite8(0x81, ICCR(pd));
da672773 MD	251	break;
4eb00c9f	252	case OP_RX: /* just read data */
da672773 MD	253	ret = ioread8(ICDR(pd));
da672773 MD	254	break;
4eb00c9f MD	255	case OP_RX_STOP: /* enable DTE interrupt, issue stop */
	256	iowrite8(ICIC_DTEE \| ICIC_WAITE \| ICIC_ALE \| ICIC_TACKE,
	257	ICIC(pd));
	258	iowrite8(0xc0, ICCR(pd));
	259	break;
	260	case OP_RX_STOP_DATA: /* enable DTE interrupt, read data, issue stop */
	261	iowrite8(ICIC_DTEE \| ICIC_WAITE \| ICIC_ALE \| ICIC_TACKE,
	262	ICIC(pd));
da672773 MD	263	ret = ioread8(ICDR(pd));
	264	iowrite8(0xc0, ICCR(pd));
	265	break;
	266	}
	267
	268	spin_unlock_irqrestore(&pd->lock, flags);
	269
	270	dev_dbg(pd->dev, "op %d, data out 0x%02x\n", op, ret);
	271	return ret;
	272	}
	273
4eb00c9f MD	274	static int sh_mobile_i2c_is_first_byte(struct sh_mobile_i2c_data *pd)
	275	{
	276	if (pd->pos == -1)
	277	return 1;
	278
	279	return 0;
	280	}
	281
	282	static int sh_mobile_i2c_is_last_byte(struct sh_mobile_i2c_data *pd)
	283	{
	284	if (pd->pos == (pd->msg->len - 1))
	285	return 1;
	286
	287	return 0;
	288	}
	289
	290	static void sh_mobile_i2c_get_data(struct sh_mobile_i2c_data *pd,
	291	unsigned char *buf)
	292	{
	293	switch (pd->pos) {
	294	case -1:
	295	*buf = (pd->msg->addr & 0x7f) << 1;
	296	*buf \|= (pd->msg->flags & I2C_M_RD) ? 1 : 0;
	297	break;
	298	default:
	299	*buf = pd->msg->buf[pd->pos];
	300	}
	301	}
	302
	303	static int sh_mobile_i2c_isr_tx(struct sh_mobile_i2c_data *pd)
	304	{
	305	unsigned char data;
	306
	307	if (pd->pos == pd->msg->len)
	308	return 1;
	309
	310	sh_mobile_i2c_get_data(pd, &data);
	311
	312	if (sh_mobile_i2c_is_last_byte(pd))
	313	i2c_op(pd, OP_TX_STOP, data);
	314	else if (sh_mobile_i2c_is_first_byte(pd))
	315	i2c_op(pd, OP_TX_FIRST, data);
	316	else
	317	i2c_op(pd, OP_TX, data);
	318
	319	pd->pos++;
	320	return 0;
	321	}
	322
	323	static int sh_mobile_i2c_isr_rx(struct sh_mobile_i2c_data *pd)
	324	{
	325	unsigned char data;
	326	int real_pos;
	327
	328	do {
	329	if (pd->pos <= -1) {
	330	sh_mobile_i2c_get_data(pd, &data);
	331
	332	if (sh_mobile_i2c_is_first_byte(pd))
	333	i2c_op(pd, OP_TX_FIRST, data);
	334	else
	335	i2c_op(pd, OP_TX, data);
	336	break;
	337	}
338
339	if (pd->pos == 0) {
340	i2c_op(pd, OP_TX_TO_RX, 0);
341	break;
342	}
343
344	real_pos = pd->pos - 2;
345
346	if (pd->pos == pd->msg->len) {
347	if (real_pos < 0) {
348	i2c_op(pd, OP_RX_STOP, 0);
349	break;
350	}
351	data = i2c_op(pd, OP_RX_STOP_DATA, 0);
352	} else
353	data = i2c_op(pd, OP_RX, 0);
354
bff4056c MD	355	if (real_pos >= 0)
bff4056c MD	356	pd->msg->buf[real_pos] = data;
4eb00c9f MD	357	} while (0);
	358
	359	pd->pos++;
	360	return pd->pos == (pd->msg->len + 2);
	361	}
	362
da672773 MD	363	static irqreturn_t sh_mobile_i2c_isr(int irq, void *dev_id)
	364	{
	365	struct platform_device *dev = dev_id;
	366	struct sh_mobile_i2c_data *pd = platform_get_drvdata(dev);
4eb00c9f MD	367	unsigned char sr;
4eb00c9f MD	368	int wakeup;
da672773 MD	369
da672773 MD	370	sr = ioread8(ICSR(pd));
4eb00c9f	371	pd->sr \|= sr; /* remember state */
da672773 MD	372
da672773 MD	373	dev_dbg(pd->dev, "i2c_isr 0x%02x 0x%02x %s %d %d!\n", sr, pd->sr,
4eb00c9f MD	374	(pd->msg->flags & I2C_M_RD) ? "read" : "write",
4eb00c9f MD	375	pd->pos, pd->msg->len);
da672773 MD	376
da672773 MD	377	if (sr & (ICSR_AL \| ICSR_TACK)) {
4eb00c9f MD	378	/* don't interrupt transaction - continue to issue stop */
	379	iowrite8(sr & ~(ICSR_AL \| ICSR_TACK), ICSR(pd));
	380	wakeup = 0;
	381	} else if (pd->msg->flags & I2C_M_RD)
	382	wakeup = sh_mobile_i2c_isr_rx(pd);
	383	else
	384	wakeup = sh_mobile_i2c_isr_tx(pd);
da672773	385
4eb00c9f MD	386	if (sr & ICSR_WAIT) /* TODO: add delay here to support slow acks */
4eb00c9f MD	387	iowrite8(sr & ~ICSR_WAIT, ICSR(pd));
da672773	388
da672773 MD	389	if (wakeup) {
	390	pd->sr \|= SW_DONE;
	391	wake_up(&pd->wait);
	392	}
	393
	394	return IRQ_HANDLED;
	395	}
	396
	397	static int start_ch(struct sh_mobile_i2c_data pd, struct i2c_msg usr_msg)
	398	{
4eb00c9f MD	399	if (usr_msg->len == 0 && (usr_msg->flags & I2C_M_RD)) {
	400	dev_err(pd->dev, "Unsupported zero length i2c read\n");
	401	return -EIO;
	402	}
	403
da672773 MD	404	/* Initialize channel registers */
	405	iowrite8(ioread8(ICCR(pd)) & ~ICCR_ICE, ICCR(pd));
	406
	407	/* Enable channel and configure rx ack */
	408	iowrite8(ioread8(ICCR(pd)) \| ICCR_ICE, ICCR(pd));
	409
	410	/* Set the clock */
	411	iowrite8(pd->iccl, ICCL(pd));
	412	iowrite8(pd->icch, ICCH(pd));
	413
	414	pd->msg = usr_msg;
	415	pd->pos = -1;
	416	pd->sr = 0;
	417
4eb00c9f MD	418	/* Enable all interrupts to begin with */
4eb00c9f MD	419	iowrite8(ICIC_WAITE \| ICIC_ALE \| ICIC_TACKE \| ICIC_DTEE, ICIC(pd));
da672773 MD	420	return 0;
	421	}
	422
	423	static int sh_mobile_i2c_xfer(struct i2c_adapter *adapter,
	424	struct i2c_msg *msgs,
	425	int num)
	426	{
	427	struct sh_mobile_i2c_data *pd = i2c_get_adapdata(adapter);
	428	struct i2c_msg *msg;
	429	int err = 0;
	430	u_int8_t val;
	431	int i, k, retry_count;
	432
	433	activate_ch(pd);
	434
	435	/* Process all messages */
	436	for (i = 0; i < num; i++) {
	437	msg = &msgs[i];
	438
	439	err = start_ch(pd, msg);
	440	if (err)
	441	break;
	442
	443	i2c_op(pd, OP_START, 0);
	444
	445	/* The interrupt handler takes care of the rest... */
	446	k = wait_event_timeout(pd->wait,
	447	pd->sr & (ICSR_TACK \| SW_DONE),
	448	5 * HZ);
	449	if (!k)
	450	dev_err(pd->dev, "Transfer request timed out\n");
	451
4eb00c9f	452	retry_count = 1000;
da672773 MD	453	again:
	454	val = ioread8(ICSR(pd));
	455
	456	dev_dbg(pd->dev, "val 0x%02x pd->sr 0x%02x\n", val, pd->sr);
	457
da672773 MD	458	/* the interrupt handler may wake us up before the
	459	* transfer is finished, so poll the hardware
	460	* until we're done.
	461	*/
4eb00c9f MD	462	if (val & ICSR_BUSY) {
4eb00c9f MD	463	udelay(10);
da672773 MD	464	if (retry_count--)
	465	goto again;
	466
	467	err = -EIO;
	468	dev_err(pd->dev, "Polling timed out\n");
	469	break;
	470	}
4eb00c9f MD	471
	472	/* handle missing acknowledge and arbitration lost */
	473	if ((val \| pd->sr) & (ICSR_TACK \| ICSR_AL)) {
	474	err = -EIO;
	475	break;
	476	}
da672773 MD	477	}
	478
	479	deactivate_ch(pd);
	480
	481	if (!err)
	482	err = num;
	483	return err;
	484	}
	485
	486	static u32 sh_mobile_i2c_func(struct i2c_adapter *adapter)
	487	{
	488	return I2C_FUNC_I2C \| I2C_FUNC_SMBUS_EMUL;
	489	}
	490
	491	static struct i2c_algorithm sh_mobile_i2c_algorithm = {
	492	.functionality = sh_mobile_i2c_func,
	493	.master_xfer = sh_mobile_i2c_xfer,
	494	};
	495
da672773 MD	496	static int sh_mobile_i2c_hook_irqs(struct platform_device *dev, int hook)
	497	{
	498	struct resource *res;
	499	int ret = -ENXIO;
	500	int q, m;
	501	int k = 0;
	502	int n = 0;
	503
	504	while ((res = platform_get_resource(dev, IORESOURCE_IRQ, k))) {
	505	for (n = res->start; hook && n <= res->end; n++) {
	506	if (request_irq(n, sh_mobile_i2c_isr, IRQF_DISABLED,
22e965c2	507	dev_name(&dev->dev), dev))
da672773 MD	508	goto rollback;
	509	}
	510	k++;
	511	}
	512
	513	if (hook)
	514	return k > 0 ? 0 : -ENOENT;
	515
	516	k--;
	517	ret = 0;
	518
	519	rollback:
	520	for (q = k; k >= 0; k--) {
	521	for (m = n; m >= res->start; m--)
	522	free_irq(m, dev);
	523
	524	res = platform_get_resource(dev, IORESOURCE_IRQ, k - 1);
	525	m = res->end;
	526	}
	527
	528	return ret;
	529	}
	530
	531	static int sh_mobile_i2c_probe(struct platform_device *dev)
	532	{
	533	struct sh_mobile_i2c_data *pd;
	534	struct i2c_adapter *adap;
	535	struct resource *res;
a5616bd0	536	char clk_name[8];
da672773 MD	537	int size;
	538	int ret;
	539
	540	pd = kzalloc(sizeof(struct sh_mobile_i2c_data), GFP_KERNEL);
	541	if (pd == NULL) {
	542	dev_err(&dev->dev, "cannot allocate private data\n");
	543	return -ENOMEM;
	544	}
	545
a5616bd0 MD	546	snprintf(clk_name, sizeof(clk_name), "i2c%d", dev->id);
a5616bd0 MD	547	pd->clk = clk_get(&dev->dev, clk_name);
da672773	548	if (IS_ERR(pd->clk)) {
a5616bd0	549	dev_err(&dev->dev, "cannot get clock \"%s\"\n", clk_name);
da672773 MD	550	ret = PTR_ERR(pd->clk);
	551	goto err;
	552	}
	553
	554	ret = sh_mobile_i2c_hook_irqs(dev, 1);
	555	if (ret) {
	556	dev_err(&dev->dev, "cannot request IRQ\n");
	557	goto err_clk;
	558	}
	559
	560	pd->dev = &dev->dev;
	561	platform_set_drvdata(dev, pd);
	562
	563	res = platform_get_resource(dev, IORESOURCE_MEM, 0);
	564	if (res == NULL) {
	565	dev_err(&dev->dev, "cannot find IO resource\n");
	566	ret = -ENOENT;
	567	goto err_irq;
	568	}
	569
59330825	570	size = resource_size(res);
da672773 MD	571
	572	pd->reg = ioremap(res->start, size);
	573	if (pd->reg == NULL) {
	574	dev_err(&dev->dev, "cannot map IO\n");
	575	ret = -ENXIO;
	576	goto err_irq;
	577	}
	578
f1a3b994 MD	579	/* Enable Runtime PM for this device.
	580	*
	581	* Also tell the Runtime PM core to ignore children
	582	* for this device since it is valid for us to suspend
	583	* this I2C master driver even though the slave devices
	584	* on the I2C bus may not be suspended.
	585	*
	586	* The state of the I2C hardware bus is unaffected by
	587	* the Runtime PM state.
	588	*/
	589	pm_suspend_ignore_children(&dev->dev, true);
	590	pm_runtime_enable(&dev->dev);
	591
da672773 MD	592	/* setup the private data */
	593	adap = &pd->adap;
	594	i2c_set_adapdata(adap, pd);
	595
	596	adap->owner = THIS_MODULE;
	597	adap->algo = &sh_mobile_i2c_algorithm;
	598	adap->dev.parent = &dev->dev;
	599	adap->retries = 5;
	600	adap->nr = dev->id;
	601
	602	strlcpy(adap->name, dev->name, sizeof(adap->name));
	603
a5616bd0 MD	604	spin_lock_init(&pd->lock);
a5616bd0 MD	605	init_waitqueue_head(&pd->wait);
da672773 MD	606
	607	ret = i2c_add_numbered_adapter(adap);
	608	if (ret < 0) {
	609	dev_err(&dev->dev, "cannot add numbered adapter\n");
	610	goto err_all;
	611	}
	612
	613	return 0;
	614
	615	err_all:
	616	iounmap(pd->reg);
	617	err_irq:
	618	sh_mobile_i2c_hook_irqs(dev, 0);
	619	err_clk:
	620	clk_put(pd->clk);
	621	err:
	622	kfree(pd);
	623	return ret;
	624	}
	625
	626	static int sh_mobile_i2c_remove(struct platform_device *dev)
	627	{
	628	struct sh_mobile_i2c_data *pd = platform_get_drvdata(dev);
	629
	630	i2c_del_adapter(&pd->adap);
	631	iounmap(pd->reg);
	632	sh_mobile_i2c_hook_irqs(dev, 0);
	633	clk_put(pd->clk);
f1a3b994	634	pm_runtime_disable(&dev->dev);
da672773 MD	635	kfree(pd);
	636	return 0;
	637	}
	638
f1a3b994 MD	639	static int sh_mobile_i2c_runtime_nop(struct device *dev)
	640	{
	641	/* Runtime PM callback shared between ->runtime_suspend()
	642	* and ->runtime_resume(). Simply returns success.
	643	*
	644	* This driver re-initializes all registers after
	645	* pm_runtime_get_sync() anyway so there is no need
	646	* to save and restore registers here.
	647	*/
	648	return 0;
	649	}
	650
47145210	651	static const struct dev_pm_ops sh_mobile_i2c_dev_pm_ops = {
f1a3b994 MD	652	.runtime_suspend = sh_mobile_i2c_runtime_nop,
	653	.runtime_resume = sh_mobile_i2c_runtime_nop,
	654	};
	655
da672773 MD	656	static struct platform_driver sh_mobile_i2c_driver = {
	657	.driver = {
	658	.name = "i2c-sh_mobile",
	659	.owner = THIS_MODULE,
f1a3b994	660	.pm = &sh_mobile_i2c_dev_pm_ops,
da672773 MD	661	},
	662	.probe = sh_mobile_i2c_probe,
	663	.remove = sh_mobile_i2c_remove,
	664	};
	665
	666	static int __init sh_mobile_i2c_adap_init(void)
	667	{
	668	return platform_driver_register(&sh_mobile_i2c_driver);
	669	}
	670
	671	static void __exit sh_mobile_i2c_adap_exit(void)
	672	{
	673	platform_driver_unregister(&sh_mobile_i2c_driver);
	674	}
	675
ccb3bc16	676	subsys_initcall(sh_mobile_i2c_adap_init);
da672773 MD	677	module_exit(sh_mobile_i2c_adap_exit);
	678
	679	MODULE_DESCRIPTION("SuperH Mobile I2C Bus Controller driver");
	680	MODULE_AUTHOR("Magnus Damm");
	681	MODULE_LICENSE("GPL v2");