[net-next-2.6.git] / drivers / i2c / busses / i2c-mpc.c

/*
 * (C) Copyright 2003-2004
 * Humboldt Solutions Ltd, adrian@humboldt.co.uk.

 * This is a combined i2c adapter and algorithm driver for the
 * MPC107/Tsi107 PowerPC northbridge and processors that include
 * the same I2C unit (8240, 8245, 85xx).
 *
 * Release 0.8
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2. This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/sched.h>
#include <linux/init.h>
#include <linux/platform_device.h>

#include <asm/io.h>
#include <linux/fsl_devices.h>
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/delay.h>

#define MPC_I2C_ADDR  0x00
#define MPC_I2C_FDR 	0x04
#define MPC_I2C_CR	0x08
#define MPC_I2C_SR	0x0c
#define MPC_I2C_DR	0x10
#define MPC_I2C_DFSRR 0x14
#define MPC_I2C_REGION 0x20

#define CCR_MEN  0x80
#define CCR_MIEN 0x40
#define CCR_MSTA 0x20
#define CCR_MTX  0x10
#define CCR_TXAK 0x08
#define CCR_RSTA 0x04

#define CSR_MCF  0x80
#define CSR_MAAS 0x40
#define CSR_MBB  0x20
#define CSR_MAL  0x10
#define CSR_SRW  0x04
#define CSR_MIF  0x02
#define CSR_RXAK 0x01

struct mpc_i2c {
	void __iomem *base;
	u32 interrupt;
	wait_queue_head_t queue;
	struct i2c_adapter adap;
	int irq;
	u32 flags;
};

static __inline__ void writeccr(struct mpc_i2c *i2c, u32 x)
{
	writeb(x, i2c->base + MPC_I2C_CR);
}

static irqreturn_t mpc_i2c_isr(int irq, void *dev_id)
{
	struct mpc_i2c *i2c = dev_id;
	if (readb(i2c->base + MPC_I2C_SR) & CSR_MIF) {
		/* Read again to allow register to stabilise */
		i2c->interrupt = readb(i2c->base + MPC_I2C_SR);
		writeb(0, i2c->base + MPC_I2C_SR);
		wake_up_interruptible(&i2c->queue);
	}
	return IRQ_HANDLED;
}

/* Sometimes 9th clock pulse isn't generated, and slave doesn't release
 * the bus, because it wants to send ACK.
 * Following sequence of enabling/disabling and sending start/stop generates
 * the pulse, so it's all OK.
 */
static void mpc_i2c_fixup(struct mpc_i2c *i2c)
{
	writeccr(i2c, 0);
	udelay(30);
	writeccr(i2c, CCR_MEN);
	udelay(30);
	writeccr(i2c, CCR_MSTA | CCR_MTX);
	udelay(30);
	writeccr(i2c, CCR_MSTA | CCR_MTX | CCR_MEN);
	udelay(30);
	writeccr(i2c, CCR_MEN);
	udelay(30);
}

static int i2c_wait(struct mpc_i2c *i2c, unsigned timeout, int writing)
{
	unsigned long orig_jiffies = jiffies;
	u32 x;
	int result = 0;

	if (i2c->irq == 0)
	{
		while (!(readb(i2c->base + MPC_I2C_SR) & CSR_MIF)) {
			schedule();
			if (time_after(jiffies, orig_jiffies + timeout)) {
				pr_debug("I2C: timeout\n");
				writeccr(i2c, 0);
				result = -EIO;
				break;
			}
		}
		x = readb(i2c->base + MPC_I2C_SR);
		writeb(0, i2c->base + MPC_I2C_SR);
	} else {
		/* Interrupt mode */
		result = wait_event_interruptible_timeout(i2c->queue,
			(i2c->interrupt & CSR_MIF), timeout * HZ);

		if (unlikely(result < 0)) {
			pr_debug("I2C: wait interrupted\n");
			writeccr(i2c, 0);
		} else if (unlikely(!(i2c->interrupt & CSR_MIF))) {
			pr_debug("I2C: wait timeout\n");
			writeccr(i2c, 0);
			result = -ETIMEDOUT;
		}

		x = i2c->interrupt;
		i2c->interrupt = 0;
	}

	if (result < 0)
		return result;

	if (!(x & CSR_MCF)) {
		pr_debug("I2C: unfinished\n");
		return -EIO;
	}

	if (x & CSR_MAL) {
		pr_debug("I2C: MAL\n");
		return -EIO;
	}

	if (writing && (x & CSR_RXAK)) {
		pr_debug("I2C: No RXAK\n");
		/* generate stop */
		writeccr(i2c, CCR_MEN);
		return -EIO;
	}
	return 0;
}

static void mpc_i2c_setclock(struct mpc_i2c *i2c)
{
	/* Set clock and filters */
	if (i2c->flags & FSL_I2C_DEV_SEPARATE_DFSRR) {
		writeb(0x31, i2c->base + MPC_I2C_FDR);
		writeb(0x10, i2c->base + MPC_I2C_DFSRR);
	} else if (i2c->flags & FSL_I2C_DEV_CLOCK_5200)
		writeb(0x3f, i2c->base + MPC_I2C_FDR);
	else
		writel(0x1031, i2c->base + MPC_I2C_FDR);
}

static void mpc_i2c_start(struct mpc_i2c *i2c)
{
	/* Clear arbitration */
	writeb(0, i2c->base + MPC_I2C_SR);
	/* Start with MEN */
	writeccr(i2c, CCR_MEN);
}

static void mpc_i2c_stop(struct mpc_i2c *i2c)
{
	writeccr(i2c, CCR_MEN);
}

static int mpc_write(struct mpc_i2c *i2c, int target,
		     const u8 * data, int length, int restart)
{
	int i;
	unsigned timeout = i2c->adap.timeout;
	u32 flags = restart ? CCR_RSTA : 0;

	/* Start with MEN */
	if (!restart)
		writeccr(i2c, CCR_MEN);
	/* Start as master */
	writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX | flags);
	/* Write target byte */
	writeb((target << 1), i2c->base + MPC_I2C_DR);

	if (i2c_wait(i2c, timeout, 1) < 0)
		return -1;

	for (i = 0; i < length; i++) {
		/* Write data byte */
		writeb(data[i], i2c->base + MPC_I2C_DR);

		if (i2c_wait(i2c, timeout, 1) < 0)
			return -1;
	}

	return 0;
}

static int mpc_read(struct mpc_i2c *i2c, int target,
		    u8 * data, int length, int restart)
{
	unsigned timeout = i2c->adap.timeout;
	int i;
	u32 flags = restart ? CCR_RSTA : 0;

	/* Start with MEN */
	if (!restart)
		writeccr(i2c, CCR_MEN);
	/* Switch to read - restart */
	writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX | flags);
	/* Write target address byte - this time with the read flag set */
	writeb((target << 1) | 1, i2c->base + MPC_I2C_DR);

	if (i2c_wait(i2c, timeout, 1) < 0)
		return -1;

	if (length) {
		if (length == 1)
			writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_TXAK);
		else
			writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA);
		/* Dummy read */
		readb(i2c->base + MPC_I2C_DR);
	}

	for (i = 0; i < length; i++) {
		if (i2c_wait(i2c, timeout, 0) < 0)
			return -1;

		/* Generate txack on next to last byte */
		if (i == length - 2)
			writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_TXAK);
		/* Generate stop on last byte */
		if (i == length - 1)
			writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_TXAK);
		data[i] = readb(i2c->base + MPC_I2C_DR);
	}

	return length;
}

static int mpc_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
{
	struct i2c_msg *pmsg;
	int i;
	int ret = 0;
	unsigned long orig_jiffies = jiffies;
	struct mpc_i2c *i2c = i2c_get_adapdata(adap);

	mpc_i2c_start(i2c);

	/* Allow bus up to 1s to become not busy */
	while (readb(i2c->base + MPC_I2C_SR) & CSR_MBB) {
		if (signal_pending(current)) {
			pr_debug("I2C: Interrupted\n");
			writeccr(i2c, 0);
			return -EINTR;
		}
		if (time_after(jiffies, orig_jiffies + HZ)) {
			pr_debug("I2C: timeout\n");
			if (readb(i2c->base + MPC_I2C_SR) ==
			    (CSR_MCF | CSR_MBB | CSR_RXAK))
				mpc_i2c_fixup(i2c);
			return -EIO;
		}
		schedule();
	}

	for (i = 0; ret >= 0 && i < num; i++) {
		pmsg = &msgs[i];
		pr_debug("Doing %s %d bytes to 0x%02x - %d of %d messages\n",
			 pmsg->flags & I2C_M_RD ? "read" : "write",
			 pmsg->len, pmsg->addr, i + 1, num);
		if (pmsg->flags & I2C_M_RD)
			ret =
			    mpc_read(i2c, pmsg->addr, pmsg->buf, pmsg->len, i);
		else
			ret =
			    mpc_write(i2c, pmsg->addr, pmsg->buf, pmsg->len, i);
	}
	mpc_i2c_stop(i2c);
	return (ret < 0) ? ret : num;
}

static u32 mpc_functionality(struct i2c_adapter *adap)
{
	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
}

static const struct i2c_algorithm mpc_algo = {
	.master_xfer = mpc_xfer,
	.functionality = mpc_functionality,
};

static struct i2c_adapter mpc_ops = {
	.owner = THIS_MODULE,
	.name = "MPC adapter",
	.id = I2C_HW_MPC107,
	.algo = &mpc_algo,
	.class = I2C_CLASS_HWMON,
	.timeout = 1,
};

static int fsl_i2c_probe(struct platform_device *pdev)
{
	int result = 0;
	struct mpc_i2c *i2c;
	struct fsl_i2c_platform_data *pdata;
	struct resource *r = platform_get_resource(pdev, IORESOURCE_MEM, 0);

	pdata = (struct fsl_i2c_platform_data *) pdev->dev.platform_data;

	if (!(i2c = kzalloc(sizeof(*i2c), GFP_KERNEL))) {
		return -ENOMEM;
	}

	i2c->irq = platform_get_irq(pdev, 0);
	if (i2c->irq < 0) {
		result = -ENXIO;
		goto fail_get_irq;
	}
	i2c->flags = pdata->device_flags;
	init_waitqueue_head(&i2c->queue);

	i2c->base = ioremap((phys_addr_t)r->start, MPC_I2C_REGION);

	if (!i2c->base) {
		printk(KERN_ERR "i2c-mpc - failed to map controller\n");
		result = -ENOMEM;
		goto fail_map;
	}

	if (i2c->irq != 0)
		if ((result = request_irq(i2c->irq, mpc_i2c_isr,
					  IRQF_SHARED, "i2c-mpc", i2c)) < 0) {
			printk(KERN_ERR
			       "i2c-mpc - failed to attach interrupt\n");
			goto fail_irq;
		}

	mpc_i2c_setclock(i2c);
	platform_set_drvdata(pdev, i2c);

	i2c->adap = mpc_ops;
	i2c->adap.nr = pdev->id;
	i2c_set_adapdata(&i2c->adap, i2c);
	i2c->adap.dev.parent = &pdev->dev;
	if ((result = i2c_add_numbered_adapter(&i2c->adap)) < 0) {
		printk(KERN_ERR "i2c-mpc - failed to add adapter\n");
		goto fail_add;
	}

	return result;

      fail_add:
	if (i2c->irq != 0)
		free_irq(i2c->irq, i2c);
      fail_irq:
	iounmap(i2c->base);
      fail_map:
      fail_get_irq:
	kfree(i2c);
	return result;
};

static int fsl_i2c_remove(struct platform_device *pdev)
{
	struct mpc_i2c *i2c = platform_get_drvdata(pdev);

	i2c_del_adapter(&i2c->adap);
	platform_set_drvdata(pdev, NULL);

	if (i2c->irq != 0)
		free_irq(i2c->irq, i2c);

	iounmap(i2c->base);
	kfree(i2c);
	return 0;
};

/* Structure for a device driver */
static struct platform_driver fsl_i2c_driver = {
	.probe = fsl_i2c_probe,
	.remove = fsl_i2c_remove,
	.driver	= {
		.owner = THIS_MODULE,
		.name = "fsl-i2c",
	},
};

static int __init fsl_i2c_init(void)
{
	return platform_driver_register(&fsl_i2c_driver);
}

static void __exit fsl_i2c_exit(void)
{
	platform_driver_unregister(&fsl_i2c_driver);
}

module_init(fsl_i2c_init);
module_exit(fsl_i2c_exit);

MODULE_AUTHOR("Adrian Cox <adrian@humboldt.co.uk>");
MODULE_DESCRIPTION
    ("I2C-Bus adapter for MPC107 bridge and MPC824x/85xx/52xx processors");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4 LT	1	/*
	2	* (C) Copyright 2003-2004
	3	* Humboldt Solutions Ltd, adrian@humboldt.co.uk.
	4
	5	* This is a combined i2c adapter and algorithm driver for the
	6	* MPC107/Tsi107 PowerPC northbridge and processors that include
	7	* the same I2C unit (8240, 8245, 85xx).
	8	*
	9	* Release 0.8
	10	*
	11	* This file is licensed under the terms of the GNU General Public
	12	* License version 2. This program is licensed "as is" without any
	13	* warranty of any kind, whether express or implied.
	14	*/
	15
1da177e4 LT	16	#include <linux/kernel.h>
	17	#include <linux/module.h>
	18	#include <linux/sched.h>
	19	#include <linux/init.h>
d052d1be RK	20	#include <linux/platform_device.h>
d052d1be RK	21
1da177e4	22	#include <asm/io.h>
1da177e4	23	#include <linux/fsl_devices.h>
1da177e4 LT	24	#include <linux/i2c.h>
	25	#include <linux/interrupt.h>
	26	#include <linux/delay.h>
	27
	28	#define MPC_I2C_ADDR 0x00
	29	#define MPC_I2C_FDR 0x04
	30	#define MPC_I2C_CR 0x08
	31	#define MPC_I2C_SR 0x0c
	32	#define MPC_I2C_DR 0x10
	33	#define MPC_I2C_DFSRR 0x14
	34	#define MPC_I2C_REGION 0x20
	35
	36	#define CCR_MEN 0x80
	37	#define CCR_MIEN 0x40
	38	#define CCR_MSTA 0x20
	39	#define CCR_MTX 0x10
	40	#define CCR_TXAK 0x08
	41	#define CCR_RSTA 0x04
	42
	43	#define CSR_MCF 0x80
	44	#define CSR_MAAS 0x40
	45	#define CSR_MBB 0x20
	46	#define CSR_MAL 0x10
	47	#define CSR_SRW 0x04
	48	#define CSR_MIF 0x02
	49	#define CSR_RXAK 0x01
	50
	51	struct mpc_i2c {
7366d36c	52	void __iomem *base;
1da177e4 LT	53	u32 interrupt;
	54	wait_queue_head_t queue;
	55	struct i2c_adapter adap;
	56	int irq;
	57	u32 flags;
	58	};
	59
	60	static __inline__ void writeccr(struct mpc_i2c *i2c, u32 x)
	61	{
	62	writeb(x, i2c->base + MPC_I2C_CR);
	63	}
	64
7d12e780	65	static irqreturn_t mpc_i2c_isr(int irq, void *dev_id)
1da177e4 LT	66	{
	67	struct mpc_i2c *i2c = dev_id;
	68	if (readb(i2c->base + MPC_I2C_SR) & CSR_MIF) {
	69	/* Read again to allow register to stabilise */
	70	i2c->interrupt = readb(i2c->base + MPC_I2C_SR);
	71	writeb(0, i2c->base + MPC_I2C_SR);
	72	wake_up_interruptible(&i2c->queue);
	73	}
	74	return IRQ_HANDLED;
	75	}
	76
254db9b5 DP	77	/* Sometimes 9th clock pulse isn't generated, and slave doesn't release
	78	* the bus, because it wants to send ACK.
	79	* Following sequence of enabling/disabling and sending start/stop generates
	80	* the pulse, so it's all OK.
	81	*/
	82	static void mpc_i2c_fixup(struct mpc_i2c *i2c)
	83	{
	84	writeccr(i2c, 0);
	85	udelay(30);
	86	writeccr(i2c, CCR_MEN);
	87	udelay(30);
	88	writeccr(i2c, CCR_MSTA \| CCR_MTX);
	89	udelay(30);
	90	writeccr(i2c, CCR_MSTA \| CCR_MTX \| CCR_MEN);
	91	udelay(30);
	92	writeccr(i2c, CCR_MEN);
	93	udelay(30);
	94	}
	95
1da177e4 LT	96	static int i2c_wait(struct mpc_i2c *i2c, unsigned timeout, int writing)
	97	{
	98	unsigned long orig_jiffies = jiffies;
	99	u32 x;
	100	int result = 0;
	101
	102	if (i2c->irq == 0)
	103	{
	104	while (!(readb(i2c->base + MPC_I2C_SR) & CSR_MIF)) {
	105	schedule();
	106	if (time_after(jiffies, orig_jiffies + timeout)) {
	107	pr_debug("I2C: timeout\n");
5af0e07f	108	writeccr(i2c, 0);
1da177e4 LT	109	result = -EIO;
	110	break;
	111	}
	112	}
	113	x = readb(i2c->base + MPC_I2C_SR);
	114	writeb(0, i2c->base + MPC_I2C_SR);
	115	} else {
	116	/* Interrupt mode */
	117	result = wait_event_interruptible_timeout(i2c->queue,
	118	(i2c->interrupt & CSR_MIF), timeout * HZ);
	119
5af0e07f	120	if (unlikely(result < 0)) {
1da177e4	121	pr_debug("I2C: wait interrupted\n");
5af0e07f DP	122	writeccr(i2c, 0);
5af0e07f DP	123	} else if (unlikely(!(i2c->interrupt & CSR_MIF))) {
1da177e4	124	pr_debug("I2C: wait timeout\n");
5af0e07f	125	writeccr(i2c, 0);
1da177e4 LT	126	result = -ETIMEDOUT;
	127	}
	128
	129	x = i2c->interrupt;
	130	i2c->interrupt = 0;
	131	}
	132
	133	if (result < 0)
	134	return result;
	135
	136	if (!(x & CSR_MCF)) {
	137	pr_debug("I2C: unfinished\n");
	138	return -EIO;
	139	}
	140
	141	if (x & CSR_MAL) {
	142	pr_debug("I2C: MAL\n");
	143	return -EIO;
	144	}
	145
	146	if (writing && (x & CSR_RXAK)) {
	147	pr_debug("I2C: No RXAK\n");
	148	/* generate stop */
	149	writeccr(i2c, CCR_MEN);
	150	return -EIO;
	151	}
	152	return 0;
	153	}
	154
	155	static void mpc_i2c_setclock(struct mpc_i2c *i2c)
	156	{
	157	/* Set clock and filters */
	158	if (i2c->flags & FSL_I2C_DEV_SEPARATE_DFSRR) {
	159	writeb(0x31, i2c->base + MPC_I2C_FDR);
	160	writeb(0x10, i2c->base + MPC_I2C_DFSRR);
	161	} else if (i2c->flags & FSL_I2C_DEV_CLOCK_5200)
	162	writeb(0x3f, i2c->base + MPC_I2C_FDR);
	163	else
	164	writel(0x1031, i2c->base + MPC_I2C_FDR);
	165	}
	166
	167	static void mpc_i2c_start(struct mpc_i2c *i2c)
	168	{
	169	/* Clear arbitration */
	170	writeb(0, i2c->base + MPC_I2C_SR);
	171	/* Start with MEN */
	172	writeccr(i2c, CCR_MEN);
	173	}
	174
	175	static void mpc_i2c_stop(struct mpc_i2c *i2c)
	176	{
	177	writeccr(i2c, CCR_MEN);
	178	}
	179
	180	static int mpc_write(struct mpc_i2c *i2c, int target,
	181	const u8 * data, int length, int restart)
	182	{
	183	int i;
	184	unsigned timeout = i2c->adap.timeout;
	185	u32 flags = restart ? CCR_RSTA : 0;
	186
	187	/* Start with MEN */
	188	if (!restart)
	189	writeccr(i2c, CCR_MEN);
190	/* Start as master */
191	writeccr(i2c, CCR_MIEN \| CCR_MEN \| CCR_MSTA \| CCR_MTX \| flags);
192	/* Write target byte */
193	writeb((target << 1), i2c->base + MPC_I2C_DR);
194
195	if (i2c_wait(i2c, timeout, 1) < 0)
196	return -1;
197
198	for (i = 0; i < length; i++) {
199	/* Write data byte */
200	writeb(data[i], i2c->base + MPC_I2C_DR);
201
202	if (i2c_wait(i2c, timeout, 1) < 0)
203	return -1;
204	}
205
206	return 0;
207	}
208
209	static int mpc_read(struct mpc_i2c *i2c, int target,
210	u8 * data, int length, int restart)
211	{
212	unsigned timeout = i2c->adap.timeout;
213	int i;
214	u32 flags = restart ? CCR_RSTA : 0;
215
216	/* Start with MEN */
217	if (!restart)
218	writeccr(i2c, CCR_MEN);
219	/* Switch to read - restart */
220	writeccr(i2c, CCR_MIEN \| CCR_MEN \| CCR_MSTA \| CCR_MTX \| flags);
221	/* Write target address byte - this time with the read flag set */
222	writeb((target << 1) \| 1, i2c->base + MPC_I2C_DR);
223
224	if (i2c_wait(i2c, timeout, 1) < 0)
225	return -1;
226
227	if (length) {
228	if (length == 1)
229	writeccr(i2c, CCR_MIEN \| CCR_MEN \| CCR_MSTA \| CCR_TXAK);
230	else
231	writeccr(i2c, CCR_MIEN \| CCR_MEN \| CCR_MSTA);
232	/* Dummy read */
233	readb(i2c->base + MPC_I2C_DR);
234	}
235
236	for (i = 0; i < length; i++) {
237	if (i2c_wait(i2c, timeout, 0) < 0)
238	return -1;
239
240	/* Generate txack on next to last byte */
241	if (i == length - 2)
242	writeccr(i2c, CCR_MIEN \| CCR_MEN \| CCR_MSTA \| CCR_TXAK);
243	/* Generate stop on last byte */
244	if (i == length - 1)
245	writeccr(i2c, CCR_MIEN \| CCR_MEN \| CCR_TXAK);
246	data[i] = readb(i2c->base + MPC_I2C_DR);
247	}
248
249	return length;
250	}
251
252	static int mpc_xfer(struct i2c_adapter adap, struct i2c_msg msgs, int num)
253	{
254	struct i2c_msg *pmsg;
255	int i;
256	int ret = 0;
257	unsigned long orig_jiffies = jiffies;
258	struct mpc_i2c *i2c = i2c_get_adapdata(adap);
259
260	mpc_i2c_start(i2c);
261
262	/* Allow bus up to 1s to become not busy */
263	while (readb(i2c->base + MPC_I2C_SR) & CSR_MBB) {
264	if (signal_pending(current)) {
265	pr_debug("I2C: Interrupted\n");
5af0e07f	266	writeccr(i2c, 0);
1da177e4 LT	267	return -EINTR;
	268	}
	269	if (time_after(jiffies, orig_jiffies + HZ)) {
	270	pr_debug("I2C: timeout\n");
254db9b5 DP	271	if (readb(i2c->base + MPC_I2C_SR) ==
	272	(CSR_MCF \| CSR_MBB \| CSR_RXAK))
	273	mpc_i2c_fixup(i2c);
1da177e4 LT	274	return -EIO;
	275	}
	276	schedule();
	277	}
	278
	279	for (i = 0; ret >= 0 && i < num; i++) {
	280	pmsg = &msgs[i];
	281	pr_debug("Doing %s %d bytes to 0x%02x - %d of %d messages\n",
	282	pmsg->flags & I2C_M_RD ? "read" : "write",
	283	pmsg->len, pmsg->addr, i + 1, num);
	284	if (pmsg->flags & I2C_M_RD)
	285	ret =
	286	mpc_read(i2c, pmsg->addr, pmsg->buf, pmsg->len, i);
	287	else
	288	ret =
	289	mpc_write(i2c, pmsg->addr, pmsg->buf, pmsg->len, i);
	290	}
	291	mpc_i2c_stop(i2c);
	292	return (ret < 0) ? ret : num;
	293	}
	294
	295	static u32 mpc_functionality(struct i2c_adapter *adap)
	296	{
	297	return I2C_FUNC_I2C \| I2C_FUNC_SMBUS_EMUL;
	298	}
	299
8f9082c5	300	static const struct i2c_algorithm mpc_algo = {
1da177e4 LT	301	.master_xfer = mpc_xfer,
	302	.functionality = mpc_functionality,
	303	};
	304
	305	static struct i2c_adapter mpc_ops = {
	306	.owner = THIS_MODULE,
	307	.name = "MPC adapter",
c7a46533	308	.id = I2C_HW_MPC107,
1da177e4 LT	309	.algo = &mpc_algo,
	310	.class = I2C_CLASS_HWMON,
	311	.timeout = 1,
1da177e4 LT	312	};
1da177e4 LT	313
3ae5eaec	314	static int fsl_i2c_probe(struct platform_device *pdev)
8c86cb12 KG	315	{
	316	int result = 0;
	317	struct mpc_i2c *i2c;
8c86cb12 KG	318	struct fsl_i2c_platform_data *pdata;
	319	struct resource *r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	320
	321	pdata = (struct fsl_i2c_platform_data *) pdev->dev.platform_data;
	322
5263ebb5	323	if (!(i2c = kzalloc(sizeof(*i2c), GFP_KERNEL))) {
8c86cb12 KG	324	return -ENOMEM;
8c86cb12 KG	325	}
8c86cb12 KG	326
8c86cb12 KG	327	i2c->irq = platform_get_irq(pdev, 0);
48944738 DV	328	if (i2c->irq < 0) {
	329	result = -ENXIO;
	330	goto fail_get_irq;
	331	}
8c86cb12 KG	332	i2c->flags = pdata->device_flags;
	333	init_waitqueue_head(&i2c->queue);
	334
	335	i2c->base = ioremap((phys_addr_t)r->start, MPC_I2C_REGION);
	336
	337	if (!i2c->base) {
	338	printk(KERN_ERR "i2c-mpc - failed to map controller\n");
	339	result = -ENOMEM;
	340	goto fail_map;
	341	}
	342
	343	if (i2c->irq != 0)
	344	if ((result = request_irq(i2c->irq, mpc_i2c_isr,
dace1453	345	IRQF_SHARED, "i2c-mpc", i2c)) < 0) {
8c86cb12 KG	346	printk(KERN_ERR
	347	"i2c-mpc - failed to attach interrupt\n");
	348	goto fail_irq;
	349	}
	350
	351	mpc_i2c_setclock(i2c);
3ae5eaec	352	platform_set_drvdata(pdev, i2c);
8c86cb12 KG	353
8c86cb12 KG	354	i2c->adap = mpc_ops;
1469fa26	355	i2c->adap.nr = pdev->id;
8c86cb12 KG	356	i2c_set_adapdata(&i2c->adap, i2c);
8c86cb12 KG	357	i2c->adap.dev.parent = &pdev->dev;
1469fa26	358	if ((result = i2c_add_numbered_adapter(&i2c->adap)) < 0) {
8c86cb12 KG	359	printk(KERN_ERR "i2c-mpc - failed to add adapter\n");
	360	goto fail_add;
	361	}
	362
	363	return result;
	364
	365	fail_add:
	366	if (i2c->irq != 0)
322454a6	367	free_irq(i2c->irq, i2c);
8c86cb12 KG	368	fail_irq:
	369	iounmap(i2c->base);
	370	fail_map:
48944738	371	fail_get_irq:
8c86cb12 KG	372	kfree(i2c);
	373	return result;
	374	};
	375
3ae5eaec	376	static int fsl_i2c_remove(struct platform_device *pdev)
8c86cb12	377	{
3ae5eaec	378	struct mpc_i2c *i2c = platform_get_drvdata(pdev);
8c86cb12 KG	379
8c86cb12 KG	380	i2c_del_adapter(&i2c->adap);
3ae5eaec	381	platform_set_drvdata(pdev, NULL);
8c86cb12 KG	382
	383	if (i2c->irq != 0)
	384	free_irq(i2c->irq, i2c);
	385
	386	iounmap(i2c->base);
	387	kfree(i2c);
	388	return 0;
	389	};
	390
	391	/* Structure for a device driver */
3ae5eaec	392	static struct platform_driver fsl_i2c_driver = {
8c86cb12 KG	393	.probe = fsl_i2c_probe,
8c86cb12 KG	394	.remove = fsl_i2c_remove,
3ae5eaec RK	395	.driver = {
	396	.owner = THIS_MODULE,
	397	.name = "fsl-i2c",
	398	},
8c86cb12 KG	399	};
	400
	401	static int __init fsl_i2c_init(void)
	402	{
3ae5eaec	403	return platform_driver_register(&fsl_i2c_driver);
8c86cb12 KG	404	}
	405
	406	static void __exit fsl_i2c_exit(void)
	407	{
3ae5eaec	408	platform_driver_unregister(&fsl_i2c_driver);
8c86cb12 KG	409	}
	410
	411	module_init(fsl_i2c_init);
	412	module_exit(fsl_i2c_exit);
	413
1da177e4 LT	414	MODULE_AUTHOR("Adrian Cox <adrian@humboldt.co.uk>");
	415	MODULE_DESCRIPTION
	416	("I2C-Bus adapter for MPC107 bridge and MPC824x/85xx/52xx processors");
	417	MODULE_LICENSE("GPL");