[net-next-2.6.git] / drivers / i2c / busses / i2c-iop3xx.c

/* ------------------------------------------------------------------------- */
/* i2c-iop3xx.c i2c driver algorithms for Intel XScale IOP3xx & IXP46x       */
/* ------------------------------------------------------------------------- */
/* Copyright (C) 2003 Peter Milne, D-TACQ Solutions Ltd
 *                    <Peter dot Milne at D hyphen TACQ dot com>
 *
 * With acknowledgements to i2c-algo-ibm_ocp.c by 
 * Ian DaSilva, MontaVista Software, Inc. idasilva@mvista.com
 *
 * And i2c-algo-pcf.c, which was created by Simon G. Vogl and Hans Berglund:
 *
 * Copyright (C) 1995-1997 Simon G. Vogl, 1998-2000 Hans Berglund
 *  
 * And which acknowledged Kyösti Mälkki <kmalkki@cc.hut.fi>,
 * Frodo Looijaard <frodol@dds.nl>, Martin Bailey<mbailey@littlefeet-inc.com>
 *
 * Major cleanup by Deepak Saxena <dsaxena@plexity.net>, 01/2005:
 *
 * - Use driver model to pass per-chip info instead of hardcoding and #ifdefs
 * - Use ioremap/__raw_readl/__raw_writel instead of direct dereference
 * - Make it work with IXP46x chips
 * - Cleanup function names, coding style, etc
 *
 * - writing to slave address causes latchup on iop331.
 *	fix: driver refuses to address self.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation, version 2.
 */

#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/slab.h>
#include <linux/init.h>
#include <linux/errno.h>
#include <linux/sched.h>
#include <linux/platform_device.h>
#include <linux/i2c.h>

#include <asm/io.h>

#include "i2c-iop3xx.h"

/* global unit counter */
static int i2c_id;

static inline unsigned char 
iic_cook_addr(struct i2c_msg *msg) 
{
	unsigned char addr;

	addr = (msg->addr << 1);

	if (msg->flags & I2C_M_RD)
		addr |= 1;

	/*
	 * Read or Write?
	 */
	if (msg->flags & I2C_M_REV_DIR_ADDR)
		addr ^= 1;

	return addr;   
}

static void 
iop3xx_i2c_reset(struct i2c_algo_iop3xx_data *iop3xx_adap)
{
	/* Follows devman 9.3 */
	__raw_writel(IOP3XX_ICR_UNIT_RESET, iop3xx_adap->ioaddr + CR_OFFSET);
	__raw_writel(IOP3XX_ISR_CLEARBITS, iop3xx_adap->ioaddr + SR_OFFSET);
	__raw_writel(0, iop3xx_adap->ioaddr + CR_OFFSET);
} 

static void 
iop3xx_i2c_enable(struct i2c_algo_iop3xx_data *iop3xx_adap)
{
	u32 cr = IOP3XX_ICR_GCD | IOP3XX_ICR_SCLEN | IOP3XX_ICR_UE;

	/* 
	 * Every time unit enable is asserted, GPOD needs to be cleared
	 * on IOP3XX to avoid data corruption on the bus.
	 */
#ifdef CONFIG_PLAT_IOP
	if (iop3xx_adap->id == 0) {
		gpio_line_set(IOP3XX_GPIO_LINE(7), GPIO_LOW);
		gpio_line_set(IOP3XX_GPIO_LINE(6), GPIO_LOW);
	} else {
		gpio_line_set(IOP3XX_GPIO_LINE(5), GPIO_LOW);
		gpio_line_set(IOP3XX_GPIO_LINE(4), GPIO_LOW);
	}
#endif
	/* NB SR bits not same position as CR IE bits :-( */
	iop3xx_adap->SR_enabled = 
		IOP3XX_ISR_ALD | IOP3XX_ISR_BERRD |
		IOP3XX_ISR_RXFULL | IOP3XX_ISR_TXEMPTY;

	cr |= IOP3XX_ICR_ALD_IE | IOP3XX_ICR_BERR_IE |
		IOP3XX_ICR_RXFULL_IE | IOP3XX_ICR_TXEMPTY_IE;

	__raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);
}

static void 
iop3xx_i2c_transaction_cleanup(struct i2c_algo_iop3xx_data *iop3xx_adap)
{
	unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET);
	
	cr &= ~(IOP3XX_ICR_MSTART | IOP3XX_ICR_TBYTE | 
		IOP3XX_ICR_MSTOP | IOP3XX_ICR_SCLEN);

	__raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);
}

/* 
 * NB: the handler has to clear the source of the interrupt! 
 * Then it passes the SR flags of interest to BH via adap data
 */
static irqreturn_t 
iop3xx_i2c_irq_handler(int this_irq, void *dev_id) 
{
	struct i2c_algo_iop3xx_data *iop3xx_adap = dev_id;
	u32 sr = __raw_readl(iop3xx_adap->ioaddr + SR_OFFSET);

	if ((sr &= iop3xx_adap->SR_enabled)) {
		__raw_writel(sr, iop3xx_adap->ioaddr + SR_OFFSET);
		iop3xx_adap->SR_received |= sr;
		wake_up_interruptible(&iop3xx_adap->waitq);
	}
	return IRQ_HANDLED;
}

/* check all error conditions, clear them , report most important */
static int 
iop3xx_i2c_error(u32 sr)
{
	int rc = 0;

	if ((sr & IOP3XX_ISR_BERRD)) {
		if ( !rc ) rc = -I2C_ERR_BERR;
	}
	if ((sr & IOP3XX_ISR_ALD)) {
		if ( !rc ) rc = -I2C_ERR_ALD;		
	}
	return rc;	
}

static inline u32 
iop3xx_i2c_get_srstat(struct i2c_algo_iop3xx_data *iop3xx_adap)
{
	unsigned long flags;
	u32 sr;

	spin_lock_irqsave(&iop3xx_adap->lock, flags);
	sr = iop3xx_adap->SR_received;
	iop3xx_adap->SR_received = 0;
	spin_unlock_irqrestore(&iop3xx_adap->lock, flags);

	return sr;
}

/*
 * sleep until interrupted, then recover and analyse the SR
 * saved by handler
 */
typedef int (* compare_func)(unsigned test, unsigned mask);
/* returns 1 on correct comparison */

static int 
iop3xx_i2c_wait_event(struct i2c_algo_iop3xx_data *iop3xx_adap, 
			  unsigned flags, unsigned* status,
			  compare_func compare)
{
	unsigned sr = 0;
	int interrupted;
	int done;
	int rc = 0;

	do {
		interrupted = wait_event_interruptible_timeout (
			iop3xx_adap->waitq,
			(done = compare( sr = iop3xx_i2c_get_srstat(iop3xx_adap) ,flags )),
			1 * HZ;
			);
		if ((rc = iop3xx_i2c_error(sr)) < 0) {
			*status = sr;
			return rc;
		} else if (!interrupted) {
			*status = sr;
			return -ETIMEDOUT;
		}
	} while(!done);

	*status = sr;

	return 0;
}

/*
 * Concrete compare_funcs 
 */
static int 
all_bits_clear(unsigned test, unsigned mask)
{
	return (test & mask) == 0;
}

static int 
any_bits_set(unsigned test, unsigned mask)
{
	return (test & mask) != 0;
}

static int 
iop3xx_i2c_wait_tx_done(struct i2c_algo_iop3xx_data *iop3xx_adap, int *status)
{
	return iop3xx_i2c_wait_event( 
		iop3xx_adap, 
	        IOP3XX_ISR_TXEMPTY | IOP3XX_ISR_ALD | IOP3XX_ISR_BERRD,
		status, any_bits_set);
}

static int 
iop3xx_i2c_wait_rx_done(struct i2c_algo_iop3xx_data *iop3xx_adap, int *status)
{
	return iop3xx_i2c_wait_event( 
		iop3xx_adap, 
		IOP3XX_ISR_RXFULL | IOP3XX_ISR_ALD | IOP3XX_ISR_BERRD,
		status,	any_bits_set);
}

static int 
iop3xx_i2c_wait_idle(struct i2c_algo_iop3xx_data *iop3xx_adap, int *status)
{
	return iop3xx_i2c_wait_event( 
		iop3xx_adap, IOP3XX_ISR_UNITBUSY, status, all_bits_clear);
}

static int 
iop3xx_i2c_send_target_addr(struct i2c_algo_iop3xx_data *iop3xx_adap, 
				struct i2c_msg* msg)
{
	unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET);
	int status;
	int rc;

	/* avoid writing to my slave address (hangs on 80331),
	 * forbidden in Intel developer manual
	 */
	if (msg->addr == MYSAR) {
		return -EBUSY;
	}

	__raw_writel(iic_cook_addr(msg), iop3xx_adap->ioaddr + DBR_OFFSET);
	
	cr &= ~(IOP3XX_ICR_MSTOP | IOP3XX_ICR_NACK);
	cr |= IOP3XX_ICR_MSTART | IOP3XX_ICR_TBYTE;

	__raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);
	rc = iop3xx_i2c_wait_tx_done(iop3xx_adap, &status);

	return rc;
}

static int 
iop3xx_i2c_write_byte(struct i2c_algo_iop3xx_data *iop3xx_adap, char byte, 
				int stop)
{
	unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET);
	int status;
	int rc = 0;

	__raw_writel(byte, iop3xx_adap->ioaddr + DBR_OFFSET);
	cr &= ~IOP3XX_ICR_MSTART;
	if (stop) {
		cr |= IOP3XX_ICR_MSTOP;
	} else {
		cr &= ~IOP3XX_ICR_MSTOP;
	}
	cr |= IOP3XX_ICR_TBYTE;
	__raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);
	rc = iop3xx_i2c_wait_tx_done(iop3xx_adap, &status);

	return rc;
} 

static int 
iop3xx_i2c_read_byte(struct i2c_algo_iop3xx_data *iop3xx_adap, char* byte, 
				int stop)
{
	unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET);
	int status;
	int rc = 0;

	cr &= ~IOP3XX_ICR_MSTART;

	if (stop) {
		cr |= IOP3XX_ICR_MSTOP | IOP3XX_ICR_NACK;
	} else {
		cr &= ~(IOP3XX_ICR_MSTOP | IOP3XX_ICR_NACK);
	}
	cr |= IOP3XX_ICR_TBYTE;
	__raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);

	rc = iop3xx_i2c_wait_rx_done(iop3xx_adap, &status);

	*byte = __raw_readl(iop3xx_adap->ioaddr + DBR_OFFSET);

	return rc;
}

static int 
iop3xx_i2c_writebytes(struct i2c_adapter *i2c_adap, const char *buf, int count)
{
	struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data;
	int ii;
	int rc = 0;

	for (ii = 0; rc == 0 && ii != count; ++ii) 
		rc = iop3xx_i2c_write_byte(iop3xx_adap, buf[ii], ii==count-1);
	return rc;
}

static int 
iop3xx_i2c_readbytes(struct i2c_adapter *i2c_adap, char *buf, int count)
{
	struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data;
	int ii;
	int rc = 0;

	for (ii = 0; rc == 0 && ii != count; ++ii)
		rc = iop3xx_i2c_read_byte(iop3xx_adap, &buf[ii], ii==count-1);
	
	return rc;
}

/*
 * Description:  This function implements combined transactions.  Combined
 * transactions consist of combinations of reading and writing blocks of data.
 * FROM THE SAME ADDRESS
 * Each transfer (i.e. a read or a write) is separated by a repeated start
 * condition.
 */
static int 
iop3xx_i2c_handle_msg(struct i2c_adapter *i2c_adap, struct i2c_msg* pmsg) 
{
	struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data;
	int rc;

	rc = iop3xx_i2c_send_target_addr(iop3xx_adap, pmsg);
	if (rc < 0) {
		return rc;
	}

	if ((pmsg->flags&I2C_M_RD)) {
		return iop3xx_i2c_readbytes(i2c_adap, pmsg->buf, pmsg->len);
	} else {
		return iop3xx_i2c_writebytes(i2c_adap, pmsg->buf, pmsg->len);
	}
}

/*
 * master_xfer() - main read/write entry
 */
static int 
iop3xx_i2c_master_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs, 
				int num)
{
	struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data;
	int im = 0;
	int ret = 0;
	int status;

	iop3xx_i2c_wait_idle(iop3xx_adap, &status);
	iop3xx_i2c_reset(iop3xx_adap);
	iop3xx_i2c_enable(iop3xx_adap);

	for (im = 0; ret == 0 && im != num; im++) {
		ret = iop3xx_i2c_handle_msg(i2c_adap, &msgs[im]);
	}

	iop3xx_i2c_transaction_cleanup(iop3xx_adap);
	
	if(ret)
		return ret;

	return im;   
}

static int 
iop3xx_i2c_algo_control(struct i2c_adapter *adapter, unsigned int cmd,
			unsigned long arg)
{
	return 0;
}

static u32 
iop3xx_i2c_func(struct i2c_adapter *adap)
{
	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
}

static const struct i2c_algorithm iop3xx_i2c_algo = {
	.master_xfer	= iop3xx_i2c_master_xfer,
	.algo_control	= iop3xx_i2c_algo_control,
	.functionality	= iop3xx_i2c_func,
};

static int 
iop3xx_i2c_remove(struct platform_device *pdev)
{
	struct i2c_adapter *padapter = platform_get_drvdata(pdev);
	struct i2c_algo_iop3xx_data *adapter_data = 
		(struct i2c_algo_iop3xx_data *)padapter->algo_data;
	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	unsigned long cr = __raw_readl(adapter_data->ioaddr + CR_OFFSET);

	/*
	 * Disable the actual HW unit
	 */
	cr &= ~(IOP3XX_ICR_ALD_IE | IOP3XX_ICR_BERR_IE |
		IOP3XX_ICR_RXFULL_IE | IOP3XX_ICR_TXEMPTY_IE);
	__raw_writel(cr, adapter_data->ioaddr + CR_OFFSET);

	iounmap((void __iomem*)adapter_data->ioaddr);
	release_mem_region(res->start, IOP3XX_I2C_IO_SIZE);
	kfree(adapter_data);
	kfree(padapter);

	platform_set_drvdata(pdev, NULL);

	return 0;
}

static int 
iop3xx_i2c_probe(struct platform_device *pdev)
{
	struct resource *res;
	int ret, irq;
	struct i2c_adapter *new_adapter;
	struct i2c_algo_iop3xx_data *adapter_data;

	new_adapter = kzalloc(sizeof(struct i2c_adapter), GFP_KERNEL);
	if (!new_adapter) {
		ret = -ENOMEM;
		goto out;
	}

	adapter_data = kzalloc(sizeof(struct i2c_algo_iop3xx_data), GFP_KERNEL);
	if (!adapter_data) {
		ret = -ENOMEM;
		goto free_adapter;
	}

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res) {
		ret = -ENODEV;
		goto free_both;
	}

	if (!request_mem_region(res->start, IOP3XX_I2C_IO_SIZE, pdev->name)) {
		ret = -EBUSY;
		goto free_both;
	}

	/* set the adapter enumeration # */
	adapter_data->id = i2c_id++;

	adapter_data->ioaddr = (u32)ioremap(res->start, IOP3XX_I2C_IO_SIZE);
	if (!adapter_data->ioaddr) {
		ret = -ENOMEM;
		goto release_region;
	}

	irq = platform_get_irq(pdev, 0);
	if (irq < 0) {
		ret = -ENXIO;
		goto unmap;
	}
	ret = request_irq(irq, iop3xx_i2c_irq_handler, 0,
				pdev->name, adapter_data);

	if (ret) {
		ret = -EIO;
		goto unmap;
	}

	memcpy(new_adapter->name, pdev->name, strlen(pdev->name));
	new_adapter->id = I2C_HW_IOP3XX;
	new_adapter->owner = THIS_MODULE;
	new_adapter->dev.parent = &pdev->dev;

	/*
	 * Default values...should these come in from board code?
	 */
	new_adapter->timeout = 100;	
	new_adapter->retries = 3;
	new_adapter->algo = &iop3xx_i2c_algo;

	init_waitqueue_head(&adapter_data->waitq);
	spin_lock_init(&adapter_data->lock);

	iop3xx_i2c_reset(adapter_data);
	iop3xx_i2c_enable(adapter_data);

	platform_set_drvdata(pdev, new_adapter);
	new_adapter->algo_data = adapter_data;

	i2c_add_adapter(new_adapter);

	return 0;

unmap:
	iounmap((void __iomem*)adapter_data->ioaddr);

release_region:
	release_mem_region(res->start, IOP3XX_I2C_IO_SIZE);

free_both:
	kfree(adapter_data);

free_adapter:
	kfree(new_adapter);

out:
	return ret;
}


static struct platform_driver iop3xx_i2c_driver = {
	.probe		= iop3xx_i2c_probe,
	.remove		= iop3xx_i2c_remove,
	.driver		= {
		.owner	= THIS_MODULE,
		.name	= "IOP3xx-I2C",
	},
};

static int __init 
i2c_iop3xx_init (void)
{
	return platform_driver_register(&iop3xx_i2c_driver);
}

static void __exit 
i2c_iop3xx_exit (void)
{
	platform_driver_unregister(&iop3xx_i2c_driver);
	return;
}

module_init (i2c_iop3xx_init);
module_exit (i2c_iop3xx_exit);

MODULE_AUTHOR("D-TACQ Solutions Ltd <www.d-tacq.com>");
MODULE_DESCRIPTION("IOP3xx iic algorithm and driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4 LT	1	/* ------------------------------------------------------------------------- */
	2	/* i2c-iop3xx.c i2c driver algorithms for Intel XScale IOP3xx & IXP46x */
	3	/* ------------------------------------------------------------------------- */
	4	/* Copyright (C) 2003 Peter Milne, D-TACQ Solutions Ltd
	5	* <Peter dot Milne at D hyphen TACQ dot com>
	6	*
	7	* With acknowledgements to i2c-algo-ibm_ocp.c by
	8	* Ian DaSilva, MontaVista Software, Inc. idasilva@mvista.com
	9	*
	10	* And i2c-algo-pcf.c, which was created by Simon G. Vogl and Hans Berglund:
	11	*
	12	* Copyright (C) 1995-1997 Simon G. Vogl, 1998-2000 Hans Berglund
	13	*
fbd9a6d7	14	* And which acknowledged Kyösti Mälkki <kmalkki@cc.hut.fi>,
1da177e4 LT	15	* Frodo Looijaard <frodol@dds.nl>, Martin Bailey<mbailey@littlefeet-inc.com>
	16	*
	17	* Major cleanup by Deepak Saxena <dsaxena@plexity.net>, 01/2005:
	18	*
	19	* - Use driver model to pass per-chip info instead of hardcoding and #ifdefs
	20	* - Use ioremap/__raw_readl/__raw_writel instead of direct dereference
	21	* - Make it work with IXP46x chips
	22	* - Cleanup function names, coding style, etc
	23	*
39288e1a PM	24	* - writing to slave address causes latchup on iop331.
	25	* fix: driver refuses to address self.
	26	*
1da177e4 LT	27	* This program is free software; you can redistribute it and/or modify
	28	* it under the terms of the GNU General Public License as published by
	29	* the Free Software Foundation, version 2.
	30	*/
	31
1da177e4 LT	32	#include <linux/interrupt.h>
	33	#include <linux/kernel.h>
	34	#include <linux/module.h>
	35	#include <linux/delay.h>
	36	#include <linux/slab.h>
	37	#include <linux/init.h>
	38	#include <linux/errno.h>
	39	#include <linux/sched.h>
d052d1be	40	#include <linux/platform_device.h>
1da177e4 LT	41	#include <linux/i2c.h>
	42
	43	#include <asm/io.h>
	44
	45	#include "i2c-iop3xx.h"
	46
	47	/* global unit counter */
60507095	48	static int i2c_id;
1da177e4 LT	49
	50	static inline unsigned char
	51	iic_cook_addr(struct i2c_msg *msg)
	52	{
	53	unsigned char addr;
	54
	55	addr = (msg->addr << 1);
	56
	57	if (msg->flags & I2C_M_RD)
	58	addr \|= 1;
	59
	60	/*
	61	* Read or Write?
	62	*/
	63	if (msg->flags & I2C_M_REV_DIR_ADDR)
	64	addr ^= 1;
	65
	66	return addr;
	67	}
	68
	69	static void
	70	iop3xx_i2c_reset(struct i2c_algo_iop3xx_data *iop3xx_adap)
	71	{
	72	/* Follows devman 9.3 */
	73	__raw_writel(IOP3XX_ICR_UNIT_RESET, iop3xx_adap->ioaddr + CR_OFFSET);
	74	__raw_writel(IOP3XX_ISR_CLEARBITS, iop3xx_adap->ioaddr + SR_OFFSET);
	75	__raw_writel(0, iop3xx_adap->ioaddr + CR_OFFSET);
	76	}
	77
1da177e4 LT	78	static void
	79	iop3xx_i2c_enable(struct i2c_algo_iop3xx_data *iop3xx_adap)
	80	{
	81	u32 cr = IOP3XX_ICR_GCD \| IOP3XX_ICR_SCLEN \| IOP3XX_ICR_UE;
	82
	83	/*
44bbe87e	84	* Every time unit enable is asserted, GPOD needs to be cleared
72edd84a	85	* on IOP3XX to avoid data corruption on the bus.
1da177e4	86	*/
72edd84a LB	87	#ifdef CONFIG_PLAT_IOP
	88	if (iop3xx_adap->id == 0) {
	89	gpio_line_set(IOP3XX_GPIO_LINE(7), GPIO_LOW);
	90	gpio_line_set(IOP3XX_GPIO_LINE(6), GPIO_LOW);
	91	} else {
	92	gpio_line_set(IOP3XX_GPIO_LINE(5), GPIO_LOW);
	93	gpio_line_set(IOP3XX_GPIO_LINE(4), GPIO_LOW);
	94	}
1da177e4 LT	95	#endif
	96	/* NB SR bits not same position as CR IE bits :-( */
	97	iop3xx_adap->SR_enabled =
	98	IOP3XX_ISR_ALD \| IOP3XX_ISR_BERRD \|
	99	IOP3XX_ISR_RXFULL \| IOP3XX_ISR_TXEMPTY;
	100
	101	cr \|= IOP3XX_ICR_ALD_IE \| IOP3XX_ICR_BERR_IE \|
	102	IOP3XX_ICR_RXFULL_IE \| IOP3XX_ICR_TXEMPTY_IE;
	103
	104	__raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);
	105	}
	106
	107	static void
	108	iop3xx_i2c_transaction_cleanup(struct i2c_algo_iop3xx_data *iop3xx_adap)
	109	{
	110	unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET);
	111
	112	cr &= ~(IOP3XX_ICR_MSTART \| IOP3XX_ICR_TBYTE \|
	113	IOP3XX_ICR_MSTOP \| IOP3XX_ICR_SCLEN);
	114
	115	__raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);
	116	}
	117
	118	/*
	119	* NB: the handler has to clear the source of the interrupt!
	120	* Then it passes the SR flags of interest to BH via adap data
	121	*/
	122	static irqreturn_t
7d12e780	123	iop3xx_i2c_irq_handler(int this_irq, void *dev_id)
1da177e4 LT	124	{
	125	struct i2c_algo_iop3xx_data *iop3xx_adap = dev_id;
	126	u32 sr = __raw_readl(iop3xx_adap->ioaddr + SR_OFFSET);
	127
	128	if ((sr &= iop3xx_adap->SR_enabled)) {
	129	__raw_writel(sr, iop3xx_adap->ioaddr + SR_OFFSET);
	130	iop3xx_adap->SR_received \|= sr;
	131	wake_up_interruptible(&iop3xx_adap->waitq);
	132	}
	133	return IRQ_HANDLED;
	134	}
	135
	136	/* check all error conditions, clear them , report most important */
	137	static int
	138	iop3xx_i2c_error(u32 sr)
	139	{
	140	int rc = 0;
	141
	142	if ((sr & IOP3XX_ISR_BERRD)) {
	143	if ( !rc ) rc = -I2C_ERR_BERR;
	144	}
	145	if ((sr & IOP3XX_ISR_ALD)) {
	146	if ( !rc ) rc = -I2C_ERR_ALD;
	147	}
	148	return rc;
	149	}
	150
	151	static inline u32
	152	iop3xx_i2c_get_srstat(struct i2c_algo_iop3xx_data *iop3xx_adap)
	153	{
	154	unsigned long flags;
	155	u32 sr;
	156
	157	spin_lock_irqsave(&iop3xx_adap->lock, flags);
	158	sr = iop3xx_adap->SR_received;
	159	iop3xx_adap->SR_received = 0;
	160	spin_unlock_irqrestore(&iop3xx_adap->lock, flags);
	161
	162	return sr;
	163	}
	164
	165	/*
	166	* sleep until interrupted, then recover and analyse the SR
	167	* saved by handler
	168	*/
	169	typedef int (* compare_func)(unsigned test, unsigned mask);
	170	/* returns 1 on correct comparison */
	171
	172	static int
	173	iop3xx_i2c_wait_event(struct i2c_algo_iop3xx_data *iop3xx_adap,
	174	unsigned flags, unsigned* status,
	175	compare_func compare)
	176	{
	177	unsigned sr = 0;
	178	int interrupted;
	179	int done;
	180	int rc = 0;
	181
	182	do {
	183	interrupted = wait_event_interruptible_timeout (
	184	iop3xx_adap->waitq,
fbd9a6d7	185	(done = compare( sr = iop3xx_i2c_get_srstat(iop3xx_adap) ,flags )),
1da177e4 LT	186	1 * HZ;
	187	);
	188	if ((rc = iop3xx_i2c_error(sr)) < 0) {
	189	*status = sr;
	190	return rc;
	191	} else if (!interrupted) {
	192	*status = sr;
	193	return -ETIMEDOUT;
	194	}
	195	} while(!done);
	196
	197	*status = sr;
	198
	199	return 0;
	200	}
	201
	202	/*
	203	* Concrete compare_funcs
	204	*/
	205	static int
	206	all_bits_clear(unsigned test, unsigned mask)
	207	{
	208	return (test & mask) == 0;
	209	}
	210
	211	static int
	212	any_bits_set(unsigned test, unsigned mask)
	213	{
	214	return (test & mask) != 0;
	215	}
	216
	217	static int
	218	iop3xx_i2c_wait_tx_done(struct i2c_algo_iop3xx_data iop3xx_adap, int status)
	219	{
	220	return iop3xx_i2c_wait_event(
	221	iop3xx_adap,
	222	IOP3XX_ISR_TXEMPTY \| IOP3XX_ISR_ALD \| IOP3XX_ISR_BERRD,
	223	status, any_bits_set);
	224	}
	225
	226	static int
	227	iop3xx_i2c_wait_rx_done(struct i2c_algo_iop3xx_data iop3xx_adap, int status)
	228	{
	229	return iop3xx_i2c_wait_event(
	230	iop3xx_adap,
	231	IOP3XX_ISR_RXFULL \| IOP3XX_ISR_ALD \| IOP3XX_ISR_BERRD,
	232	status, any_bits_set);
	233	}
	234
	235	static int
	236	iop3xx_i2c_wait_idle(struct i2c_algo_iop3xx_data iop3xx_adap, int status)
	237	{
	238	return iop3xx_i2c_wait_event(
	239	iop3xx_adap, IOP3XX_ISR_UNITBUSY, status, all_bits_clear);
	240	}
	241
	242	static int
	243	iop3xx_i2c_send_target_addr(struct i2c_algo_iop3xx_data *iop3xx_adap,
	244	struct i2c_msg* msg)
	245	{
	246	unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET);
	247	int status;
	248	int rc;
	249
39288e1a PM	250	/* avoid writing to my slave address (hangs on 80331),
	251	* forbidden in Intel developer manual
	252	*/
	253	if (msg->addr == MYSAR) {
	254	return -EBUSY;
	255	}
	256
1da177e4 LT	257	__raw_writel(iic_cook_addr(msg), iop3xx_adap->ioaddr + DBR_OFFSET);
	258
	259	cr &= ~(IOP3XX_ICR_MSTOP \| IOP3XX_ICR_NACK);
	260	cr \|= IOP3XX_ICR_MSTART \| IOP3XX_ICR_TBYTE;
	261
	262	__raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);
	263	rc = iop3xx_i2c_wait_tx_done(iop3xx_adap, &status);
	264
	265	return rc;
	266	}
	267
	268	static int
	269	iop3xx_i2c_write_byte(struct i2c_algo_iop3xx_data *iop3xx_adap, char byte,
	270	int stop)
	271	{
	272	unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET);
	273	int status;
	274	int rc = 0;
	275
	276	__raw_writel(byte, iop3xx_adap->ioaddr + DBR_OFFSET);
	277	cr &= ~IOP3XX_ICR_MSTART;
	278	if (stop) {
	279	cr \|= IOP3XX_ICR_MSTOP;
	280	} else {
	281	cr &= ~IOP3XX_ICR_MSTOP;
	282	}
	283	cr \|= IOP3XX_ICR_TBYTE;
	284	__raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);
	285	rc = iop3xx_i2c_wait_tx_done(iop3xx_adap, &status);
	286
	287	return rc;
	288	}
	289
	290	static int
	291	iop3xx_i2c_read_byte(struct i2c_algo_iop3xx_data iop3xx_adap, char byte,
	292	int stop)
	293	{
	294	unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET);
	295	int status;
	296	int rc = 0;
	297
	298	cr &= ~IOP3XX_ICR_MSTART;
	299
	300	if (stop) {
	301	cr \|= IOP3XX_ICR_MSTOP \| IOP3XX_ICR_NACK;
	302	} else {
	303	cr &= ~(IOP3XX_ICR_MSTOP \| IOP3XX_ICR_NACK);
	304	}
	305	cr \|= IOP3XX_ICR_TBYTE;
	306	__raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);
	307
	308	rc = iop3xx_i2c_wait_rx_done(iop3xx_adap, &status);
	309
	310	*byte = __raw_readl(iop3xx_adap->ioaddr + DBR_OFFSET);
	311
	312	return rc;
	313	}
	314
	315	static int
	316	iop3xx_i2c_writebytes(struct i2c_adapter i2c_adap, const char buf, int count)
	317	{
	318	struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data;
	319	int ii;
	320	int rc = 0;
321
322	for (ii = 0; rc == 0 && ii != count; ++ii)
323	rc = iop3xx_i2c_write_byte(iop3xx_adap, buf[ii], ii==count-1);
324	return rc;
325	}
326
327	static int
328	iop3xx_i2c_readbytes(struct i2c_adapter i2c_adap, char buf, int count)
329	{
330	struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data;
331	int ii;
332	int rc = 0;
333
334	for (ii = 0; rc == 0 && ii != count; ++ii)
335	rc = iop3xx_i2c_read_byte(iop3xx_adap, &buf[ii], ii==count-1);
336
337	return rc;
338	}
339
340	/*
341	* Description: This function implements combined transactions. Combined
342	* transactions consist of combinations of reading and writing blocks of data.
343	* FROM THE SAME ADDRESS
344	* Each transfer (i.e. a read or a write) is separated by a repeated start
345	* condition.
346	*/
347	static int
348	iop3xx_i2c_handle_msg(struct i2c_adapter i2c_adap, struct i2c_msg pmsg)
349	{
350	struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data;
351	int rc;
352
353	rc = iop3xx_i2c_send_target_addr(iop3xx_adap, pmsg);
354	if (rc < 0) {
355	return rc;
356	}
357
358	if ((pmsg->flags&I2C_M_RD)) {
359	return iop3xx_i2c_readbytes(i2c_adap, pmsg->buf, pmsg->len);
360	} else {
361	return iop3xx_i2c_writebytes(i2c_adap, pmsg->buf, pmsg->len);
362	}
363	}
364
365	/*
366	* master_xfer() - main read/write entry
367	*/
368	static int
369	iop3xx_i2c_master_xfer(struct i2c_adapter i2c_adap, struct i2c_msg msgs,
370	int num)
371	{
372	struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data;
373	int im = 0;
374	int ret = 0;
375	int status;
376
377	iop3xx_i2c_wait_idle(iop3xx_adap, &status);
378	iop3xx_i2c_reset(iop3xx_adap);
379	iop3xx_i2c_enable(iop3xx_adap);
380
381	for (im = 0; ret == 0 && im != num; im++) {
382	ret = iop3xx_i2c_handle_msg(i2c_adap, &msgs[im]);
383	}
384
385	iop3xx_i2c_transaction_cleanup(iop3xx_adap);
386
387	if(ret)
388	return ret;
389
390	return im;
391	}
392
393	static int
394	iop3xx_i2c_algo_control(struct i2c_adapter *adapter, unsigned int cmd,
395	unsigned long arg)
396	{
397	return 0;
398	}
399
400	static u32
401	iop3xx_i2c_func(struct i2c_adapter *adap)
402	{
403	return I2C_FUNC_I2C \| I2C_FUNC_SMBUS_EMUL;
404	}
405
8f9082c5	406	static const struct i2c_algorithm iop3xx_i2c_algo = {
1da177e4 LT	407	.master_xfer = iop3xx_i2c_master_xfer,
	408	.algo_control = iop3xx_i2c_algo_control,
	409	.functionality = iop3xx_i2c_func,
	410	};
	411
	412	static int
3ae5eaec	413	iop3xx_i2c_remove(struct platform_device *pdev)
1da177e4	414	{
3ae5eaec	415	struct i2c_adapter *padapter = platform_get_drvdata(pdev);
1da177e4 LT	416	struct i2c_algo_iop3xx_data *adapter_data =
	417	(struct i2c_algo_iop3xx_data *)padapter->algo_data;
	418	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	419	unsigned long cr = __raw_readl(adapter_data->ioaddr + CR_OFFSET);
	420
	421	/*
	422	* Disable the actual HW unit
	423	*/
	424	cr &= ~(IOP3XX_ICR_ALD_IE \| IOP3XX_ICR_BERR_IE \|
	425	IOP3XX_ICR_RXFULL_IE \| IOP3XX_ICR_TXEMPTY_IE);
	426	__raw_writel(cr, adapter_data->ioaddr + CR_OFFSET);
	427
	428	iounmap((void __iomem*)adapter_data->ioaddr);
	429	release_mem_region(res->start, IOP3XX_I2C_IO_SIZE);
	430	kfree(adapter_data);
	431	kfree(padapter);
	432
3ae5eaec	433	platform_set_drvdata(pdev, NULL);
1da177e4 LT	434
	435	return 0;
	436	}
	437
	438	static int
3ae5eaec	439	iop3xx_i2c_probe(struct platform_device *pdev)
1da177e4	440	{
1da177e4	441	struct resource *res;
48944738	442	int ret, irq;
1da177e4 LT	443	struct i2c_adapter *new_adapter;
	444	struct i2c_algo_iop3xx_data *adapter_data;
	445
5263ebb5	446	new_adapter = kzalloc(sizeof(struct i2c_adapter), GFP_KERNEL);
1da177e4 LT	447	if (!new_adapter) {
	448	ret = -ENOMEM;
	449	goto out;
	450	}
1da177e4	451
5263ebb5	452	adapter_data = kzalloc(sizeof(struct i2c_algo_iop3xx_data), GFP_KERNEL);
1da177e4 LT	453	if (!adapter_data) {
	454	ret = -ENOMEM;
	455	goto free_adapter;
	456	}
1da177e4 LT	457
	458	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	459	if (!res) {
	460	ret = -ENODEV;
	461	goto free_both;
	462	}
	463
	464	if (!request_mem_region(res->start, IOP3XX_I2C_IO_SIZE, pdev->name)) {
	465	ret = -EBUSY;
	466	goto free_both;
	467	}
	468
	469	/* set the adapter enumeration # */
	470	adapter_data->id = i2c_id++;
	471
	472	adapter_data->ioaddr = (u32)ioremap(res->start, IOP3XX_I2C_IO_SIZE);
	473	if (!adapter_data->ioaddr) {
	474	ret = -ENOMEM;
	475	goto release_region;
	476	}
	477
48944738 DV	478	irq = platform_get_irq(pdev, 0);
	479	if (irq < 0) {
	480	ret = -ENXIO;
	481	goto unmap;
	482	}
	483	ret = request_irq(irq, iop3xx_i2c_irq_handler, 0,
1da177e4	484	pdev->name, adapter_data);
fbd9a6d7 DW	485
fbd9a6d7 DW	486	if (ret) {
1da177e4 LT	487	ret = -EIO;
	488	goto unmap;
	489	}
	490
	491	memcpy(new_adapter->name, pdev->name, strlen(pdev->name));
	492	new_adapter->id = I2C_HW_IOP3XX;
	493	new_adapter->owner = THIS_MODULE;
	494	new_adapter->dev.parent = &pdev->dev;
	495
	496	/*
	497	* Default values...should these come in from board code?
	498	*/
	499	new_adapter->timeout = 100;
	500	new_adapter->retries = 3;
	501	new_adapter->algo = &iop3xx_i2c_algo;
	502
	503	init_waitqueue_head(&adapter_data->waitq);
	504	spin_lock_init(&adapter_data->lock);
	505
	506	iop3xx_i2c_reset(adapter_data);
1da177e4 LT	507	iop3xx_i2c_enable(adapter_data);
1da177e4 LT	508
3ae5eaec	509	platform_set_drvdata(pdev, new_adapter);
1da177e4 LT	510	new_adapter->algo_data = adapter_data;
	511
	512	i2c_add_adapter(new_adapter);
	513
	514	return 0;
	515
	516	unmap:
	517	iounmap((void __iomem*)adapter_data->ioaddr);
	518
	519	release_region:
	520	release_mem_region(res->start, IOP3XX_I2C_IO_SIZE);
	521
	522	free_both:
	523	kfree(adapter_data);
	524
	525	free_adapter:
	526	kfree(new_adapter);
	527
	528	out:
	529	return ret;
	530	}
	531
	532
3ae5eaec	533	static struct platform_driver iop3xx_i2c_driver = {
1da177e4	534	.probe = iop3xx_i2c_probe,
3ae5eaec RK	535	.remove = iop3xx_i2c_remove,
	536	.driver = {
	537	.owner = THIS_MODULE,
	538	.name = "IOP3xx-I2C",
	539	},
1da177e4 LT	540	};
	541
	542	static int __init
	543	i2c_iop3xx_init (void)
	544	{
3ae5eaec	545	return platform_driver_register(&iop3xx_i2c_driver);
1da177e4 LT	546	}
	547
	548	static void __exit
	549	i2c_iop3xx_exit (void)
	550	{
3ae5eaec	551	platform_driver_unregister(&iop3xx_i2c_driver);
1da177e4 LT	552	return;
	553	}
	554
	555	module_init (i2c_iop3xx_init);
	556	module_exit (i2c_iop3xx_exit);
	557
	558	MODULE_AUTHOR("D-TACQ Solutions Ltd <www.d-tacq.com>");
	559	MODULE_DESCRIPTION("IOP3xx iic algorithm and driver");
	560	MODULE_LICENSE("GPL");