[net-next-2.6.git] / drivers / i2c / busses / i2c-imx.c

/*
 *	Copyright (C) 2002 Motorola GSG-China
 *
 *	This program is free software; you can redistribute it and/or
 *	modify it under the terms of the GNU General Public License
 *	as published by the Free Software Foundation; either version 2
 *	of the License, or (at your option) any later version.
 *
 *	This program is distributed in the hope that it will be useful,
 *	but WITHOUT ANY WARRANTY; without even the implied warranty of
 *	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *	GNU General Public License for more details.
 *
 *	You should have received a copy of the GNU General Public License
 *	along with this program; if not, write to the Free Software
 *	Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307,
 *	USA.
 *
 * Author:
 *	Darius Augulis, Teltonika Inc.
 *
 * Desc.:
 *	Implementation of I2C Adapter/Algorithm Driver
 *	for I2C Bus integrated in Freescale i.MX/MXC processors
 *
 *	Derived from Motorola GSG China I2C example driver
 *
 *	Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de
 *	Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de
 *	Copyright (C) 2007 RightHand Technologies, Inc.
 *	Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
 *
 */

/** Includes *******************************************************************
*******************************************************************************/

#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/io.h>
#include <linux/sched.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/slab.h>

#include <mach/irqs.h>
#include <mach/hardware.h>
#include <mach/i2c.h>

/** Defines ********************************************************************
*******************************************************************************/

/* This will be the driver name the kernel reports */
#define DRIVER_NAME "imx-i2c"

/* Default value */
#define IMX_I2C_BIT_RATE	100000	/* 100kHz */

/* IMX I2C registers */
#define IMX_I2C_IADR	0x00	/* i2c slave address */
#define IMX_I2C_IFDR	0x04	/* i2c frequency divider */
#define IMX_I2C_I2CR	0x08	/* i2c control */
#define IMX_I2C_I2SR	0x0C	/* i2c status */
#define IMX_I2C_I2DR	0x10	/* i2c transfer data */

/* Bits of IMX I2C registers */
#define I2SR_RXAK	0x01
#define I2SR_IIF	0x02
#define I2SR_SRW	0x04
#define I2SR_IAL	0x10
#define I2SR_IBB	0x20
#define I2SR_IAAS	0x40
#define I2SR_ICF	0x80
#define I2CR_RSTA	0x04
#define I2CR_TXAK	0x08
#define I2CR_MTX	0x10
#define I2CR_MSTA	0x20
#define I2CR_IIEN	0x40
#define I2CR_IEN	0x80

/** Variables ******************************************************************
*******************************************************************************/

/*
 * sorted list of clock divider, register value pairs
 * taken from table 26-5, p.26-9, Freescale i.MX
 * Integrated Portable System Processor Reference Manual
 * Document Number: MC9328MXLRM, Rev. 5.1, 06/2007
 *
 * Duplicated divider values removed from list
 */

static u16 __initdata i2c_clk_div[50][2] = {
	{ 22,	0x20 }, { 24,	0x21 }, { 26,	0x22 }, { 28,	0x23 },
	{ 30,	0x00 },	{ 32,	0x24 }, { 36,	0x25 }, { 40,	0x26 },
	{ 42,	0x03 }, { 44,	0x27 },	{ 48,	0x28 }, { 52,	0x05 },
	{ 56,	0x29 }, { 60,	0x06 }, { 64,	0x2A },	{ 72,	0x2B },
	{ 80,	0x2C }, { 88,	0x09 }, { 96,	0x2D }, { 104,	0x0A },
	{ 112,	0x2E }, { 128,	0x2F }, { 144,	0x0C }, { 160,	0x30 },
	{ 192,	0x31 },	{ 224,	0x32 }, { 240,	0x0F }, { 256,	0x33 },
	{ 288,	0x10 }, { 320,	0x34 },	{ 384,	0x35 }, { 448,	0x36 },
	{ 480,	0x13 }, { 512,	0x37 }, { 576,	0x14 },	{ 640,	0x38 },
	{ 768,	0x39 }, { 896,	0x3A }, { 960,	0x17 }, { 1024,	0x3B },
	{ 1152,	0x18 }, { 1280,	0x3C }, { 1536,	0x3D }, { 1792,	0x3E },
	{ 1920,	0x1B },	{ 2048,	0x3F }, { 2304,	0x1C }, { 2560,	0x1D },
	{ 3072,	0x1E }, { 3840,	0x1F }
};

struct imx_i2c_struct {
	struct i2c_adapter	adapter;
	struct resource		*res;
	struct clk		*clk;
	void __iomem		*base;
	int			irq;
	wait_queue_head_t	queue;
	unsigned long		i2csr;
	unsigned int 		disable_delay;
	int			stopped;
	unsigned int		ifdr; /* IMX_I2C_IFDR */
};

/** Functions for IMX I2C adapter driver ***************************************
*******************************************************************************/

static int i2c_imx_bus_busy(struct imx_i2c_struct *i2c_imx, int for_busy)
{
	unsigned long orig_jiffies = jiffies;
	unsigned int temp;

	dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);

	while (1) {
		temp = readb(i2c_imx->base + IMX_I2C_I2SR);
		if (for_busy && (temp & I2SR_IBB))
			break;
		if (!for_busy && !(temp & I2SR_IBB))
			break;
		if (signal_pending(current)) {
			dev_dbg(&i2c_imx->adapter.dev,
				"<%s> I2C Interrupted\n", __func__);
			return -EINTR;
		}
		if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) {
			dev_dbg(&i2c_imx->adapter.dev,
				"<%s> I2C bus is busy\n", __func__);
			return -ETIMEDOUT;
		}
		schedule();
	}

	return 0;
}

static int i2c_imx_trx_complete(struct imx_i2c_struct *i2c_imx)
{
	wait_event_timeout(i2c_imx->queue, i2c_imx->i2csr & I2SR_IIF, HZ / 10);

	if (unlikely(!(i2c_imx->i2csr & I2SR_IIF))) {
		dev_dbg(&i2c_imx->adapter.dev, "<%s> Timeout\n", __func__);
		return -ETIMEDOUT;
	}
	dev_dbg(&i2c_imx->adapter.dev, "<%s> TRX complete\n", __func__);
	i2c_imx->i2csr = 0;
	return 0;
}

static int i2c_imx_acked(struct imx_i2c_struct *i2c_imx)
{
	if (readb(i2c_imx->base + IMX_I2C_I2SR) & I2SR_RXAK) {
		dev_dbg(&i2c_imx->adapter.dev, "<%s> No ACK\n", __func__);
		return -EIO;  /* No ACK */
	}

	dev_dbg(&i2c_imx->adapter.dev, "<%s> ACK received\n", __func__);
	return 0;
}

static int i2c_imx_start(struct imx_i2c_struct *i2c_imx)
{
	unsigned int temp = 0;
	int result;

	dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);

	clk_enable(i2c_imx->clk);
	writeb(i2c_imx->ifdr, i2c_imx->base + IMX_I2C_IFDR);
	/* Enable I2C controller */
	writeb(0, i2c_imx->base + IMX_I2C_I2SR);
	writeb(I2CR_IEN, i2c_imx->base + IMX_I2C_I2CR);

	/* Wait controller to be stable */
	udelay(50);

	/* Start I2C transaction */
	temp = readb(i2c_imx->base + IMX_I2C_I2CR);
	temp |= I2CR_MSTA;
	writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
	result = i2c_imx_bus_busy(i2c_imx, 1);
	if (result)
		return result;
	i2c_imx->stopped = 0;

	temp |= I2CR_IIEN | I2CR_MTX | I2CR_TXAK;
	writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
	return result;
}

static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx)
{
	unsigned int temp = 0;

	if (!i2c_imx->stopped) {
		/* Stop I2C transaction */
		dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
		temp = readb(i2c_imx->base + IMX_I2C_I2CR);
		temp &= ~(I2CR_MSTA | I2CR_MTX);
		writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
	}
	if (cpu_is_mx1()) {
		/*
		 * This delay caused by an i.MXL hardware bug.
		 * If no (or too short) delay, no "STOP" bit will be generated.
		 */
		udelay(i2c_imx->disable_delay);
	}

	if (!i2c_imx->stopped) {
		i2c_imx_bus_busy(i2c_imx, 0);
		i2c_imx->stopped = 1;
	}

	/* Disable I2C controller */
	writeb(0, i2c_imx->base + IMX_I2C_I2CR);
	clk_disable(i2c_imx->clk);
}

static void __init i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx,
							unsigned int rate)
{
	unsigned int i2c_clk_rate;
	unsigned int div;
	int i;

	/* Divider value calculation */
	i2c_clk_rate = clk_get_rate(i2c_imx->clk);
	div = (i2c_clk_rate + rate - 1) / rate;
	if (div < i2c_clk_div[0][0])
		i = 0;
	else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1][0])
		i = ARRAY_SIZE(i2c_clk_div) - 1;
	else
		for (i = 0; i2c_clk_div[i][0] < div; i++);

	/* Store divider value */
	i2c_imx->ifdr = i2c_clk_div[i][1];

	/*
	 * There dummy delay is calculated.
	 * It should be about one I2C clock period long.
	 * This delay is used in I2C bus disable function
	 * to fix chip hardware bug.
	 */
	i2c_imx->disable_delay = (500000U * i2c_clk_div[i][0]
		+ (i2c_clk_rate / 2) - 1) / (i2c_clk_rate / 2);

	/* dev_dbg() can't be used, because adapter is not yet registered */
#ifdef CONFIG_I2C_DEBUG_BUS
	printk(KERN_DEBUG "I2C: <%s> I2C_CLK=%d, REQ DIV=%d\n",
		__func__, i2c_clk_rate, div);
	printk(KERN_DEBUG "I2C: <%s> IFDR[IC]=0x%x, REAL DIV=%d\n",
		__func__, i2c_clk_div[i][1], i2c_clk_div[i][0]);
#endif
}

static irqreturn_t i2c_imx_isr(int irq, void *dev_id)
{
	struct imx_i2c_struct *i2c_imx = dev_id;
	unsigned int temp;

	temp = readb(i2c_imx->base + IMX_I2C_I2SR);
	if (temp & I2SR_IIF) {
		/* save status register */
		i2c_imx->i2csr = temp;
		temp &= ~I2SR_IIF;
		writeb(temp, i2c_imx->base + IMX_I2C_I2SR);
		wake_up(&i2c_imx->queue);
		return IRQ_HANDLED;
	}

	return IRQ_NONE;
}

static int i2c_imx_write(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs)
{
	int i, result;

	dev_dbg(&i2c_imx->adapter.dev, "<%s> write slave address: addr=0x%x\n",
		__func__, msgs->addr << 1);

	/* write slave address */
	writeb(msgs->addr << 1, i2c_imx->base + IMX_I2C_I2DR);
	result = i2c_imx_trx_complete(i2c_imx);
	if (result)
		return result;
	result = i2c_imx_acked(i2c_imx);
	if (result)
		return result;
	dev_dbg(&i2c_imx->adapter.dev, "<%s> write data\n", __func__);

	/* write data */
	for (i = 0; i < msgs->len; i++) {
		dev_dbg(&i2c_imx->adapter.dev,
			"<%s> write byte: B%d=0x%X\n",
			__func__, i, msgs->buf[i]);
		writeb(msgs->buf[i], i2c_imx->base + IMX_I2C_I2DR);
		result = i2c_imx_trx_complete(i2c_imx);
		if (result)
			return result;
		result = i2c_imx_acked(i2c_imx);
		if (result)
			return result;
	}
	return 0;
}

static int i2c_imx_read(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs)
{
	int i, result;
	unsigned int temp;

	dev_dbg(&i2c_imx->adapter.dev,
		"<%s> write slave address: addr=0x%x\n",
		__func__, (msgs->addr << 1) | 0x01);

	/* write slave address */
	writeb((msgs->addr << 1) | 0x01, i2c_imx->base + IMX_I2C_I2DR);
	result = i2c_imx_trx_complete(i2c_imx);
	if (result)
		return result;
	result = i2c_imx_acked(i2c_imx);
	if (result)
		return result;

	dev_dbg(&i2c_imx->adapter.dev, "<%s> setup bus\n", __func__);

	/* setup bus to read data */
	temp = readb(i2c_imx->base + IMX_I2C_I2CR);
	temp &= ~I2CR_MTX;
	if (msgs->len - 1)
		temp &= ~I2CR_TXAK;
	writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
	readb(i2c_imx->base + IMX_I2C_I2DR); /* dummy read */

	dev_dbg(&i2c_imx->adapter.dev, "<%s> read data\n", __func__);

	/* read data */
	for (i = 0; i < msgs->len; i++) {
		result = i2c_imx_trx_complete(i2c_imx);
		if (result)
			return result;
		if (i == (msgs->len - 1)) {
			/* It must generate STOP before read I2DR to prevent
			   controller from generating another clock cycle */
			dev_dbg(&i2c_imx->adapter.dev,
				"<%s> clear MSTA\n", __func__);
			temp = readb(i2c_imx->base + IMX_I2C_I2CR);
			temp &= ~(I2CR_MSTA | I2CR_MTX);
			writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
			i2c_imx_bus_busy(i2c_imx, 0);
			i2c_imx->stopped = 1;
		} else if (i == (msgs->len - 2)) {
			dev_dbg(&i2c_imx->adapter.dev,
				"<%s> set TXAK\n", __func__);
			temp = readb(i2c_imx->base + IMX_I2C_I2CR);
			temp |= I2CR_TXAK;
			writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
		}
		msgs->buf[i] = readb(i2c_imx->base + IMX_I2C_I2DR);
		dev_dbg(&i2c_imx->adapter.dev,
			"<%s> read byte: B%d=0x%X\n",
			__func__, i, msgs->buf[i]);
	}
	return 0;
}

static int i2c_imx_xfer(struct i2c_adapter *adapter,
						struct i2c_msg *msgs, int num)
{
	unsigned int i, temp;
	int result;
	struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter);

	dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);

	/* Start I2C transfer */
	result = i2c_imx_start(i2c_imx);
	if (result)
		goto fail0;

	/* read/write data */
	for (i = 0; i < num; i++) {
		if (i) {
			dev_dbg(&i2c_imx->adapter.dev,
				"<%s> repeated start\n", __func__);
			temp = readb(i2c_imx->base + IMX_I2C_I2CR);
			temp |= I2CR_RSTA;
			writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
			result =  i2c_imx_bus_busy(i2c_imx, 1);
			if (result)
				goto fail0;
		}
		dev_dbg(&i2c_imx->adapter.dev,
			"<%s> transfer message: %d\n", __func__, i);
		/* write/read data */
#ifdef CONFIG_I2C_DEBUG_BUS
		temp = readb(i2c_imx->base + IMX_I2C_I2CR);
		dev_dbg(&i2c_imx->adapter.dev, "<%s> CONTROL: IEN=%d, IIEN=%d, "
			"MSTA=%d, MTX=%d, TXAK=%d, RSTA=%d\n", __func__,
			(temp & I2CR_IEN ? 1 : 0), (temp & I2CR_IIEN ? 1 : 0),
			(temp & I2CR_MSTA ? 1 : 0), (temp & I2CR_MTX ? 1 : 0),
			(temp & I2CR_TXAK ? 1 : 0), (temp & I2CR_RSTA ? 1 : 0));
		temp = readb(i2c_imx->base + IMX_I2C_I2SR);
		dev_dbg(&i2c_imx->adapter.dev,
			"<%s> STATUS: ICF=%d, IAAS=%d, IBB=%d, "
			"IAL=%d, SRW=%d, IIF=%d, RXAK=%d\n", __func__,
			(temp & I2SR_ICF ? 1 : 0), (temp & I2SR_IAAS ? 1 : 0),
			(temp & I2SR_IBB ? 1 : 0), (temp & I2SR_IAL ? 1 : 0),
			(temp & I2SR_SRW ? 1 : 0), (temp & I2SR_IIF ? 1 : 0),
			(temp & I2SR_RXAK ? 1 : 0));
#endif
		if (msgs[i].flags & I2C_M_RD)
			result = i2c_imx_read(i2c_imx, &msgs[i]);
		else
			result = i2c_imx_write(i2c_imx, &msgs[i]);
		if (result)
			goto fail0;
	}

fail0:
	/* Stop I2C transfer */
	i2c_imx_stop(i2c_imx);

	dev_dbg(&i2c_imx->adapter.dev, "<%s> exit with: %s: %d\n", __func__,
		(result < 0) ? "error" : "success msg",
			(result < 0) ? result : num);
	return (result < 0) ? result : num;
}

static u32 i2c_imx_func(struct i2c_adapter *adapter)
{
	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
}

static struct i2c_algorithm i2c_imx_algo = {
	.master_xfer	= i2c_imx_xfer,
	.functionality	= i2c_imx_func,
};

static int __init i2c_imx_probe(struct platform_device *pdev)
{
	struct imx_i2c_struct *i2c_imx;
	struct resource *res;
	struct imxi2c_platform_data *pdata;
	void __iomem *base;
	resource_size_t res_size;
	int irq;
	int ret;

	dev_dbg(&pdev->dev, "<%s>\n", __func__);

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res) {
		dev_err(&pdev->dev, "can't get device resources\n");
		return -ENOENT;
	}
	irq = platform_get_irq(pdev, 0);
	if (irq < 0) {
		dev_err(&pdev->dev, "can't get irq number\n");
		return -ENOENT;
	}

	pdata = pdev->dev.platform_data;

	if (pdata && pdata->init) {
		ret = pdata->init(&pdev->dev);
		if (ret)
			return ret;
	}

	res_size = resource_size(res);

	if (!request_mem_region(res->start, res_size, DRIVER_NAME)) {
		ret = -EBUSY;
		goto fail0;
	}

	base = ioremap(res->start, res_size);
	if (!base) {
		dev_err(&pdev->dev, "ioremap failed\n");
		ret = -EIO;
		goto fail1;
	}

	i2c_imx = kzalloc(sizeof(struct imx_i2c_struct), GFP_KERNEL);
	if (!i2c_imx) {
		dev_err(&pdev->dev, "can't allocate interface\n");
		ret = -ENOMEM;
		goto fail2;
	}

	/* Setup i2c_imx driver structure */
	strcpy(i2c_imx->adapter.name, pdev->name);
	i2c_imx->adapter.owner		= THIS_MODULE;
	i2c_imx->adapter.algo		= &i2c_imx_algo;
	i2c_imx->adapter.dev.parent	= &pdev->dev;
	i2c_imx->adapter.nr 		= pdev->id;
	i2c_imx->irq			= irq;
	i2c_imx->base			= base;
	i2c_imx->res			= res;

	/* Get I2C clock */
	i2c_imx->clk = clk_get(&pdev->dev, "i2c_clk");
	if (IS_ERR(i2c_imx->clk)) {
		ret = PTR_ERR(i2c_imx->clk);
		dev_err(&pdev->dev, "can't get I2C clock\n");
		goto fail3;
	}

	/* Request IRQ */
	ret = request_irq(i2c_imx->irq, i2c_imx_isr, 0, pdev->name, i2c_imx);
	if (ret) {
		dev_err(&pdev->dev, "can't claim irq %d\n", i2c_imx->irq);
		goto fail4;
	}

	/* Init queue */
	init_waitqueue_head(&i2c_imx->queue);

	/* Set up adapter data */
	i2c_set_adapdata(&i2c_imx->adapter, i2c_imx);

	/* Set up clock divider */
	if (pdata && pdata->bitrate)
		i2c_imx_set_clk(i2c_imx, pdata->bitrate);
	else
		i2c_imx_set_clk(i2c_imx, IMX_I2C_BIT_RATE);

	/* Set up chip registers to defaults */
	writeb(0, i2c_imx->base + IMX_I2C_I2CR);
	writeb(0, i2c_imx->base + IMX_I2C_I2SR);

	/* Add I2C adapter */
	ret = i2c_add_numbered_adapter(&i2c_imx->adapter);
	if (ret < 0) {
		dev_err(&pdev->dev, "registration failed\n");
		goto fail5;
	}

	/* Set up platform driver data */
	platform_set_drvdata(pdev, i2c_imx);

	dev_dbg(&i2c_imx->adapter.dev, "claimed irq %d\n", i2c_imx->irq);
	dev_dbg(&i2c_imx->adapter.dev, "device resources from 0x%x to 0x%x\n",
		i2c_imx->res->start, i2c_imx->res->end);
	dev_dbg(&i2c_imx->adapter.dev, "allocated %d bytes at 0x%x \n",
		res_size, i2c_imx->res->start);
	dev_dbg(&i2c_imx->adapter.dev, "adapter name: \"%s\"\n",
		i2c_imx->adapter.name);
	dev_dbg(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n");

	return 0;   /* Return OK */

fail5:
	free_irq(i2c_imx->irq, i2c_imx);
fail4:
	clk_put(i2c_imx->clk);
fail3:
	kfree(i2c_imx);
fail2:
	iounmap(base);
fail1:
	release_mem_region(res->start, resource_size(res));
fail0:
	if (pdata && pdata->exit)
		pdata->exit(&pdev->dev);
	return ret; /* Return error number */
}

static int __exit i2c_imx_remove(struct platform_device *pdev)
{
	struct imx_i2c_struct *i2c_imx = platform_get_drvdata(pdev);
	struct imxi2c_platform_data *pdata = pdev->dev.platform_data;

	/* remove adapter */
	dev_dbg(&i2c_imx->adapter.dev, "adapter removed\n");
	i2c_del_adapter(&i2c_imx->adapter);
	platform_set_drvdata(pdev, NULL);

	/* free interrupt */
	free_irq(i2c_imx->irq, i2c_imx);

	/* setup chip registers to defaults */
	writeb(0, i2c_imx->base + IMX_I2C_IADR);
	writeb(0, i2c_imx->base + IMX_I2C_IFDR);
	writeb(0, i2c_imx->base + IMX_I2C_I2CR);
	writeb(0, i2c_imx->base + IMX_I2C_I2SR);

	/* Shut down hardware */
	if (pdata && pdata->exit)
		pdata->exit(&pdev->dev);

	clk_put(i2c_imx->clk);

	iounmap(i2c_imx->base);
	release_mem_region(i2c_imx->res->start, resource_size(i2c_imx->res));
	kfree(i2c_imx);
	return 0;
}

static struct platform_driver i2c_imx_driver = {
	.remove		= __exit_p(i2c_imx_remove),
	.driver	= {
		.name	= DRIVER_NAME,
		.owner	= THIS_MODULE,
	}
};

static int __init i2c_adap_imx_init(void)
{
	return platform_driver_probe(&i2c_imx_driver, i2c_imx_probe);
}
subsys_initcall(i2c_adap_imx_init);

static void __exit i2c_adap_imx_exit(void)
{
	platform_driver_unregister(&i2c_imx_driver);
}
module_exit(i2c_adap_imx_exit);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Darius Augulis");
MODULE_DESCRIPTION("I2C adapter driver for IMX I2C bus");
MODULE_ALIAS("platform:" DRIVER_NAME);
Commit	Line	Data
aa11e38c DA	1	/*
	2	* Copyright (C) 2002 Motorola GSG-China
	3	*
	4	* This program is free software; you can redistribute it and/or
	5	* modify it under the terms of the GNU General Public License
	6	* as published by the Free Software Foundation; either version 2
	7	* of the License, or (at your option) any later version.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program; if not, write to the Free Software
	16	* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307,
	17	* USA.
	18	*
	19	* Author:
	20	* Darius Augulis, Teltonika Inc.
	21	*
	22	* Desc.:
	23	* Implementation of I2C Adapter/Algorithm Driver
	24	* for I2C Bus integrated in Freescale i.MX/MXC processors
	25	*
	26	* Derived from Motorola GSG China I2C example driver
	27	*
	28	* Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de
	29	* Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de
	30	* Copyright (C) 2007 RightHand Technologies, Inc.
	31	* Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
	32	*
	33	*/
	34
	35	/ Includes *****************************************************************
	36	*******************************************************************************/
	37
	38	#include <linux/init.h>
	39	#include <linux/kernel.h>
	40	#include <linux/module.h>
	41	#include <linux/errno.h>
	42	#include <linux/err.h>
	43	#include <linux/interrupt.h>
	44	#include <linux/delay.h>
	45	#include <linux/i2c.h>
	46	#include <linux/io.h>
	47	#include <linux/sched.h>
	48	#include <linux/platform_device.h>
	49	#include <linux/clk.h>
5a0e3ad6	50	#include <linux/slab.h>
aa11e38c DA	51
	52	#include <mach/irqs.h>
	53	#include <mach/hardware.h>
	54	#include <mach/i2c.h>
	55
	56	/ Defines ******************************************************************
	57	*******************************************************************************/
	58
	59	/* This will be the driver name the kernel reports */
	60	#define DRIVER_NAME "imx-i2c"
	61
	62	/* Default value */
	63	#define IMX_I2C_BIT_RATE 100000 /* 100kHz */
	64
	65	/* IMX I2C registers */
	66	#define IMX_I2C_IADR 0x00 /* i2c slave address */
	67	#define IMX_I2C_IFDR 0x04 /* i2c frequency divider */
	68	#define IMX_I2C_I2CR 0x08 /* i2c control */
	69	#define IMX_I2C_I2SR 0x0C /* i2c status */
	70	#define IMX_I2C_I2DR 0x10 /* i2c transfer data */
	71
	72	/* Bits of IMX I2C registers */
	73	#define I2SR_RXAK 0x01
	74	#define I2SR_IIF 0x02
	75	#define I2SR_SRW 0x04
	76	#define I2SR_IAL 0x10
	77	#define I2SR_IBB 0x20
	78	#define I2SR_IAAS 0x40
	79	#define I2SR_ICF 0x80
	80	#define I2CR_RSTA 0x04
	81	#define I2CR_TXAK 0x08
	82	#define I2CR_MTX 0x10
	83	#define I2CR_MSTA 0x20
	84	#define I2CR_IIEN 0x40
	85	#define I2CR_IEN 0x80
	86
	87	/ Variables ****************************************************************
	88	*******************************************************************************/
	89
aa11e38c DA	90	/*
	91	* sorted list of clock divider, register value pairs
	92	* taken from table 26-5, p.26-9, Freescale i.MX
	93	* Integrated Portable System Processor Reference Manual
	94	* Document Number: MC9328MXLRM, Rev. 5.1, 06/2007
	95	*
	96	* Duplicated divider values removed from list
	97	*/
	98
	99	static u16 __initdata i2c_clk_div[50][2] = {
	100	{ 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 },
	101	{ 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 },
	102	{ 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 },
	103	{ 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B },
	104	{ 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A },
	105	{ 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 },
	106	{ 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 },
	107	{ 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 },
	108	{ 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 },
	109	{ 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B },
	110	{ 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E },
	111	{ 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
	112	{ 3072, 0x1E }, { 3840, 0x1F }
	113	};
	114
	115	struct imx_i2c_struct {
	116	struct i2c_adapter adapter;
	117	struct resource *res;
	118	struct clk *clk;
	119	void __iomem *base;
	120	int irq;
	121	wait_queue_head_t queue;
	122	unsigned long i2csr;
65de394d	123	unsigned int disable_delay;
43309f3b	124	int stopped;
db3a3d4e	125	unsigned int ifdr; /* IMX_I2C_IFDR */
aa11e38c DA	126	};
	127
	128	/ Functions for IMX I2C adapter driver *************************************
	129	*******************************************************************************/
	130
43309f3b	131	static int i2c_imx_bus_busy(struct imx_i2c_struct *i2c_imx, int for_busy)
aa11e38c DA	132	{
aa11e38c DA	133	unsigned long orig_jiffies = jiffies;
43309f3b	134	unsigned int temp;
aa11e38c DA	135
	136	dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
	137
43309f3b RZ	138	while (1) {
	139	temp = readb(i2c_imx->base + IMX_I2C_I2SR);
	140	if (for_busy && (temp & I2SR_IBB))
	141	break;
	142	if (!for_busy && !(temp & I2SR_IBB))
	143	break;
aa11e38c DA	144	if (signal_pending(current)) {
	145	dev_dbg(&i2c_imx->adapter.dev,
	146	"<%s> I2C Interrupted\n", __func__);
	147	return -EINTR;
	148	}
da9c99fc	149	if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) {
aa11e38c DA	150	dev_dbg(&i2c_imx->adapter.dev,
aa11e38c DA	151	"<%s> I2C bus is busy\n", __func__);
da9c99fc	152	return -ETIMEDOUT;
aa11e38c DA	153	}
	154	schedule();
	155	}
	156
	157	return 0;
	158	}
	159
	160	static int i2c_imx_trx_complete(struct imx_i2c_struct *i2c_imx)
	161	{
e39428d5	162	wait_event_timeout(i2c_imx->queue, i2c_imx->i2csr & I2SR_IIF, HZ / 10);
aa11e38c	163
e39428d5	164	if (unlikely(!(i2c_imx->i2csr & I2SR_IIF))) {
aa11e38c DA	165	dev_dbg(&i2c_imx->adapter.dev, "<%s> Timeout\n", __func__);
	166	return -ETIMEDOUT;
	167	}
	168	dev_dbg(&i2c_imx->adapter.dev, "<%s> TRX complete\n", __func__);
	169	i2c_imx->i2csr = 0;
	170	return 0;
	171	}
	172
	173	static int i2c_imx_acked(struct imx_i2c_struct *i2c_imx)
	174	{
	175	if (readb(i2c_imx->base + IMX_I2C_I2SR) & I2SR_RXAK) {
	176	dev_dbg(&i2c_imx->adapter.dev, "<%s> No ACK\n", __func__);
	177	return -EIO; /* No ACK */
	178	}
	179
	180	dev_dbg(&i2c_imx->adapter.dev, "<%s> ACK received\n", __func__);
	181	return 0;
	182	}
	183
43309f3b	184	static int i2c_imx_start(struct imx_i2c_struct *i2c_imx)
aa11e38c DA	185	{
aa11e38c DA	186	unsigned int temp = 0;
43309f3b	187	int result;
aa11e38c DA	188
	189	dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
	190
db3a3d4e RZ	191	clk_enable(i2c_imx->clk);
db3a3d4e RZ	192	writeb(i2c_imx->ifdr, i2c_imx->base + IMX_I2C_IFDR);
aa11e38c	193	/* Enable I2C controller */
43309f3b	194	writeb(0, i2c_imx->base + IMX_I2C_I2SR);
aa11e38c	195	writeb(I2CR_IEN, i2c_imx->base + IMX_I2C_I2CR);
43309f3b RZ	196
	197	/* Wait controller to be stable */
	198	udelay(50);
	199
aa11e38c DA	200	/* Start I2C transaction */
	201	temp = readb(i2c_imx->base + IMX_I2C_I2CR);
	202	temp \|= I2CR_MSTA;
	203	writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
43309f3b RZ	204	result = i2c_imx_bus_busy(i2c_imx, 1);
	205	if (result)
	206	return result;
	207	i2c_imx->stopped = 0;
	208
aa11e38c DA	209	temp \|= I2CR_IIEN \| I2CR_MTX \| I2CR_TXAK;
aa11e38c DA	210	writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
43309f3b	211	return result;
aa11e38c DA	212	}
	213
	214	static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx)
	215	{
	216	unsigned int temp = 0;
	217
43309f3b RZ	218	if (!i2c_imx->stopped) {
	219	/* Stop I2C transaction */
	220	dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
	221	temp = readb(i2c_imx->base + IMX_I2C_I2CR);
	222	temp &= ~(I2CR_MSTA \| I2CR_MTX);
	223	writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
43309f3b	224	}
a4094a76 RZ	225	if (cpu_is_mx1()) {
	226	/*
	227	* This delay caused by an i.MXL hardware bug.
	228	* If no (or too short) delay, no "STOP" bit will be generated.
	229	*/
	230	udelay(i2c_imx->disable_delay);
	231	}
43309f3b	232
a1ee06b7	233	if (!i2c_imx->stopped) {
43309f3b	234	i2c_imx_bus_busy(i2c_imx, 0);
a1ee06b7 VL	235	i2c_imx->stopped = 1;
a1ee06b7 VL	236	}
43309f3b	237
aa11e38c DA	238	/* Disable I2C controller */
aa11e38c DA	239	writeb(0, i2c_imx->base + IMX_I2C_I2CR);
db3a3d4e	240	clk_disable(i2c_imx->clk);
aa11e38c DA	241	}
	242
	243	static void __init i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx,
	244	unsigned int rate)
	245	{
	246	unsigned int i2c_clk_rate;
	247	unsigned int div;
	248	int i;
	249
	250	/* Divider value calculation */
	251	i2c_clk_rate = clk_get_rate(i2c_imx->clk);
	252	div = (i2c_clk_rate + rate - 1) / rate;
	253	if (div < i2c_clk_div[0][0])
	254	i = 0;
	255	else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1][0])
	256	i = ARRAY_SIZE(i2c_clk_div) - 1;
	257	else
	258	for (i = 0; i2c_clk_div[i][0] < div; i++);
	259
db3a3d4e RZ	260	/* Store divider value */
db3a3d4e RZ	261	i2c_imx->ifdr = i2c_clk_div[i][1];
aa11e38c DA	262
	263	/*
	264	* There dummy delay is calculated.
	265	* It should be about one I2C clock period long.
	266	* This delay is used in I2C bus disable function
	267	* to fix chip hardware bug.
	268	*/
65de394d	269	i2c_imx->disable_delay = (500000U * i2c_clk_div[i][0]
aa11e38c DA	270	+ (i2c_clk_rate / 2) - 1) / (i2c_clk_rate / 2);
	271
	272	/* dev_dbg() can't be used, because adapter is not yet registered */
	273	#ifdef CONFIG_I2C_DEBUG_BUS
	274	printk(KERN_DEBUG "I2C: <%s> I2C_CLK=%d, REQ DIV=%d\n",
	275	__func__, i2c_clk_rate, div);
	276	printk(KERN_DEBUG "I2C: <%s> IFDR[IC]=0x%x, REAL DIV=%d\n",
	277	__func__, i2c_clk_div[i][1], i2c_clk_div[i][0]);
	278	#endif
	279	}
	280
	281	static irqreturn_t i2c_imx_isr(int irq, void *dev_id)
	282	{
	283	struct imx_i2c_struct *i2c_imx = dev_id;
	284	unsigned int temp;
	285
	286	temp = readb(i2c_imx->base + IMX_I2C_I2SR);
	287	if (temp & I2SR_IIF) {
	288	/* save status register */
	289	i2c_imx->i2csr = temp;
	290	temp &= ~I2SR_IIF;
	291	writeb(temp, i2c_imx->base + IMX_I2C_I2SR);
e39428d5	292	wake_up(&i2c_imx->queue);
aa11e38c DA	293	return IRQ_HANDLED;
	294	}
	295
	296	return IRQ_NONE;
	297	}
	298
	299	static int i2c_imx_write(struct imx_i2c_struct i2c_imx, struct i2c_msg msgs)
	300	{
	301	int i, result;
	302
	303	dev_dbg(&i2c_imx->adapter.dev, "<%s> write slave address: addr=0x%x\n",
	304	__func__, msgs->addr << 1);
	305
	306	/* write slave address */
	307	writeb(msgs->addr << 1, i2c_imx->base + IMX_I2C_I2DR);
	308	result = i2c_imx_trx_complete(i2c_imx);
	309	if (result)
	310	return result;
	311	result = i2c_imx_acked(i2c_imx);
	312	if (result)
	313	return result;
	314	dev_dbg(&i2c_imx->adapter.dev, "<%s> write data\n", __func__);
	315
	316	/* write data */
	317	for (i = 0; i < msgs->len; i++) {
	318	dev_dbg(&i2c_imx->adapter.dev,
	319	"<%s> write byte: B%d=0x%X\n",
	320	__func__, i, msgs->buf[i]);
	321	writeb(msgs->buf[i], i2c_imx->base + IMX_I2C_I2DR);
	322	result = i2c_imx_trx_complete(i2c_imx);
	323	if (result)
	324	return result;
	325	result = i2c_imx_acked(i2c_imx);
	326	if (result)
	327	return result;
	328	}
	329	return 0;
	330	}
	331
	332	static int i2c_imx_read(struct imx_i2c_struct i2c_imx, struct i2c_msg msgs)
	333	{
	334	int i, result;
	335	unsigned int temp;
	336
	337	dev_dbg(&i2c_imx->adapter.dev,
	338	"<%s> write slave address: addr=0x%x\n",
	339	__func__, (msgs->addr << 1) \| 0x01);
	340
	341	/* write slave address */
	342	writeb((msgs->addr << 1) \| 0x01, i2c_imx->base + IMX_I2C_I2DR);
	343	result = i2c_imx_trx_complete(i2c_imx);
	344	if (result)
	345	return result;
	346	result = i2c_imx_acked(i2c_imx);
	347	if (result)
	348	return result;
	349
	350	dev_dbg(&i2c_imx->adapter.dev, "<%s> setup bus\n", __func__);
	351
	352	/* setup bus to read data */
	353	temp = readb(i2c_imx->base + IMX_I2C_I2CR);
	354	temp &= ~I2CR_MTX;
	355	if (msgs->len - 1)
	356	temp &= ~I2CR_TXAK;
357	writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
358	readb(i2c_imx->base + IMX_I2C_I2DR); /* dummy read */
359
360	dev_dbg(&i2c_imx->adapter.dev, "<%s> read data\n", __func__);
361
362	/* read data */
363	for (i = 0; i < msgs->len; i++) {
364	result = i2c_imx_trx_complete(i2c_imx);
365	if (result)
366	return result;
367	if (i == (msgs->len - 1)) {
43309f3b RZ	368	/* It must generate STOP before read I2DR to prevent
43309f3b RZ	369	controller from generating another clock cycle */
aa11e38c DA	370	dev_dbg(&i2c_imx->adapter.dev,
	371	"<%s> clear MSTA\n", __func__);
	372	temp = readb(i2c_imx->base + IMX_I2C_I2CR);
43309f3b	373	temp &= ~(I2CR_MSTA \| I2CR_MTX);
aa11e38c	374	writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
43309f3b RZ	375	i2c_imx_bus_busy(i2c_imx, 0);
43309f3b RZ	376	i2c_imx->stopped = 1;
aa11e38c DA	377	} else if (i == (msgs->len - 2)) {
	378	dev_dbg(&i2c_imx->adapter.dev,
	379	"<%s> set TXAK\n", __func__);
	380	temp = readb(i2c_imx->base + IMX_I2C_I2CR);
	381	temp \|= I2CR_TXAK;
	382	writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
	383	}
	384	msgs->buf[i] = readb(i2c_imx->base + IMX_I2C_I2DR);
	385	dev_dbg(&i2c_imx->adapter.dev,
	386	"<%s> read byte: B%d=0x%X\n",
	387	__func__, i, msgs->buf[i]);
	388	}
	389	return 0;
	390	}
	391
	392	static int i2c_imx_xfer(struct i2c_adapter *adapter,
	393	struct i2c_msg *msgs, int num)
	394	{
	395	unsigned int i, temp;
	396	int result;
	397	struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter);
	398
	399	dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
	400
43309f3b RZ	401	/* Start I2C transfer */
43309f3b RZ	402	result = i2c_imx_start(i2c_imx);
aa11e38c DA	403	if (result)
	404	goto fail0;
	405
aa11e38c DA	406	/* read/write data */
	407	for (i = 0; i < num; i++) {
	408	if (i) {
	409	dev_dbg(&i2c_imx->adapter.dev,
	410	"<%s> repeated start\n", __func__);
	411	temp = readb(i2c_imx->base + IMX_I2C_I2CR);
	412	temp \|= I2CR_RSTA;
	413	writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
43309f3b RZ	414	result = i2c_imx_bus_busy(i2c_imx, 1);
	415	if (result)
	416	goto fail0;
aa11e38c DA	417	}
	418	dev_dbg(&i2c_imx->adapter.dev,
	419	"<%s> transfer message: %d\n", __func__, i);
	420	/* write/read data */
	421	#ifdef CONFIG_I2C_DEBUG_BUS
	422	temp = readb(i2c_imx->base + IMX_I2C_I2CR);
	423	dev_dbg(&i2c_imx->adapter.dev, "<%s> CONTROL: IEN=%d, IIEN=%d, "
	424	"MSTA=%d, MTX=%d, TXAK=%d, RSTA=%d\n", __func__,
	425	(temp & I2CR_IEN ? 1 : 0), (temp & I2CR_IIEN ? 1 : 0),
	426	(temp & I2CR_MSTA ? 1 : 0), (temp & I2CR_MTX ? 1 : 0),
	427	(temp & I2CR_TXAK ? 1 : 0), (temp & I2CR_RSTA ? 1 : 0));
	428	temp = readb(i2c_imx->base + IMX_I2C_I2SR);
	429	dev_dbg(&i2c_imx->adapter.dev,
	430	"<%s> STATUS: ICF=%d, IAAS=%d, IBB=%d, "
	431	"IAL=%d, SRW=%d, IIF=%d, RXAK=%d\n", __func__,
	432	(temp & I2SR_ICF ? 1 : 0), (temp & I2SR_IAAS ? 1 : 0),
	433	(temp & I2SR_IBB ? 1 : 0), (temp & I2SR_IAL ? 1 : 0),
	434	(temp & I2SR_SRW ? 1 : 0), (temp & I2SR_IIF ? 1 : 0),
	435	(temp & I2SR_RXAK ? 1 : 0));
	436	#endif
	437	if (msgs[i].flags & I2C_M_RD)
	438	result = i2c_imx_read(i2c_imx, &msgs[i]);
	439	else
	440	result = i2c_imx_write(i2c_imx, &msgs[i]);
da9c99fc AP	441	if (result)
da9c99fc AP	442	goto fail0;
aa11e38c DA	443	}
	444
	445	fail0:
	446	/* Stop I2C transfer */
	447	i2c_imx_stop(i2c_imx);
	448
	449	dev_dbg(&i2c_imx->adapter.dev, "<%s> exit with: %s: %d\n", __func__,
	450	(result < 0) ? "error" : "success msg",
	451	(result < 0) ? result : num);
	452	return (result < 0) ? result : num;
	453	}
	454
	455	static u32 i2c_imx_func(struct i2c_adapter *adapter)
	456	{
	457	return I2C_FUNC_I2C \| I2C_FUNC_SMBUS_EMUL;
	458	}
	459
	460	static struct i2c_algorithm i2c_imx_algo = {
	461	.master_xfer = i2c_imx_xfer,
	462	.functionality = i2c_imx_func,
	463	};
	464
	465	static int __init i2c_imx_probe(struct platform_device *pdev)
	466	{
	467	struct imx_i2c_struct *i2c_imx;
	468	struct resource *res;
	469	struct imxi2c_platform_data *pdata;
	470	void __iomem *base;
	471	resource_size_t res_size;
	472	int irq;
	473	int ret;
	474
	475	dev_dbg(&pdev->dev, "<%s>\n", __func__);
	476
	477	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	478	if (!res) {
	479	dev_err(&pdev->dev, "can't get device resources\n");
	480	return -ENOENT;
	481	}
	482	irq = platform_get_irq(pdev, 0);
	483	if (irq < 0) {
	484	dev_err(&pdev->dev, "can't get irq number\n");
	485	return -ENOENT;
	486	}
	487
	488	pdata = pdev->dev.platform_data;
	489
	490	if (pdata && pdata->init) {
	491	ret = pdata->init(&pdev->dev);
	492	if (ret)
	493	return ret;
	494	}
	495
	496	res_size = resource_size(res);
4927fbf1 UKK	497
	498	if (!request_mem_region(res->start, res_size, DRIVER_NAME)) {
	499	ret = -EBUSY;
	500	goto fail0;
	501	}
	502
aa11e38c DA	503	base = ioremap(res->start, res_size);
	504	if (!base) {
	505	dev_err(&pdev->dev, "ioremap failed\n");
	506	ret = -EIO;
4927fbf1	507	goto fail1;
aa11e38c DA	508	}
	509
	510	i2c_imx = kzalloc(sizeof(struct imx_i2c_struct), GFP_KERNEL);
	511	if (!i2c_imx) {
	512	dev_err(&pdev->dev, "can't allocate interface\n");
	513	ret = -ENOMEM;
309c18d2 DA	514	goto fail2;
	515	}
	516
aa11e38c DA	517	/* Setup i2c_imx driver structure */
	518	strcpy(i2c_imx->adapter.name, pdev->name);
	519	i2c_imx->adapter.owner = THIS_MODULE;
	520	i2c_imx->adapter.algo = &i2c_imx_algo;
	521	i2c_imx->adapter.dev.parent = &pdev->dev;
	522	i2c_imx->adapter.nr = pdev->id;
	523	i2c_imx->irq = irq;
	524	i2c_imx->base = base;
	525	i2c_imx->res = res;
	526
	527	/* Get I2C clock */
	528	i2c_imx->clk = clk_get(&pdev->dev, "i2c_clk");
	529	if (IS_ERR(i2c_imx->clk)) {
	530	ret = PTR_ERR(i2c_imx->clk);
	531	dev_err(&pdev->dev, "can't get I2C clock\n");
309c18d2	532	goto fail3;
aa11e38c	533	}
aa11e38c DA	534
	535	/* Request IRQ */
	536	ret = request_irq(i2c_imx->irq, i2c_imx_isr, 0, pdev->name, i2c_imx);
	537	if (ret) {
	538	dev_err(&pdev->dev, "can't claim irq %d\n", i2c_imx->irq);
309c18d2	539	goto fail4;
aa11e38c DA	540	}
	541
	542	/* Init queue */
	543	init_waitqueue_head(&i2c_imx->queue);
	544
	545	/* Set up adapter data */
	546	i2c_set_adapdata(&i2c_imx->adapter, i2c_imx);
	547
	548	/* Set up clock divider */
	549	if (pdata && pdata->bitrate)
	550	i2c_imx_set_clk(i2c_imx, pdata->bitrate);
	551	else
	552	i2c_imx_set_clk(i2c_imx, IMX_I2C_BIT_RATE);
	553
	554	/* Set up chip registers to defaults */
	555	writeb(0, i2c_imx->base + IMX_I2C_I2CR);
	556	writeb(0, i2c_imx->base + IMX_I2C_I2SR);
	557
	558	/* Add I2C adapter */
	559	ret = i2c_add_numbered_adapter(&i2c_imx->adapter);
	560	if (ret < 0) {
	561	dev_err(&pdev->dev, "registration failed\n");
309c18d2	562	goto fail5;
aa11e38c DA	563	}
	564
	565	/* Set up platform driver data */
	566	platform_set_drvdata(pdev, i2c_imx);
	567
	568	dev_dbg(&i2c_imx->adapter.dev, "claimed irq %d\n", i2c_imx->irq);
	569	dev_dbg(&i2c_imx->adapter.dev, "device resources from 0x%x to 0x%x\n",
	570	i2c_imx->res->start, i2c_imx->res->end);
	571	dev_dbg(&i2c_imx->adapter.dev, "allocated %d bytes at 0x%x \n",
	572	res_size, i2c_imx->res->start);
	573	dev_dbg(&i2c_imx->adapter.dev, "adapter name: \"%s\"\n",
	574	i2c_imx->adapter.name);
	575	dev_dbg(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n");
	576
	577	return 0; /* Return OK */
	578
309c18d2	579	fail5:
aa11e38c	580	free_irq(i2c_imx->irq, i2c_imx);
309c18d2	581	fail4:
aa11e38c	582	clk_put(i2c_imx->clk);
309c18d2	583	fail3:
aa11e38c	584	kfree(i2c_imx);
4927fbf1	585	fail2:
aa11e38c	586	iounmap(base);
4927fbf1 UKK	587	fail1:
4927fbf1 UKK	588	release_mem_region(res->start, resource_size(res));
aa11e38c DA	589	fail0:
	590	if (pdata && pdata->exit)
	591	pdata->exit(&pdev->dev);
	592	return ret; /* Return error number */
	593	}
	594
	595	static int __exit i2c_imx_remove(struct platform_device *pdev)
	596	{
	597	struct imx_i2c_struct *i2c_imx = platform_get_drvdata(pdev);
	598	struct imxi2c_platform_data *pdata = pdev->dev.platform_data;
	599
	600	/* remove adapter */
	601	dev_dbg(&i2c_imx->adapter.dev, "adapter removed\n");
	602	i2c_del_adapter(&i2c_imx->adapter);
	603	platform_set_drvdata(pdev, NULL);
	604
	605	/* free interrupt */
	606	free_irq(i2c_imx->irq, i2c_imx);
	607
	608	/* setup chip registers to defaults */
	609	writeb(0, i2c_imx->base + IMX_I2C_IADR);
	610	writeb(0, i2c_imx->base + IMX_I2C_IFDR);
	611	writeb(0, i2c_imx->base + IMX_I2C_I2CR);
	612	writeb(0, i2c_imx->base + IMX_I2C_I2SR);
	613
	614	/* Shut down hardware */
	615	if (pdata && pdata->exit)
	616	pdata->exit(&pdev->dev);
	617
aa11e38c DA	618	clk_put(i2c_imx->clk);
	619
	620	iounmap(i2c_imx->base);
4927fbf1	621	release_mem_region(i2c_imx->res->start, resource_size(i2c_imx->res));
aa11e38c DA	622	kfree(i2c_imx);
	623	return 0;
	624	}
	625
	626	static struct platform_driver i2c_imx_driver = {
aa11e38c DA	627	.remove = __exit_p(i2c_imx_remove),
	628	.driver = {
	629	.name = DRIVER_NAME,
	630	.owner = THIS_MODULE,
	631	}
	632	};
	633
	634	static int __init i2c_adap_imx_init(void)
	635	{
	636	return platform_driver_probe(&i2c_imx_driver, i2c_imx_probe);
	637	}
5d3f3331	638	subsys_initcall(i2c_adap_imx_init);
aa11e38c DA	639
	640	static void __exit i2c_adap_imx_exit(void)
	641	{
	642	platform_driver_unregister(&i2c_imx_driver);
	643	}
aa11e38c DA	644	module_exit(i2c_adap_imx_exit);
	645
	646	MODULE_LICENSE("GPL");
	647	MODULE_AUTHOR("Darius Augulis");
	648	MODULE_DESCRIPTION("I2C adapter driver for IMX I2C bus");
	649	MODULE_ALIAS("platform:" DRIVER_NAME);