]> bbs.cooldavid.org Git - net-next-2.6.git/blame - drivers/i2c/busses/i2c-i801.c
git://bbs.cooldavid.org / net-next-2.6.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/penberg...
[net-next-2.6.git] / drivers / i2c / busses / i2c-i801.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>,
3 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
4 <mdsxyz123@yahoo.com>
cf898dc5 5 Copyright (C) 2007, 2008 Jean Delvare <khali@linux-fr.org>
1da177e4
LT		 6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20*/
21
22/*
ae7b0497
JD		 23 Supports the following Intel I/O Controller Hubs (ICH):
24
25 I/O Block I2C
26 region SMBus Block proc. block
27 Chip name PCI ID size PEC buffer call read
28 ----------------------------------------------------------------------
29 82801AA (ICH) 0x2413 16 no no no no
30 82801AB (ICH0) 0x2423 16 no no no no
31 82801BA (ICH2) 0x2443 16 no no no no
32 82801CA (ICH3) 0x2483 32 soft no no no
33 82801DB (ICH4) 0x24c3 32 hard yes no no
34 82801E (ICH5) 0x24d3 32 hard yes yes yes
35 6300ESB 0x25a4 32 hard yes yes yes
36 82801F (ICH6) 0x266a 32 hard yes yes yes
37 6310ESB/6320ESB 0x269b 32 hard yes yes yes
38 82801G (ICH7) 0x27da 32 hard yes yes yes
39 82801H (ICH8) 0x283e 32 hard yes yes yes
40 82801I (ICH9) 0x2930 32 hard yes yes yes
d28dc711
GJ		 41 Tolapai 0x5032 32 hard yes yes yes
42 ICH10 0x3a30 32 hard yes yes yes
43 ICH10 0x3a60 32 hard yes yes yes
c429a247 44 PCH 0x3b30 32 hard yes yes yes
ae7b0497
JD		 45
46 Features supported by this driver:
47 Software PEC no
48 Hardware PEC yes
49 Block buffer yes
50 Block process call transaction no
6342064c 51 I2C block read transaction yes (doesn't use the block buffer)
ae7b0497
JD		 52
53 See the file Documentation/i2c/busses/i2c-i801 for details.
1da177e4
LT		 54*/
55
56/* Note: we assume there can only be one I801, with one SMBus interface */
57
1da177e4
LT		 58#include <linux/module.h>
59#include <linux/pci.h>
60#include <linux/kernel.h>
61#include <linux/stddef.h>
62#include <linux/delay.h>
1da177e4
LT		 63#include <linux/ioport.h>
64#include <linux/init.h>
65#include <linux/i2c.h>
54fb4a05 66#include <linux/acpi.h>
1561bfe5 67#include <linux/io.h>
1da177e4 68
1da177e4
LT		 69/* I801 SMBus address offsets */
70#define SMBHSTSTS (0 + i801_smba)
71#define SMBHSTCNT (2 + i801_smba)
72#define SMBHSTCMD (3 + i801_smba)
73#define SMBHSTADD (4 + i801_smba)
74#define SMBHSTDAT0 (5 + i801_smba)
75#define SMBHSTDAT1 (6 + i801_smba)
76#define SMBBLKDAT (7 + i801_smba)
ae7b0497
JD		 77#define SMBPEC (8 + i801_smba) /* ICH3 and later */
78#define SMBAUXSTS (12 + i801_smba) /* ICH4 and later */
79#define SMBAUXCTL (13 + i801_smba) /* ICH4 and later */
1da177e4
LT		 80
81/* PCI Address Constants */
6dcc19df 82#define SMBBAR 4
1da177e4 83#define SMBHSTCFG 0x040
1da177e4
LT		 84
85/* Host configuration bits for SMBHSTCFG */
86#define SMBHSTCFG_HST_EN 1
87#define SMBHSTCFG_SMB_SMI_EN 2
88#define SMBHSTCFG_I2C_EN 4
89
ca8b9e32
OR		 90/* Auxillary control register bits, ICH4+ only */
91#define SMBAUXCTL_CRC 1
92#define SMBAUXCTL_E32B 2
93
94/* kill bit for SMBHSTCNT */
95#define SMBHSTCNT_KILL 2
96
1da177e4
LT		 97/* Other settings */
98#define MAX_TIMEOUT 100
99#define ENABLE_INT9 0 /* set to 0x01 to enable - untested */
100
101/* I801 command constants */
102#define I801_QUICK 0x00
103#define I801_BYTE 0x04
104#define I801_BYTE_DATA 0x08
105#define I801_WORD_DATA 0x0C
ae7b0497 106#define I801_PROC_CALL 0x10 /* unimplemented */
1da177e4 107#define I801_BLOCK_DATA 0x14
6342064c 108#define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */
1da177e4 109#define I801_BLOCK_LAST 0x34
6342064c 110#define I801_I2C_BLOCK_LAST 0x38 /* ICH5 and later */
1da177e4 111#define I801_START 0x40
ae7b0497 112#define I801_PEC_EN 0x80 /* ICH3 and later */
1da177e4 113
ca8b9e32
OR		 114/* I801 Hosts Status register bits */
115#define SMBHSTSTS_BYTE_DONE 0x80
116#define SMBHSTSTS_INUSE_STS 0x40
117#define SMBHSTSTS_SMBALERT_STS 0x20
118#define SMBHSTSTS_FAILED 0x10
119#define SMBHSTSTS_BUS_ERR 0x08
120#define SMBHSTSTS_DEV_ERR 0x04
121#define SMBHSTSTS_INTR 0x02
122#define SMBHSTSTS_HOST_BUSY 0x01
1da177e4 123
cf898dc5
JD		 124#define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_FAILED | \
125 SMBHSTSTS_BUS_ERR | SMBHSTSTS_DEV_ERR | \
126 SMBHSTSTS_INTR)
127
6dcc19df 128static unsigned long i801_smba;
a5aaea37 129static unsigned char i801_original_hstcfg;
d6072f84 130static struct pci_driver i801_driver;
1da177e4 131static struct pci_dev *I801_dev;
369f6f4a
JD		 132
133#define FEATURE_SMBUS_PEC (1 << 0)
134#define FEATURE_BLOCK_BUFFER (1 << 1)
135#define FEATURE_BLOCK_PROC (1 << 2)
136#define FEATURE_I2C_BLOCK_READ (1 << 3)
137static unsigned int i801_features;
1da177e4 138
cf898dc5
JD		 139/* Make sure the SMBus host is ready to start transmitting.
140 Return 0 if it is, -EBUSY if it is not. */
141static int i801_check_pre(void)
1da177e4 142{
2b73809d 143 int status;
1da177e4 144
cf898dc5
JD		 145 status = inb_p(SMBHSTSTS);
146 if (status & SMBHSTSTS_HOST_BUSY) {
147 dev_err(&I801_dev->dev, "SMBus is busy, can't use it!\n");
148 return -EBUSY;
149 }
150
151 status &= STATUS_FLAGS;
152 if (status) {
153 dev_dbg(&I801_dev->dev, "Clearing status flags (%02x)\n",
2b73809d
JD		 154 status);
155 outb_p(status, SMBHSTSTS);
cf898dc5
JD		 156 status = inb_p(SMBHSTSTS) & STATUS_FLAGS;
157 if (status) {
158 dev_err(&I801_dev->dev,
159 "Failed clearing status flags (%02x)\n",
160 status);
97140342 161 return -EBUSY;
1da177e4
LT		 162 }
163 }
164
cf898dc5
JD		 165 return 0;
166}
1da177e4 167
cf898dc5
JD		 168/* Convert the status register to an error code, and clear it. */
169static int i801_check_post(int status, int timeout)
170{
171 int result = 0;
1da177e4
LT		 172
173 /* If the SMBus is still busy, we give up */
cf898dc5
JD		 174 if (timeout) {
175 dev_err(&I801_dev->dev, "Transaction timeout\n");
ca8b9e32
OR		 176 /* try to stop the current command */
177 dev_dbg(&I801_dev->dev, "Terminating the current operation\n");
178 outb_p(inb_p(SMBHSTCNT) | SMBHSTCNT_KILL, SMBHSTCNT);
179 msleep(1);
180 outb_p(inb_p(SMBHSTCNT) & (~SMBHSTCNT_KILL), SMBHSTCNT);
cf898dc5
JD		 181
182 /* Check if it worked */
183 status = inb_p(SMBHSTSTS);
184 if ((status & SMBHSTSTS_HOST_BUSY) ||
185 !(status & SMBHSTSTS_FAILED))
186 dev_err(&I801_dev->dev,
187 "Failed terminating the transaction\n");
188 outb_p(STATUS_FLAGS, SMBHSTSTS);
189 return -ETIMEDOUT;
1da177e4
LT		 190 }
191
2b73809d 192 if (status & SMBHSTSTS_FAILED) {
97140342 193 result = -EIO;
cf898dc5
JD		 194 dev_err(&I801_dev->dev, "Transaction failed\n");
195 }
196 if (status & SMBHSTSTS_DEV_ERR) {
197 result = -ENXIO;
198 dev_dbg(&I801_dev->dev, "No response\n");
1da177e4 199 }
2b73809d 200 if (status & SMBHSTSTS_BUS_ERR) {
dcb5c923
JD		 201 result = -EAGAIN;
202 dev_dbg(&I801_dev->dev, "Lost arbitration\n");
1da177e4
LT		 203 }
204
cf898dc5
JD		 205 if (result) {
206 /* Clear error flags */
207 outb_p(status & STATUS_FLAGS, SMBHSTSTS);
208 status = inb_p(SMBHSTSTS) & STATUS_FLAGS;
209 if (status) {
210 dev_warn(&I801_dev->dev, "Failed clearing status "
211 "flags at end of transaction (%02x)\n",
212 status);
213 }
1da177e4
LT		 214 }
215
1da177e4
LT		 216 return result;
217}
218
cf898dc5
JD		 219static int i801_transaction(int xact)
220{
221 int status;
222 int result;
223 int timeout = 0;
224
225 result = i801_check_pre();
226 if (result < 0)
227 return result;
228
229 /* the current contents of SMBHSTCNT can be overwritten, since PEC,
230 * INTREN, SMBSCMD are passed in xact */
231 outb_p(xact | I801_START, SMBHSTCNT);
232
233 /* We will always wait for a fraction of a second! */
234 do {
235 msleep(1);
236 status = inb_p(SMBHSTSTS);
237 } while ((status & SMBHSTSTS_HOST_BUSY) && (timeout++ < MAX_TIMEOUT));
238
239 result = i801_check_post(status, timeout >= MAX_TIMEOUT);
240 if (result < 0)
241 return result;
242
243 outb_p(SMBHSTSTS_INTR, SMBHSTSTS);
244 return 0;
245}
246
ca8b9e32
OR		 247/* wait for INTR bit as advised by Intel */
248static void i801_wait_hwpec(void)
249{
250 int timeout = 0;
2b73809d 251 int status;
ca8b9e32
OR		 252
253 do {
254 msleep(1);
2b73809d
JD		 255 status = inb_p(SMBHSTSTS);
256 } while ((!(status & SMBHSTSTS_INTR))
ca8b9e32
OR		 257 && (timeout++ < MAX_TIMEOUT));
258
259 if (timeout >= MAX_TIMEOUT) {
260 dev_dbg(&I801_dev->dev, "PEC Timeout!\n");
261 }
2b73809d 262 outb_p(status, SMBHSTSTS);
ca8b9e32
OR		 263}
264
7edcb9ab
OR		 265static int i801_block_transaction_by_block(union i2c_smbus_data *data,
266 char read_write, int hwpec)
267{
268 int i, len;
97140342 269 int status;
7edcb9ab
OR		 270
271 inb_p(SMBHSTCNT); /* reset the data buffer index */
272
273 /* Use 32-byte buffer to process this transaction */
274 if (read_write == I2C_SMBUS_WRITE) {
275 len = data->block[0];
276 outb_p(len, SMBHSTDAT0);
277 for (i = 0; i < len; i++)
278 outb_p(data->block[i+1], SMBBLKDAT);
279 }
280
97140342
DB		 281 status = i801_transaction(I801_BLOCK_DATA | ENABLE_INT9 |
282 I801_PEC_EN * hwpec);
283 if (status)
284 return status;
7edcb9ab
OR		 285
286 if (read_write == I2C_SMBUS_READ) {
287 len = inb_p(SMBHSTDAT0);
288 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
97140342 289 return -EPROTO;
7edcb9ab
OR		 290
291 data->block[0] = len;
292 for (i = 0; i < len; i++)
293 data->block[i + 1] = inb_p(SMBBLKDAT);
294 }
295 return 0;
296}
297
298static int i801_block_transaction_byte_by_byte(union i2c_smbus_data *data,
6342064c
JD		 299 char read_write, int command,
300 int hwpec)
1da177e4
LT		 301{
302 int i, len;
303 int smbcmd;
2b73809d 304 int status;
cf898dc5 305 int result;
1da177e4 306 int timeout;
cf898dc5
JD		 307
308 result = i801_check_pre();
309 if (result < 0)
310 return result;
1da177e4 311
7edcb9ab 312 len = data->block[0];
1da177e4
LT		 313
314 if (read_write == I2C_SMBUS_WRITE) {
1da177e4
LT		 315 outb_p(len, SMBHSTDAT0);
316 outb_p(data->block[1], SMBBLKDAT);
1da177e4
LT		 317 }
318
319 for (i = 1; i <= len; i++) {
6342064c
JD		 320 if (i == len && read_write == I2C_SMBUS_READ) {
321 if (command == I2C_SMBUS_I2C_BLOCK_DATA)
322 smbcmd = I801_I2C_BLOCK_LAST;
323 else
324 smbcmd = I801_BLOCK_LAST;
325 } else {
326 if (command == I2C_SMBUS_I2C_BLOCK_DATA
327 && read_write == I2C_SMBUS_READ)
328 smbcmd = I801_I2C_BLOCK_DATA;
329 else
330 smbcmd = I801_BLOCK_DATA;
331 }
1da177e4
LT		 332 outb_p(smbcmd | ENABLE_INT9, SMBHSTCNT);
333
1da177e4
LT		 334 if (i == 1)
335 outb_p(inb(SMBHSTCNT) | I801_START, SMBHSTCNT);
336
337 /* We will always wait for a fraction of a second! */
338 timeout = 0;
339 do {
1da177e4 340 msleep(1);
2b73809d 341 status = inb_p(SMBHSTSTS);
1da177e4 342 }
2b73809d 343 while ((!(status & SMBHSTSTS_BYTE_DONE))
ca8b9e32 344 && (timeout++ < MAX_TIMEOUT));
1da177e4 345
cf898dc5
JD		 346 result = i801_check_post(status, timeout >= MAX_TIMEOUT);
347 if (result < 0)
348 return result;
1da177e4 349
6342064c
JD		 350 if (i == 1 && read_write == I2C_SMBUS_READ
351 && command != I2C_SMBUS_I2C_BLOCK_DATA) {
1da177e4 352 len = inb_p(SMBHSTDAT0);
cf898dc5
JD		 353 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
354 dev_err(&I801_dev->dev,
355 "Illegal SMBus block read size %d\n",
356 len);
357 /* Recover */
358 while (inb_p(SMBHSTSTS) & SMBHSTSTS_HOST_BUSY)
359 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS);
360 outb_p(SMBHSTSTS_INTR, SMBHSTSTS);
97140342 361 return -EPROTO;
cf898dc5 362 }
1da177e4
LT		 363 data->block[0] = len;
364 }
365
366 /* Retrieve/store value in SMBBLKDAT */
367 if (read_write == I2C_SMBUS_READ)
368 data->block[i] = inb_p(SMBBLKDAT);
369 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
370 outb_p(data->block[i+1], SMBBLKDAT);
1da177e4 371
cf898dc5
JD		 372 /* signals SMBBLKDAT ready */
373 outb_p(SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR, SMBHSTSTS);
1da177e4 374 }
cf898dc5
JD		 375
376 return 0;
7edcb9ab 377}
1da177e4 378
7edcb9ab
OR		 379static int i801_set_block_buffer_mode(void)
380{
381 outb_p(inb_p(SMBAUXCTL) | SMBAUXCTL_E32B, SMBAUXCTL);
382 if ((inb_p(SMBAUXCTL) & SMBAUXCTL_E32B) == 0)
97140342 383 return -EIO;
7edcb9ab
OR		 384 return 0;
385}
386
387/* Block transaction function */
388static int i801_block_transaction(union i2c_smbus_data *data, char read_write,
389 int command, int hwpec)
390{
391 int result = 0;
392 unsigned char hostc;
393
394 if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
395 if (read_write == I2C_SMBUS_WRITE) {
396 /* set I2C_EN bit in configuration register */
397 pci_read_config_byte(I801_dev, SMBHSTCFG, &hostc);
398 pci_write_config_byte(I801_dev, SMBHSTCFG,
399 hostc | SMBHSTCFG_I2C_EN);
6342064c 400 } else if (!(i801_features & FEATURE_I2C_BLOCK_READ)) {
7edcb9ab 401 dev_err(&I801_dev->dev,
6342064c 402 "I2C block read is unsupported!\n");
97140342 403 return -EOPNOTSUPP;
7edcb9ab
OR		 404 }
405 }
406
6342064c
JD		 407 if (read_write == I2C_SMBUS_WRITE
408 || command == I2C_SMBUS_I2C_BLOCK_DATA) {
7edcb9ab
OR		 409 if (data->block[0] < 1)
410 data->block[0] = 1;
411 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
412 data->block[0] = I2C_SMBUS_BLOCK_MAX;
413 } else {
6342064c 414 data->block[0] = 32; /* max for SMBus block reads */
7edcb9ab
OR		 415 }
416
369f6f4a 417 if ((i801_features & FEATURE_BLOCK_BUFFER)
6342064c
JD		 418 && !(command == I2C_SMBUS_I2C_BLOCK_DATA
419 && read_write == I2C_SMBUS_READ)
369f6f4a 420 && i801_set_block_buffer_mode() == 0)
7edcb9ab
OR		 421 result = i801_block_transaction_by_block(data, read_write,
422 hwpec);
423 else
424 result = i801_block_transaction_byte_by_byte(data, read_write,
6342064c 425 command, hwpec);
7edcb9ab
OR		 426
427 if (result == 0 && hwpec)
ca8b9e32 428 i801_wait_hwpec();
1da177e4 429
6342064c
JD		 430 if (command == I2C_SMBUS_I2C_BLOCK_DATA
431 && read_write == I2C_SMBUS_WRITE) {
1da177e4
LT		 432 /* restore saved configuration register value */
433 pci_write_config_byte(I801_dev, SMBHSTCFG, hostc);
434 }
435 return result;
436}
437
97140342 438/* Return negative errno on error. */
1da177e4
LT		 439static s32 i801_access(struct i2c_adapter * adap, u16 addr,
440 unsigned short flags, char read_write, u8 command,
441 int size, union i2c_smbus_data * data)
442{
e8aac4a9 443 int hwpec;
1da177e4
LT		 444 int block = 0;
445 int ret, xact = 0;
446
369f6f4a 447 hwpec = (i801_features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
e8aac4a9
JD		 448 && size != I2C_SMBUS_QUICK
449 && size != I2C_SMBUS_I2C_BLOCK_DATA;
1da177e4
LT		 450
451 switch (size) {
452 case I2C_SMBUS_QUICK:
453 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
454 SMBHSTADD);
455 xact = I801_QUICK;
456 break;
457 case I2C_SMBUS_BYTE:
458 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
459 SMBHSTADD);
460 if (read_write == I2C_SMBUS_WRITE)
461 outb_p(command, SMBHSTCMD);
462 xact = I801_BYTE;
463 break;
464 case I2C_SMBUS_BYTE_DATA:
465 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
466 SMBHSTADD);
467 outb_p(command, SMBHSTCMD);
468 if (read_write == I2C_SMBUS_WRITE)
469 outb_p(data->byte, SMBHSTDAT0);
470 xact = I801_BYTE_DATA;
471 break;
472 case I2C_SMBUS_WORD_DATA:
473 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
474 SMBHSTADD);
475 outb_p(command, SMBHSTCMD);
476 if (read_write == I2C_SMBUS_WRITE) {
477 outb_p(data->word & 0xff, SMBHSTDAT0);
478 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1);
479 }
480 xact = I801_WORD_DATA;
481 break;
482 case I2C_SMBUS_BLOCK_DATA:
1da177e4
LT		 483 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
484 SMBHSTADD);
485 outb_p(command, SMBHSTCMD);
486 block = 1;
487 break;
6342064c
JD		 488 case I2C_SMBUS_I2C_BLOCK_DATA:
489 /* NB: page 240 of ICH5 datasheet shows that the R/#W
490 * bit should be cleared here, even when reading */
491 outb_p((addr & 0x7f) << 1, SMBHSTADD);
492 if (read_write == I2C_SMBUS_READ) {
493 /* NB: page 240 of ICH5 datasheet also shows
494 * that DATA1 is the cmd field when reading */
495 outb_p(command, SMBHSTDAT1);
496 } else
497 outb_p(command, SMBHSTCMD);
498 block = 1;
499 break;
1da177e4
LT		 500 default:
501 dev_err(&I801_dev->dev, "Unsupported transaction %d\n", size);
97140342 502 return -EOPNOTSUPP;
1da177e4
LT		 503 }
504
ca8b9e32
OR		 505 if (hwpec) /* enable/disable hardware PEC */
506 outb_p(inb_p(SMBAUXCTL) | SMBAUXCTL_CRC, SMBAUXCTL);
507 else
508 outb_p(inb_p(SMBAUXCTL) & (~SMBAUXCTL_CRC), SMBAUXCTL);
e8aac4a9 509
1da177e4 510 if(block)
585b3160 511 ret = i801_block_transaction(data, read_write, size, hwpec);
7edcb9ab
OR		 512 else
513 ret = i801_transaction(xact | ENABLE_INT9);
1da177e4 514
c79cfbac 515 /* Some BIOSes don't like it when PEC is enabled at reboot or resume
7edcb9ab
OR		 516 time, so we forcibly disable it after every transaction. Turn off
517 E32B for the same reason. */
a0921b6c 518 if (hwpec || block)
7edcb9ab
OR		 519 outb_p(inb_p(SMBAUXCTL) & ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B),
520 SMBAUXCTL);
c79cfbac 521
1da177e4
LT		 522 if(block)
523 return ret;
524 if(ret)
97140342 525 return ret;
1da177e4
LT		 526 if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
527 return 0;
528
529 switch (xact & 0x7f) {
530 case I801_BYTE: /* Result put in SMBHSTDAT0 */
531 case I801_BYTE_DATA:
532 data->byte = inb_p(SMBHSTDAT0);
533 break;
534 case I801_WORD_DATA:
535 data->word = inb_p(SMBHSTDAT0) + (inb_p(SMBHSTDAT1) << 8);
536 break;
537 }
538 return 0;
539}
540
541
542static u32 i801_func(struct i2c_adapter *adapter)
543{
544 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
369f6f4a
JD		 545 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
546 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
6342064c
JD		 547 ((i801_features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
548 ((i801_features & FEATURE_I2C_BLOCK_READ) ?
549 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0);
1da177e4
LT		 550}
551
8f9082c5 552static const struct i2c_algorithm smbus_algorithm = {
1da177e4
LT		 553 .smbus_xfer = i801_access,
554 .functionality = i801_func,
555};
556
557static struct i2c_adapter i801_adapter = {
558 .owner = THIS_MODULE,
3401b2ff 559 .class = I2C_CLASS_HWMON | I2C_CLASS_SPD,
1da177e4 560 .algo = &smbus_algorithm,
1da177e4
LT		 561};
562
563static struct pci_device_id i801_ids[] = {
564 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
565 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
566 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
567 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
568 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
569 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
570 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
571 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
572 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
b0a70b57 573 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
8254fc4a 574 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
adbc2a10 575 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
e07bc679 576 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TOLAPAI_1) },
d28dc711
GJ		 577 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
578 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
c429a247 579 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PCH_SMBUS) },
1da177e4
LT		 580 { 0, }
581};
582
583MODULE_DEVICE_TABLE (pci, i801_ids);
584
1561bfe5
JD		 585#if defined CONFIG_INPUT_APANEL || defined CONFIG_INPUT_APANEL_MODULE
586static unsigned char apanel_addr;
587
588/* Scan the system ROM for the signature "FJKEYINF" */
589static __init const void __iomem *bios_signature(const void __iomem *bios)
590{
591 ssize_t offset;
592 const unsigned char signature[] = "FJKEYINF";
593
594 for (offset = 0; offset < 0x10000; offset += 0x10) {
595 if (check_signature(bios + offset, signature,
596 sizeof(signature)-1))
597 return bios + offset;
598 }
599 return NULL;
600}
601
602static void __init input_apanel_init(void)
603{
604 void __iomem *bios;
605 const void __iomem *p;
606
607 bios = ioremap(0xF0000, 0x10000); /* Can't fail */
608 p = bios_signature(bios);
609 if (p) {
610 /* just use the first address */
611 apanel_addr = readb(p + 8 + 3) >> 1;
612 }
613 iounmap(bios);
614}
615#else
616static void __init input_apanel_init(void) {}
617#endif
618
1da177e4
LT		 619static int __devinit i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
620{
02dd7ae2 621 unsigned char temp;
455f3323 622 int err;
1da177e4 623
02dd7ae2 624 I801_dev = dev;
369f6f4a 625 i801_features = 0;
250d1bd3 626 switch (dev->device) {
250d1bd3
JD		 627 case PCI_DEVICE_ID_INTEL_82801EB_3:
628 case PCI_DEVICE_ID_INTEL_ESB_4:
629 case PCI_DEVICE_ID_INTEL_ICH6_16:
630 case PCI_DEVICE_ID_INTEL_ICH7_17:
631 case PCI_DEVICE_ID_INTEL_ESB2_17:
632 case PCI_DEVICE_ID_INTEL_ICH8_5:
633 case PCI_DEVICE_ID_INTEL_ICH9_6:
d28dc711
GJ		 634 case PCI_DEVICE_ID_INTEL_TOLAPAI_1:
635 case PCI_DEVICE_ID_INTEL_ICH10_4:
636 case PCI_DEVICE_ID_INTEL_ICH10_5:
c429a247 637 case PCI_DEVICE_ID_INTEL_PCH_SMBUS:
6342064c
JD		 638 i801_features |= FEATURE_I2C_BLOCK_READ;
639 /* fall through */
640 case PCI_DEVICE_ID_INTEL_82801DB_3:
369f6f4a
JD		 641 i801_features |= FEATURE_SMBUS_PEC;
642 i801_features |= FEATURE_BLOCK_BUFFER;
250d1bd3 643 break;
250d1bd3 644 }
02dd7ae2
JD		 645
646 err = pci_enable_device(dev);
647 if (err) {
648 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
649 err);
650 goto exit;
651 }
652
653 /* Determine the address of the SMBus area */
654 i801_smba = pci_resource_start(dev, SMBBAR);
655 if (!i801_smba) {
656 dev_err(&dev->dev, "SMBus base address uninitialized, "
657 "upgrade BIOS\n");
658 err = -ENODEV;
d6fcb3b9 659 goto exit;
02dd7ae2
JD		 660 }
661
54fb4a05
JD		 662 err = acpi_check_resource_conflict(&dev->resource[SMBBAR]);
663 if (err)
664 goto exit;
665
02dd7ae2
JD		 666 err = pci_request_region(dev, SMBBAR, i801_driver.name);
667 if (err) {
668 dev_err(&dev->dev, "Failed to request SMBus region "
598736c5
AM		 669 "0x%lx-0x%Lx\n", i801_smba,
670 (unsigned long long)pci_resource_end(dev, SMBBAR));
d6fcb3b9 671 goto exit;
02dd7ae2
JD		 672 }
673
674 pci_read_config_byte(I801_dev, SMBHSTCFG, &temp);
a5aaea37 675 i801_original_hstcfg = temp;
02dd7ae2
JD		 676 temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */
677 if (!(temp & SMBHSTCFG_HST_EN)) {
678 dev_info(&dev->dev, "Enabling SMBus device\n");
679 temp |= SMBHSTCFG_HST_EN;
680 }
681 pci_write_config_byte(I801_dev, SMBHSTCFG, temp);
682
683 if (temp & SMBHSTCFG_SMB_SMI_EN)
684 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
685 else
686 dev_dbg(&dev->dev, "SMBus using PCI Interrupt\n");
1da177e4 687
a0921b6c
JD		 688 /* Clear special mode bits */
689 if (i801_features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
690 outb_p(inb_p(SMBAUXCTL) & ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B),
691 SMBAUXCTL);
692
405ae7d3 693 /* set up the sysfs linkage to our parent device */
1da177e4
LT		 694 i801_adapter.dev.parent = &dev->dev;
695
2096b956 696 snprintf(i801_adapter.name, sizeof(i801_adapter.name),
6dcc19df 697 "SMBus I801 adapter at %04lx", i801_smba);
02dd7ae2
JD		 698 err = i2c_add_adapter(&i801_adapter);
699 if (err) {
700 dev_err(&dev->dev, "Failed to add SMBus adapter\n");
d6fcb3b9 701 goto exit_release;
02dd7ae2 702 }
1561bfe5
JD		 703
704 /* Register optional slaves */
705#if defined CONFIG_INPUT_APANEL || defined CONFIG_INPUT_APANEL_MODULE
706 if (apanel_addr) {
707 struct i2c_board_info info;
708
709 memset(&info, 0, sizeof(struct i2c_board_info));
710 info.addr = apanel_addr;
711 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE);
712 i2c_new_device(&i801_adapter, &info);
713 }
714#endif
715
d6fcb3b9 716 return 0;
02dd7ae2 717
d6fcb3b9
DR		 718exit_release:
719 pci_release_region(dev, SMBBAR);
02dd7ae2
JD		 720exit:
721 return err;
1da177e4
LT		 722}
723
724static void __devexit i801_remove(struct pci_dev *dev)
725{
726 i2c_del_adapter(&i801_adapter);
a5aaea37 727 pci_write_config_byte(I801_dev, SMBHSTCFG, i801_original_hstcfg);
6dcc19df 728 pci_release_region(dev, SMBBAR);
d6fcb3b9
DR		 729 /*
730 * do not call pci_disable_device(dev) since it can cause hard hangs on
731 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
732 */
1da177e4
LT		 733}
734
a5aaea37
JD		 735#ifdef CONFIG_PM
736static int i801_suspend(struct pci_dev *dev, pm_message_t mesg)
737{
738 pci_save_state(dev);
739 pci_write_config_byte(dev, SMBHSTCFG, i801_original_hstcfg);
740 pci_set_power_state(dev, pci_choose_state(dev, mesg));
741 return 0;
742}
743
744static int i801_resume(struct pci_dev *dev)
745{
746 pci_set_power_state(dev, PCI_D0);
747 pci_restore_state(dev);
748 return pci_enable_device(dev);
749}
750#else
751#define i801_suspend NULL
752#define i801_resume NULL
753#endif
754
1da177e4
LT		 755static struct pci_driver i801_driver = {
756 .name = "i801_smbus",
757 .id_table = i801_ids,
758 .probe = i801_probe,
759 .remove = __devexit_p(i801_remove),
a5aaea37
JD		 760 .suspend = i801_suspend,
761 .resume = i801_resume,
1da177e4
LT		 762};
763
764static int __init i2c_i801_init(void)
765{
1561bfe5 766 input_apanel_init();
1da177e4
LT		 767 return pci_register_driver(&i801_driver);
768}
769
770static void __exit i2c_i801_exit(void)
771{
772 pci_unregister_driver(&i801_driver);
773}
774
6342064c
JD		 775MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, "
776 "Jean Delvare <khali@linux-fr.org>");
1da177e4
LT		 777MODULE_DESCRIPTION("I801 SMBus driver");
778MODULE_LICENSE("GPL");
779
780module_init(i2c_i801_init);
781module_exit(i2c_i801_exit);
Clone of davem's net-next-2.6 tree