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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/penberg...
[net-next-2.6.git] / drivers / i2c / busses / i2c-bfin-twi.c
CommitLineData
d24ecfcc 1/*
bd584996 2 * Blackfin On-Chip Two Wire Interface Driver
d24ecfcc 3 *
bd584996 4 * Copyright 2005-2007 Analog Devices Inc.
d24ecfcc 5 *
bd584996 6 * Enter bugs at http://blackfin.uclinux.org/
d24ecfcc 7 *
bd584996 8 * Licensed under the GPL-2 or later.
d24ecfcc
BW		 9 */
10
11#include <linux/module.h>
12#include <linux/kernel.h>
13#include <linux/init.h>
14#include <linux/i2c.h>
15#include <linux/mm.h>
16#include <linux/timer.h>
17#include <linux/spinlock.h>
18#include <linux/completion.h>
19#include <linux/interrupt.h>
20#include <linux/platform_device.h>
21
22#include <asm/blackfin.h>
74d362e0 23#include <asm/portmux.h>
d24ecfcc
BW		 24#include <asm/irq.h>
25
26#define POLL_TIMEOUT (2 * HZ)
27
28/* SMBus mode*/
4dd39bb1
SZ		 29#define TWI_I2C_MODE_STANDARD 1
30#define TWI_I2C_MODE_STANDARDSUB 2
31#define TWI_I2C_MODE_COMBINED 3
32#define TWI_I2C_MODE_REPEAT 4
d24ecfcc
BW		 33
34struct bfin_twi_iface {
d24ecfcc
BW		 35 int irq;
36 spinlock_t lock;
37 char read_write;
38 u8 command;
39 u8 *transPtr;
40 int readNum;
41 int writeNum;
42 int cur_mode;
43 int manual_stop;
44 int result;
45 int timeout_count;
46 struct timer_list timeout_timer;
47 struct i2c_adapter adap;
48 struct completion complete;
4dd39bb1
SZ		 49 struct i2c_msg *pmsg;
50 int msg_num;
51 int cur_msg;
958585f5
MH		 52 u16 saved_clkdiv;
53 u16 saved_control;
aa3d0209 54 void __iomem *regs_base;
d24ecfcc
BW		 55};
56
aa3d0209
BW		 57
58#define DEFINE_TWI_REG(reg, off) \
59static inline u16 read_##reg(struct bfin_twi_iface *iface) \
60 { return bfin_read16(iface->regs_base + (off)); } \
61static inline void write_##reg(struct bfin_twi_iface *iface, u16 v) \
62 { bfin_write16(iface->regs_base + (off), v); }
63
64DEFINE_TWI_REG(CLKDIV, 0x00)
65DEFINE_TWI_REG(CONTROL, 0x04)
66DEFINE_TWI_REG(SLAVE_CTL, 0x08)
67DEFINE_TWI_REG(SLAVE_STAT, 0x0C)
68DEFINE_TWI_REG(SLAVE_ADDR, 0x10)
69DEFINE_TWI_REG(MASTER_CTL, 0x14)
70DEFINE_TWI_REG(MASTER_STAT, 0x18)
71DEFINE_TWI_REG(MASTER_ADDR, 0x1C)
72DEFINE_TWI_REG(INT_STAT, 0x20)
73DEFINE_TWI_REG(INT_MASK, 0x24)
74DEFINE_TWI_REG(FIFO_CTL, 0x28)
75DEFINE_TWI_REG(FIFO_STAT, 0x2C)
76DEFINE_TWI_REG(XMT_DATA8, 0x80)
77DEFINE_TWI_REG(XMT_DATA16, 0x84)
78DEFINE_TWI_REG(RCV_DATA8, 0x88)
79DEFINE_TWI_REG(RCV_DATA16, 0x8C)
d24ecfcc 80
74d362e0
BW		 81static const u16 pin_req[2][3] = {
82 {P_TWI0_SCL, P_TWI0_SDA, 0},
83 {P_TWI1_SCL, P_TWI1_SDA, 0},
84};
85
d24ecfcc
BW		 86static void bfin_twi_handle_interrupt(struct bfin_twi_iface *iface)
87{
aa3d0209
BW		 88 unsigned short twi_int_status = read_INT_STAT(iface);
89 unsigned short mast_stat = read_MASTER_STAT(iface);
d24ecfcc
BW		 90
91 if (twi_int_status & XMTSERV) {
92 /* Transmit next data */
93 if (iface->writeNum > 0) {
aa3d0209 94 write_XMT_DATA8(iface, *(iface->transPtr++));
d24ecfcc
BW		 95 iface->writeNum--;
96 }
97 /* start receive immediately after complete sending in
98 * combine mode.
99 */
4dd39bb1 100 else if (iface->cur_mode == TWI_I2C_MODE_COMBINED)
aa3d0209
BW		 101 write_MASTER_CTL(iface,
102 read_MASTER_CTL(iface) | MDIR | RSTART);
4dd39bb1 103 else if (iface->manual_stop)
aa3d0209
BW		 104 write_MASTER_CTL(iface,
105 read_MASTER_CTL(iface) | STOP);
4dd39bb1
SZ		 106 else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
107 iface->cur_msg+1 < iface->msg_num)
aa3d0209
BW		 108 write_MASTER_CTL(iface,
109 read_MASTER_CTL(iface) | RSTART);
d24ecfcc
BW		 110 SSYNC();
111 /* Clear status */
aa3d0209 112 write_INT_STAT(iface, XMTSERV);
d24ecfcc
BW		 113 SSYNC();
114 }
115 if (twi_int_status & RCVSERV) {
116 if (iface->readNum > 0) {
117 /* Receive next data */
aa3d0209 118 *(iface->transPtr) = read_RCV_DATA8(iface);
d24ecfcc
BW		 119 if (iface->cur_mode == TWI_I2C_MODE_COMBINED) {
120 /* Change combine mode into sub mode after
121 * read first data.
122 */
123 iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
124 /* Get read number from first byte in block
125 * combine mode.
126 */
127 if (iface->readNum == 1 && iface->manual_stop)
128 iface->readNum = *iface->transPtr + 1;
129 }
130 iface->transPtr++;
131 iface->readNum--;
132 } else if (iface->manual_stop) {
aa3d0209
BW		 133 write_MASTER_CTL(iface,
134 read_MASTER_CTL(iface) | STOP);
d24ecfcc 135 SSYNC();
4dd39bb1
SZ		 136 } else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
137 iface->cur_msg+1 < iface->msg_num) {
aa3d0209
BW		 138 write_MASTER_CTL(iface,
139 read_MASTER_CTL(iface) | RSTART);
4dd39bb1 140 SSYNC();
d24ecfcc
BW		 141 }
142 /* Clear interrupt source */
aa3d0209 143 write_INT_STAT(iface, RCVSERV);
d24ecfcc
BW		 144 SSYNC();
145 }
146 if (twi_int_status & MERR) {
aa3d0209
BW		 147 write_INT_STAT(iface, MERR);
148 write_INT_MASK(iface, 0);
149 write_MASTER_STAT(iface, 0x3e);
150 write_MASTER_CTL(iface, 0);
d24ecfcc 151 SSYNC();
4dd39bb1 152 iface->result = -EIO;
d24ecfcc
BW		 153 /* if both err and complete int stats are set, return proper
154 * results.
155 */
156 if (twi_int_status & MCOMP) {
aa3d0209
BW		 157 write_INT_STAT(iface, MCOMP);
158 write_INT_MASK(iface, 0);
159 write_MASTER_CTL(iface, 0);
d24ecfcc
BW		 160 SSYNC();
161 /* If it is a quick transfer, only address bug no data,
162 * not an err, return 1.
163 */
164 if (iface->writeNum == 0 && (mast_stat & BUFRDERR))
165 iface->result = 1;
166 /* If address not acknowledged return -1,
167 * else return 0.
168 */
169 else if (!(mast_stat & ANAK))
170 iface->result = 0;
171 }
172 complete(&iface->complete);
173 return;
174 }
175 if (twi_int_status & MCOMP) {
aa3d0209 176 write_INT_STAT(iface, MCOMP);
d24ecfcc
BW		 177 SSYNC();
178 if (iface->cur_mode == TWI_I2C_MODE_COMBINED) {
179 if (iface->readNum == 0) {
180 /* set the read number to 1 and ask for manual
181 * stop in block combine mode
182 */
183 iface->readNum = 1;
184 iface->manual_stop = 1;
aa3d0209
BW		 185 write_MASTER_CTL(iface,
186 read_MASTER_CTL(iface) | (0xff << 6));
d24ecfcc
BW		 187 } else {
188 /* set the readd number in other
189 * combine mode.
190 */
aa3d0209
BW		 191 write_MASTER_CTL(iface,
192 (read_MASTER_CTL(iface) &
d24ecfcc 193 (~(0xff << 6))) |
aa3d0209 194 (iface->readNum << 6));
d24ecfcc
BW		 195 }
196 /* remove restart bit and enable master receive */
aa3d0209
BW		 197 write_MASTER_CTL(iface,
198 read_MASTER_CTL(iface) & ~RSTART);
199 write_MASTER_CTL(iface,
200 read_MASTER_CTL(iface) | MEN | MDIR);
d24ecfcc 201 SSYNC();
4dd39bb1
SZ		 202 } else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
203 iface->cur_msg+1 < iface->msg_num) {
204 iface->cur_msg++;
205 iface->transPtr = iface->pmsg[iface->cur_msg].buf;
206 iface->writeNum = iface->readNum =
207 iface->pmsg[iface->cur_msg].len;
208 /* Set Transmit device address */
aa3d0209 209 write_MASTER_ADDR(iface,
4dd39bb1
SZ		 210 iface->pmsg[iface->cur_msg].addr);
211 if (iface->pmsg[iface->cur_msg].flags & I2C_M_RD)
212 iface->read_write = I2C_SMBUS_READ;
213 else {
214 iface->read_write = I2C_SMBUS_WRITE;
215 /* Transmit first data */
216 if (iface->writeNum > 0) {
aa3d0209 217 write_XMT_DATA8(iface,
4dd39bb1
SZ		 218 *(iface->transPtr++));
219 iface->writeNum--;
220 SSYNC();
221 }
222 }
223
224 if (iface->pmsg[iface->cur_msg].len <= 255)
aa3d0209 225 write_MASTER_CTL(iface,
4dd39bb1
SZ		 226 iface->pmsg[iface->cur_msg].len << 6);
227 else {
aa3d0209 228 write_MASTER_CTL(iface, 0xff << 6);
4dd39bb1
SZ		 229 iface->manual_stop = 1;
230 }
231 /* remove restart bit and enable master receive */
aa3d0209
BW		 232 write_MASTER_CTL(iface,
233 read_MASTER_CTL(iface) & ~RSTART);
234 write_MASTER_CTL(iface, read_MASTER_CTL(iface) |
4dd39bb1
SZ		 235 MEN | ((iface->read_write == I2C_SMBUS_READ) ?
236 MDIR : 0));
237 SSYNC();
d24ecfcc
BW		 238 } else {
239 iface->result = 1;
aa3d0209
BW		 240 write_INT_MASK(iface, 0);
241 write_MASTER_CTL(iface, 0);
d24ecfcc
BW		 242 SSYNC();
243 complete(&iface->complete);
244 }
245 }
246}
247
248/* Interrupt handler */
249static irqreturn_t bfin_twi_interrupt_entry(int irq, void *dev_id)
250{
251 struct bfin_twi_iface *iface = dev_id;
252 unsigned long flags;
253
254 spin_lock_irqsave(&iface->lock, flags);
255 del_timer(&iface->timeout_timer);
256 bfin_twi_handle_interrupt(iface);
257 spin_unlock_irqrestore(&iface->lock, flags);
258 return IRQ_HANDLED;
259}
260
261static void bfin_twi_timeout(unsigned long data)
262{
263 struct bfin_twi_iface *iface = (struct bfin_twi_iface *)data;
264 unsigned long flags;
265
266 spin_lock_irqsave(&iface->lock, flags);
267 bfin_twi_handle_interrupt(iface);
268 if (iface->result == 0) {
269 iface->timeout_count--;
270 if (iface->timeout_count > 0) {
271 iface->timeout_timer.expires = jiffies + POLL_TIMEOUT;
272 add_timer(&iface->timeout_timer);
273 } else {
274 iface->result = -1;
275 complete(&iface->complete);
276 }
277 }
278 spin_unlock_irqrestore(&iface->lock, flags);
279}
280
281/*
282 * Generic i2c master transfer entrypoint
283 */
284static int bfin_twi_master_xfer(struct i2c_adapter *adap,
285 struct i2c_msg *msgs, int num)
286{
287 struct bfin_twi_iface *iface = adap->algo_data;
288 struct i2c_msg *pmsg;
d24ecfcc
BW		 289 int rc = 0;
290
aa3d0209 291 if (!(read_CONTROL(iface) & TWI_ENA))
d24ecfcc
BW		 292 return -ENXIO;
293
aa3d0209 294 while (read_MASTER_STAT(iface) & BUSBUSY)
d24ecfcc 295 yield();
d24ecfcc 296
4dd39bb1
SZ		 297 iface->pmsg = msgs;
298 iface->msg_num = num;
299 iface->cur_msg = 0;
d24ecfcc 300
4dd39bb1
SZ		 301 pmsg = &msgs[0];
302 if (pmsg->flags & I2C_M_TEN) {
303 dev_err(&adap->dev, "10 bits addr not supported!\n");
304 return -EINVAL;
305 }
d24ecfcc 306
4dd39bb1
SZ		 307 iface->cur_mode = TWI_I2C_MODE_REPEAT;
308 iface->manual_stop = 0;
309 iface->transPtr = pmsg->buf;
310 iface->writeNum = iface->readNum = pmsg->len;
311 iface->result = 0;
312 iface->timeout_count = 10;
afc13b76 313 init_completion(&(iface->complete));
4dd39bb1 314 /* Set Transmit device address */
aa3d0209 315 write_MASTER_ADDR(iface, pmsg->addr);
4dd39bb1
SZ		 316
317 /* FIFO Initiation. Data in FIFO should be
318 * discarded before start a new operation.
319 */
aa3d0209 320 write_FIFO_CTL(iface, 0x3);
4dd39bb1 321 SSYNC();
aa3d0209 322 write_FIFO_CTL(iface, 0);
4dd39bb1
SZ		 323 SSYNC();
324
325 if (pmsg->flags & I2C_M_RD)
326 iface->read_write = I2C_SMBUS_READ;
327 else {
328 iface->read_write = I2C_SMBUS_WRITE;
329 /* Transmit first data */
330 if (iface->writeNum > 0) {
aa3d0209 331 write_XMT_DATA8(iface, *(iface->transPtr++));
4dd39bb1
SZ		 332 iface->writeNum--;
333 SSYNC();
d24ecfcc 334 }
4dd39bb1 335 }
d24ecfcc 336
4dd39bb1 337 /* clear int stat */
aa3d0209 338 write_INT_STAT(iface, MERR | MCOMP | XMTSERV | RCVSERV);
d24ecfcc 339
4dd39bb1 340 /* Interrupt mask . Enable XMT, RCV interrupt */
aa3d0209 341 write_INT_MASK(iface, MCOMP | MERR | RCVSERV | XMTSERV);
4dd39bb1 342 SSYNC();
d24ecfcc 343
4dd39bb1 344 if (pmsg->len <= 255)
aa3d0209 345 write_MASTER_CTL(iface, pmsg->len << 6);
4dd39bb1 346 else {
aa3d0209 347 write_MASTER_CTL(iface, 0xff << 6);
4dd39bb1
SZ		 348 iface->manual_stop = 1;
349 }
d24ecfcc 350
4dd39bb1
SZ		 351 iface->timeout_timer.expires = jiffies + POLL_TIMEOUT;
352 add_timer(&iface->timeout_timer);
d24ecfcc 353
4dd39bb1 354 /* Master enable */
aa3d0209 355 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
4dd39bb1
SZ		 356 ((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) |
357 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ > 100) ? FAST : 0));
358 SSYNC();
359
360 wait_for_completion(&iface->complete);
361
362 rc = iface->result;
d24ecfcc 363
4dd39bb1
SZ		 364 if (rc == 1)
365 return num;
366 else
367 return rc;
d24ecfcc
BW		 368}
369
370/*
371 * SMBus type transfer entrypoint
372 */
373
374int bfin_twi_smbus_xfer(struct i2c_adapter *adap, u16 addr,
375 unsigned short flags, char read_write,
376 u8 command, int size, union i2c_smbus_data *data)
377{
378 struct bfin_twi_iface *iface = adap->algo_data;
379 int rc = 0;
380
aa3d0209 381 if (!(read_CONTROL(iface) & TWI_ENA))
d24ecfcc
BW		 382 return -ENXIO;
383
aa3d0209 384 while (read_MASTER_STAT(iface) & BUSBUSY)
d24ecfcc 385 yield();
d24ecfcc
BW		 386
387 iface->writeNum = 0;
388 iface->readNum = 0;
389
390 /* Prepare datas & select mode */
391 switch (size) {
392 case I2C_SMBUS_QUICK:
393 iface->transPtr = NULL;
394 iface->cur_mode = TWI_I2C_MODE_STANDARD;
395 break;
396 case I2C_SMBUS_BYTE:
397 if (data == NULL)
398 iface->transPtr = NULL;
399 else {
400 if (read_write == I2C_SMBUS_READ)
401 iface->readNum = 1;
402 else
403 iface->writeNum = 1;
404 iface->transPtr = &data->byte;
405 }
406 iface->cur_mode = TWI_I2C_MODE_STANDARD;
407 break;
408 case I2C_SMBUS_BYTE_DATA:
409 if (read_write == I2C_SMBUS_READ) {
410 iface->readNum = 1;
411 iface->cur_mode = TWI_I2C_MODE_COMBINED;
412 } else {
413 iface->writeNum = 1;
414 iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
415 }
416 iface->transPtr = &data->byte;
417 break;
418 case I2C_SMBUS_WORD_DATA:
419 if (read_write == I2C_SMBUS_READ) {
420 iface->readNum = 2;
421 iface->cur_mode = TWI_I2C_MODE_COMBINED;
422 } else {
423 iface->writeNum = 2;
424 iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
425 }
426 iface->transPtr = (u8 *)&data->word;
427 break;
428 case I2C_SMBUS_PROC_CALL:
429 iface->writeNum = 2;
430 iface->readNum = 2;
431 iface->cur_mode = TWI_I2C_MODE_COMBINED;
432 iface->transPtr = (u8 *)&data->word;
433 break;
434 case I2C_SMBUS_BLOCK_DATA:
435 if (read_write == I2C_SMBUS_READ) {
436 iface->readNum = 0;
437 iface->cur_mode = TWI_I2C_MODE_COMBINED;
438 } else {
439 iface->writeNum = data->block[0] + 1;
440 iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
441 }
442 iface->transPtr = data->block;
443 break;
444 default:
445 return -1;
446 }
447
448 iface->result = 0;
449 iface->manual_stop = 0;
450 iface->read_write = read_write;
451 iface->command = command;
452 iface->timeout_count = 10;
afc13b76 453 init_completion(&(iface->complete));
d24ecfcc
BW		 454
455 /* FIFO Initiation. Data in FIFO should be discarded before
456 * start a new operation.
457 */
aa3d0209 458 write_FIFO_CTL(iface, 0x3);
d24ecfcc 459 SSYNC();
aa3d0209 460 write_FIFO_CTL(iface, 0);
d24ecfcc
BW		 461
462 /* clear int stat */
aa3d0209 463 write_INT_STAT(iface, MERR | MCOMP | XMTSERV | RCVSERV);
d24ecfcc
BW		 464
465 /* Set Transmit device address */
aa3d0209 466 write_MASTER_ADDR(iface, addr);
d24ecfcc
BW		 467 SSYNC();
468
469 iface->timeout_timer.expires = jiffies + POLL_TIMEOUT;
470 add_timer(&iface->timeout_timer);
471
472 switch (iface->cur_mode) {
473 case TWI_I2C_MODE_STANDARDSUB:
aa3d0209
BW		 474 write_XMT_DATA8(iface, iface->command);
475 write_INT_MASK(iface, MCOMP | MERR |
d24ecfcc
BW		 476 ((iface->read_write == I2C_SMBUS_READ) ?
477 RCVSERV : XMTSERV));
478 SSYNC();
479
480 if (iface->writeNum + 1 <= 255)
aa3d0209 481 write_MASTER_CTL(iface, (iface->writeNum + 1) << 6);
d24ecfcc 482 else {
aa3d0209 483 write_MASTER_CTL(iface, 0xff << 6);
d24ecfcc
BW		 484 iface->manual_stop = 1;
485 }
486 /* Master enable */
aa3d0209 487 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
d24ecfcc
BW		 488 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0));
489 break;
490 case TWI_I2C_MODE_COMBINED:
aa3d0209
BW		 491 write_XMT_DATA8(iface, iface->command);
492 write_INT_MASK(iface, MCOMP | MERR | RCVSERV | XMTSERV);
d24ecfcc
BW		 493 SSYNC();
494
495 if (iface->writeNum > 0)
aa3d0209 496 write_MASTER_CTL(iface, (iface->writeNum + 1) << 6);
d24ecfcc 497 else
aa3d0209 498 write_MASTER_CTL(iface, 0x1 << 6);
d24ecfcc 499 /* Master enable */
aa3d0209 500 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
d24ecfcc
BW		 501 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0));
502 break;
503 default:
aa3d0209 504 write_MASTER_CTL(iface, 0);
d24ecfcc
BW		 505 if (size != I2C_SMBUS_QUICK) {
506 /* Don't access xmit data register when this is a
507 * read operation.
508 */
509 if (iface->read_write != I2C_SMBUS_READ) {
510 if (iface->writeNum > 0) {
aa3d0209
BW		 511 write_XMT_DATA8(iface,
512 *(iface->transPtr++));
d24ecfcc 513 if (iface->writeNum <= 255)
aa3d0209
BW		 514 write_MASTER_CTL(iface,
515 iface->writeNum << 6);
d24ecfcc 516 else {
aa3d0209
BW		 517 write_MASTER_CTL(iface,
518 0xff << 6);
d24ecfcc
BW		 519 iface->manual_stop = 1;
520 }
521 iface->writeNum--;
522 } else {
aa3d0209
BW		 523 write_XMT_DATA8(iface, iface->command);
524 write_MASTER_CTL(iface, 1 << 6);
d24ecfcc
BW		 525 }
526 } else {
527 if (iface->readNum > 0 && iface->readNum <= 255)
aa3d0209
BW		 528 write_MASTER_CTL(iface,
529 iface->readNum << 6);
d24ecfcc 530 else if (iface->readNum > 255) {
aa3d0209 531 write_MASTER_CTL(iface, 0xff << 6);
d24ecfcc
BW		 532 iface->manual_stop = 1;
533 } else {
534 del_timer(&iface->timeout_timer);
535 break;
536 }
537 }
538 }
aa3d0209 539 write_INT_MASK(iface, MCOMP | MERR |
d24ecfcc
BW		 540 ((iface->read_write == I2C_SMBUS_READ) ?
541 RCVSERV : XMTSERV));
542 SSYNC();
543
544 /* Master enable */
aa3d0209 545 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
d24ecfcc
BW		 546 ((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) |
547 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ > 100) ? FAST : 0));
548 break;
549 }
550 SSYNC();
551
552 wait_for_completion(&iface->complete);
553
554 rc = (iface->result >= 0) ? 0 : -1;
555
d24ecfcc
BW		 556 return rc;
557}
558
559/*
560 * Return what the adapter supports
561 */
562static u32 bfin_twi_functionality(struct i2c_adapter *adap)
563{
564 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
565 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
566 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_PROC_CALL |
567 I2C_FUNC_I2C;
568}
569
d24ecfcc
BW		 570static struct i2c_algorithm bfin_twi_algorithm = {
571 .master_xfer = bfin_twi_master_xfer,
572 .smbus_xfer = bfin_twi_smbus_xfer,
573 .functionality = bfin_twi_functionality,
574};
575
958585f5 576static int i2c_bfin_twi_suspend(struct platform_device *pdev, pm_message_t state)
d24ecfcc 577{
958585f5
MH		 578 struct bfin_twi_iface *iface = platform_get_drvdata(pdev);
579
580 iface->saved_clkdiv = read_CLKDIV(iface);
581 iface->saved_control = read_CONTROL(iface);
582
583 free_irq(iface->irq, iface);
d24ecfcc
BW		 584
585 /* Disable TWI */
958585f5 586 write_CONTROL(iface, iface->saved_control & ~TWI_ENA);
d24ecfcc
BW		 587
588 return 0;
589}
590
958585f5 591static int i2c_bfin_twi_resume(struct platform_device *pdev)
d24ecfcc 592{
958585f5 593 struct bfin_twi_iface *iface = platform_get_drvdata(pdev);
d24ecfcc 594
958585f5
MH		 595 int rc = request_irq(iface->irq, bfin_twi_interrupt_entry,
596 IRQF_DISABLED, pdev->name, iface);
597 if (rc) {
598 dev_err(&pdev->dev, "Can't get IRQ %d !\n", iface->irq);
599 return -ENODEV;
600 }
601
602 /* Resume TWI interface clock as specified */
603 write_CLKDIV(iface, iface->saved_clkdiv);
604
605 /* Resume TWI */
606 write_CONTROL(iface, iface->saved_control);
d24ecfcc
BW		 607
608 return 0;
609}
610
aa3d0209 611static int i2c_bfin_twi_probe(struct platform_device *pdev)
d24ecfcc 612{
aa3d0209 613 struct bfin_twi_iface *iface;
d24ecfcc 614 struct i2c_adapter *p_adap;
aa3d0209 615 struct resource *res;
d24ecfcc
BW		 616 int rc;
617
aa3d0209
BW		 618 iface = kzalloc(sizeof(struct bfin_twi_iface), GFP_KERNEL);
619 if (!iface) {
620 dev_err(&pdev->dev, "Cannot allocate memory\n");
621 rc = -ENOMEM;
622 goto out_error_nomem;
623 }
624
d24ecfcc 625 spin_lock_init(&(iface->lock));
aa3d0209
BW		 626
627 /* Find and map our resources */
628 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
629 if (res == NULL) {
630 dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
631 rc = -ENOENT;
632 goto out_error_get_res;
633 }
634
635 iface->regs_base = ioremap(res->start, res->end - res->start + 1);
636 if (iface->regs_base == NULL) {
637 dev_err(&pdev->dev, "Cannot map IO\n");
638 rc = -ENXIO;
639 goto out_error_ioremap;
640 }
641
642 iface->irq = platform_get_irq(pdev, 0);
643 if (iface->irq < 0) {
644 dev_err(&pdev->dev, "No IRQ specified\n");
645 rc = -ENOENT;
646 goto out_error_no_irq;
647 }
d24ecfcc
BW		 648
649 init_timer(&(iface->timeout_timer));
650 iface->timeout_timer.function = bfin_twi_timeout;
651 iface->timeout_timer.data = (unsigned long)iface;
652
653 p_adap = &iface->adap;
aa3d0209
BW		 654 p_adap->nr = pdev->id;
655 strlcpy(p_adap->name, pdev->name, sizeof(p_adap->name));
d24ecfcc
BW		 656 p_adap->algo = &bfin_twi_algorithm;
657 p_adap->algo_data = iface;
e1995f65 658 p_adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
aa3d0209 659 p_adap->dev.parent = &pdev->dev;
d24ecfcc 660
74d362e0
BW		 661 rc = peripheral_request_list(pin_req[pdev->id], "i2c-bfin-twi");
662 if (rc) {
663 dev_err(&pdev->dev, "Can't setup pin mux!\n");
664 goto out_error_pin_mux;
665 }
666
d24ecfcc 667 rc = request_irq(iface->irq, bfin_twi_interrupt_entry,
aa3d0209 668 IRQF_DISABLED, pdev->name, iface);
d24ecfcc 669 if (rc) {
aa3d0209
BW		 670 dev_err(&pdev->dev, "Can't get IRQ %d !\n", iface->irq);
671 rc = -ENODEV;
672 goto out_error_req_irq;
d24ecfcc
BW		 673 }
674
675 /* Set TWI internal clock as 10MHz */
aa3d0209 676 write_CONTROL(iface, ((get_sclk() / 1024 / 1024 + 5) / 10) & 0x7F);
d24ecfcc
BW		 677
678 /* Set Twi interface clock as specified */
aa3d0209
BW		 679 write_CLKDIV(iface, ((5*1024 / CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ)
680 << 8) | ((5*1024 / CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ)
d24ecfcc
BW		 681 & 0xFF));
682
683 /* Enable TWI */
aa3d0209 684 write_CONTROL(iface, read_CONTROL(iface) | TWI_ENA);
d24ecfcc
BW		 685 SSYNC();
686
991dee59 687 rc = i2c_add_numbered_adapter(p_adap);
aa3d0209
BW		 688 if (rc < 0) {
689 dev_err(&pdev->dev, "Can't add i2c adapter!\n");
690 goto out_error_add_adapter;
691 }
692
693 platform_set_drvdata(pdev, iface);
d24ecfcc 694
fa6ad222
BW		 695 dev_info(&pdev->dev, "Blackfin BF5xx on-chip I2C TWI Contoller, "
696 "regs_base@%p\n", iface->regs_base);
aa3d0209
BW		 697
698 return 0;
699
700out_error_add_adapter:
701 free_irq(iface->irq, iface);
702out_error_req_irq:
703out_error_no_irq:
74d362e0
BW		 704 peripheral_free_list(pin_req[pdev->id]);
705out_error_pin_mux:
aa3d0209
BW		 706 iounmap(iface->regs_base);
707out_error_ioremap:
708out_error_get_res:
709 kfree(iface);
710out_error_nomem:
d24ecfcc
BW		 711 return rc;
712}
713
714static int i2c_bfin_twi_remove(struct platform_device *pdev)
715{
716 struct bfin_twi_iface *iface = platform_get_drvdata(pdev);
717
718 platform_set_drvdata(pdev, NULL);
719
720 i2c_del_adapter(&(iface->adap));
721 free_irq(iface->irq, iface);
74d362e0 722 peripheral_free_list(pin_req[pdev->id]);
aa3d0209
BW		 723 iounmap(iface->regs_base);
724 kfree(iface);
d24ecfcc
BW		 725
726 return 0;
727}
728
729static struct platform_driver i2c_bfin_twi_driver = {
730 .probe = i2c_bfin_twi_probe,
731 .remove = i2c_bfin_twi_remove,
732 .suspend = i2c_bfin_twi_suspend,
733 .resume = i2c_bfin_twi_resume,
734 .driver = {
735 .name = "i2c-bfin-twi",
736 .owner = THIS_MODULE,
737 },
738};
739
740static int __init i2c_bfin_twi_init(void)
741{
d24ecfcc
BW		 742 return platform_driver_register(&i2c_bfin_twi_driver);
743}
744
745static void __exit i2c_bfin_twi_exit(void)
746{
747 platform_driver_unregister(&i2c_bfin_twi_driver);
748}
749
d24ecfcc
BW		 750module_init(i2c_bfin_twi_init);
751module_exit(i2c_bfin_twi_exit);
fa6ad222
BW		 752
753MODULE_AUTHOR("Bryan Wu, Sonic Zhang");
754MODULE_DESCRIPTION("Blackfin BF5xx on-chip I2C TWI Contoller Driver");
755MODULE_LICENSE("GPL");
add8eda7 756MODULE_ALIAS("platform:i2c-bfin-twi");
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