[net-next-2.6.git] / drivers / i2c / busses / i2c-amd8111.c

/*
 * SMBus 2.0 driver for AMD-8111 IO-Hub.
 *
 * Copyright (c) 2002 Vojtech Pavlik
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation version 2.
 */

#include <linux/module.h>
#include <linux/pci.h>
#include <linux/kernel.h>
#include <linux/stddef.h>
#include <linux/ioport.h>
#include <linux/init.h>
#include <linux/i2c.h>
#include <linux/delay.h>
#include <asm/io.h>

MODULE_LICENSE("GPL");
MODULE_AUTHOR ("Vojtech Pavlik <vojtech@suse.cz>");
MODULE_DESCRIPTION("AMD8111 SMBus 2.0 driver");

struct amd_smbus {
	struct pci_dev *dev;
	struct i2c_adapter adapter;
	int base;
	int size;
};

static struct pci_driver amd8111_driver;

/*
 * AMD PCI control registers definitions.
 */

#define AMD_PCI_MISC	0x48

#define AMD_PCI_MISC_SCI	0x04	/* deliver SCI */
#define AMD_PCI_MISC_INT	0x02	/* deliver PCI IRQ */
#define AMD_PCI_MISC_SPEEDUP	0x01	/* 16x clock speedup */

/*
 * ACPI 2.0 chapter 13 PCI interface definitions.
 */

#define AMD_EC_DATA	0x00	/* data register */
#define AMD_EC_SC	0x04	/* status of controller */
#define AMD_EC_CMD	0x04	/* command register */
#define AMD_EC_ICR	0x08	/* interrupt control register */

#define AMD_EC_SC_SMI	0x04	/* smi event pending */
#define AMD_EC_SC_SCI	0x02	/* sci event pending */
#define AMD_EC_SC_BURST	0x01	/* burst mode enabled */
#define AMD_EC_SC_CMD	0x08	/* byte in data reg is command */
#define AMD_EC_SC_IBF	0x02	/* data ready for embedded controller */
#define AMD_EC_SC_OBF	0x01	/* data ready for host */

#define AMD_EC_CMD_RD	0x80	/* read EC */
#define AMD_EC_CMD_WR	0x81	/* write EC */
#define AMD_EC_CMD_BE	0x82	/* enable burst mode */
#define AMD_EC_CMD_BD	0x83	/* disable burst mode */
#define AMD_EC_CMD_QR	0x84	/* query EC */

/*
 * ACPI 2.0 chapter 13 access of registers of the EC
 */

static unsigned int amd_ec_wait_write(struct amd_smbus *smbus)
{
	int timeout = 500;

	while (timeout-- && (inb(smbus->base + AMD_EC_SC) & AMD_EC_SC_IBF))
		udelay(1);

	if (!timeout) {
		dev_warn(&smbus->dev->dev,
			 "Timeout while waiting for IBF to clear\n");
		return -1;
	}

	return 0;
}

static unsigned int amd_ec_wait_read(struct amd_smbus *smbus)
{
	int timeout = 500;

	while (timeout-- && (~inb(smbus->base + AMD_EC_SC) & AMD_EC_SC_OBF))
		udelay(1);

	if (!timeout) {
		dev_warn(&smbus->dev->dev,
			 "Timeout while waiting for OBF to set\n");
		return -1;
	}

	return 0;
}

static unsigned int amd_ec_read(struct amd_smbus *smbus, unsigned char address,
		unsigned char *data)
{
	if (amd_ec_wait_write(smbus))
		return -1;
	outb(AMD_EC_CMD_RD, smbus->base + AMD_EC_CMD);

	if (amd_ec_wait_write(smbus))
		return -1;
	outb(address, smbus->base + AMD_EC_DATA);

	if (amd_ec_wait_read(smbus))
		return -1;
	*data = inb(smbus->base + AMD_EC_DATA);

	return 0;
}

static unsigned int amd_ec_write(struct amd_smbus *smbus, unsigned char address,
		unsigned char data)
{
	if (amd_ec_wait_write(smbus))
		return -1;
	outb(AMD_EC_CMD_WR, smbus->base + AMD_EC_CMD);

	if (amd_ec_wait_write(smbus))
		return -1;
	outb(address, smbus->base + AMD_EC_DATA);

	if (amd_ec_wait_write(smbus))
		return -1;
	outb(data, smbus->base + AMD_EC_DATA);

	return 0;
}

/*
 * ACPI 2.0 chapter 13 SMBus 2.0 EC register model
 */

#define AMD_SMB_PRTCL	0x00	/* protocol, PEC */
#define AMD_SMB_STS	0x01	/* status */
#define AMD_SMB_ADDR	0x02	/* address */
#define AMD_SMB_CMD	0x03	/* command */
#define AMD_SMB_DATA	0x04	/* 32 data registers */
#define AMD_SMB_BCNT	0x24	/* number of data bytes */
#define AMD_SMB_ALRM_A	0x25	/* alarm address */
#define AMD_SMB_ALRM_D	0x26	/* 2 bytes alarm data */

#define AMD_SMB_STS_DONE	0x80
#define AMD_SMB_STS_ALRM	0x40
#define AMD_SMB_STS_RES		0x20
#define AMD_SMB_STS_STATUS	0x1f

#define AMD_SMB_STATUS_OK	0x00
#define AMD_SMB_STATUS_FAIL	0x07
#define AMD_SMB_STATUS_DNAK	0x10
#define AMD_SMB_STATUS_DERR	0x11
#define AMD_SMB_STATUS_CMD_DENY	0x12
#define AMD_SMB_STATUS_UNKNOWN	0x13
#define AMD_SMB_STATUS_ACC_DENY	0x17
#define AMD_SMB_STATUS_TIMEOUT	0x18
#define AMD_SMB_STATUS_NOTSUP	0x19
#define AMD_SMB_STATUS_BUSY	0x1A
#define AMD_SMB_STATUS_PEC	0x1F

#define AMD_SMB_PRTCL_WRITE		0x00
#define AMD_SMB_PRTCL_READ		0x01
#define AMD_SMB_PRTCL_QUICK		0x02
#define AMD_SMB_PRTCL_BYTE		0x04
#define AMD_SMB_PRTCL_BYTE_DATA		0x06
#define AMD_SMB_PRTCL_WORD_DATA		0x08
#define AMD_SMB_PRTCL_BLOCK_DATA	0x0a
#define AMD_SMB_PRTCL_PROC_CALL		0x0c
#define AMD_SMB_PRTCL_BLOCK_PROC_CALL	0x0d
#define AMD_SMB_PRTCL_I2C_BLOCK_DATA	0x4a
#define AMD_SMB_PRTCL_PEC		0x80


static s32 amd8111_access(struct i2c_adapter * adap, u16 addr,
		unsigned short flags, char read_write, u8 command, int size,
		union i2c_smbus_data * data)
{
	struct amd_smbus *smbus = adap->algo_data;
	unsigned char protocol, len, pec, temp[2];
	int i;

	protocol = (read_write == I2C_SMBUS_READ) ? AMD_SMB_PRTCL_READ
						  : AMD_SMB_PRTCL_WRITE;
	pec = (flags & I2C_CLIENT_PEC) ? AMD_SMB_PRTCL_PEC : 0;

	switch (size) {
		case I2C_SMBUS_QUICK:
			protocol |= AMD_SMB_PRTCL_QUICK;
			read_write = I2C_SMBUS_WRITE;
			break;

		case I2C_SMBUS_BYTE:
			if (read_write == I2C_SMBUS_WRITE)
				amd_ec_write(smbus, AMD_SMB_CMD, command);
			protocol |= AMD_SMB_PRTCL_BYTE;
			break;

		case I2C_SMBUS_BYTE_DATA:
			amd_ec_write(smbus, AMD_SMB_CMD, command);
			if (read_write == I2C_SMBUS_WRITE)
				amd_ec_write(smbus, AMD_SMB_DATA, data->byte);
			protocol |= AMD_SMB_PRTCL_BYTE_DATA;
			break;

		case I2C_SMBUS_WORD_DATA:
			amd_ec_write(smbus, AMD_SMB_CMD, command);
			if (read_write == I2C_SMBUS_WRITE) {
				amd_ec_write(smbus, AMD_SMB_DATA,
					     data->word & 0xff);
				amd_ec_write(smbus, AMD_SMB_DATA + 1,
					     data->word >> 8);
			}
			protocol |= AMD_SMB_PRTCL_WORD_DATA | pec;
			break;

		case I2C_SMBUS_BLOCK_DATA:
			amd_ec_write(smbus, AMD_SMB_CMD, command);
			if (read_write == I2C_SMBUS_WRITE) {
				len = min_t(u8, data->block[0],
					    I2C_SMBUS_BLOCK_MAX);
				amd_ec_write(smbus, AMD_SMB_BCNT, len);
				for (i = 0; i < len; i++)
					amd_ec_write(smbus, AMD_SMB_DATA + i,
						     data->block[i + 1]);
			}
			protocol |= AMD_SMB_PRTCL_BLOCK_DATA | pec;
			break;

		case I2C_SMBUS_I2C_BLOCK_DATA:
			len = min_t(u8, data->block[0],
				    I2C_SMBUS_BLOCK_MAX);
			amd_ec_write(smbus, AMD_SMB_CMD, command);
			amd_ec_write(smbus, AMD_SMB_BCNT, len);
			if (read_write == I2C_SMBUS_WRITE)
				for (i = 0; i < len; i++)
					amd_ec_write(smbus, AMD_SMB_DATA + i,
						     data->block[i + 1]);
			protocol |= AMD_SMB_PRTCL_I2C_BLOCK_DATA;
			break;

		case I2C_SMBUS_PROC_CALL:
			amd_ec_write(smbus, AMD_SMB_CMD, command);
			amd_ec_write(smbus, AMD_SMB_DATA, data->word & 0xff);
			amd_ec_write(smbus, AMD_SMB_DATA + 1, data->word >> 8);
			protocol = AMD_SMB_PRTCL_PROC_CALL | pec;
			read_write = I2C_SMBUS_READ;
			break;

		case I2C_SMBUS_BLOCK_PROC_CALL:
			len = min_t(u8, data->block[0], 31);
			amd_ec_write(smbus, AMD_SMB_CMD, command);
			amd_ec_write(smbus, AMD_SMB_BCNT, len);
			for (i = 0; i < len; i++)
				amd_ec_write(smbus, AMD_SMB_DATA + i,
					     data->block[i + 1]);
			protocol = AMD_SMB_PRTCL_BLOCK_PROC_CALL | pec;
			read_write = I2C_SMBUS_READ;
			break;

		default:
			dev_warn(&adap->dev, "Unsupported transaction %d\n", size);
			return -1;
	}

	amd_ec_write(smbus, AMD_SMB_ADDR, addr << 1);
	amd_ec_write(smbus, AMD_SMB_PRTCL, protocol);

	amd_ec_read(smbus, AMD_SMB_STS, temp + 0);

	if (~temp[0] & AMD_SMB_STS_DONE) {
		udelay(500);
		amd_ec_read(smbus, AMD_SMB_STS, temp + 0);
	}

	if (~temp[0] & AMD_SMB_STS_DONE) {
		msleep(1);
		amd_ec_read(smbus, AMD_SMB_STS, temp + 0);
	}

	if ((~temp[0] & AMD_SMB_STS_DONE) || (temp[0] & AMD_SMB_STS_STATUS))
		return -1;

	if (read_write == I2C_SMBUS_WRITE)
		return 0;

	switch (size) {
		case I2C_SMBUS_BYTE:
		case I2C_SMBUS_BYTE_DATA:
			amd_ec_read(smbus, AMD_SMB_DATA, &data->byte);
			break;

		case I2C_SMBUS_WORD_DATA:
		case I2C_SMBUS_PROC_CALL:
			amd_ec_read(smbus, AMD_SMB_DATA, temp + 0);
			amd_ec_read(smbus, AMD_SMB_DATA + 1, temp + 1);
			data->word = (temp[1] << 8) | temp[0];
			break;

		case I2C_SMBUS_BLOCK_DATA:
		case I2C_SMBUS_BLOCK_PROC_CALL:
			amd_ec_read(smbus, AMD_SMB_BCNT, &len);
			len = min_t(u8, len, I2C_SMBUS_BLOCK_MAX);
		case I2C_SMBUS_I2C_BLOCK_DATA:
			for (i = 0; i < len; i++)
				amd_ec_read(smbus, AMD_SMB_DATA + i,
					    data->block + i + 1);
			data->block[0] = len;
			break;
	}

	return 0;
}


static u32 amd8111_func(struct i2c_adapter *adapter)
{
	return	I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
		I2C_FUNC_SMBUS_BYTE_DATA |
		I2C_FUNC_SMBUS_WORD_DATA | I2C_FUNC_SMBUS_BLOCK_DATA |
		I2C_FUNC_SMBUS_PROC_CALL | I2C_FUNC_SMBUS_BLOCK_PROC_CALL |
		I2C_FUNC_SMBUS_I2C_BLOCK | I2C_FUNC_SMBUS_HWPEC_CALC;
}

static const struct i2c_algorithm smbus_algorithm = {
	.smbus_xfer = amd8111_access,
	.functionality = amd8111_func,
};


static struct pci_device_id amd8111_ids[] = {
	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS2) },
	{ 0, }
};

MODULE_DEVICE_TABLE (pci, amd8111_ids);

static int __devinit amd8111_probe(struct pci_dev *dev,
		const struct pci_device_id *id)
{
	struct amd_smbus *smbus;
	int error;

	if (!(pci_resource_flags(dev, 0) & IORESOURCE_IO))
		return -ENODEV;

	smbus = kzalloc(sizeof(struct amd_smbus), GFP_KERNEL);
	if (!smbus)
		return -ENOMEM;

	smbus->dev = dev;
	smbus->base = pci_resource_start(dev, 0);
	smbus->size = pci_resource_len(dev, 0);

	if (!request_region(smbus->base, smbus->size, amd8111_driver.name)) {
		error = -EBUSY;
		goto out_kfree;
	}

	smbus->adapter.owner = THIS_MODULE;
	snprintf(smbus->adapter.name, I2C_NAME_SIZE,
		"SMBus2 AMD8111 adapter at %04x", smbus->base);
	smbus->adapter.id = I2C_HW_SMBUS_AMD8111;
	smbus->adapter.class = I2C_CLASS_HWMON;
	smbus->adapter.algo = &smbus_algorithm;
	smbus->adapter.algo_data = smbus;

	/* set up the driverfs linkage to our parent device */
	smbus->adapter.dev.parent = &dev->dev;

	pci_write_config_dword(smbus->dev, AMD_PCI_MISC, 0);
	error = i2c_add_adapter(&smbus->adapter);
	if (error)
		goto out_release_region;

	pci_set_drvdata(dev, smbus);
	return 0;

 out_release_region:
	release_region(smbus->base, smbus->size);
 out_kfree:
	kfree(smbus);
	return error;
}

static void __devexit amd8111_remove(struct pci_dev *dev)
{
	struct amd_smbus *smbus = pci_get_drvdata(dev);

	i2c_del_adapter(&smbus->adapter);
	release_region(smbus->base, smbus->size);
	kfree(smbus);
}

static struct pci_driver amd8111_driver = {
	.name		= "amd8111_smbus2",
	.id_table	= amd8111_ids,
	.probe		= amd8111_probe,
	.remove		= __devexit_p(amd8111_remove),
};

static int __init i2c_amd8111_init(void)
{
	return pci_register_driver(&amd8111_driver);
}

static void __exit i2c_amd8111_exit(void)
{
	pci_unregister_driver(&amd8111_driver);
}

module_init(i2c_amd8111_init);
module_exit(i2c_amd8111_exit);
Commit	Line	Data
1da177e4 LT	1	/*
	2	* SMBus 2.0 driver for AMD-8111 IO-Hub.
	3	*
	4	* Copyright (c) 2002 Vojtech Pavlik
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation version 2.
	9	*/
	10
1da177e4 LT	11	#include <linux/module.h>
	12	#include <linux/pci.h>
	13	#include <linux/kernel.h>
	14	#include <linux/stddef.h>
1da177e4 LT	15	#include <linux/ioport.h>
	16	#include <linux/init.h>
	17	#include <linux/i2c.h>
	18	#include <linux/delay.h>
	19	#include <asm/io.h>
	20
	21	MODULE_LICENSE("GPL");
	22	MODULE_AUTHOR ("Vojtech Pavlik <vojtech@suse.cz>");
	23	MODULE_DESCRIPTION("AMD8111 SMBus 2.0 driver");
	24
	25	struct amd_smbus {
	26	struct pci_dev *dev;
	27	struct i2c_adapter adapter;
	28	int base;
	29	int size;
	30	};
	31
d6072f84 JD	32	static struct pci_driver amd8111_driver;
d6072f84 JD	33
1da177e4 LT	34	/*
	35	* AMD PCI control registers definitions.
	36	*/
	37
	38	#define AMD_PCI_MISC 0x48
	39
	40	#define AMD_PCI_MISC_SCI 0x04 /* deliver SCI */
	41	#define AMD_PCI_MISC_INT 0x02 /* deliver PCI IRQ */
	42	#define AMD_PCI_MISC_SPEEDUP 0x01 /* 16x clock speedup */
	43
	44	/*
	45	* ACPI 2.0 chapter 13 PCI interface definitions.
	46	*/
	47
	48	#define AMD_EC_DATA 0x00 /* data register */
	49	#define AMD_EC_SC 0x04 /* status of controller */
	50	#define AMD_EC_CMD 0x04 /* command register */
	51	#define AMD_EC_ICR 0x08 /* interrupt control register */
	52
	53	#define AMD_EC_SC_SMI 0x04 /* smi event pending */
	54	#define AMD_EC_SC_SCI 0x02 /* sci event pending */
	55	#define AMD_EC_SC_BURST 0x01 /* burst mode enabled */
	56	#define AMD_EC_SC_CMD 0x08 /* byte in data reg is command */
	57	#define AMD_EC_SC_IBF 0x02 /* data ready for embedded controller */
	58	#define AMD_EC_SC_OBF 0x01 /* data ready for host */
	59
	60	#define AMD_EC_CMD_RD 0x80 /* read EC */
	61	#define AMD_EC_CMD_WR 0x81 /* write EC */
	62	#define AMD_EC_CMD_BE 0x82 /* enable burst mode */
	63	#define AMD_EC_CMD_BD 0x83 /* disable burst mode */
	64	#define AMD_EC_CMD_QR 0x84 /* query EC */
	65
	66	/*
	67	* ACPI 2.0 chapter 13 access of registers of the EC
	68	*/
	69
	70	static unsigned int amd_ec_wait_write(struct amd_smbus *smbus)
	71	{
	72	int timeout = 500;
	73
	74	while (timeout-- && (inb(smbus->base + AMD_EC_SC) & AMD_EC_SC_IBF))
	75	udelay(1);
	76
	77	if (!timeout) {
88b9e750 JD	78	dev_warn(&smbus->dev->dev,
88b9e750 JD	79	"Timeout while waiting for IBF to clear\n");
1da177e4 LT	80	return -1;
	81	}
	82
	83	return 0;
	84	}
	85
	86	static unsigned int amd_ec_wait_read(struct amd_smbus *smbus)
	87	{
	88	int timeout = 500;
	89
	90	while (timeout-- && (~inb(smbus->base + AMD_EC_SC) & AMD_EC_SC_OBF))
	91	udelay(1);
	92
	93	if (!timeout) {
88b9e750 JD	94	dev_warn(&smbus->dev->dev,
88b9e750 JD	95	"Timeout while waiting for OBF to set\n");
1da177e4 LT	96	return -1;
	97	}
	98
	99	return 0;
	100	}
	101
88b9e750 JD	102	static unsigned int amd_ec_read(struct amd_smbus *smbus, unsigned char address,
88b9e750 JD	103	unsigned char *data)
1da177e4 LT	104	{
	105	if (amd_ec_wait_write(smbus))
	106	return -1;
	107	outb(AMD_EC_CMD_RD, smbus->base + AMD_EC_CMD);
	108
	109	if (amd_ec_wait_write(smbus))
	110	return -1;
	111	outb(address, smbus->base + AMD_EC_DATA);
	112
	113	if (amd_ec_wait_read(smbus))
	114	return -1;
	115	*data = inb(smbus->base + AMD_EC_DATA);
	116
	117	return 0;
	118	}
	119
88b9e750 JD	120	static unsigned int amd_ec_write(struct amd_smbus *smbus, unsigned char address,
88b9e750 JD	121	unsigned char data)
1da177e4 LT	122	{
	123	if (amd_ec_wait_write(smbus))
	124	return -1;
	125	outb(AMD_EC_CMD_WR, smbus->base + AMD_EC_CMD);
	126
	127	if (amd_ec_wait_write(smbus))
	128	return -1;
	129	outb(address, smbus->base + AMD_EC_DATA);
	130
	131	if (amd_ec_wait_write(smbus))
	132	return -1;
	133	outb(data, smbus->base + AMD_EC_DATA);
	134
	135	return 0;
	136	}
	137
	138	/*
	139	* ACPI 2.0 chapter 13 SMBus 2.0 EC register model
	140	*/
	141
	142	#define AMD_SMB_PRTCL 0x00 /* protocol, PEC */
	143	#define AMD_SMB_STS 0x01 /* status */
	144	#define AMD_SMB_ADDR 0x02 /* address */
	145	#define AMD_SMB_CMD 0x03 /* command */
	146	#define AMD_SMB_DATA 0x04 /* 32 data registers */
	147	#define AMD_SMB_BCNT 0x24 /* number of data bytes */
	148	#define AMD_SMB_ALRM_A 0x25 /* alarm address */
	149	#define AMD_SMB_ALRM_D 0x26 /* 2 bytes alarm data */
	150
	151	#define AMD_SMB_STS_DONE 0x80
	152	#define AMD_SMB_STS_ALRM 0x40
	153	#define AMD_SMB_STS_RES 0x20
	154	#define AMD_SMB_STS_STATUS 0x1f
	155
	156	#define AMD_SMB_STATUS_OK 0x00
	157	#define AMD_SMB_STATUS_FAIL 0x07
	158	#define AMD_SMB_STATUS_DNAK 0x10
	159	#define AMD_SMB_STATUS_DERR 0x11
	160	#define AMD_SMB_STATUS_CMD_DENY 0x12
	161	#define AMD_SMB_STATUS_UNKNOWN 0x13
	162	#define AMD_SMB_STATUS_ACC_DENY 0x17
	163	#define AMD_SMB_STATUS_TIMEOUT 0x18
	164	#define AMD_SMB_STATUS_NOTSUP 0x19
	165	#define AMD_SMB_STATUS_BUSY 0x1A
	166	#define AMD_SMB_STATUS_PEC 0x1F
	167
	168	#define AMD_SMB_PRTCL_WRITE 0x00
	169	#define AMD_SMB_PRTCL_READ 0x01
	170	#define AMD_SMB_PRTCL_QUICK 0x02
	171	#define AMD_SMB_PRTCL_BYTE 0x04
	172	#define AMD_SMB_PRTCL_BYTE_DATA 0x06
	173	#define AMD_SMB_PRTCL_WORD_DATA 0x08
	174	#define AMD_SMB_PRTCL_BLOCK_DATA 0x0a
	175	#define AMD_SMB_PRTCL_PROC_CALL 0x0c
	176	#define AMD_SMB_PRTCL_BLOCK_PROC_CALL 0x0d
	177	#define AMD_SMB_PRTCL_I2C_BLOCK_DATA 0x4a
	178	#define AMD_SMB_PRTCL_PEC 0x80
	179
	180
88b9e750 JD	181	static s32 amd8111_access(struct i2c_adapter * adap, u16 addr,
	182	unsigned short flags, char read_write, u8 command, int size,
	183	union i2c_smbus_data * data)
1da177e4 LT	184	{
	185	struct amd_smbus *smbus = adap->algo_data;
	186	unsigned char protocol, len, pec, temp[2];
	187	int i;
	188
88b9e750 JD	189	protocol = (read_write == I2C_SMBUS_READ) ? AMD_SMB_PRTCL_READ
88b9e750 JD	190	: AMD_SMB_PRTCL_WRITE;
1da177e4 LT	191	pec = (flags & I2C_CLIENT_PEC) ? AMD_SMB_PRTCL_PEC : 0;
	192
	193	switch (size) {
1da177e4 LT	194	case I2C_SMBUS_QUICK:
	195	protocol \|= AMD_SMB_PRTCL_QUICK;
	196	read_write = I2C_SMBUS_WRITE;
	197	break;
	198
	199	case I2C_SMBUS_BYTE:
	200	if (read_write == I2C_SMBUS_WRITE)
	201	amd_ec_write(smbus, AMD_SMB_CMD, command);
	202	protocol \|= AMD_SMB_PRTCL_BYTE;
	203	break;
	204
	205	case I2C_SMBUS_BYTE_DATA:
	206	amd_ec_write(smbus, AMD_SMB_CMD, command);
	207	if (read_write == I2C_SMBUS_WRITE)
	208	amd_ec_write(smbus, AMD_SMB_DATA, data->byte);
	209	protocol \|= AMD_SMB_PRTCL_BYTE_DATA;
	210	break;
	211
	212	case I2C_SMBUS_WORD_DATA:
	213	amd_ec_write(smbus, AMD_SMB_CMD, command);
	214	if (read_write == I2C_SMBUS_WRITE) {
88b9e750 JD	215	amd_ec_write(smbus, AMD_SMB_DATA,
	216	data->word & 0xff);
	217	amd_ec_write(smbus, AMD_SMB_DATA + 1,
	218	data->word >> 8);
1da177e4 LT	219	}
	220	protocol \|= AMD_SMB_PRTCL_WORD_DATA \| pec;
	221	break;
	222
	223	case I2C_SMBUS_BLOCK_DATA:
	224	amd_ec_write(smbus, AMD_SMB_CMD, command);
	225	if (read_write == I2C_SMBUS_WRITE) {
88b9e750 JD	226	len = min_t(u8, data->block[0],
88b9e750 JD	227	I2C_SMBUS_BLOCK_MAX);
1da177e4 LT	228	amd_ec_write(smbus, AMD_SMB_BCNT, len);
1da177e4 LT	229	for (i = 0; i < len; i++)
88b9e750 JD	230	amd_ec_write(smbus, AMD_SMB_DATA + i,
88b9e750 JD	231	data->block[i + 1]);
1da177e4 LT	232	}
	233	protocol \|= AMD_SMB_PRTCL_BLOCK_DATA \| pec;
	234	break;
	235
	236	case I2C_SMBUS_I2C_BLOCK_DATA:
88b9e750 JD	237	len = min_t(u8, data->block[0],
88b9e750 JD	238	I2C_SMBUS_BLOCK_MAX);
1da177e4 LT	239	amd_ec_write(smbus, AMD_SMB_CMD, command);
	240	amd_ec_write(smbus, AMD_SMB_BCNT, len);
	241	if (read_write == I2C_SMBUS_WRITE)
	242	for (i = 0; i < len; i++)
88b9e750 JD	243	amd_ec_write(smbus, AMD_SMB_DATA + i,
88b9e750 JD	244	data->block[i + 1]);
1da177e4 LT	245	protocol \|= AMD_SMB_PRTCL_I2C_BLOCK_DATA;
	246	break;
	247
	248	case I2C_SMBUS_PROC_CALL:
	249	amd_ec_write(smbus, AMD_SMB_CMD, command);
88b9e750	250	amd_ec_write(smbus, AMD_SMB_DATA, data->word & 0xff);
1da177e4 LT	251	amd_ec_write(smbus, AMD_SMB_DATA + 1, data->word >> 8);
	252	protocol = AMD_SMB_PRTCL_PROC_CALL \| pec;
	253	read_write = I2C_SMBUS_READ;
	254	break;
	255
	256	case I2C_SMBUS_BLOCK_PROC_CALL:
1da177e4 LT	257	len = min_t(u8, data->block[0], 31);
	258	amd_ec_write(smbus, AMD_SMB_CMD, command);
	259	amd_ec_write(smbus, AMD_SMB_BCNT, len);
	260	for (i = 0; i < len; i++)
88b9e750 JD	261	amd_ec_write(smbus, AMD_SMB_DATA + i,
88b9e750 JD	262	data->block[i + 1]);
1da177e4 LT	263	protocol = AMD_SMB_PRTCL_BLOCK_PROC_CALL \| pec;
	264	read_write = I2C_SMBUS_READ;
	265	break;
	266
1da177e4 LT	267	default:
	268	dev_warn(&adap->dev, "Unsupported transaction %d\n", size);
	269	return -1;
	270	}
	271
	272	amd_ec_write(smbus, AMD_SMB_ADDR, addr << 1);
	273	amd_ec_write(smbus, AMD_SMB_PRTCL, protocol);
	274
	275	amd_ec_read(smbus, AMD_SMB_STS, temp + 0);
	276
	277	if (~temp[0] & AMD_SMB_STS_DONE) {
	278	udelay(500);
	279	amd_ec_read(smbus, AMD_SMB_STS, temp + 0);
	280	}
	281
	282	if (~temp[0] & AMD_SMB_STS_DONE) {
	283	msleep(1);
	284	amd_ec_read(smbus, AMD_SMB_STS, temp + 0);
	285	}
	286
	287	if ((~temp[0] & AMD_SMB_STS_DONE) \|\| (temp[0] & AMD_SMB_STS_STATUS))
	288	return -1;
	289
	290	if (read_write == I2C_SMBUS_WRITE)
	291	return 0;
	292
	293	switch (size) {
1da177e4 LT	294	case I2C_SMBUS_BYTE:
	295	case I2C_SMBUS_BYTE_DATA:
	296	amd_ec_read(smbus, AMD_SMB_DATA, &data->byte);
	297	break;
	298
	299	case I2C_SMBUS_WORD_DATA:
	300	case I2C_SMBUS_PROC_CALL:
	301	amd_ec_read(smbus, AMD_SMB_DATA, temp + 0);
	302	amd_ec_read(smbus, AMD_SMB_DATA + 1, temp + 1);
	303	data->word = (temp[1] << 8) \| temp[0];
	304	break;
	305
	306	case I2C_SMBUS_BLOCK_DATA:
	307	case I2C_SMBUS_BLOCK_PROC_CALL:
	308	amd_ec_read(smbus, AMD_SMB_BCNT, &len);
88b9e750	309	len = min_t(u8, len, I2C_SMBUS_BLOCK_MAX);
1da177e4 LT	310	case I2C_SMBUS_I2C_BLOCK_DATA:
1da177e4 LT	311	for (i = 0; i < len; i++)
88b9e750 JD	312	amd_ec_read(smbus, AMD_SMB_DATA + i,
88b9e750 JD	313	data->block + i + 1);
1da177e4 LT	314	data->block[0] = len;
	315	break;
	316	}
	317
	318	return 0;
	319	}
	320
	321
	322	static u32 amd8111_func(struct i2c_adapter *adapter)
	323	{
88b9e750 JD	324	return I2C_FUNC_SMBUS_QUICK \| I2C_FUNC_SMBUS_BYTE \|
88b9e750 JD	325	I2C_FUNC_SMBUS_BYTE_DATA \|
1da177e4 LT	326	I2C_FUNC_SMBUS_WORD_DATA \| I2C_FUNC_SMBUS_BLOCK_DATA \|
	327	I2C_FUNC_SMBUS_PROC_CALL \| I2C_FUNC_SMBUS_BLOCK_PROC_CALL \|
	328	I2C_FUNC_SMBUS_I2C_BLOCK \| I2C_FUNC_SMBUS_HWPEC_CALC;
	329	}
	330
8f9082c5	331	static const struct i2c_algorithm smbus_algorithm = {
1da177e4 LT	332	.smbus_xfer = amd8111_access,
	333	.functionality = amd8111_func,
	334	};
	335
	336
	337	static struct pci_device_id amd8111_ids[] = {
	338	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS2) },
	339	{ 0, }
	340	};
	341
	342	MODULE_DEVICE_TABLE (pci, amd8111_ids);
	343
88b9e750 JD	344	static int __devinit amd8111_probe(struct pci_dev *dev,
88b9e750 JD	345	const struct pci_device_id *id)
1da177e4 LT	346	{
1da177e4 LT	347	struct amd_smbus *smbus;
88b9e750	348	int error;
1da177e4	349
88b9e750	350	if (!(pci_resource_flags(dev, 0) & IORESOURCE_IO))
1da177e4 LT	351	return -ENODEV;
1da177e4 LT	352
5263ebb5	353	smbus = kzalloc(sizeof(struct amd_smbus), GFP_KERNEL);
1da177e4 LT	354	if (!smbus)
1da177e4 LT	355	return -ENOMEM;
1da177e4 LT	356
	357	smbus->dev = dev;
	358	smbus->base = pci_resource_start(dev, 0);
	359	smbus->size = pci_resource_len(dev, 0);
	360
88b9e750 JD	361	if (!request_region(smbus->base, smbus->size, amd8111_driver.name)) {
88b9e750 JD	362	error = -EBUSY;
1da177e4	363	goto out_kfree;
88b9e750	364	}
1da177e4 LT	365
	366	smbus->adapter.owner = THIS_MODULE;
	367	snprintf(smbus->adapter.name, I2C_NAME_SIZE,
	368	"SMBus2 AMD8111 adapter at %04x", smbus->base);
9ace555d	369	smbus->adapter.id = I2C_HW_SMBUS_AMD8111;
1da177e4 LT	370	smbus->adapter.class = I2C_CLASS_HWMON;
	371	smbus->adapter.algo = &smbus_algorithm;
	372	smbus->adapter.algo_data = smbus;
	373
	374	/* set up the driverfs linkage to our parent device */
	375	smbus->adapter.dev.parent = &dev->dev;
	376
88b9e750	377	pci_write_config_dword(smbus->dev, AMD_PCI_MISC, 0);
1da177e4 LT	378	error = i2c_add_adapter(&smbus->adapter);
	379	if (error)
	380	goto out_release_region;
	381
1da177e4 LT	382	pci_set_drvdata(dev, smbus);
	383	return 0;
	384
	385	out_release_region:
	386	release_region(smbus->base, smbus->size);
	387	out_kfree:
	388	kfree(smbus);
88b9e750	389	return error;
1da177e4 LT	390	}
1da177e4 LT	391
1da177e4 LT	392	static void __devexit amd8111_remove(struct pci_dev *dev)
	393	{
	394	struct amd_smbus *smbus = pci_get_drvdata(dev);
	395
	396	i2c_del_adapter(&smbus->adapter);
	397	release_region(smbus->base, smbus->size);
	398	kfree(smbus);
	399	}
	400
	401	static struct pci_driver amd8111_driver = {
	402	.name = "amd8111_smbus2",
	403	.id_table = amd8111_ids,
	404	.probe = amd8111_probe,
	405	.remove = __devexit_p(amd8111_remove),
	406	};
	407
	408	static int __init i2c_amd8111_init(void)
	409	{
	410	return pci_register_driver(&amd8111_driver);
	411	}
	412
1da177e4 LT	413	static void __exit i2c_amd8111_exit(void)
	414	{
	415	pci_unregister_driver(&amd8111_driver);
	416	}
	417
	418	module_init(i2c_amd8111_init);
	419	module_exit(i2c_amd8111_exit);