[net-next-2.6.git] / drivers / hwmon / hwmon-vid.c

/*
 * hwmon-vid.c - VID/VRM/VRD voltage conversions
 *
 * Copyright (c) 2004 Rudolf Marek <r.marek@assembler.cz>
 *
 * Partly imported from i2c-vid.h of the lm_sensors project
 * Copyright (c) 2002 Mark D. Studebaker <mdsxyz123@yahoo.com>
 * With assistance from Trent Piepho <xyzzy@speakeasy.org>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/hwmon-vid.h>

/*
 * Common code for decoding VID pins.
 *
 * References:
 *
 * For VRM 8.4 to 9.1, "VRM x.y DC-DC Converter Design Guidelines",
 * available at http://developer.intel.com/.
 *
 * For VRD 10.0 and up, "VRD x.y Design Guide",
 * available at http://developer.intel.com/.
 *
 * AMD Athlon 64 and AMD Opteron Processors, AMD Publication 26094,
 * http://support.amd.com/us/Processor_TechDocs/26094.PDF 
 * Table 74. VID Code Voltages
 * This corresponds to an arbitrary VRM code of 24 in the functions below.
 * These CPU models (K8 revision <= E) have 5 VID pins. See also:
 * Revision Guide for AMD Athlon 64 and AMD Opteron Processors, AMD Publication 25759,
 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25759.pdf
 *
 * AMD NPT Family 0Fh Processors, AMD Publication 32559,
 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/32559.pdf
 * Table 71. VID Code Voltages
 * This corresponds to an arbitrary VRM code of 25 in the functions below.
 * These CPU models (K8 revision >= F) have 6 VID pins. See also:
 * Revision Guide for AMD NPT Family 0Fh Processors, AMD Publication 33610,
 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
 *
 * The 17 specification is in fact Intel Mobile Voltage Positioning -
 * (IMVP-II). You can find more information in the datasheet of Max1718
 * http://www.maxim-ic.com/quick_view2.cfm/qv_pk/2452
 *
 * The 13 specification corresponds to the Intel Pentium M series. There
 * doesn't seem to be any named specification for these. The conversion
 * tables are detailed directly in the various Pentium M datasheets:
 * http://www.intel.com/design/intarch/pentiumm/docs_pentiumm.htm
 *
 * The 14 specification corresponds to Intel Core series. There
 * doesn't seem to be any named specification for these. The conversion
 * tables are detailed directly in the various Pentium Core datasheets:
 * http://www.intel.com/design/mobile/datashts/309221.htm
 *
 * The 110 (VRM 11) specification corresponds to Intel Conroe based series.
 * http://www.intel.com/design/processor/applnots/313214.htm
 */

/*
 * vrm is the VRM/VRD document version multiplied by 10.
 * val is the 4-bit or more VID code.
 * Returned value is in mV to avoid floating point in the kernel.
 * Some VID have some bits in uV scale, this is rounded to mV.
 */
int vid_from_reg(int val, u8 vrm)
{
	int vid;

	switch(vrm) {

	case 100:               /* VRD 10.0 */
		/* compute in uV, round to mV */
		val &= 0x3f;
		if((val & 0x1f) == 0x1f)
			return 0;
		if((val & 0x1f) <= 0x09 || val == 0x0a)
			vid = 1087500 - (val & 0x1f) * 25000;
		else
			vid = 1862500 - (val & 0x1f) * 25000;
		if(val & 0x20)
			vid -= 12500;
		return((vid + 500) / 1000);

	case 110:		/* Intel Conroe */
				/* compute in uV, round to mV */
		val &= 0xff;
		if (val < 0x02 || val > 0xb2)
			return 0;
		return((1600000 - (val - 2) * 6250 + 500) / 1000);

	case 24:		/* Athlon64 & Opteron */
		val &= 0x1f;
		if (val == 0x1f)
			return 0;
				/* fall through */
	case 25:		/* AMD NPT 0Fh */
		val &= 0x3f;
		return (val < 32) ? 1550 - 25 * val
			: 775 - (25 * (val - 31)) / 2;

	case 91:		/* VRM 9.1 */
	case 90:		/* VRM 9.0 */
		val &= 0x1f;
		return(val == 0x1f ? 0 :
		                       1850 - val * 25);

	case 85:		/* VRM 8.5 */
		val &= 0x1f;
		return((val & 0x10  ? 25 : 0) +
		       ((val & 0x0f) > 0x04 ? 2050 : 1250) -
		       ((val & 0x0f) * 50));

	case 84:		/* VRM 8.4 */
		val &= 0x0f;
				/* fall through */
	case 82:		/* VRM 8.2 */
		val &= 0x1f;
		return(val == 0x1f ? 0 :
		       val & 0x10  ? 5100 - (val) * 100 :
		                     2050 - (val) * 50);
	case 17:		/* Intel IMVP-II */
		val &= 0x1f;
		return(val & 0x10 ? 975 - (val & 0xF) * 25 :
				    1750 - val * 50);
	case 13:
		val &= 0x3f;
		return(1708 - val * 16);
	case 14:		/* Intel Core */
				/* compute in uV, round to mV */
		val &= 0x7f;
		return(val > 0x77 ? 0 : (1500000 - (val * 12500) + 500) / 1000);
	default:		/* report 0 for unknown */
		if (vrm)
			printk(KERN_WARNING "hwmon-vid: Requested unsupported "
			       "VRM version (%u)\n", (unsigned int)vrm);
		return 0;
	}
}


/*
 * After this point is the code to automatically determine which
 * VRM/VRD specification should be used depending on the CPU.
 */

struct vrm_model {
	u8 vendor;
	u8 eff_family;
	u8 eff_model;
	u8 eff_stepping;
	u8 vrm_type;
};

#define ANY 0xFF

#ifdef CONFIG_X86

/*
 * The stepping parameter is highest acceptable stepping for current line.
 * The model match must be exact for 4-bit values. For model values 0x10
 * and above (extended model), all models below the parameter will match.
 */

static struct vrm_model vrm_models[] = {
	{X86_VENDOR_AMD, 0x6, ANY, ANY, 90},		/* Athlon Duron etc */
	{X86_VENDOR_AMD, 0xF, 0x3F, ANY, 24},		/* Athlon 64, Opteron */
	/* In theory, all NPT family 0Fh processors have 6 VID pins and should
	   thus use vrm 25, however in practice not all mainboards route the
	   6th VID pin because it is never needed. So we use the 5 VID pin
	   variant (vrm 24) for the models which exist today. */
	{X86_VENDOR_AMD, 0xF, 0x7F, ANY, 24},		/* NPT family 0Fh */
	{X86_VENDOR_AMD, 0xF, ANY, ANY, 25},		/* future fam. 0Fh */
	{X86_VENDOR_AMD, 0x10, ANY, ANY, 25},		/* NPT family 10h */

	{X86_VENDOR_INTEL, 0x6, 0x9, ANY, 13},		/* Pentium M (130 nm) */
	{X86_VENDOR_INTEL, 0x6, 0xB, ANY, 85},		/* Tualatin */
	{X86_VENDOR_INTEL, 0x6, 0xD, ANY, 13},		/* Pentium M (90 nm) */
	{X86_VENDOR_INTEL, 0x6, 0xE, ANY, 14},		/* Intel Core (65 nm) */
	{X86_VENDOR_INTEL, 0x6, 0xF, ANY, 110},		/* Intel Conroe */
	{X86_VENDOR_INTEL, 0x6, ANY, ANY, 82},		/* any P6 */
	{X86_VENDOR_INTEL, 0xF, 0x0, ANY, 90},		/* P4 */
	{X86_VENDOR_INTEL, 0xF, 0x1, ANY, 90},		/* P4 Willamette */
	{X86_VENDOR_INTEL, 0xF, 0x2, ANY, 90},		/* P4 Northwood */
	{X86_VENDOR_INTEL, 0xF, ANY, ANY, 100},		/* Prescott and above assume VRD 10 */

	{X86_VENDOR_CENTAUR, 0x6, 0x7, ANY, 85},	/* Eden ESP/Ezra */
	{X86_VENDOR_CENTAUR, 0x6, 0x8, 0x7, 85},	/* Ezra T */
	{X86_VENDOR_CENTAUR, 0x6, 0x9, 0x7, 85},	/* Nemiah */
	{X86_VENDOR_CENTAUR, 0x6, 0x9, ANY, 17},	/* C3-M, Eden-N */
	{X86_VENDOR_CENTAUR, 0x6, 0xA, 0x7, 0},		/* No information */
	{X86_VENDOR_CENTAUR, 0x6, 0xA, ANY, 13},	/* C7, Esther */

	{X86_VENDOR_UNKNOWN, ANY, ANY, ANY, 0}		/* stop here */
};

static u8 find_vrm(u8 eff_family, u8 eff_model, u8 eff_stepping, u8 vendor)
{
	int i = 0;

	while (vrm_models[i].vendor!=X86_VENDOR_UNKNOWN) {
		if (vrm_models[i].vendor==vendor)
			if ((vrm_models[i].eff_family==eff_family)
			 && ((vrm_models[i].eff_model==eff_model) ||
			     (vrm_models[i].eff_model >= 0x10 &&
			      eff_model <= vrm_models[i].eff_model) ||
			     (vrm_models[i].eff_model==ANY)) &&
			     (eff_stepping <= vrm_models[i].eff_stepping))
				return vrm_models[i].vrm_type;
		i++;
	}

	return 0;
}

u8 vid_which_vrm(void)
{
	struct cpuinfo_x86 *c = &cpu_data(0);
	u32 eax;
	u8 eff_family, eff_model, eff_stepping, vrm_ret;

	if (c->x86 < 6)		/* Any CPU with family lower than 6 */
		return 0;	/* doesn't have VID and/or CPUID */

	eax = cpuid_eax(1);
	eff_family = ((eax & 0x00000F00)>>8);
	eff_model  = ((eax & 0x000000F0)>>4);
	eff_stepping = eax & 0xF;
	if (eff_family == 0xF) {	/* use extended model & family */
		eff_family += ((eax & 0x00F00000)>>20);
		eff_model += ((eax & 0x000F0000)>>16)<<4;
	}
	vrm_ret = find_vrm(eff_family, eff_model, eff_stepping, c->x86_vendor);
	if (vrm_ret == 0)
		printk(KERN_INFO "hwmon-vid: Unknown VRM version of your "
		       "x86 CPU\n");
	return vrm_ret;
}

/* and now for something completely different for the non-x86 world */
#else
u8 vid_which_vrm(void)
{
	printk(KERN_INFO "hwmon-vid: Unknown VRM version of your CPU\n");
	return 0;
}
#endif

EXPORT_SYMBOL(vid_from_reg);
EXPORT_SYMBOL(vid_which_vrm);

MODULE_AUTHOR("Rudolf Marek <r.marek@assembler.cz>");

MODULE_DESCRIPTION("hwmon-vid driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4	1	/*
15872212 FM	2	* hwmon-vid.c - VID/VRM/VRD voltage conversions
	3	*
	4	* Copyright (c) 2004 Rudolf Marek <r.marek@assembler.cz>
	5	*
	6	* Partly imported from i2c-vid.h of the lm_sensors project
	7	* Copyright (c) 2002 Mark D. Studebaker <mdsxyz123@yahoo.com>
	8	* With assistance from Trent Piepho <xyzzy@speakeasy.org>
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; either version 2 of the License, or
	13	* (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	23	*/
1da177e4	24
1da177e4 LT	25	#include <linux/module.h>
1da177e4 LT	26	#include <linux/kernel.h>
303760b4	27	#include <linux/hwmon-vid.h>
1da177e4	28
d0f28270	29	/*
15872212 FM	30	* Common code for decoding VID pins.
	31	*
	32	* References:
	33	*
	34	* For VRM 8.4 to 9.1, "VRM x.y DC-DC Converter Design Guidelines",
	35	* available at http://developer.intel.com/.
	36	*
	37	* For VRD 10.0 and up, "VRD x.y Design Guide",
	38	* available at http://developer.intel.com/.
	39	*
cebd7709	40	* AMD Athlon 64 and AMD Opteron Processors, AMD Publication 26094,
631dd1a8	41	* http://support.amd.com/us/Processor_TechDocs/26094.PDF
cebd7709 JD	42	* Table 74. VID Code Voltages
	43	* This corresponds to an arbitrary VRM code of 24 in the functions below.
	44	* These CPU models (K8 revision <= E) have 5 VID pins. See also:
	45	* Revision Guide for AMD Athlon 64 and AMD Opteron Processors, AMD Publication 25759,
	46	* http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25759.pdf
	47	*
	48	* AMD NPT Family 0Fh Processors, AMD Publication 32559,
116d0486 FM	49	* http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/32559.pdf
116d0486 FM	50	* Table 71. VID Code Voltages
cebd7709 JD	51	* This corresponds to an arbitrary VRM code of 25 in the functions below.
	52	* These CPU models (K8 revision >= F) have 6 VID pins. See also:
	53	* Revision Guide for AMD NPT Family 0Fh Processors, AMD Publication 33610,
	54	* http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
15872212	55	*
15872212 FM	56	* The 17 specification is in fact Intel Mobile Voltage Positioning -
	57	* (IMVP-II). You can find more information in the datasheet of Max1718
	58	* http://www.maxim-ic.com/quick_view2.cfm/qv_pk/2452
	59	*
	60	* The 13 specification corresponds to the Intel Pentium M series. There
	61	* doesn't seem to be any named specification for these. The conversion
	62	* tables are detailed directly in the various Pentium M datasheets:
	63	* http://www.intel.com/design/intarch/pentiumm/docs_pentiumm.htm
	64	*
	65	* The 14 specification corresponds to Intel Core series. There
	66	* doesn't seem to be any named specification for these. The conversion
	67	* tables are detailed directly in the various Pentium Core datasheets:
	68	* http://www.intel.com/design/mobile/datashts/309221.htm
	69	*
	70	* The 110 (VRM 11) specification corresponds to Intel Conroe based series.
	71	* http://www.intel.com/design/processor/applnots/313214.htm
	72	*/
	73
	74	/*
	75	* vrm is the VRM/VRD document version multiplied by 10.
	76	* val is the 4-bit or more VID code.
	77	* Returned value is in mV to avoid floating point in the kernel.
	78	* Some VID have some bits in uV scale, this is rounded to mV.
	79	*/
734a12a3	80	int vid_from_reg(int val, u8 vrm)
d0f28270 JD	81	{
	82	int vid;
	83
	84	switch(vrm) {
	85
d0f28270	86	case 100: /* VRD 10.0 */
6af586dc	87	/* compute in uV, round to mV */
177d165d	88	val &= 0x3f;
d0f28270 JD	89	if((val & 0x1f) == 0x1f)
	90	return 0;
	91	if((val & 0x1f) <= 0x09 \|\| val == 0x0a)
6af586dc	92	vid = 1087500 - (val & 0x1f) * 25000;
d0f28270	93	else
6af586dc	94	vid = 1862500 - (val & 0x1f) * 25000;
d0f28270	95	if(val & 0x20)
6af586dc RM	96	vid -= 12500;
6af586dc RM	97	return((vid + 500) / 1000);
d0f28270	98
6af586dc RM	99	case 110: /* Intel Conroe */
	100	/* compute in uV, round to mV */
	101	val &= 0xff;
9fab2d8b	102	if (val < 0x02 \|\| val > 0xb2)
6af586dc RM	103	return 0;
6af586dc RM	104	return((1600000 - (val - 2) * 6250 + 500) / 1000);
116d0486	105
cebd7709 JD	106	case 24: /* Athlon64 & Opteron */
	107	val &= 0x1f;
	108	if (val == 0x1f)
	109	return 0;
	110	/* fall through */
	111	case 25: /* AMD NPT 0Fh */
116d0486 FM	112	val &= 0x3f;
	113	return (val < 32) ? 1550 - 25 * val
	114	: 775 - (25 * (val - 31)) / 2;
d0f28270 JD	115
	116	case 91: /* VRM 9.1 */
	117	case 90: /* VRM 9.0 */
177d165d	118	val &= 0x1f;
d0f28270 JD	119	return(val == 0x1f ? 0 :
	120	1850 - val * 25);
	121
	122	case 85: /* VRM 8.5 */
177d165d	123	val &= 0x1f;
d0f28270 JD	124	return((val & 0x10 ? 25 : 0) +
	125	((val & 0x0f) > 0x04 ? 2050 : 1250) -
	126	((val & 0x0f) * 50));
	127
	128	case 84: /* VRM 8.4 */
	129	val &= 0x0f;
	130	/* fall through */
734a12a3	131	case 82: /* VRM 8.2 */
177d165d	132	val &= 0x1f;
d0f28270 JD	133	return(val == 0x1f ? 0 :
	134	val & 0x10 ? 5100 - (val) * 100 :
	135	2050 - (val) * 50);
734a12a3	136	case 17: /* Intel IMVP-II */
177d165d	137	val &= 0x1f;
734a12a3 RM	138	return(val & 0x10 ? 975 - (val & 0xF) * 25 :
734a12a3 RM	139	1750 - val * 50);
4c537fb2	140	case 13:
177d165d RM	141	val &= 0x3f;
177d165d RM	142	return(1708 - val * 16);
6af586dc RM	143	case 14: /* Intel Core */
	144	/* compute in uV, round to mV */
	145	val &= 0x7f;
	146	return(val > 0x77 ? 0 : (1500000 - (val * 12500) + 500) / 1000);
734a12a3	147	default: /* report 0 for unknown */
45f2acc4 JD	148	if (vrm)
	149	printk(KERN_WARNING "hwmon-vid: Requested unsupported "
	150	"VRM version (%u)\n", (unsigned int)vrm);
734a12a3	151	return 0;
d0f28270 JD	152	}
	153	}
	154
	155
	156	/*
15872212 FM	157	* After this point is the code to automatically determine which
	158	* VRM/VRD specification should be used depending on the CPU.
	159	*/
d0f28270	160
1da177e4 LT	161	struct vrm_model {
	162	u8 vendor;
	163	u8 eff_family;
	164	u8 eff_model;
734a12a3 RM	165	u8 eff_stepping;
734a12a3 RM	166	u8 vrm_type;
1da177e4 LT	167	};
	168
	169	#define ANY 0xFF
	170
	171	#ifdef CONFIG_X86
	172
cebd7709 JD	173	/*
	174	* The stepping parameter is highest acceptable stepping for current line.
	175	* The model match must be exact for 4-bit values. For model values 0x10
	176	* and above (extended model), all models below the parameter will match.
	177	*/
734a12a3	178
1da177e4	179	static struct vrm_model vrm_models[] = {
734a12a3	180	{X86_VENDOR_AMD, 0x6, ANY, ANY, 90}, /* Athlon Duron etc */
cebd7709	181	{X86_VENDOR_AMD, 0xF, 0x3F, ANY, 24}, /* Athlon 64, Opteron */
5bed13f5 JD	182	/* In theory, all NPT family 0Fh processors have 6 VID pins and should
	183	thus use vrm 25, however in practice not all mainboards route the
	184	6th VID pin because it is never needed. So we use the 5 VID pin
	185	variant (vrm 24) for the models which exist today. */
	186	{X86_VENDOR_AMD, 0xF, 0x7F, ANY, 24}, /* NPT family 0Fh */
	187	{X86_VENDOR_AMD, 0xF, ANY, ANY, 25}, /* future fam. 0Fh */
1b871826	188	{X86_VENDOR_AMD, 0x10, ANY, ANY, 25}, /* NPT family 10h */
5bed13f5	189
4c537fb2	190	{X86_VENDOR_INTEL, 0x6, 0x9, ANY, 13}, /* Pentium M (130 nm) */
734a12a3	191	{X86_VENDOR_INTEL, 0x6, 0xB, ANY, 85}, /* Tualatin */
4c537fb2	192	{X86_VENDOR_INTEL, 0x6, 0xD, ANY, 13}, /* Pentium M (90 nm) */
6af586dc RM	193	{X86_VENDOR_INTEL, 0x6, 0xE, ANY, 14}, /* Intel Core (65 nm) */
6af586dc RM	194	{X86_VENDOR_INTEL, 0x6, 0xF, ANY, 110}, /* Intel Conroe */
734a12a3	195	{X86_VENDOR_INTEL, 0x6, ANY, ANY, 82}, /* any P6 */
734a12a3 RM	196	{X86_VENDOR_INTEL, 0xF, 0x0, ANY, 90}, /* P4 */
	197	{X86_VENDOR_INTEL, 0xF, 0x1, ANY, 90}, /* P4 Willamette */
	198	{X86_VENDOR_INTEL, 0xF, 0x2, ANY, 90}, /* P4 Northwood */
	199	{X86_VENDOR_INTEL, 0xF, ANY, ANY, 100}, /* Prescott and above assume VRD 10 */
5bed13f5	200
734a12a3 RM	201	{X86_VENDOR_CENTAUR, 0x6, 0x7, ANY, 85}, /* Eden ESP/Ezra */
	202	{X86_VENDOR_CENTAUR, 0x6, 0x8, 0x7, 85}, /* Ezra T */
	203	{X86_VENDOR_CENTAUR, 0x6, 0x9, 0x7, 85}, /* Nemiah */
e46751bf RM	204	{X86_VENDOR_CENTAUR, 0x6, 0x9, ANY, 17}, /* C3-M, Eden-N */
	205	{X86_VENDOR_CENTAUR, 0x6, 0xA, 0x7, 0}, /* No information */
	206	{X86_VENDOR_CENTAUR, 0x6, 0xA, ANY, 13}, /* C7, Esther */
5bed13f5	207
734a12a3	208	{X86_VENDOR_UNKNOWN, ANY, ANY, ANY, 0} /* stop here */
da97a5a3	209	};
1da177e4	210
734a12a3	211	static u8 find_vrm(u8 eff_family, u8 eff_model, u8 eff_stepping, u8 vendor)
1da177e4 LT	212	{
	213	int i = 0;
	214
	215	while (vrm_models[i].vendor!=X86_VENDOR_UNKNOWN) {
	216	if (vrm_models[i].vendor==vendor)
da97a5a3 JD	217	if ((vrm_models[i].eff_family==eff_family)
da97a5a3 JD	218	&& ((vrm_models[i].eff_model==eff_model) \|\|
cebd7709 JD	219	(vrm_models[i].eff_model >= 0x10 &&
cebd7709 JD	220	eff_model <= vrm_models[i].eff_model) \|\|
734a12a3 RM	221	(vrm_models[i].eff_model==ANY)) &&
734a12a3 RM	222	(eff_stepping <= vrm_models[i].eff_stepping))
1da177e4 LT	223	return vrm_models[i].vrm_type;
	224	i++;
	225	}
	226
	227	return 0;
	228	}
	229
734a12a3	230	u8 vid_which_vrm(void)
1da177e4	231	{
92cb7612	232	struct cpuinfo_x86 *c = &cpu_data(0);
1da177e4	233	u32 eax;
734a12a3	234	u8 eff_family, eff_model, eff_stepping, vrm_ret;
1da177e4	235
da97a5a3 JD	236	if (c->x86 < 6) /* Any CPU with family lower than 6 */
	237	return 0; /* doesn't have VID and/or CPUID */
	238
1da177e4 LT	239	eax = cpuid_eax(1);
	240	eff_family = ((eax & 0x00000F00)>>8);
	241	eff_model = ((eax & 0x000000F0)>>4);
734a12a3	242	eff_stepping = eax & 0xF;
1da177e4 LT	243	if (eff_family == 0xF) { /* use extended model & family */
	244	eff_family += ((eax & 0x00F00000)>>20);
	245	eff_model += ((eax & 0x000F0000)>>16)<<4;
	246	}
734a12a3	247	vrm_ret = find_vrm(eff_family, eff_model, eff_stepping, c->x86_vendor);
1da177e4	248	if (vrm_ret == 0)
da97a5a3 JD	249	printk(KERN_INFO "hwmon-vid: Unknown VRM version of your "
da97a5a3 JD	250	"x86 CPU\n");
1da177e4 LT	251	return vrm_ret;
	252	}
	253
734a12a3	254	/* and now for something completely different for the non-x86 world */
1da177e4	255	#else
734a12a3	256	u8 vid_which_vrm(void)
1da177e4	257	{
303760b4	258	printk(KERN_INFO "hwmon-vid: Unknown VRM version of your CPU\n");
1da177e4 LT	259	return 0;
	260	}
	261	#endif
	262
d0f28270	263	EXPORT_SYMBOL(vid_from_reg);
303760b4	264	EXPORT_SYMBOL(vid_which_vrm);
96478ef3	265
7188cc66	266	MODULE_AUTHOR("Rudolf Marek <r.marek@assembler.cz>");
96478ef3	267
303760b4	268	MODULE_DESCRIPTION("hwmon-vid driver");
96478ef3	269	MODULE_LICENSE("GPL");