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Merge branch 'fix/hda' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound-2.6
[net-next-2.6.git] / drivers / gpu / drm / radeon / rv515.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include <linux/seq_file.h>
5a0e3ad6 29#include <linux/slab.h>
771fe6b9 30#include "drmP.h"
3ce0a23d 31#include "rv515d.h"
771fe6b9 32#include "radeon.h"
e6990375 33#include "radeon_asic.h"
d39c3b89 34#include "atom.h"
50f15303 35#include "rv515_reg_safe.h"
d39c3b89
JG		 36
37/* This files gather functions specifics to: rv515 */
771fe6b9
JG		 38int rv515_debugfs_pipes_info_init(struct radeon_device *rdev);
39int rv515_debugfs_ga_info_init(struct radeon_device *rdev);
40void rv515_gpu_init(struct radeon_device *rdev);
41int rv515_mc_wait_for_idle(struct radeon_device *rdev);
42
f0ed1f65 43void rv515_debugfs(struct radeon_device *rdev)
771fe6b9 44{
771fe6b9
JG		 45 if (r100_debugfs_rbbm_init(rdev)) {
46 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
47 }
48 if (rv515_debugfs_pipes_info_init(rdev)) {
49 DRM_ERROR("Failed to register debugfs file for pipes !\n");
50 }
51 if (rv515_debugfs_ga_info_init(rdev)) {
52 DRM_ERROR("Failed to register debugfs file for pipes !\n");
53 }
771fe6b9
JG		 54}
55
771fe6b9
JG		 56void rv515_ring_start(struct radeon_device *rdev)
57{
771fe6b9
JG		 58 int r;
59
771fe6b9
JG		 60 r = radeon_ring_lock(rdev, 64);
61 if (r) {
62 return;
63 }
c93bb85b 64 radeon_ring_write(rdev, PACKET0(ISYNC_CNTL, 0));
771fe6b9 65 radeon_ring_write(rdev,
c93bb85b
JG		 66 ISYNC_ANY2D_IDLE3D |
67 ISYNC_ANY3D_IDLE2D |
68 ISYNC_WAIT_IDLEGUI |
69 ISYNC_CPSCRATCH_IDLEGUI);
70 radeon_ring_write(rdev, PACKET0(WAIT_UNTIL, 0));
71 radeon_ring_write(rdev, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN);
771fe6b9
JG		 72 radeon_ring_write(rdev, PACKET0(0x170C, 0));
73 radeon_ring_write(rdev, 1 << 31);
c93bb85b 74 radeon_ring_write(rdev, PACKET0(GB_SELECT, 0));
771fe6b9 75 radeon_ring_write(rdev, 0);
c93bb85b 76 radeon_ring_write(rdev, PACKET0(GB_ENABLE, 0));
771fe6b9
JG		 77 radeon_ring_write(rdev, 0);
78 radeon_ring_write(rdev, PACKET0(0x42C8, 0));
79 radeon_ring_write(rdev, (1 << rdev->num_gb_pipes) - 1);
c93bb85b 80 radeon_ring_write(rdev, PACKET0(VAP_INDEX_OFFSET, 0));
771fe6b9 81 radeon_ring_write(rdev, 0);
c93bb85b
JG		 82 radeon_ring_write(rdev, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));
83 radeon_ring_write(rdev, RB3D_DC_FLUSH | RB3D_DC_FREE);
84 radeon_ring_write(rdev, PACKET0(ZB_ZCACHE_CTLSTAT, 0));
85 radeon_ring_write(rdev, ZC_FLUSH | ZC_FREE);
86 radeon_ring_write(rdev, PACKET0(WAIT_UNTIL, 0));
87 radeon_ring_write(rdev, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN);
88 radeon_ring_write(rdev, PACKET0(GB_AA_CONFIG, 0));
771fe6b9 89 radeon_ring_write(rdev, 0);
c93bb85b
JG		 90 radeon_ring_write(rdev, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));
91 radeon_ring_write(rdev, RB3D_DC_FLUSH | RB3D_DC_FREE);
92 radeon_ring_write(rdev, PACKET0(ZB_ZCACHE_CTLSTAT, 0));
93 radeon_ring_write(rdev, ZC_FLUSH | ZC_FREE);
94 radeon_ring_write(rdev, PACKET0(GB_MSPOS0, 0));
771fe6b9 95 radeon_ring_write(rdev,
c93bb85b
JG		 96 ((6 << MS_X0_SHIFT) |
97 (6 << MS_Y0_SHIFT) |
98 (6 << MS_X1_SHIFT) |
99 (6 << MS_Y1_SHIFT) |
100 (6 << MS_X2_SHIFT) |
101 (6 << MS_Y2_SHIFT) |
102 (6 << MSBD0_Y_SHIFT) |
103 (6 << MSBD0_X_SHIFT)));
104 radeon_ring_write(rdev, PACKET0(GB_MSPOS1, 0));
771fe6b9 105 radeon_ring_write(rdev,
c93bb85b
JG		 106 ((6 << MS_X3_SHIFT) |
107 (6 << MS_Y3_SHIFT) |
108 (6 << MS_X4_SHIFT) |
109 (6 << MS_Y4_SHIFT) |
110 (6 << MS_X5_SHIFT) |
111 (6 << MS_Y5_SHIFT) |
112 (6 << MSBD1_SHIFT)));
113 radeon_ring_write(rdev, PACKET0(GA_ENHANCE, 0));
114 radeon_ring_write(rdev, GA_DEADLOCK_CNTL | GA_FASTSYNC_CNTL);
115 radeon_ring_write(rdev, PACKET0(GA_POLY_MODE, 0));
116 radeon_ring_write(rdev, FRONT_PTYPE_TRIANGE | BACK_PTYPE_TRIANGE);
117 radeon_ring_write(rdev, PACKET0(GA_ROUND_MODE, 0));
118 radeon_ring_write(rdev, GEOMETRY_ROUND_NEAREST | COLOR_ROUND_NEAREST);
068a117c
JG		 119 radeon_ring_write(rdev, PACKET0(0x20C8, 0));
120 radeon_ring_write(rdev, 0);
771fe6b9
JG		 121 radeon_ring_unlock_commit(rdev);
122}
123
771fe6b9
JG		 124int rv515_mc_wait_for_idle(struct radeon_device *rdev)
125{
126 unsigned i;
127 uint32_t tmp;
128
129 for (i = 0; i < rdev->usec_timeout; i++) {
130 /* read MC_STATUS */
c93bb85b
JG		 131 tmp = RREG32_MC(MC_STATUS);
132 if (tmp & MC_STATUS_IDLE) {
771fe6b9
JG		 133 return 0;
134 }
135 DRM_UDELAY(1);
136 }
137 return -1;
138}
139
d39c3b89
JG		 140void rv515_vga_render_disable(struct radeon_device *rdev)
141{
142 WREG32(R_000300_VGA_RENDER_CONTROL,
143 RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL);
144}
145
771fe6b9
JG		 146void rv515_gpu_init(struct radeon_device *rdev)
147{
148 unsigned pipe_select_current, gb_pipe_select, tmp;
149
771fe6b9
JG		 150 if (r100_gui_wait_for_idle(rdev)) {
151 printk(KERN_WARNING "Failed to wait GUI idle while "
152 "reseting GPU. Bad things might happen.\n");
153 }
d39c3b89 154 rv515_vga_render_disable(rdev);
771fe6b9
JG		 155 r420_pipes_init(rdev);
156 gb_pipe_select = RREG32(0x402C);
157 tmp = RREG32(0x170C);
158 pipe_select_current = (tmp >> 2) & 3;
159 tmp = (1 << pipe_select_current) |
160 (((gb_pipe_select >> 8) & 0xF) << 4);
161 WREG32_PLL(0x000D, tmp);
162 if (r100_gui_wait_for_idle(rdev)) {
163 printk(KERN_WARNING "Failed to wait GUI idle while "
164 "reseting GPU. Bad things might happen.\n");
165 }
166 if (rv515_mc_wait_for_idle(rdev)) {
167 printk(KERN_WARNING "Failed to wait MC idle while "
168 "programming pipes. Bad things might happen.\n");
169 }
170}
171
771fe6b9
JG		 172static void rv515_vram_get_type(struct radeon_device *rdev)
173{
174 uint32_t tmp;
175
176 rdev->mc.vram_width = 128;
177 rdev->mc.vram_is_ddr = true;
c93bb85b 178 tmp = RREG32_MC(RV515_MC_CNTL) & MEM_NUM_CHANNELS_MASK;
771fe6b9
JG		 179 switch (tmp) {
180 case 0:
181 rdev->mc.vram_width = 64;
182 break;
183 case 1:
184 rdev->mc.vram_width = 128;
185 break;
186 default:
187 rdev->mc.vram_width = 128;
188 break;
189 }
190}
191
d594e46a 192void rv515_mc_init(struct radeon_device *rdev)
771fe6b9 193{
c93bb85b 194
771fe6b9 195 rv515_vram_get_type(rdev);
0924d942 196 r100_vram_init_sizes(rdev);
d594e46a 197 radeon_vram_location(rdev, &rdev->mc, 0);
8d369bb1 198 rdev->mc.gtt_base_align = 0;
d594e46a
JG		 199 if (!(rdev->flags & RADEON_IS_AGP))
200 radeon_gtt_location(rdev, &rdev->mc);
f47299c5 201 radeon_update_bandwidth_info(rdev);
771fe6b9
JG		 202}
203
771fe6b9
JG		 204uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg)
205{
206 uint32_t r;
207
c93bb85b
JG		 208 WREG32(MC_IND_INDEX, 0x7f0000 | (reg & 0xffff));
209 r = RREG32(MC_IND_DATA);
210 WREG32(MC_IND_INDEX, 0);
771fe6b9
JG		 211 return r;
212}
213
214void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
215{
c93bb85b
JG		 216 WREG32(MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff));
217 WREG32(MC_IND_DATA, (v));
218 WREG32(MC_IND_INDEX, 0);
771fe6b9
JG		 219}
220
771fe6b9
JG		 221#if defined(CONFIG_DEBUG_FS)
222static int rv515_debugfs_pipes_info(struct seq_file *m, void *data)
223{
224 struct drm_info_node *node = (struct drm_info_node *) m->private;
225 struct drm_device *dev = node->minor->dev;
226 struct radeon_device *rdev = dev->dev_private;
227 uint32_t tmp;
228
c93bb85b 229 tmp = RREG32(GB_PIPE_SELECT);
771fe6b9 230 seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);
c93bb85b 231 tmp = RREG32(SU_REG_DEST);
771fe6b9 232 seq_printf(m, "SU_REG_DEST 0x%08x\n", tmp);
c93bb85b 233 tmp = RREG32(GB_TILE_CONFIG);
771fe6b9 234 seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);
c93bb85b 235 tmp = RREG32(DST_PIPE_CONFIG);
771fe6b9
JG		 236 seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);
237 return 0;
238}
239
240static int rv515_debugfs_ga_info(struct seq_file *m, void *data)
241{
242 struct drm_info_node *node = (struct drm_info_node *) m->private;
243 struct drm_device *dev = node->minor->dev;
244 struct radeon_device *rdev = dev->dev_private;
245 uint32_t tmp;
246
247 tmp = RREG32(0x2140);
248 seq_printf(m, "VAP_CNTL_STATUS 0x%08x\n", tmp);
a2d07b74 249 radeon_asic_reset(rdev);
771fe6b9
JG		 250 tmp = RREG32(0x425C);
251 seq_printf(m, "GA_IDLE 0x%08x\n", tmp);
252 return 0;
253}
254
255static struct drm_info_list rv515_pipes_info_list[] = {
256 {"rv515_pipes_info", rv515_debugfs_pipes_info, 0, NULL},
257};
258
259static struct drm_info_list rv515_ga_info_list[] = {
260 {"rv515_ga_info", rv515_debugfs_ga_info, 0, NULL},
261};
262#endif
263
264int rv515_debugfs_pipes_info_init(struct radeon_device *rdev)
265{
266#if defined(CONFIG_DEBUG_FS)
267 return radeon_debugfs_add_files(rdev, rv515_pipes_info_list, 1);
268#else
269 return 0;
270#endif
271}
272
273int rv515_debugfs_ga_info_init(struct radeon_device *rdev)
274{
275#if defined(CONFIG_DEBUG_FS)
276 return radeon_debugfs_add_files(rdev, rv515_ga_info_list, 1);
277#else
278 return 0;
279#endif
280}
068a117c 281
d39c3b89
JG		 282void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save)
283{
284 save->d1vga_control = RREG32(R_000330_D1VGA_CONTROL);
285 save->d2vga_control = RREG32(R_000338_D2VGA_CONTROL);
286 save->vga_render_control = RREG32(R_000300_VGA_RENDER_CONTROL);
287 save->vga_hdp_control = RREG32(R_000328_VGA_HDP_CONTROL);
288 save->d1crtc_control = RREG32(R_006080_D1CRTC_CONTROL);
289 save->d2crtc_control = RREG32(R_006880_D2CRTC_CONTROL);
290
291 /* Stop all video */
d39c3b89
JG		 292 WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);
293 WREG32(R_000300_VGA_RENDER_CONTROL, 0);
294 WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1);
295 WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 1);
296 WREG32(R_006080_D1CRTC_CONTROL, 0);
297 WREG32(R_006880_D2CRTC_CONTROL, 0);
298 WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0);
299 WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);
ef630627
DA		 300 WREG32(R_000330_D1VGA_CONTROL, 0);
301 WREG32(R_000338_D2VGA_CONTROL, 0);
d39c3b89
JG		 302}
303
304void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save)
305{
306 WREG32(R_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS, rdev->mc.vram_start);
307 WREG32(R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS, rdev->mc.vram_start);
308 WREG32(R_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS, rdev->mc.vram_start);
309 WREG32(R_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS, rdev->mc.vram_start);
310 WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, rdev->mc.vram_start);
311 /* Unlock host access */
312 WREG32(R_000328_VGA_HDP_CONTROL, save->vga_hdp_control);
313 mdelay(1);
314 /* Restore video state */
ef630627
DA		 315 WREG32(R_000330_D1VGA_CONTROL, save->d1vga_control);
316 WREG32(R_000338_D2VGA_CONTROL, save->d2vga_control);
d39c3b89
JG		 317 WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1);
318 WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 1);
319 WREG32(R_006080_D1CRTC_CONTROL, save->d1crtc_control);
320 WREG32(R_006880_D2CRTC_CONTROL, save->d2crtc_control);
321 WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0);
322 WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);
d39c3b89
JG		 323 WREG32(R_000300_VGA_RENDER_CONTROL, save->vga_render_control);
324}
325
326void rv515_mc_program(struct radeon_device *rdev)
327{
328 struct rv515_mc_save save;
329
330 /* Stops all mc clients */
331 rv515_mc_stop(rdev, &save);
332
333 /* Wait for mc idle */
334 if (rv515_mc_wait_for_idle(rdev))
335 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
336 /* Write VRAM size in case we are limiting it */
337 WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
338 /* Program MC, should be a 32bits limited address space */
339 WREG32_MC(R_000001_MC_FB_LOCATION,
340 S_000001_MC_FB_START(rdev->mc.vram_start >> 16) |
341 S_000001_MC_FB_TOP(rdev->mc.vram_end >> 16));
342 WREG32(R_000134_HDP_FB_LOCATION,
343 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
344 if (rdev->flags & RADEON_IS_AGP) {
345 WREG32_MC(R_000002_MC_AGP_LOCATION,
346 S_000002_MC_AGP_START(rdev->mc.gtt_start >> 16) |
347 S_000002_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
348 WREG32_MC(R_000003_MC_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
349 WREG32_MC(R_000004_MC_AGP_BASE_2,
350 S_000004_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base)));
351 } else {
352 WREG32_MC(R_000002_MC_AGP_LOCATION, 0xFFFFFFFF);
353 WREG32_MC(R_000003_MC_AGP_BASE, 0);
354 WREG32_MC(R_000004_MC_AGP_BASE_2, 0);
355 }
356
357 rv515_mc_resume(rdev, &save);
358}
359
360void rv515_clock_startup(struct radeon_device *rdev)
361{
362 if (radeon_dynclks != -1 && radeon_dynclks)
363 radeon_atom_set_clock_gating(rdev, 1);
364 /* We need to force on some of the block */
365 WREG32_PLL(R_00000F_CP_DYN_CNTL,
366 RREG32_PLL(R_00000F_CP_DYN_CNTL) | S_00000F_CP_FORCEON(1));
367 WREG32_PLL(R_000011_E2_DYN_CNTL,
368 RREG32_PLL(R_000011_E2_DYN_CNTL) | S_000011_E2_FORCEON(1));
369 WREG32_PLL(R_000013_IDCT_DYN_CNTL,
370 RREG32_PLL(R_000013_IDCT_DYN_CNTL) | S_000013_IDCT_FORCEON(1));
371}
372
373static int rv515_startup(struct radeon_device *rdev)
374{
375 int r;
376
377 rv515_mc_program(rdev);
378 /* Resume clock */
379 rv515_clock_startup(rdev);
380 /* Initialize GPU configuration (# pipes, ...) */
381 rv515_gpu_init(rdev);
382 /* Initialize GART (initialize after TTM so we can allocate
383 * memory through TTM but finalize after TTM) */
384 if (rdev->flags & RADEON_IS_PCIE) {
385 r = rv370_pcie_gart_enable(rdev);
386 if (r)
387 return r;
388 }
389 /* Enable IRQ */
ac447df4 390 rs600_irq_set(rdev);
cafe6609 391 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
d39c3b89
JG		 392 /* 1M ring buffer */
393 r = r100_cp_init(rdev, 1024 * 1024);
394 if (r) {
395 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
396 return r;
397 }
398 r = r100_wb_init(rdev);
399 if (r)
400 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
401 r = r100_ib_init(rdev);
402 if (r) {
403 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
404 return r;
405 }
406 return 0;
407}
408
409int rv515_resume(struct radeon_device *rdev)
410{
411 /* Make sur GART are not working */
412 if (rdev->flags & RADEON_IS_PCIE)
413 rv370_pcie_gart_disable(rdev);
414 /* Resume clock before doing reset */
415 rv515_clock_startup(rdev);
416 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
a2d07b74 417 if (radeon_asic_reset(rdev)) {
d39c3b89
JG		 418 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
419 RREG32(R_000E40_RBBM_STATUS),
420 RREG32(R_0007C0_CP_STAT));
421 }
422 /* post */
423 atom_asic_init(rdev->mode_info.atom_context);
424 /* Resume clock after posting */
425 rv515_clock_startup(rdev);
550e2d92
DA		 426 /* Initialize surface registers */
427 radeon_surface_init(rdev);
d39c3b89
JG		 428 return rv515_startup(rdev);
429}
430
431int rv515_suspend(struct radeon_device *rdev)
432{
433 r100_cp_disable(rdev);
434 r100_wb_disable(rdev);
ac447df4 435 rs600_irq_disable(rdev);
d39c3b89
JG		 436 if (rdev->flags & RADEON_IS_PCIE)
437 rv370_pcie_gart_disable(rdev);
438 return 0;
439}
440
441void rv515_set_safe_registers(struct radeon_device *rdev)
068a117c 442{
50f15303
DA		 443 rdev->config.r300.reg_safe_bm = rv515_reg_safe_bm;
444 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rv515_reg_safe_bm);
d39c3b89
JG		 445}
446
447void rv515_fini(struct radeon_device *rdev)
448{
d39c3b89
JG		 449 r100_cp_fini(rdev);
450 r100_wb_fini(rdev);
451 r100_ib_fini(rdev);
452 radeon_gem_fini(rdev);
4c788679 453 rv370_pcie_gart_fini(rdev);
d39c3b89
JG		 454 radeon_agp_fini(rdev);
455 radeon_irq_kms_fini(rdev);
456 radeon_fence_driver_fini(rdev);
4c788679 457 radeon_bo_fini(rdev);
d39c3b89
JG		 458 radeon_atombios_fini(rdev);
459 kfree(rdev->bios);
460 rdev->bios = NULL;
461}
462
463int rv515_init(struct radeon_device *rdev)
464{
465 int r;
466
d39c3b89
JG		 467 /* Initialize scratch registers */
468 radeon_scratch_init(rdev);
469 /* Initialize surface registers */
470 radeon_surface_init(rdev);
471 /* TODO: disable VGA need to use VGA request */
472 /* BIOS*/
473 if (!radeon_get_bios(rdev)) {
474 if (ASIC_IS_AVIVO(rdev))
475 return -EINVAL;
476 }
477 if (rdev->is_atom_bios) {
478 r = radeon_atombios_init(rdev);
479 if (r)
480 return r;
481 } else {
482 dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");
483 return -EINVAL;
484 }
485 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
a2d07b74 486 if (radeon_asic_reset(rdev)) {
d39c3b89
JG		 487 dev_warn(rdev->dev,
488 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
489 RREG32(R_000E40_RBBM_STATUS),
490 RREG32(R_0007C0_CP_STAT));
491 }
492 /* check if cards are posted or not */
72542d77
DA		 493 if (radeon_boot_test_post_card(rdev) == false)
494 return -EINVAL;
d39c3b89
JG		 495 /* Initialize clocks */
496 radeon_get_clock_info(rdev->ddev);
d594e46a
JG		 497 /* initialize AGP */
498 if (rdev->flags & RADEON_IS_AGP) {
499 r = radeon_agp_init(rdev);
500 if (r) {
501 radeon_agp_disable(rdev);
502 }
503 }
504 /* initialize memory controller */
505 rv515_mc_init(rdev);
d39c3b89
JG		 506 rv515_debugfs(rdev);
507 /* Fence driver */
508 r = radeon_fence_driver_init(rdev);
509 if (r)
510 return r;
511 r = radeon_irq_kms_init(rdev);
512 if (r)
513 return r;
514 /* Memory manager */
4c788679 515 r = radeon_bo_init(rdev);
d39c3b89
JG		 516 if (r)
517 return r;
518 r = rv370_pcie_gart_init(rdev);
519 if (r)
520 return r;
521 rv515_set_safe_registers(rdev);
522 rdev->accel_working = true;
523 r = rv515_startup(rdev);
524 if (r) {
525 /* Somethings want wront with the accel init stop accel */
526 dev_err(rdev->dev, "Disabling GPU acceleration\n");
d39c3b89
JG		 527 r100_cp_fini(rdev);
528 r100_wb_fini(rdev);
529 r100_ib_fini(rdev);
655efd3d 530 radeon_irq_kms_fini(rdev);
d39c3b89
JG		 531 rv370_pcie_gart_fini(rdev);
532 radeon_agp_fini(rdev);
d39c3b89
JG		 533 rdev->accel_working = false;
534 }
068a117c
JG		 535 return 0;
536}
c93bb85b 537
4ce001ab 538void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *crtc)
c93bb85b 539{
4ce001ab
DA		 540 int index_reg = 0x6578 + crtc->crtc_offset;
541 int data_reg = 0x657c + crtc->crtc_offset;
542
543 WREG32(0x659C + crtc->crtc_offset, 0x0);
544 WREG32(0x6594 + crtc->crtc_offset, 0x705);
545 WREG32(0x65A4 + crtc->crtc_offset, 0x10001);
546 WREG32(0x65D8 + crtc->crtc_offset, 0x0);
547 WREG32(0x65B0 + crtc->crtc_offset, 0x0);
548 WREG32(0x65C0 + crtc->crtc_offset, 0x0);
549 WREG32(0x65D4 + crtc->crtc_offset, 0x0);
550 WREG32(index_reg, 0x0);
551 WREG32(data_reg, 0x841880A8);
552 WREG32(index_reg, 0x1);
553 WREG32(data_reg, 0x84208680);
554 WREG32(index_reg, 0x2);
555 WREG32(data_reg, 0xBFF880B0);
556 WREG32(index_reg, 0x100);
557 WREG32(data_reg, 0x83D88088);
558 WREG32(index_reg, 0x101);
559 WREG32(data_reg, 0x84608680);
560 WREG32(index_reg, 0x102);
561 WREG32(data_reg, 0xBFF080D0);
562 WREG32(index_reg, 0x200);
563 WREG32(data_reg, 0x83988068);
564 WREG32(index_reg, 0x201);
565 WREG32(data_reg, 0x84A08680);
566 WREG32(index_reg, 0x202);
567 WREG32(data_reg, 0xBFF080F8);
568 WREG32(index_reg, 0x300);
569 WREG32(data_reg, 0x83588058);
570 WREG32(index_reg, 0x301);
571 WREG32(data_reg, 0x84E08660);
572 WREG32(index_reg, 0x302);
573 WREG32(data_reg, 0xBFF88120);
574 WREG32(index_reg, 0x400);
575 WREG32(data_reg, 0x83188040);
576 WREG32(index_reg, 0x401);
577 WREG32(data_reg, 0x85008660);
578 WREG32(index_reg, 0x402);
579 WREG32(data_reg, 0xBFF88150);
580 WREG32(index_reg, 0x500);
581 WREG32(data_reg, 0x82D88030);
582 WREG32(index_reg, 0x501);
583 WREG32(data_reg, 0x85408640);
584 WREG32(index_reg, 0x502);
585 WREG32(data_reg, 0xBFF88180);
586 WREG32(index_reg, 0x600);
587 WREG32(data_reg, 0x82A08018);
588 WREG32(index_reg, 0x601);
589 WREG32(data_reg, 0x85808620);
590 WREG32(index_reg, 0x602);
591 WREG32(data_reg, 0xBFF081B8);
592 WREG32(index_reg, 0x700);
593 WREG32(data_reg, 0x82608010);
594 WREG32(index_reg, 0x701);
595 WREG32(data_reg, 0x85A08600);
596 WREG32(index_reg, 0x702);
597 WREG32(data_reg, 0x800081F0);
598 WREG32(index_reg, 0x800);
599 WREG32(data_reg, 0x8228BFF8);
600 WREG32(index_reg, 0x801);
601 WREG32(data_reg, 0x85E085E0);
602 WREG32(index_reg, 0x802);
603 WREG32(data_reg, 0xBFF88228);
604 WREG32(index_reg, 0x10000);
605 WREG32(data_reg, 0x82A8BF00);
606 WREG32(index_reg, 0x10001);
607 WREG32(data_reg, 0x82A08CC0);
608 WREG32(index_reg, 0x10002);
609 WREG32(data_reg, 0x8008BEF8);
610 WREG32(index_reg, 0x10100);
611 WREG32(data_reg, 0x81F0BF28);
612 WREG32(index_reg, 0x10101);
613 WREG32(data_reg, 0x83608CA0);
614 WREG32(index_reg, 0x10102);
615 WREG32(data_reg, 0x8018BED0);
616 WREG32(index_reg, 0x10200);
617 WREG32(data_reg, 0x8148BF38);
618 WREG32(index_reg, 0x10201);
619 WREG32(data_reg, 0x84408C80);
620 WREG32(index_reg, 0x10202);
621 WREG32(data_reg, 0x8008BEB8);
622 WREG32(index_reg, 0x10300);
623 WREG32(data_reg, 0x80B0BF78);
624 WREG32(index_reg, 0x10301);
625 WREG32(data_reg, 0x85008C20);
626 WREG32(index_reg, 0x10302);
627 WREG32(data_reg, 0x8020BEA0);
628 WREG32(index_reg, 0x10400);
629 WREG32(data_reg, 0x8028BF90);
630 WREG32(index_reg, 0x10401);
631 WREG32(data_reg, 0x85E08BC0);
632 WREG32(index_reg, 0x10402);
633 WREG32(data_reg, 0x8018BE90);
634 WREG32(index_reg, 0x10500);
635 WREG32(data_reg, 0xBFB8BFB0);
636 WREG32(index_reg, 0x10501);
637 WREG32(data_reg, 0x86C08B40);
638 WREG32(index_reg, 0x10502);
639 WREG32(data_reg, 0x8010BE90);
640 WREG32(index_reg, 0x10600);
641 WREG32(data_reg, 0xBF58BFC8);
642 WREG32(index_reg, 0x10601);
643 WREG32(data_reg, 0x87A08AA0);
644 WREG32(index_reg, 0x10602);
645 WREG32(data_reg, 0x8010BE98);
646 WREG32(index_reg, 0x10700);
647 WREG32(data_reg, 0xBF10BFF0);
648 WREG32(index_reg, 0x10701);
649 WREG32(data_reg, 0x886089E0);
650 WREG32(index_reg, 0x10702);
651 WREG32(data_reg, 0x8018BEB0);
652 WREG32(index_reg, 0x10800);
653 WREG32(data_reg, 0xBED8BFE8);
654 WREG32(index_reg, 0x10801);
655 WREG32(data_reg, 0x89408940);
656 WREG32(index_reg, 0x10802);
657 WREG32(data_reg, 0xBFE8BED8);
658 WREG32(index_reg, 0x20000);
659 WREG32(data_reg, 0x80008000);
660 WREG32(index_reg, 0x20001);
661 WREG32(data_reg, 0x90008000);
662 WREG32(index_reg, 0x20002);
663 WREG32(data_reg, 0x80008000);
664 WREG32(index_reg, 0x20003);
665 WREG32(data_reg, 0x80008000);
666 WREG32(index_reg, 0x20100);
667 WREG32(data_reg, 0x80108000);
668 WREG32(index_reg, 0x20101);
669 WREG32(data_reg, 0x8FE0BF70);
670 WREG32(index_reg, 0x20102);
671 WREG32(data_reg, 0xBFE880C0);
672 WREG32(index_reg, 0x20103);
673 WREG32(data_reg, 0x80008000);
674 WREG32(index_reg, 0x20200);
675 WREG32(data_reg, 0x8018BFF8);
676 WREG32(index_reg, 0x20201);
677 WREG32(data_reg, 0x8F80BF08);
678 WREG32(index_reg, 0x20202);
679 WREG32(data_reg, 0xBFD081A0);
680 WREG32(index_reg, 0x20203);
681 WREG32(data_reg, 0xBFF88000);
682 WREG32(index_reg, 0x20300);
683 WREG32(data_reg, 0x80188000);
684 WREG32(index_reg, 0x20301);
685 WREG32(data_reg, 0x8EE0BEC0);
686 WREG32(index_reg, 0x20302);
687 WREG32(data_reg, 0xBFB082A0);
688 WREG32(index_reg, 0x20303);
689 WREG32(data_reg, 0x80008000);
690 WREG32(index_reg, 0x20400);
691 WREG32(data_reg, 0x80188000);
692 WREG32(index_reg, 0x20401);
693 WREG32(data_reg, 0x8E00BEA0);
694 WREG32(index_reg, 0x20402);
695 WREG32(data_reg, 0xBF8883C0);
696 WREG32(index_reg, 0x20403);
697 WREG32(data_reg, 0x80008000);
698 WREG32(index_reg, 0x20500);
699 WREG32(data_reg, 0x80188000);
700 WREG32(index_reg, 0x20501);
701 WREG32(data_reg, 0x8D00BE90);
702 WREG32(index_reg, 0x20502);
703 WREG32(data_reg, 0xBF588500);
704 WREG32(index_reg, 0x20503);
705 WREG32(data_reg, 0x80008008);
706 WREG32(index_reg, 0x20600);
707 WREG32(data_reg, 0x80188000);
708 WREG32(index_reg, 0x20601);
709 WREG32(data_reg, 0x8BC0BE98);
710 WREG32(index_reg, 0x20602);
711 WREG32(data_reg, 0xBF308660);
712 WREG32(index_reg, 0x20603);
713 WREG32(data_reg, 0x80008008);
714 WREG32(index_reg, 0x20700);
715 WREG32(data_reg, 0x80108000);
716 WREG32(index_reg, 0x20701);
717 WREG32(data_reg, 0x8A80BEB0);
718 WREG32(index_reg, 0x20702);
719 WREG32(data_reg, 0xBF0087C0);
720 WREG32(index_reg, 0x20703);
721 WREG32(data_reg, 0x80008008);
722 WREG32(index_reg, 0x20800);
723 WREG32(data_reg, 0x80108000);
724 WREG32(index_reg, 0x20801);
725 WREG32(data_reg, 0x8920BED0);
726 WREG32(index_reg, 0x20802);
727 WREG32(data_reg, 0xBED08920);
728 WREG32(index_reg, 0x20803);
729 WREG32(data_reg, 0x80008010);
730 WREG32(index_reg, 0x30000);
731 WREG32(data_reg, 0x90008000);
732 WREG32(index_reg, 0x30001);
733 WREG32(data_reg, 0x80008000);
734 WREG32(index_reg, 0x30100);
735 WREG32(data_reg, 0x8FE0BF90);
736 WREG32(index_reg, 0x30101);
737 WREG32(data_reg, 0xBFF880A0);
738 WREG32(index_reg, 0x30200);
739 WREG32(data_reg, 0x8F60BF40);
740 WREG32(index_reg, 0x30201);
741 WREG32(data_reg, 0xBFE88180);
742 WREG32(index_reg, 0x30300);
743 WREG32(data_reg, 0x8EC0BF00);
744 WREG32(index_reg, 0x30301);
745 WREG32(data_reg, 0xBFC88280);
746 WREG32(index_reg, 0x30400);
747 WREG32(data_reg, 0x8DE0BEE0);
748 WREG32(index_reg, 0x30401);
749 WREG32(data_reg, 0xBFA083A0);
750 WREG32(index_reg, 0x30500);
751 WREG32(data_reg, 0x8CE0BED0);
752 WREG32(index_reg, 0x30501);
753 WREG32(data_reg, 0xBF7884E0);
754 WREG32(index_reg, 0x30600);
755 WREG32(data_reg, 0x8BA0BED8);
756 WREG32(index_reg, 0x30601);
757 WREG32(data_reg, 0xBF508640);
758 WREG32(index_reg, 0x30700);
759 WREG32(data_reg, 0x8A60BEE8);
760 WREG32(index_reg, 0x30701);
761 WREG32(data_reg, 0xBF2087A0);
762 WREG32(index_reg, 0x30800);
763 WREG32(data_reg, 0x8900BF00);
764 WREG32(index_reg, 0x30801);
765 WREG32(data_reg, 0xBF008900);
c93bb85b
JG		 766}
767
768struct rv515_watermark {
769 u32 lb_request_fifo_depth;
770 fixed20_12 num_line_pair;
771 fixed20_12 estimated_width;
772 fixed20_12 worst_case_latency;
773 fixed20_12 consumption_rate;
774 fixed20_12 active_time;
775 fixed20_12 dbpp;
776 fixed20_12 priority_mark_max;
777 fixed20_12 priority_mark;
778 fixed20_12 sclk;
779};
780
781void rv515_crtc_bandwidth_compute(struct radeon_device *rdev,
782 struct radeon_crtc *crtc,
783 struct rv515_watermark *wm)
784{
785 struct drm_display_mode *mode = &crtc->base.mode;
786 fixed20_12 a, b, c;
787 fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width;
788 fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency;
789
790 if (!crtc->base.enabled) {
791 /* FIXME: wouldn't it better to set priority mark to maximum */
792 wm->lb_request_fifo_depth = 4;
793 return;
794 }
795
68adac5e
BS		 796 if (crtc->vsc.full > dfixed_const(2))
797 wm->num_line_pair.full = dfixed_const(2);
c93bb85b 798 else
68adac5e 799 wm->num_line_pair.full = dfixed_const(1);
c93bb85b 800
68adac5e
BS		 801 b.full = dfixed_const(mode->crtc_hdisplay);
802 c.full = dfixed_const(256);
803 a.full = dfixed_div(b, c);
804 request_fifo_depth.full = dfixed_mul(a, wm->num_line_pair);
805 request_fifo_depth.full = dfixed_ceil(request_fifo_depth);
806 if (a.full < dfixed_const(4)) {
c93bb85b
JG		 807 wm->lb_request_fifo_depth = 4;
808 } else {
68adac5e 809 wm->lb_request_fifo_depth = dfixed_trunc(request_fifo_depth);
c93bb85b
JG		 810 }
811
812 /* Determine consumption rate
813 * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000)
814 * vtaps = number of vertical taps,
815 * vsc = vertical scaling ratio, defined as source/destination
816 * hsc = horizontal scaling ration, defined as source/destination
817 */
68adac5e
BS		 818 a.full = dfixed_const(mode->clock);
819 b.full = dfixed_const(1000);
820 a.full = dfixed_div(a, b);
821 pclk.full = dfixed_div(b, a);
c93bb85b 822 if (crtc->rmx_type != RMX_OFF) {
68adac5e 823 b.full = dfixed_const(2);
c93bb85b
JG		 824 if (crtc->vsc.full > b.full)
825 b.full = crtc->vsc.full;
68adac5e
BS		 826 b.full = dfixed_mul(b, crtc->hsc);
827 c.full = dfixed_const(2);
828 b.full = dfixed_div(b, c);
829 consumption_time.full = dfixed_div(pclk, b);
c93bb85b
JG		 830 } else {
831 consumption_time.full = pclk.full;
832 }
68adac5e
BS		 833 a.full = dfixed_const(1);
834 wm->consumption_rate.full = dfixed_div(a, consumption_time);
c93bb85b
JG		 835
836
837 /* Determine line time
838 * LineTime = total time for one line of displayhtotal
839 * LineTime = total number of horizontal pixels
840 * pclk = pixel clock period(ns)
841 */
68adac5e
BS		 842 a.full = dfixed_const(crtc->base.mode.crtc_htotal);
843 line_time.full = dfixed_mul(a, pclk);
c93bb85b
JG		 844
845 /* Determine active time
846 * ActiveTime = time of active region of display within one line,
847 * hactive = total number of horizontal active pixels
848 * htotal = total number of horizontal pixels
849 */
68adac5e
BS		 850 a.full = dfixed_const(crtc->base.mode.crtc_htotal);
851 b.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
852 wm->active_time.full = dfixed_mul(line_time, b);
853 wm->active_time.full = dfixed_div(wm->active_time, a);
c93bb85b
JG		 854
855 /* Determine chunk time
856 * ChunkTime = the time it takes the DCP to send one chunk of data
857 * to the LB which consists of pipeline delay and inter chunk gap
858 * sclk = system clock(Mhz)
859 */
68adac5e
BS		 860 a.full = dfixed_const(600 * 1000);
861 chunk_time.full = dfixed_div(a, rdev->pm.sclk);
862 read_delay_latency.full = dfixed_const(1000);
c93bb85b
JG		 863
864 /* Determine the worst case latency
865 * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines)
866 * WorstCaseLatency = worst case time from urgent to when the MC starts
867 * to return data
868 * READ_DELAY_IDLE_MAX = constant of 1us
869 * ChunkTime = time it takes the DCP to send one chunk of data to the LB
870 * which consists of pipeline delay and inter chunk gap
871 */
68adac5e
BS		 872 if (dfixed_trunc(wm->num_line_pair) > 1) {
873 a.full = dfixed_const(3);
874 wm->worst_case_latency.full = dfixed_mul(a, chunk_time);
c93bb85b
JG		 875 wm->worst_case_latency.full += read_delay_latency.full;
876 } else {
877 wm->worst_case_latency.full = chunk_time.full + read_delay_latency.full;
878 }
879
880 /* Determine the tolerable latency
881 * TolerableLatency = Any given request has only 1 line time
882 * for the data to be returned
883 * LBRequestFifoDepth = Number of chunk requests the LB can
884 * put into the request FIFO for a display
885 * LineTime = total time for one line of display
886 * ChunkTime = the time it takes the DCP to send one chunk
887 * of data to the LB which consists of
888 * pipeline delay and inter chunk gap
889 */
68adac5e 890 if ((2+wm->lb_request_fifo_depth) >= dfixed_trunc(request_fifo_depth)) {
c93bb85b
JG		 891 tolerable_latency.full = line_time.full;
892 } else {
68adac5e 893 tolerable_latency.full = dfixed_const(wm->lb_request_fifo_depth - 2);
c93bb85b 894 tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full;
68adac5e 895 tolerable_latency.full = dfixed_mul(tolerable_latency, chunk_time);
c93bb85b
JG		 896 tolerable_latency.full = line_time.full - tolerable_latency.full;
897 }
898 /* We assume worst case 32bits (4 bytes) */
68adac5e 899 wm->dbpp.full = dfixed_const(2 * 16);
c93bb85b
JG		 900
901 /* Determine the maximum priority mark
902 * width = viewport width in pixels
903 */
68adac5e
BS		 904 a.full = dfixed_const(16);
905 wm->priority_mark_max.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
906 wm->priority_mark_max.full = dfixed_div(wm->priority_mark_max, a);
907 wm->priority_mark_max.full = dfixed_ceil(wm->priority_mark_max);
c93bb85b
JG		 908
909 /* Determine estimated width */
910 estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full;
68adac5e
BS		 911 estimated_width.full = dfixed_div(estimated_width, consumption_time);
912 if (dfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) {
69b3b5e5 913 wm->priority_mark.full = wm->priority_mark_max.full;
c93bb85b 914 } else {
68adac5e
BS		 915 a.full = dfixed_const(16);
916 wm->priority_mark.full = dfixed_div(estimated_width, a);
917 wm->priority_mark.full = dfixed_ceil(wm->priority_mark);
c93bb85b
JG		 918 wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full;
919 }
920}
921
922void rv515_bandwidth_avivo_update(struct radeon_device *rdev)
923{
924 struct drm_display_mode *mode0 = NULL;
925 struct drm_display_mode *mode1 = NULL;
926 struct rv515_watermark wm0;
927 struct rv515_watermark wm1;
f46c0120 928 u32 tmp, d1mode_priority_a_cnt, d2mode_priority_a_cnt;
c93bb85b
JG		 929 fixed20_12 priority_mark02, priority_mark12, fill_rate;
930 fixed20_12 a, b;
931
932 if (rdev->mode_info.crtcs[0]->base.enabled)
933 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
934 if (rdev->mode_info.crtcs[1]->base.enabled)
935 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
936 rs690_line_buffer_adjust(rdev, mode0, mode1);
937
938 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0);
939 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1);
940
941 tmp = wm0.lb_request_fifo_depth;
942 tmp |= wm1.lb_request_fifo_depth << 16;
943 WREG32(LB_MAX_REQ_OUTSTANDING, tmp);
944
945 if (mode0 && mode1) {
68adac5e
BS		 946 if (dfixed_trunc(wm0.dbpp) > 64)
947 a.full = dfixed_div(wm0.dbpp, wm0.num_line_pair);
c93bb85b
JG		 948 else
949 a.full = wm0.num_line_pair.full;
68adac5e
BS		 950 if (dfixed_trunc(wm1.dbpp) > 64)
951 b.full = dfixed_div(wm1.dbpp, wm1.num_line_pair);
c93bb85b
JG		 952 else
953 b.full = wm1.num_line_pair.full;
954 a.full += b.full;
68adac5e 955 fill_rate.full = dfixed_div(wm0.sclk, a);
c93bb85b
JG		 956 if (wm0.consumption_rate.full > fill_rate.full) {
957 b.full = wm0.consumption_rate.full - fill_rate.full;
68adac5e
BS		 958 b.full = dfixed_mul(b, wm0.active_time);
959 a.full = dfixed_const(16);
960 b.full = dfixed_div(b, a);
961 a.full = dfixed_mul(wm0.worst_case_latency,
c93bb85b
JG		 962 wm0.consumption_rate);
963 priority_mark02.full = a.full + b.full;
964 } else {
68adac5e 965 a.full = dfixed_mul(wm0.worst_case_latency,
c93bb85b 966 wm0.consumption_rate);
68adac5e
BS		 967 b.full = dfixed_const(16 * 1000);
968 priority_mark02.full = dfixed_div(a, b);
c93bb85b
JG		 969 }
970 if (wm1.consumption_rate.full > fill_rate.full) {
971 b.full = wm1.consumption_rate.full - fill_rate.full;
68adac5e
BS		 972 b.full = dfixed_mul(b, wm1.active_time);
973 a.full = dfixed_const(16);
974 b.full = dfixed_div(b, a);
975 a.full = dfixed_mul(wm1.worst_case_latency,
c93bb85b
JG		 976 wm1.consumption_rate);
977 priority_mark12.full = a.full + b.full;
978 } else {
68adac5e 979 a.full = dfixed_mul(wm1.worst_case_latency,
c93bb85b 980 wm1.consumption_rate);
68adac5e
BS		 981 b.full = dfixed_const(16 * 1000);
982 priority_mark12.full = dfixed_div(a, b);
c93bb85b
JG		 983 }
984 if (wm0.priority_mark.full > priority_mark02.full)
985 priority_mark02.full = wm0.priority_mark.full;
68adac5e 986 if (dfixed_trunc(priority_mark02) < 0)
c93bb85b
JG		 987 priority_mark02.full = 0;
988 if (wm0.priority_mark_max.full > priority_mark02.full)
989 priority_mark02.full = wm0.priority_mark_max.full;
990 if (wm1.priority_mark.full > priority_mark12.full)
991 priority_mark12.full = wm1.priority_mark.full;
68adac5e 992 if (dfixed_trunc(priority_mark12) < 0)
c93bb85b
JG		 993 priority_mark12.full = 0;
994 if (wm1.priority_mark_max.full > priority_mark12.full)
995 priority_mark12.full = wm1.priority_mark_max.full;
68adac5e
BS		 996 d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
997 d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
f46c0120
AD		 998 if (rdev->disp_priority == 2) {
999 d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
1000 d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
1001 }
1002 WREG32(D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
1003 WREG32(D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
1004 WREG32(D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
1005 WREG32(D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
c93bb85b 1006 } else if (mode0) {
68adac5e
BS		 1007 if (dfixed_trunc(wm0.dbpp) > 64)
1008 a.full = dfixed_div(wm0.dbpp, wm0.num_line_pair);
c93bb85b
JG		 1009 else
1010 a.full = wm0.num_line_pair.full;
68adac5e 1011 fill_rate.full = dfixed_div(wm0.sclk, a);
c93bb85b
JG		 1012 if (wm0.consumption_rate.full > fill_rate.full) {
1013 b.full = wm0.consumption_rate.full - fill_rate.full;
68adac5e
BS		 1014 b.full = dfixed_mul(b, wm0.active_time);
1015 a.full = dfixed_const(16);
1016 b.full = dfixed_div(b, a);
1017 a.full = dfixed_mul(wm0.worst_case_latency,
c93bb85b
JG		 1018 wm0.consumption_rate);
1019 priority_mark02.full = a.full + b.full;
1020 } else {
68adac5e 1021 a.full = dfixed_mul(wm0.worst_case_latency,
c93bb85b 1022 wm0.consumption_rate);
68adac5e
BS		 1023 b.full = dfixed_const(16);
1024 priority_mark02.full = dfixed_div(a, b);
c93bb85b
JG		 1025 }
1026 if (wm0.priority_mark.full > priority_mark02.full)
1027 priority_mark02.full = wm0.priority_mark.full;
68adac5e 1028 if (dfixed_trunc(priority_mark02) < 0)
c93bb85b
JG		 1029 priority_mark02.full = 0;
1030 if (wm0.priority_mark_max.full > priority_mark02.full)
1031 priority_mark02.full = wm0.priority_mark_max.full;
68adac5e 1032 d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
f46c0120
AD		 1033 if (rdev->disp_priority == 2)
1034 d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
1035 WREG32(D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
1036 WREG32(D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
c93bb85b
JG		 1037 WREG32(D2MODE_PRIORITY_A_CNT, MODE_PRIORITY_OFF);
1038 WREG32(D2MODE_PRIORITY_B_CNT, MODE_PRIORITY_OFF);
1039 } else {
68adac5e
BS		 1040 if (dfixed_trunc(wm1.dbpp) > 64)
1041 a.full = dfixed_div(wm1.dbpp, wm1.num_line_pair);
c93bb85b
JG		 1042 else
1043 a.full = wm1.num_line_pair.full;
68adac5e 1044 fill_rate.full = dfixed_div(wm1.sclk, a);
c93bb85b
JG		 1045 if (wm1.consumption_rate.full > fill_rate.full) {
1046 b.full = wm1.consumption_rate.full - fill_rate.full;
68adac5e
BS		 1047 b.full = dfixed_mul(b, wm1.active_time);
1048 a.full = dfixed_const(16);
1049 b.full = dfixed_div(b, a);
1050 a.full = dfixed_mul(wm1.worst_case_latency,
c93bb85b
JG		 1051 wm1.consumption_rate);
1052 priority_mark12.full = a.full + b.full;
1053 } else {
68adac5e 1054 a.full = dfixed_mul(wm1.worst_case_latency,
c93bb85b 1055 wm1.consumption_rate);
68adac5e
BS		 1056 b.full = dfixed_const(16 * 1000);
1057 priority_mark12.full = dfixed_div(a, b);
c93bb85b
JG		 1058 }
1059 if (wm1.priority_mark.full > priority_mark12.full)
1060 priority_mark12.full = wm1.priority_mark.full;
68adac5e 1061 if (dfixed_trunc(priority_mark12) < 0)
c93bb85b
JG		 1062 priority_mark12.full = 0;
1063 if (wm1.priority_mark_max.full > priority_mark12.full)
1064 priority_mark12.full = wm1.priority_mark_max.full;
68adac5e 1065 d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
f46c0120
AD		 1066 if (rdev->disp_priority == 2)
1067 d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
c93bb85b
JG		 1068 WREG32(D1MODE_PRIORITY_A_CNT, MODE_PRIORITY_OFF);
1069 WREG32(D1MODE_PRIORITY_B_CNT, MODE_PRIORITY_OFF);
f46c0120
AD		 1070 WREG32(D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
1071 WREG32(D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
c93bb85b
JG		 1072 }
1073}
1074
1075void rv515_bandwidth_update(struct radeon_device *rdev)
1076{
1077 uint32_t tmp;
1078 struct drm_display_mode *mode0 = NULL;
1079 struct drm_display_mode *mode1 = NULL;
1080
f46c0120
AD		 1081 radeon_update_display_priority(rdev);
1082
c93bb85b
JG		 1083 if (rdev->mode_info.crtcs[0]->base.enabled)
1084 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
1085 if (rdev->mode_info.crtcs[1]->base.enabled)
1086 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
1087 /*
1088 * Set display0/1 priority up in the memory controller for
1089 * modes if the user specifies HIGH for displaypriority
1090 * option.
1091 */
f46c0120
AD		 1092 if ((rdev->disp_priority == 2) &&
1093 (rdev->family == CHIP_RV515)) {
c93bb85b
JG		 1094 tmp = RREG32_MC(MC_MISC_LAT_TIMER);
1095 tmp &= ~MC_DISP1R_INIT_LAT_MASK;
1096 tmp &= ~MC_DISP0R_INIT_LAT_MASK;
1097 if (mode1)
1098 tmp |= (1 << MC_DISP1R_INIT_LAT_SHIFT);
1099 if (mode0)
1100 tmp |= (1 << MC_DISP0R_INIT_LAT_SHIFT);
1101 WREG32_MC(MC_MISC_LAT_TIMER, tmp);
1102 }
1103 rv515_bandwidth_avivo_update(rdev);
1104}
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