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drm/radeon/kms: don't call suspend path before cleaning up GPU
[net-next-2.6.git] / drivers / gpu / drm / radeon / rv515.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include <linux/seq_file.h>
29#include "drmP.h"
3ce0a23d 30#include "rv515d.h"
771fe6b9 31#include "radeon.h"
d39c3b89 32#include "atom.h"
50f15303 33#include "rv515_reg_safe.h"
d39c3b89
JG		 34
35/* This files gather functions specifics to: rv515 */
771fe6b9
JG		 36int rv515_debugfs_pipes_info_init(struct radeon_device *rdev);
37int rv515_debugfs_ga_info_init(struct radeon_device *rdev);
38void rv515_gpu_init(struct radeon_device *rdev);
39int rv515_mc_wait_for_idle(struct radeon_device *rdev);
40
f0ed1f65 41void rv515_debugfs(struct radeon_device *rdev)
771fe6b9 42{
771fe6b9
JG		 43 if (r100_debugfs_rbbm_init(rdev)) {
44 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
45 }
46 if (rv515_debugfs_pipes_info_init(rdev)) {
47 DRM_ERROR("Failed to register debugfs file for pipes !\n");
48 }
49 if (rv515_debugfs_ga_info_init(rdev)) {
50 DRM_ERROR("Failed to register debugfs file for pipes !\n");
51 }
771fe6b9
JG		 52}
53
771fe6b9
JG		 54void rv515_ring_start(struct radeon_device *rdev)
55{
771fe6b9
JG		 56 int r;
57
771fe6b9
JG		 58 r = radeon_ring_lock(rdev, 64);
59 if (r) {
60 return;
61 }
c93bb85b 62 radeon_ring_write(rdev, PACKET0(ISYNC_CNTL, 0));
771fe6b9 63 radeon_ring_write(rdev,
c93bb85b
JG		 64 ISYNC_ANY2D_IDLE3D |
65 ISYNC_ANY3D_IDLE2D |
66 ISYNC_WAIT_IDLEGUI |
67 ISYNC_CPSCRATCH_IDLEGUI);
68 radeon_ring_write(rdev, PACKET0(WAIT_UNTIL, 0));
69 radeon_ring_write(rdev, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN);
771fe6b9
JG		 70 radeon_ring_write(rdev, PACKET0(0x170C, 0));
71 radeon_ring_write(rdev, 1 << 31);
c93bb85b 72 radeon_ring_write(rdev, PACKET0(GB_SELECT, 0));
771fe6b9 73 radeon_ring_write(rdev, 0);
c93bb85b 74 radeon_ring_write(rdev, PACKET0(GB_ENABLE, 0));
771fe6b9
JG		 75 radeon_ring_write(rdev, 0);
76 radeon_ring_write(rdev, PACKET0(0x42C8, 0));
77 radeon_ring_write(rdev, (1 << rdev->num_gb_pipes) - 1);
c93bb85b 78 radeon_ring_write(rdev, PACKET0(VAP_INDEX_OFFSET, 0));
771fe6b9 79 radeon_ring_write(rdev, 0);
c93bb85b
JG		 80 radeon_ring_write(rdev, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));
81 radeon_ring_write(rdev, RB3D_DC_FLUSH | RB3D_DC_FREE);
82 radeon_ring_write(rdev, PACKET0(ZB_ZCACHE_CTLSTAT, 0));
83 radeon_ring_write(rdev, ZC_FLUSH | ZC_FREE);
84 radeon_ring_write(rdev, PACKET0(WAIT_UNTIL, 0));
85 radeon_ring_write(rdev, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN);
86 radeon_ring_write(rdev, PACKET0(GB_AA_CONFIG, 0));
771fe6b9 87 radeon_ring_write(rdev, 0);
c93bb85b
JG		 88 radeon_ring_write(rdev, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));
89 radeon_ring_write(rdev, RB3D_DC_FLUSH | RB3D_DC_FREE);
90 radeon_ring_write(rdev, PACKET0(ZB_ZCACHE_CTLSTAT, 0));
91 radeon_ring_write(rdev, ZC_FLUSH | ZC_FREE);
92 radeon_ring_write(rdev, PACKET0(GB_MSPOS0, 0));
771fe6b9 93 radeon_ring_write(rdev,
c93bb85b
JG		 94 ((6 << MS_X0_SHIFT) |
95 (6 << MS_Y0_SHIFT) |
96 (6 << MS_X1_SHIFT) |
97 (6 << MS_Y1_SHIFT) |
98 (6 << MS_X2_SHIFT) |
99 (6 << MS_Y2_SHIFT) |
100 (6 << MSBD0_Y_SHIFT) |
101 (6 << MSBD0_X_SHIFT)));
102 radeon_ring_write(rdev, PACKET0(GB_MSPOS1, 0));
771fe6b9 103 radeon_ring_write(rdev,
c93bb85b
JG		 104 ((6 << MS_X3_SHIFT) |
105 (6 << MS_Y3_SHIFT) |
106 (6 << MS_X4_SHIFT) |
107 (6 << MS_Y4_SHIFT) |
108 (6 << MS_X5_SHIFT) |
109 (6 << MS_Y5_SHIFT) |
110 (6 << MSBD1_SHIFT)));
111 radeon_ring_write(rdev, PACKET0(GA_ENHANCE, 0));
112 radeon_ring_write(rdev, GA_DEADLOCK_CNTL | GA_FASTSYNC_CNTL);
113 radeon_ring_write(rdev, PACKET0(GA_POLY_MODE, 0));
114 radeon_ring_write(rdev, FRONT_PTYPE_TRIANGE | BACK_PTYPE_TRIANGE);
115 radeon_ring_write(rdev, PACKET0(GA_ROUND_MODE, 0));
116 radeon_ring_write(rdev, GEOMETRY_ROUND_NEAREST | COLOR_ROUND_NEAREST);
068a117c
JG		 117 radeon_ring_write(rdev, PACKET0(0x20C8, 0));
118 radeon_ring_write(rdev, 0);
771fe6b9
JG		 119 radeon_ring_unlock_commit(rdev);
120}
121
771fe6b9
JG		 122int rv515_mc_wait_for_idle(struct radeon_device *rdev)
123{
124 unsigned i;
125 uint32_t tmp;
126
127 for (i = 0; i < rdev->usec_timeout; i++) {
128 /* read MC_STATUS */
c93bb85b
JG		 129 tmp = RREG32_MC(MC_STATUS);
130 if (tmp & MC_STATUS_IDLE) {
771fe6b9
JG		 131 return 0;
132 }
133 DRM_UDELAY(1);
134 }
135 return -1;
136}
137
d39c3b89
JG		 138void rv515_vga_render_disable(struct radeon_device *rdev)
139{
140 WREG32(R_000300_VGA_RENDER_CONTROL,
141 RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL);
142}
143
771fe6b9
JG		 144void rv515_gpu_init(struct radeon_device *rdev)
145{
146 unsigned pipe_select_current, gb_pipe_select, tmp;
147
148 r100_hdp_reset(rdev);
149 r100_rb2d_reset(rdev);
150
151 if (r100_gui_wait_for_idle(rdev)) {
152 printk(KERN_WARNING "Failed to wait GUI idle while "
153 "reseting GPU. Bad things might happen.\n");
154 }
155
d39c3b89 156 rv515_vga_render_disable(rdev);
771fe6b9
JG		 157
158 r420_pipes_init(rdev);
159 gb_pipe_select = RREG32(0x402C);
160 tmp = RREG32(0x170C);
161 pipe_select_current = (tmp >> 2) & 3;
162 tmp = (1 << pipe_select_current) |
163 (((gb_pipe_select >> 8) & 0xF) << 4);
164 WREG32_PLL(0x000D, tmp);
165 if (r100_gui_wait_for_idle(rdev)) {
166 printk(KERN_WARNING "Failed to wait GUI idle while "
167 "reseting GPU. Bad things might happen.\n");
168 }
169 if (rv515_mc_wait_for_idle(rdev)) {
170 printk(KERN_WARNING "Failed to wait MC idle while "
171 "programming pipes. Bad things might happen.\n");
172 }
173}
174
175int rv515_ga_reset(struct radeon_device *rdev)
176{
177 uint32_t tmp;
178 bool reinit_cp;
179 int i;
180
181 reinit_cp = rdev->cp.ready;
182 rdev->cp.ready = false;
183 for (i = 0; i < rdev->usec_timeout; i++) {
c93bb85b
JG		 184 WREG32(CP_CSQ_MODE, 0);
185 WREG32(CP_CSQ_CNTL, 0);
186 WREG32(RBBM_SOFT_RESET, 0x32005);
187 (void)RREG32(RBBM_SOFT_RESET);
771fe6b9 188 udelay(200);
c93bb85b 189 WREG32(RBBM_SOFT_RESET, 0);
771fe6b9
JG		 190 /* Wait to prevent race in RBBM_STATUS */
191 mdelay(1);
c93bb85b 192 tmp = RREG32(RBBM_STATUS);
771fe6b9
JG		 193 if (tmp & ((1 << 20) | (1 << 26))) {
194 DRM_ERROR("VAP & CP still busy (RBBM_STATUS=0x%08X)\n", tmp);
195 /* GA still busy soft reset it */
196 WREG32(0x429C, 0x200);
c93bb85b 197 WREG32(VAP_PVS_STATE_FLUSH_REG, 0);
771fe6b9
JG		 198 WREG32(0x43E0, 0);
199 WREG32(0x43E4, 0);
200 WREG32(0x24AC, 0);
201 }
202 /* Wait to prevent race in RBBM_STATUS */
203 mdelay(1);
c93bb85b 204 tmp = RREG32(RBBM_STATUS);
771fe6b9
JG		 205 if (!(tmp & ((1 << 20) | (1 << 26)))) {
206 break;
207 }
208 }
209 for (i = 0; i < rdev->usec_timeout; i++) {
c93bb85b 210 tmp = RREG32(RBBM_STATUS);
771fe6b9
JG		 211 if (!(tmp & ((1 << 20) | (1 << 26)))) {
212 DRM_INFO("GA reset succeed (RBBM_STATUS=0x%08X)\n",
213 tmp);
214 DRM_INFO("GA_IDLE=0x%08X\n", RREG32(0x425C));
215 DRM_INFO("RB3D_RESET_STATUS=0x%08X\n", RREG32(0x46f0));
216 DRM_INFO("ISYNC_CNTL=0x%08X\n", RREG32(0x1724));
217 if (reinit_cp) {
218 return r100_cp_init(rdev, rdev->cp.ring_size);
219 }
220 return 0;
221 }
222 DRM_UDELAY(1);
223 }
c93bb85b 224 tmp = RREG32(RBBM_STATUS);
771fe6b9
JG		 225 DRM_ERROR("Failed to reset GA ! (RBBM_STATUS=0x%08X)\n", tmp);
226 return -1;
227}
228
229int rv515_gpu_reset(struct radeon_device *rdev)
230{
231 uint32_t status;
232
233 /* reset order likely matter */
c93bb85b 234 status = RREG32(RBBM_STATUS);
771fe6b9
JG		 235 /* reset HDP */
236 r100_hdp_reset(rdev);
237 /* reset rb2d */
238 if (status & ((1 << 17) | (1 << 18) | (1 << 27))) {
239 r100_rb2d_reset(rdev);
240 }
241 /* reset GA */
242 if (status & ((1 << 20) | (1 << 26))) {
243 rv515_ga_reset(rdev);
244 }
245 /* reset CP */
c93bb85b 246 status = RREG32(RBBM_STATUS);
771fe6b9
JG		 247 if (status & (1 << 16)) {
248 r100_cp_reset(rdev);
249 }
250 /* Check if GPU is idle */
c93bb85b 251 status = RREG32(RBBM_STATUS);
771fe6b9
JG		 252 if (status & (1 << 31)) {
253 DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
254 return -1;
255 }
256 DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
257 return 0;
258}
259
771fe6b9
JG		 260static void rv515_vram_get_type(struct radeon_device *rdev)
261{
262 uint32_t tmp;
263
264 rdev->mc.vram_width = 128;
265 rdev->mc.vram_is_ddr = true;
c93bb85b 266 tmp = RREG32_MC(RV515_MC_CNTL) & MEM_NUM_CHANNELS_MASK;
771fe6b9
JG		 267 switch (tmp) {
268 case 0:
269 rdev->mc.vram_width = 64;
270 break;
271 case 1:
272 rdev->mc.vram_width = 128;
273 break;
274 default:
275 rdev->mc.vram_width = 128;
276 break;
277 }
278}
279
280void rv515_vram_info(struct radeon_device *rdev)
281{
c93bb85b
JG		 282 fixed20_12 a;
283
771fe6b9 284 rv515_vram_get_type(rdev);
c93bb85b 285
0924d942 286 r100_vram_init_sizes(rdev);
c93bb85b
JG		 287 /* FIXME: we should enforce default clock in case GPU is not in
288 * default setup
289 */
290 a.full = rfixed_const(100);
291 rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
292 rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
771fe6b9
JG		 293}
294
771fe6b9
JG		 295uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg)
296{
297 uint32_t r;
298
c93bb85b
JG		 299 WREG32(MC_IND_INDEX, 0x7f0000 | (reg & 0xffff));
300 r = RREG32(MC_IND_DATA);
301 WREG32(MC_IND_INDEX, 0);
771fe6b9
JG		 302 return r;
303}
304
305void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
306{
c93bb85b
JG		 307 WREG32(MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff));
308 WREG32(MC_IND_DATA, (v));
309 WREG32(MC_IND_INDEX, 0);
771fe6b9
JG		 310}
311
771fe6b9
JG		 312#if defined(CONFIG_DEBUG_FS)
313static int rv515_debugfs_pipes_info(struct seq_file *m, void *data)
314{
315 struct drm_info_node *node = (struct drm_info_node *) m->private;
316 struct drm_device *dev = node->minor->dev;
317 struct radeon_device *rdev = dev->dev_private;
318 uint32_t tmp;
319
c93bb85b 320 tmp = RREG32(GB_PIPE_SELECT);
771fe6b9 321 seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);
c93bb85b 322 tmp = RREG32(SU_REG_DEST);
771fe6b9 323 seq_printf(m, "SU_REG_DEST 0x%08x\n", tmp);
c93bb85b 324 tmp = RREG32(GB_TILE_CONFIG);
771fe6b9 325 seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);
c93bb85b 326 tmp = RREG32(DST_PIPE_CONFIG);
771fe6b9
JG		 327 seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);
328 return 0;
329}
330
331static int rv515_debugfs_ga_info(struct seq_file *m, void *data)
332{
333 struct drm_info_node *node = (struct drm_info_node *) m->private;
334 struct drm_device *dev = node->minor->dev;
335 struct radeon_device *rdev = dev->dev_private;
336 uint32_t tmp;
337
338 tmp = RREG32(0x2140);
339 seq_printf(m, "VAP_CNTL_STATUS 0x%08x\n", tmp);
340 radeon_gpu_reset(rdev);
341 tmp = RREG32(0x425C);
342 seq_printf(m, "GA_IDLE 0x%08x\n", tmp);
343 return 0;
344}
345
346static struct drm_info_list rv515_pipes_info_list[] = {
347 {"rv515_pipes_info", rv515_debugfs_pipes_info, 0, NULL},
348};
349
350static struct drm_info_list rv515_ga_info_list[] = {
351 {"rv515_ga_info", rv515_debugfs_ga_info, 0, NULL},
352};
353#endif
354
355int rv515_debugfs_pipes_info_init(struct radeon_device *rdev)
356{
357#if defined(CONFIG_DEBUG_FS)
358 return radeon_debugfs_add_files(rdev, rv515_pipes_info_list, 1);
359#else
360 return 0;
361#endif
362}
363
364int rv515_debugfs_ga_info_init(struct radeon_device *rdev)
365{
366#if defined(CONFIG_DEBUG_FS)
367 return radeon_debugfs_add_files(rdev, rv515_ga_info_list, 1);
368#else
369 return 0;
370#endif
371}
068a117c 372
d39c3b89
JG		 373void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save)
374{
375 save->d1vga_control = RREG32(R_000330_D1VGA_CONTROL);
376 save->d2vga_control = RREG32(R_000338_D2VGA_CONTROL);
377 save->vga_render_control = RREG32(R_000300_VGA_RENDER_CONTROL);
378 save->vga_hdp_control = RREG32(R_000328_VGA_HDP_CONTROL);
379 save->d1crtc_control = RREG32(R_006080_D1CRTC_CONTROL);
380 save->d2crtc_control = RREG32(R_006880_D2CRTC_CONTROL);
381
382 /* Stop all video */
d39c3b89
JG		 383 WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);
384 WREG32(R_000300_VGA_RENDER_CONTROL, 0);
385 WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1);
386 WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 1);
387 WREG32(R_006080_D1CRTC_CONTROL, 0);
388 WREG32(R_006880_D2CRTC_CONTROL, 0);
389 WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0);
390 WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);
ef630627
DA		 391 WREG32(R_000330_D1VGA_CONTROL, 0);
392 WREG32(R_000338_D2VGA_CONTROL, 0);
d39c3b89
JG		 393}
394
395void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save)
396{
397 WREG32(R_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS, rdev->mc.vram_start);
398 WREG32(R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS, rdev->mc.vram_start);
399 WREG32(R_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS, rdev->mc.vram_start);
400 WREG32(R_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS, rdev->mc.vram_start);
401 WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, rdev->mc.vram_start);
402 /* Unlock host access */
403 WREG32(R_000328_VGA_HDP_CONTROL, save->vga_hdp_control);
404 mdelay(1);
405 /* Restore video state */
ef630627
DA		 406 WREG32(R_000330_D1VGA_CONTROL, save->d1vga_control);
407 WREG32(R_000338_D2VGA_CONTROL, save->d2vga_control);
d39c3b89
JG		 408 WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1);
409 WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 1);
410 WREG32(R_006080_D1CRTC_CONTROL, save->d1crtc_control);
411 WREG32(R_006880_D2CRTC_CONTROL, save->d2crtc_control);
412 WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0);
413 WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);
d39c3b89
JG		 414 WREG32(R_000300_VGA_RENDER_CONTROL, save->vga_render_control);
415}
416
417void rv515_mc_program(struct radeon_device *rdev)
418{
419 struct rv515_mc_save save;
420
421 /* Stops all mc clients */
422 rv515_mc_stop(rdev, &save);
423
424 /* Wait for mc idle */
425 if (rv515_mc_wait_for_idle(rdev))
426 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
427 /* Write VRAM size in case we are limiting it */
428 WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
429 /* Program MC, should be a 32bits limited address space */
430 WREG32_MC(R_000001_MC_FB_LOCATION,
431 S_000001_MC_FB_START(rdev->mc.vram_start >> 16) |
432 S_000001_MC_FB_TOP(rdev->mc.vram_end >> 16));
433 WREG32(R_000134_HDP_FB_LOCATION,
434 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
435 if (rdev->flags & RADEON_IS_AGP) {
436 WREG32_MC(R_000002_MC_AGP_LOCATION,
437 S_000002_MC_AGP_START(rdev->mc.gtt_start >> 16) |
438 S_000002_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
439 WREG32_MC(R_000003_MC_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
440 WREG32_MC(R_000004_MC_AGP_BASE_2,
441 S_000004_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base)));
442 } else {
443 WREG32_MC(R_000002_MC_AGP_LOCATION, 0xFFFFFFFF);
444 WREG32_MC(R_000003_MC_AGP_BASE, 0);
445 WREG32_MC(R_000004_MC_AGP_BASE_2, 0);
446 }
447
448 rv515_mc_resume(rdev, &save);
449}
450
451void rv515_clock_startup(struct radeon_device *rdev)
452{
453 if (radeon_dynclks != -1 && radeon_dynclks)
454 radeon_atom_set_clock_gating(rdev, 1);
455 /* We need to force on some of the block */
456 WREG32_PLL(R_00000F_CP_DYN_CNTL,
457 RREG32_PLL(R_00000F_CP_DYN_CNTL) | S_00000F_CP_FORCEON(1));
458 WREG32_PLL(R_000011_E2_DYN_CNTL,
459 RREG32_PLL(R_000011_E2_DYN_CNTL) | S_000011_E2_FORCEON(1));
460 WREG32_PLL(R_000013_IDCT_DYN_CNTL,
461 RREG32_PLL(R_000013_IDCT_DYN_CNTL) | S_000013_IDCT_FORCEON(1));
462}
463
464static int rv515_startup(struct radeon_device *rdev)
465{
466 int r;
467
468 rv515_mc_program(rdev);
469 /* Resume clock */
470 rv515_clock_startup(rdev);
471 /* Initialize GPU configuration (# pipes, ...) */
472 rv515_gpu_init(rdev);
473 /* Initialize GART (initialize after TTM so we can allocate
474 * memory through TTM but finalize after TTM) */
475 if (rdev->flags & RADEON_IS_PCIE) {
476 r = rv370_pcie_gart_enable(rdev);
477 if (r)
478 return r;
479 }
480 /* Enable IRQ */
ac447df4 481 rs600_irq_set(rdev);
cafe6609 482 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
d39c3b89
JG		 483 /* 1M ring buffer */
484 r = r100_cp_init(rdev, 1024 * 1024);
485 if (r) {
486 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
487 return r;
488 }
489 r = r100_wb_init(rdev);
490 if (r)
491 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
492 r = r100_ib_init(rdev);
493 if (r) {
494 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
495 return r;
496 }
497 return 0;
498}
499
500int rv515_resume(struct radeon_device *rdev)
501{
502 /* Make sur GART are not working */
503 if (rdev->flags & RADEON_IS_PCIE)
504 rv370_pcie_gart_disable(rdev);
505 /* Resume clock before doing reset */
506 rv515_clock_startup(rdev);
507 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
508 if (radeon_gpu_reset(rdev)) {
509 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
510 RREG32(R_000E40_RBBM_STATUS),
511 RREG32(R_0007C0_CP_STAT));
512 }
513 /* post */
514 atom_asic_init(rdev->mode_info.atom_context);
515 /* Resume clock after posting */
516 rv515_clock_startup(rdev);
550e2d92
DA		 517 /* Initialize surface registers */
518 radeon_surface_init(rdev);
d39c3b89
JG		 519 return rv515_startup(rdev);
520}
521
522int rv515_suspend(struct radeon_device *rdev)
523{
524 r100_cp_disable(rdev);
525 r100_wb_disable(rdev);
ac447df4 526 rs600_irq_disable(rdev);
d39c3b89
JG		 527 if (rdev->flags & RADEON_IS_PCIE)
528 rv370_pcie_gart_disable(rdev);
529 return 0;
530}
531
532void rv515_set_safe_registers(struct radeon_device *rdev)
068a117c 533{
50f15303
DA		 534 rdev->config.r300.reg_safe_bm = rv515_reg_safe_bm;
535 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rv515_reg_safe_bm);
d39c3b89
JG		 536}
537
538void rv515_fini(struct radeon_device *rdev)
539{
d39c3b89
JG		 540 r100_cp_fini(rdev);
541 r100_wb_fini(rdev);
542 r100_ib_fini(rdev);
543 radeon_gem_fini(rdev);
4c788679 544 rv370_pcie_gart_fini(rdev);
d39c3b89
JG		 545 radeon_agp_fini(rdev);
546 radeon_irq_kms_fini(rdev);
547 radeon_fence_driver_fini(rdev);
4c788679 548 radeon_bo_fini(rdev);
d39c3b89
JG		 549 radeon_atombios_fini(rdev);
550 kfree(rdev->bios);
551 rdev->bios = NULL;
552}
553
554int rv515_init(struct radeon_device *rdev)
555{
556 int r;
557
d39c3b89
JG		 558 /* Initialize scratch registers */
559 radeon_scratch_init(rdev);
560 /* Initialize surface registers */
561 radeon_surface_init(rdev);
562 /* TODO: disable VGA need to use VGA request */
563 /* BIOS*/
564 if (!radeon_get_bios(rdev)) {
565 if (ASIC_IS_AVIVO(rdev))
566 return -EINVAL;
567 }
568 if (rdev->is_atom_bios) {
569 r = radeon_atombios_init(rdev);
570 if (r)
571 return r;
572 } else {
573 dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");
574 return -EINVAL;
575 }
576 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
577 if (radeon_gpu_reset(rdev)) {
578 dev_warn(rdev->dev,
579 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
580 RREG32(R_000E40_RBBM_STATUS),
581 RREG32(R_0007C0_CP_STAT));
582 }
583 /* check if cards are posted or not */
72542d77
DA		 584 if (radeon_boot_test_post_card(rdev) == false)
585 return -EINVAL;
d39c3b89
JG		 586 /* Initialize clocks */
587 radeon_get_clock_info(rdev->ddev);
7433874e
RM		 588 /* Initialize power management */
589 radeon_pm_init(rdev);
d39c3b89
JG		 590 /* Get vram informations */
591 rv515_vram_info(rdev);
592 /* Initialize memory controller (also test AGP) */
593 r = r420_mc_init(rdev);
594 if (r)
595 return r;
596 rv515_debugfs(rdev);
597 /* Fence driver */
598 r = radeon_fence_driver_init(rdev);
599 if (r)
600 return r;
601 r = radeon_irq_kms_init(rdev);
602 if (r)
603 return r;
604 /* Memory manager */
4c788679 605 r = radeon_bo_init(rdev);
d39c3b89
JG		 606 if (r)
607 return r;
608 r = rv370_pcie_gart_init(rdev);
609 if (r)
610 return r;
611 rv515_set_safe_registers(rdev);
612 rdev->accel_working = true;
613 r = rv515_startup(rdev);
614 if (r) {
615 /* Somethings want wront with the accel init stop accel */
616 dev_err(rdev->dev, "Disabling GPU acceleration\n");
d39c3b89
JG		 617 r100_cp_fini(rdev);
618 r100_wb_fini(rdev);
619 r100_ib_fini(rdev);
655efd3d 620 radeon_irq_kms_fini(rdev);
d39c3b89
JG		 621 rv370_pcie_gart_fini(rdev);
622 radeon_agp_fini(rdev);
d39c3b89
JG		 623 rdev->accel_working = false;
624 }
068a117c
JG		 625 return 0;
626}
c93bb85b 627
4ce001ab 628void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *crtc)
c93bb85b 629{
4ce001ab
DA		 630 int index_reg = 0x6578 + crtc->crtc_offset;
631 int data_reg = 0x657c + crtc->crtc_offset;
632
633 WREG32(0x659C + crtc->crtc_offset, 0x0);
634 WREG32(0x6594 + crtc->crtc_offset, 0x705);
635 WREG32(0x65A4 + crtc->crtc_offset, 0x10001);
636 WREG32(0x65D8 + crtc->crtc_offset, 0x0);
637 WREG32(0x65B0 + crtc->crtc_offset, 0x0);
638 WREG32(0x65C0 + crtc->crtc_offset, 0x0);
639 WREG32(0x65D4 + crtc->crtc_offset, 0x0);
640 WREG32(index_reg, 0x0);
641 WREG32(data_reg, 0x841880A8);
642 WREG32(index_reg, 0x1);
643 WREG32(data_reg, 0x84208680);
644 WREG32(index_reg, 0x2);
645 WREG32(data_reg, 0xBFF880B0);
646 WREG32(index_reg, 0x100);
647 WREG32(data_reg, 0x83D88088);
648 WREG32(index_reg, 0x101);
649 WREG32(data_reg, 0x84608680);
650 WREG32(index_reg, 0x102);
651 WREG32(data_reg, 0xBFF080D0);
652 WREG32(index_reg, 0x200);
653 WREG32(data_reg, 0x83988068);
654 WREG32(index_reg, 0x201);
655 WREG32(data_reg, 0x84A08680);
656 WREG32(index_reg, 0x202);
657 WREG32(data_reg, 0xBFF080F8);
658 WREG32(index_reg, 0x300);
659 WREG32(data_reg, 0x83588058);
660 WREG32(index_reg, 0x301);
661 WREG32(data_reg, 0x84E08660);
662 WREG32(index_reg, 0x302);
663 WREG32(data_reg, 0xBFF88120);
664 WREG32(index_reg, 0x400);
665 WREG32(data_reg, 0x83188040);
666 WREG32(index_reg, 0x401);
667 WREG32(data_reg, 0x85008660);
668 WREG32(index_reg, 0x402);
669 WREG32(data_reg, 0xBFF88150);
670 WREG32(index_reg, 0x500);
671 WREG32(data_reg, 0x82D88030);
672 WREG32(index_reg, 0x501);
673 WREG32(data_reg, 0x85408640);
674 WREG32(index_reg, 0x502);
675 WREG32(data_reg, 0xBFF88180);
676 WREG32(index_reg, 0x600);
677 WREG32(data_reg, 0x82A08018);
678 WREG32(index_reg, 0x601);
679 WREG32(data_reg, 0x85808620);
680 WREG32(index_reg, 0x602);
681 WREG32(data_reg, 0xBFF081B8);
682 WREG32(index_reg, 0x700);
683 WREG32(data_reg, 0x82608010);
684 WREG32(index_reg, 0x701);
685 WREG32(data_reg, 0x85A08600);
686 WREG32(index_reg, 0x702);
687 WREG32(data_reg, 0x800081F0);
688 WREG32(index_reg, 0x800);
689 WREG32(data_reg, 0x8228BFF8);
690 WREG32(index_reg, 0x801);
691 WREG32(data_reg, 0x85E085E0);
692 WREG32(index_reg, 0x802);
693 WREG32(data_reg, 0xBFF88228);
694 WREG32(index_reg, 0x10000);
695 WREG32(data_reg, 0x82A8BF00);
696 WREG32(index_reg, 0x10001);
697 WREG32(data_reg, 0x82A08CC0);
698 WREG32(index_reg, 0x10002);
699 WREG32(data_reg, 0x8008BEF8);
700 WREG32(index_reg, 0x10100);
701 WREG32(data_reg, 0x81F0BF28);
702 WREG32(index_reg, 0x10101);
703 WREG32(data_reg, 0x83608CA0);
704 WREG32(index_reg, 0x10102);
705 WREG32(data_reg, 0x8018BED0);
706 WREG32(index_reg, 0x10200);
707 WREG32(data_reg, 0x8148BF38);
708 WREG32(index_reg, 0x10201);
709 WREG32(data_reg, 0x84408C80);
710 WREG32(index_reg, 0x10202);
711 WREG32(data_reg, 0x8008BEB8);
712 WREG32(index_reg, 0x10300);
713 WREG32(data_reg, 0x80B0BF78);
714 WREG32(index_reg, 0x10301);
715 WREG32(data_reg, 0x85008C20);
716 WREG32(index_reg, 0x10302);
717 WREG32(data_reg, 0x8020BEA0);
718 WREG32(index_reg, 0x10400);
719 WREG32(data_reg, 0x8028BF90);
720 WREG32(index_reg, 0x10401);
721 WREG32(data_reg, 0x85E08BC0);
722 WREG32(index_reg, 0x10402);
723 WREG32(data_reg, 0x8018BE90);
724 WREG32(index_reg, 0x10500);
725 WREG32(data_reg, 0xBFB8BFB0);
726 WREG32(index_reg, 0x10501);
727 WREG32(data_reg, 0x86C08B40);
728 WREG32(index_reg, 0x10502);
729 WREG32(data_reg, 0x8010BE90);
730 WREG32(index_reg, 0x10600);
731 WREG32(data_reg, 0xBF58BFC8);
732 WREG32(index_reg, 0x10601);
733 WREG32(data_reg, 0x87A08AA0);
734 WREG32(index_reg, 0x10602);
735 WREG32(data_reg, 0x8010BE98);
736 WREG32(index_reg, 0x10700);
737 WREG32(data_reg, 0xBF10BFF0);
738 WREG32(index_reg, 0x10701);
739 WREG32(data_reg, 0x886089E0);
740 WREG32(index_reg, 0x10702);
741 WREG32(data_reg, 0x8018BEB0);
742 WREG32(index_reg, 0x10800);
743 WREG32(data_reg, 0xBED8BFE8);
744 WREG32(index_reg, 0x10801);
745 WREG32(data_reg, 0x89408940);
746 WREG32(index_reg, 0x10802);
747 WREG32(data_reg, 0xBFE8BED8);
748 WREG32(index_reg, 0x20000);
749 WREG32(data_reg, 0x80008000);
750 WREG32(index_reg, 0x20001);
751 WREG32(data_reg, 0x90008000);
752 WREG32(index_reg, 0x20002);
753 WREG32(data_reg, 0x80008000);
754 WREG32(index_reg, 0x20003);
755 WREG32(data_reg, 0x80008000);
756 WREG32(index_reg, 0x20100);
757 WREG32(data_reg, 0x80108000);
758 WREG32(index_reg, 0x20101);
759 WREG32(data_reg, 0x8FE0BF70);
760 WREG32(index_reg, 0x20102);
761 WREG32(data_reg, 0xBFE880C0);
762 WREG32(index_reg, 0x20103);
763 WREG32(data_reg, 0x80008000);
764 WREG32(index_reg, 0x20200);
765 WREG32(data_reg, 0x8018BFF8);
766 WREG32(index_reg, 0x20201);
767 WREG32(data_reg, 0x8F80BF08);
768 WREG32(index_reg, 0x20202);
769 WREG32(data_reg, 0xBFD081A0);
770 WREG32(index_reg, 0x20203);
771 WREG32(data_reg, 0xBFF88000);
772 WREG32(index_reg, 0x20300);
773 WREG32(data_reg, 0x80188000);
774 WREG32(index_reg, 0x20301);
775 WREG32(data_reg, 0x8EE0BEC0);
776 WREG32(index_reg, 0x20302);
777 WREG32(data_reg, 0xBFB082A0);
778 WREG32(index_reg, 0x20303);
779 WREG32(data_reg, 0x80008000);
780 WREG32(index_reg, 0x20400);
781 WREG32(data_reg, 0x80188000);
782 WREG32(index_reg, 0x20401);
783 WREG32(data_reg, 0x8E00BEA0);
784 WREG32(index_reg, 0x20402);
785 WREG32(data_reg, 0xBF8883C0);
786 WREG32(index_reg, 0x20403);
787 WREG32(data_reg, 0x80008000);
788 WREG32(index_reg, 0x20500);
789 WREG32(data_reg, 0x80188000);
790 WREG32(index_reg, 0x20501);
791 WREG32(data_reg, 0x8D00BE90);
792 WREG32(index_reg, 0x20502);
793 WREG32(data_reg, 0xBF588500);
794 WREG32(index_reg, 0x20503);
795 WREG32(data_reg, 0x80008008);
796 WREG32(index_reg, 0x20600);
797 WREG32(data_reg, 0x80188000);
798 WREG32(index_reg, 0x20601);
799 WREG32(data_reg, 0x8BC0BE98);
800 WREG32(index_reg, 0x20602);
801 WREG32(data_reg, 0xBF308660);
802 WREG32(index_reg, 0x20603);
803 WREG32(data_reg, 0x80008008);
804 WREG32(index_reg, 0x20700);
805 WREG32(data_reg, 0x80108000);
806 WREG32(index_reg, 0x20701);
807 WREG32(data_reg, 0x8A80BEB0);
808 WREG32(index_reg, 0x20702);
809 WREG32(data_reg, 0xBF0087C0);
810 WREG32(index_reg, 0x20703);
811 WREG32(data_reg, 0x80008008);
812 WREG32(index_reg, 0x20800);
813 WREG32(data_reg, 0x80108000);
814 WREG32(index_reg, 0x20801);
815 WREG32(data_reg, 0x8920BED0);
816 WREG32(index_reg, 0x20802);
817 WREG32(data_reg, 0xBED08920);
818 WREG32(index_reg, 0x20803);
819 WREG32(data_reg, 0x80008010);
820 WREG32(index_reg, 0x30000);
821 WREG32(data_reg, 0x90008000);
822 WREG32(index_reg, 0x30001);
823 WREG32(data_reg, 0x80008000);
824 WREG32(index_reg, 0x30100);
825 WREG32(data_reg, 0x8FE0BF90);
826 WREG32(index_reg, 0x30101);
827 WREG32(data_reg, 0xBFF880A0);
828 WREG32(index_reg, 0x30200);
829 WREG32(data_reg, 0x8F60BF40);
830 WREG32(index_reg, 0x30201);
831 WREG32(data_reg, 0xBFE88180);
832 WREG32(index_reg, 0x30300);
833 WREG32(data_reg, 0x8EC0BF00);
834 WREG32(index_reg, 0x30301);
835 WREG32(data_reg, 0xBFC88280);
836 WREG32(index_reg, 0x30400);
837 WREG32(data_reg, 0x8DE0BEE0);
838 WREG32(index_reg, 0x30401);
839 WREG32(data_reg, 0xBFA083A0);
840 WREG32(index_reg, 0x30500);
841 WREG32(data_reg, 0x8CE0BED0);
842 WREG32(index_reg, 0x30501);
843 WREG32(data_reg, 0xBF7884E0);
844 WREG32(index_reg, 0x30600);
845 WREG32(data_reg, 0x8BA0BED8);
846 WREG32(index_reg, 0x30601);
847 WREG32(data_reg, 0xBF508640);
848 WREG32(index_reg, 0x30700);
849 WREG32(data_reg, 0x8A60BEE8);
850 WREG32(index_reg, 0x30701);
851 WREG32(data_reg, 0xBF2087A0);
852 WREG32(index_reg, 0x30800);
853 WREG32(data_reg, 0x8900BF00);
854 WREG32(index_reg, 0x30801);
855 WREG32(data_reg, 0xBF008900);
c93bb85b
JG		 856}
857
858struct rv515_watermark {
859 u32 lb_request_fifo_depth;
860 fixed20_12 num_line_pair;
861 fixed20_12 estimated_width;
862 fixed20_12 worst_case_latency;
863 fixed20_12 consumption_rate;
864 fixed20_12 active_time;
865 fixed20_12 dbpp;
866 fixed20_12 priority_mark_max;
867 fixed20_12 priority_mark;
868 fixed20_12 sclk;
869};
870
871void rv515_crtc_bandwidth_compute(struct radeon_device *rdev,
872 struct radeon_crtc *crtc,
873 struct rv515_watermark *wm)
874{
875 struct drm_display_mode *mode = &crtc->base.mode;
876 fixed20_12 a, b, c;
877 fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width;
878 fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency;
879
880 if (!crtc->base.enabled) {
881 /* FIXME: wouldn't it better to set priority mark to maximum */
882 wm->lb_request_fifo_depth = 4;
883 return;
884 }
885
886 if (crtc->vsc.full > rfixed_const(2))
887 wm->num_line_pair.full = rfixed_const(2);
888 else
889 wm->num_line_pair.full = rfixed_const(1);
890
891 b.full = rfixed_const(mode->crtc_hdisplay);
892 c.full = rfixed_const(256);
69b3b5e5
AD		 893 a.full = rfixed_div(b, c);
894 request_fifo_depth.full = rfixed_mul(a, wm->num_line_pair);
895 request_fifo_depth.full = rfixed_ceil(request_fifo_depth);
c93bb85b
JG		 896 if (a.full < rfixed_const(4)) {
897 wm->lb_request_fifo_depth = 4;
898 } else {
899 wm->lb_request_fifo_depth = rfixed_trunc(request_fifo_depth);
900 }
901
902 /* Determine consumption rate
903 * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000)
904 * vtaps = number of vertical taps,
905 * vsc = vertical scaling ratio, defined as source/destination
906 * hsc = horizontal scaling ration, defined as source/destination
907 */
908 a.full = rfixed_const(mode->clock);
909 b.full = rfixed_const(1000);
910 a.full = rfixed_div(a, b);
911 pclk.full = rfixed_div(b, a);
912 if (crtc->rmx_type != RMX_OFF) {
913 b.full = rfixed_const(2);
914 if (crtc->vsc.full > b.full)
915 b.full = crtc->vsc.full;
916 b.full = rfixed_mul(b, crtc->hsc);
917 c.full = rfixed_const(2);
918 b.full = rfixed_div(b, c);
919 consumption_time.full = rfixed_div(pclk, b);
920 } else {
921 consumption_time.full = pclk.full;
922 }
923 a.full = rfixed_const(1);
924 wm->consumption_rate.full = rfixed_div(a, consumption_time);
925
926
927 /* Determine line time
928 * LineTime = total time for one line of displayhtotal
929 * LineTime = total number of horizontal pixels
930 * pclk = pixel clock period(ns)
931 */
932 a.full = rfixed_const(crtc->base.mode.crtc_htotal);
933 line_time.full = rfixed_mul(a, pclk);
934
935 /* Determine active time
936 * ActiveTime = time of active region of display within one line,
937 * hactive = total number of horizontal active pixels
938 * htotal = total number of horizontal pixels
939 */
940 a.full = rfixed_const(crtc->base.mode.crtc_htotal);
941 b.full = rfixed_const(crtc->base.mode.crtc_hdisplay);
942 wm->active_time.full = rfixed_mul(line_time, b);
943 wm->active_time.full = rfixed_div(wm->active_time, a);
944
945 /* Determine chunk time
946 * ChunkTime = the time it takes the DCP to send one chunk of data
947 * to the LB which consists of pipeline delay and inter chunk gap
948 * sclk = system clock(Mhz)
949 */
950 a.full = rfixed_const(600 * 1000);
951 chunk_time.full = rfixed_div(a, rdev->pm.sclk);
952 read_delay_latency.full = rfixed_const(1000);
953
954 /* Determine the worst case latency
955 * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines)
956 * WorstCaseLatency = worst case time from urgent to when the MC starts
957 * to return data
958 * READ_DELAY_IDLE_MAX = constant of 1us
959 * ChunkTime = time it takes the DCP to send one chunk of data to the LB
960 * which consists of pipeline delay and inter chunk gap
961 */
962 if (rfixed_trunc(wm->num_line_pair) > 1) {
963 a.full = rfixed_const(3);
964 wm->worst_case_latency.full = rfixed_mul(a, chunk_time);
965 wm->worst_case_latency.full += read_delay_latency.full;
966 } else {
967 wm->worst_case_latency.full = chunk_time.full + read_delay_latency.full;
968 }
969
970 /* Determine the tolerable latency
971 * TolerableLatency = Any given request has only 1 line time
972 * for the data to be returned
973 * LBRequestFifoDepth = Number of chunk requests the LB can
974 * put into the request FIFO for a display
975 * LineTime = total time for one line of display
976 * ChunkTime = the time it takes the DCP to send one chunk
977 * of data to the LB which consists of
978 * pipeline delay and inter chunk gap
979 */
980 if ((2+wm->lb_request_fifo_depth) >= rfixed_trunc(request_fifo_depth)) {
981 tolerable_latency.full = line_time.full;
982 } else {
983 tolerable_latency.full = rfixed_const(wm->lb_request_fifo_depth - 2);
984 tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full;
985 tolerable_latency.full = rfixed_mul(tolerable_latency, chunk_time);
986 tolerable_latency.full = line_time.full - tolerable_latency.full;
987 }
988 /* We assume worst case 32bits (4 bytes) */
989 wm->dbpp.full = rfixed_const(2 * 16);
990
991 /* Determine the maximum priority mark
992 * width = viewport width in pixels
993 */
994 a.full = rfixed_const(16);
995 wm->priority_mark_max.full = rfixed_const(crtc->base.mode.crtc_hdisplay);
996 wm->priority_mark_max.full = rfixed_div(wm->priority_mark_max, a);
69b3b5e5 997 wm->priority_mark_max.full = rfixed_ceil(wm->priority_mark_max);
c93bb85b
JG		 998
999 /* Determine estimated width */
1000 estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full;
1001 estimated_width.full = rfixed_div(estimated_width, consumption_time);
1002 if (rfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) {
69b3b5e5 1003 wm->priority_mark.full = wm->priority_mark_max.full;
c93bb85b
JG		 1004 } else {
1005 a.full = rfixed_const(16);
1006 wm->priority_mark.full = rfixed_div(estimated_width, a);
69b3b5e5 1007 wm->priority_mark.full = rfixed_ceil(wm->priority_mark);
c93bb85b
JG		 1008 wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full;
1009 }
1010}
1011
1012void rv515_bandwidth_avivo_update(struct radeon_device *rdev)
1013{
1014 struct drm_display_mode *mode0 = NULL;
1015 struct drm_display_mode *mode1 = NULL;
1016 struct rv515_watermark wm0;
1017 struct rv515_watermark wm1;
1018 u32 tmp;
1019 fixed20_12 priority_mark02, priority_mark12, fill_rate;
1020 fixed20_12 a, b;
1021
1022 if (rdev->mode_info.crtcs[0]->base.enabled)
1023 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
1024 if (rdev->mode_info.crtcs[1]->base.enabled)
1025 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
1026 rs690_line_buffer_adjust(rdev, mode0, mode1);
1027
1028 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0);
1029 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1);
1030
1031 tmp = wm0.lb_request_fifo_depth;
1032 tmp |= wm1.lb_request_fifo_depth << 16;
1033 WREG32(LB_MAX_REQ_OUTSTANDING, tmp);
1034
1035 if (mode0 && mode1) {
1036 if (rfixed_trunc(wm0.dbpp) > 64)
1037 a.full = rfixed_div(wm0.dbpp, wm0.num_line_pair);
1038 else
1039 a.full = wm0.num_line_pair.full;
1040 if (rfixed_trunc(wm1.dbpp) > 64)
1041 b.full = rfixed_div(wm1.dbpp, wm1.num_line_pair);
1042 else
1043 b.full = wm1.num_line_pair.full;
1044 a.full += b.full;
1045 fill_rate.full = rfixed_div(wm0.sclk, a);
1046 if (wm0.consumption_rate.full > fill_rate.full) {
1047 b.full = wm0.consumption_rate.full - fill_rate.full;
1048 b.full = rfixed_mul(b, wm0.active_time);
1049 a.full = rfixed_const(16);
1050 b.full = rfixed_div(b, a);
1051 a.full = rfixed_mul(wm0.worst_case_latency,
1052 wm0.consumption_rate);
1053 priority_mark02.full = a.full + b.full;
1054 } else {
1055 a.full = rfixed_mul(wm0.worst_case_latency,
1056 wm0.consumption_rate);
1057 b.full = rfixed_const(16 * 1000);
1058 priority_mark02.full = rfixed_div(a, b);
1059 }
1060 if (wm1.consumption_rate.full > fill_rate.full) {
1061 b.full = wm1.consumption_rate.full - fill_rate.full;
1062 b.full = rfixed_mul(b, wm1.active_time);
1063 a.full = rfixed_const(16);
1064 b.full = rfixed_div(b, a);
1065 a.full = rfixed_mul(wm1.worst_case_latency,
1066 wm1.consumption_rate);
1067 priority_mark12.full = a.full + b.full;
1068 } else {
1069 a.full = rfixed_mul(wm1.worst_case_latency,
1070 wm1.consumption_rate);
1071 b.full = rfixed_const(16 * 1000);
1072 priority_mark12.full = rfixed_div(a, b);
1073 }
1074 if (wm0.priority_mark.full > priority_mark02.full)
1075 priority_mark02.full = wm0.priority_mark.full;
1076 if (rfixed_trunc(priority_mark02) < 0)
1077 priority_mark02.full = 0;
1078 if (wm0.priority_mark_max.full > priority_mark02.full)
1079 priority_mark02.full = wm0.priority_mark_max.full;
1080 if (wm1.priority_mark.full > priority_mark12.full)
1081 priority_mark12.full = wm1.priority_mark.full;
1082 if (rfixed_trunc(priority_mark12) < 0)
1083 priority_mark12.full = 0;
1084 if (wm1.priority_mark_max.full > priority_mark12.full)
1085 priority_mark12.full = wm1.priority_mark_max.full;
1086 WREG32(D1MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark02));
1087 WREG32(D1MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark02));
1088 WREG32(D2MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark12));
1089 WREG32(D2MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark12));
1090 } else if (mode0) {
1091 if (rfixed_trunc(wm0.dbpp) > 64)
1092 a.full = rfixed_div(wm0.dbpp, wm0.num_line_pair);
1093 else
1094 a.full = wm0.num_line_pair.full;
1095 fill_rate.full = rfixed_div(wm0.sclk, a);
1096 if (wm0.consumption_rate.full > fill_rate.full) {
1097 b.full = wm0.consumption_rate.full - fill_rate.full;
1098 b.full = rfixed_mul(b, wm0.active_time);
1099 a.full = rfixed_const(16);
1100 b.full = rfixed_div(b, a);
1101 a.full = rfixed_mul(wm0.worst_case_latency,
1102 wm0.consumption_rate);
1103 priority_mark02.full = a.full + b.full;
1104 } else {
1105 a.full = rfixed_mul(wm0.worst_case_latency,
1106 wm0.consumption_rate);
1107 b.full = rfixed_const(16);
1108 priority_mark02.full = rfixed_div(a, b);
1109 }
1110 if (wm0.priority_mark.full > priority_mark02.full)
1111 priority_mark02.full = wm0.priority_mark.full;
1112 if (rfixed_trunc(priority_mark02) < 0)
1113 priority_mark02.full = 0;
1114 if (wm0.priority_mark_max.full > priority_mark02.full)
1115 priority_mark02.full = wm0.priority_mark_max.full;
1116 WREG32(D1MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark02));
1117 WREG32(D1MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark02));
1118 WREG32(D2MODE_PRIORITY_A_CNT, MODE_PRIORITY_OFF);
1119 WREG32(D2MODE_PRIORITY_B_CNT, MODE_PRIORITY_OFF);
1120 } else {
1121 if (rfixed_trunc(wm1.dbpp) > 64)
1122 a.full = rfixed_div(wm1.dbpp, wm1.num_line_pair);
1123 else
1124 a.full = wm1.num_line_pair.full;
1125 fill_rate.full = rfixed_div(wm1.sclk, a);
1126 if (wm1.consumption_rate.full > fill_rate.full) {
1127 b.full = wm1.consumption_rate.full - fill_rate.full;
1128 b.full = rfixed_mul(b, wm1.active_time);
1129 a.full = rfixed_const(16);
1130 b.full = rfixed_div(b, a);
1131 a.full = rfixed_mul(wm1.worst_case_latency,
1132 wm1.consumption_rate);
1133 priority_mark12.full = a.full + b.full;
1134 } else {
1135 a.full = rfixed_mul(wm1.worst_case_latency,
1136 wm1.consumption_rate);
1137 b.full = rfixed_const(16 * 1000);
1138 priority_mark12.full = rfixed_div(a, b);
1139 }
1140 if (wm1.priority_mark.full > priority_mark12.full)
1141 priority_mark12.full = wm1.priority_mark.full;
1142 if (rfixed_trunc(priority_mark12) < 0)
1143 priority_mark12.full = 0;
1144 if (wm1.priority_mark_max.full > priority_mark12.full)
1145 priority_mark12.full = wm1.priority_mark_max.full;
1146 WREG32(D1MODE_PRIORITY_A_CNT, MODE_PRIORITY_OFF);
1147 WREG32(D1MODE_PRIORITY_B_CNT, MODE_PRIORITY_OFF);
1148 WREG32(D2MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark12));
1149 WREG32(D2MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark12));
1150 }
1151}
1152
1153void rv515_bandwidth_update(struct radeon_device *rdev)
1154{
1155 uint32_t tmp;
1156 struct drm_display_mode *mode0 = NULL;
1157 struct drm_display_mode *mode1 = NULL;
1158
1159 if (rdev->mode_info.crtcs[0]->base.enabled)
1160 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
1161 if (rdev->mode_info.crtcs[1]->base.enabled)
1162 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
1163 /*
1164 * Set display0/1 priority up in the memory controller for
1165 * modes if the user specifies HIGH for displaypriority
1166 * option.
1167 */
1168 if (rdev->disp_priority == 2) {
1169 tmp = RREG32_MC(MC_MISC_LAT_TIMER);
1170 tmp &= ~MC_DISP1R_INIT_LAT_MASK;
1171 tmp &= ~MC_DISP0R_INIT_LAT_MASK;
1172 if (mode1)
1173 tmp |= (1 << MC_DISP1R_INIT_LAT_SHIFT);
1174 if (mode0)
1175 tmp |= (1 << MC_DISP0R_INIT_LAT_SHIFT);
1176 WREG32_MC(MC_MISC_LAT_TIMER, tmp);
1177 }
1178 rv515_bandwidth_avivo_update(rdev);
1179}
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