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drm/radeon/kms: check for valid PCI bios and not OF rom
[net-next-2.6.git] / drivers / gpu / drm / radeon / rs600.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
c010f800
JG		 28/* RS600 / Radeon X1250/X1270 integrated GPU
29 *
30 * This file gather function specific to RS600 which is the IGP of
31 * the X1250/X1270 family supporting intel CPU (while RS690/RS740
32 * is the X1250/X1270 supporting AMD CPU). The display engine are
33 * the avivo one, bios is an atombios, 3D block are the one of the
34 * R4XX family. The GART is different from the RS400 one and is very
35 * close to the one of the R600 family (R600 likely being an evolution
36 * of the RS600 GART block).
37 */
771fe6b9 38#include "drmP.h"
771fe6b9 39#include "radeon.h"
c010f800
JG		 40#include "atom.h"
41#include "rs600d.h"
771fe6b9 42
3f7dc91a
DA		 43#include "rs600_reg_safe.h"
44
771fe6b9
JG		 45void rs600_gpu_init(struct radeon_device *rdev);
46int rs600_mc_wait_for_idle(struct radeon_device *rdev);
771fe6b9 47
64bffd03
DA		 48int rs600_mc_init(struct radeon_device *rdev)
49{
50 /* read back the MC value from the hw */
64bffd03 51 int r;
22dd5013 52 u32 tmp;
64bffd03 53
22dd5013
AD		 54 /* Setup GPU memory space */
55 tmp = RREG32_MC(R_000004_MC_FB_LOCATION);
56 rdev->mc.vram_location = G_000004_MC_FB_START(tmp) << 16;
64bffd03
DA		 57 rdev->mc.gtt_location = 0xffffffffUL;
58 r = radeon_mc_setup(rdev);
06b6476d 59 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
64bffd03
DA		 60 if (r)
61 return r;
62 return 0;
63}
dcfdd408
AD		 64
65/* hpd for digital panel detect/disconnect */
66bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
67{
68 u32 tmp;
69 bool connected = false;
70
71 switch (hpd) {
72 case RADEON_HPD_1:
73 tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS);
74 if (G_007D04_DC_HOT_PLUG_DETECT1_SENSE(tmp))
75 connected = true;
76 break;
77 case RADEON_HPD_2:
78 tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS);
79 if (G_007D14_DC_HOT_PLUG_DETECT2_SENSE(tmp))
80 connected = true;
81 break;
82 default:
83 break;
84 }
85 return connected;
86}
87
88void rs600_hpd_set_polarity(struct radeon_device *rdev,
89 enum radeon_hpd_id hpd)
90{
91 u32 tmp;
92 bool connected = rs600_hpd_sense(rdev, hpd);
93
94 switch (hpd) {
95 case RADEON_HPD_1:
96 tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
97 if (connected)
98 tmp &= ~S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
99 else
100 tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
101 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
102 break;
103 case RADEON_HPD_2:
104 tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
105 if (connected)
106 tmp &= ~S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
107 else
108 tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
109 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
110 break;
111 default:
112 break;
113 }
114}
115
116void rs600_hpd_init(struct radeon_device *rdev)
117{
118 struct drm_device *dev = rdev->ddev;
119 struct drm_connector *connector;
120
121 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
122 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
123 switch (radeon_connector->hpd.hpd) {
124 case RADEON_HPD_1:
125 WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
126 S_007D00_DC_HOT_PLUG_DETECT1_EN(1));
127 rdev->irq.hpd[0] = true;
128 break;
129 case RADEON_HPD_2:
130 WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
131 S_007D10_DC_HOT_PLUG_DETECT2_EN(1));
132 rdev->irq.hpd[1] = true;
133 break;
134 default:
135 break;
136 }
137 }
003e69f9
JG		 138 if (rdev->irq.installed)
139 rs600_irq_set(rdev);
dcfdd408
AD		 140}
141
142void rs600_hpd_fini(struct radeon_device *rdev)
143{
144 struct drm_device *dev = rdev->ddev;
145 struct drm_connector *connector;
146
147 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
148 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
149 switch (radeon_connector->hpd.hpd) {
150 case RADEON_HPD_1:
151 WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
152 S_007D00_DC_HOT_PLUG_DETECT1_EN(0));
153 rdev->irq.hpd[0] = false;
154 break;
155 case RADEON_HPD_2:
156 WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
157 S_007D10_DC_HOT_PLUG_DETECT2_EN(0));
158 rdev->irq.hpd[1] = false;
159 break;
160 default:
161 break;
162 }
163 }
164}
165
771fe6b9
JG		 166/*
167 * GART.
168 */
169void rs600_gart_tlb_flush(struct radeon_device *rdev)
170{
171 uint32_t tmp;
172
c010f800
JG		 173 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
174 tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
175 WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
771fe6b9 176
c010f800
JG		 177 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
178 tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) & S_000100_INVALIDATE_L2_CACHE(1);
179 WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
771fe6b9 180
c010f800
JG		 181 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
182 tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
183 WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
184 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
771fe6b9
JG		 185}
186
4aac0473 187int rs600_gart_init(struct radeon_device *rdev)
771fe6b9 188{
771fe6b9
JG		 189 int r;
190
4aac0473
JG		 191 if (rdev->gart.table.vram.robj) {
192 WARN(1, "RS600 GART already initialized.\n");
193 return 0;
194 }
771fe6b9
JG		 195 /* Initialize common gart structure */
196 r = radeon_gart_init(rdev);
197 if (r) {
198 return r;
199 }
200 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
4aac0473
JG		 201 return radeon_gart_table_vram_alloc(rdev);
202}
203
204int rs600_gart_enable(struct radeon_device *rdev)
205{
c010f800 206 u32 tmp;
4aac0473
JG		 207 int r, i;
208
209 if (rdev->gart.table.vram.robj == NULL) {
210 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
211 return -EINVAL;
771fe6b9 212 }
4aac0473
JG		 213 r = radeon_gart_table_vram_pin(rdev);
214 if (r)
215 return r;
c010f800
JG		 216 /* Enable bus master */
217 tmp = RREG32(R_00004C_BUS_CNTL) & C_00004C_BUS_MASTER_DIS;
218 WREG32(R_00004C_BUS_CNTL, tmp);
771fe6b9 219 /* FIXME: setup default page */
c010f800 220 WREG32_MC(R_000100_MC_PT0_CNTL,
4f15d24a
AD		 221 (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) |
222 S_000100_EFFECTIVE_L2_QUEUE_SIZE(6)));
223
771fe6b9 224 for (i = 0; i < 19; i++) {
c010f800 225 WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i,
4f15d24a
AD		 226 S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) |
227 S_00016C_SYSTEM_ACCESS_MODE_MASK(
228 V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS) |
229 S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS(
230 V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH) |
231 S_00016C_EFFECTIVE_L1_CACHE_SIZE(3) |
232 S_00016C_ENABLE_FRAGMENT_PROCESSING(1) |
233 S_00016C_EFFECTIVE_L1_QUEUE_SIZE(3));
771fe6b9 234 }
771fe6b9 235 /* enable first context */
c010f800 236 WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL,
4f15d24a
AD		 237 S_000102_ENABLE_PAGE_TABLE(1) |
238 S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT));
239
771fe6b9 240 /* disable all other contexts */
4f15d24a 241 for (i = 1; i < 8; i++)
c010f800 242 WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0);
771fe6b9
JG		 243
244 /* setup the page table */
c010f800 245 WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR,
4f15d24a
AD		 246 rdev->gart.table_addr);
247 WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start);
248 WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end);
c010f800 249 WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0);
771fe6b9 250
4f15d24a
AD		 251 /* System context maps to VRAM space */
252 WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start);
253 WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end);
254
771fe6b9 255 /* enable page tables */
c010f800
JG		 256 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
257 WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1)));
258 tmp = RREG32_MC(R_000009_MC_CNTL1);
259 WREG32_MC(R_000009_MC_CNTL1, (tmp | S_000009_ENABLE_PAGE_TABLES(1)));
771fe6b9
JG		 260 rs600_gart_tlb_flush(rdev);
261 rdev->gart.ready = true;
262 return 0;
263}
264
265void rs600_gart_disable(struct radeon_device *rdev)
266{
4c788679
JG		 267 u32 tmp;
268 int r;
771fe6b9
JG		 269
270 /* FIXME: disable out of gart access */
c010f800
JG		 271 WREG32_MC(R_000100_MC_PT0_CNTL, 0);
272 tmp = RREG32_MC(R_000009_MC_CNTL1);
273 WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES);
4aac0473 274 if (rdev->gart.table.vram.robj) {
4c788679
JG		 275 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
276 if (r == 0) {
277 radeon_bo_kunmap(rdev->gart.table.vram.robj);
278 radeon_bo_unpin(rdev->gart.table.vram.robj);
279 radeon_bo_unreserve(rdev->gart.table.vram.robj);
280 }
4aac0473
JG		 281 }
282}
283
284void rs600_gart_fini(struct radeon_device *rdev)
285{
286 rs600_gart_disable(rdev);
287 radeon_gart_table_vram_free(rdev);
288 radeon_gart_fini(rdev);
771fe6b9
JG		 289}
290
291#define R600_PTE_VALID (1 << 0)
292#define R600_PTE_SYSTEM (1 << 1)
293#define R600_PTE_SNOOPED (1 << 2)
294#define R600_PTE_READABLE (1 << 5)
295#define R600_PTE_WRITEABLE (1 << 6)
296
297int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
298{
299 void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
300
301 if (i < 0 || i > rdev->gart.num_gpu_pages) {
302 return -EINVAL;
303 }
304 addr = addr & 0xFFFFFFFFFFFFF000ULL;
305 addr |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED;
306 addr |= R600_PTE_READABLE | R600_PTE_WRITEABLE;
307 writeq(addr, ((void __iomem *)ptr) + (i * 8));
308 return 0;
309}
310
7ed220d7
MD		 311int rs600_irq_set(struct radeon_device *rdev)
312{
313 uint32_t tmp = 0;
314 uint32_t mode_int = 0;
dcfdd408
AD		 315 u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) &
316 ~S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
317 u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) &
318 ~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
7ed220d7 319
003e69f9
JG		 320 if (!rdev->irq.installed) {
321 WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
322 WREG32(R_000040_GEN_INT_CNTL, 0);
323 return -EINVAL;
324 }
7ed220d7 325 if (rdev->irq.sw_int) {
c010f800 326 tmp |= S_000040_SW_INT_EN(1);
7ed220d7
MD		 327 }
328 if (rdev->irq.crtc_vblank_int[0]) {
c010f800 329 mode_int |= S_006540_D1MODE_VBLANK_INT_MASK(1);
7ed220d7
MD		 330 }
331 if (rdev->irq.crtc_vblank_int[1]) {
c010f800 332 mode_int |= S_006540_D2MODE_VBLANK_INT_MASK(1);
7ed220d7 333 }
dcfdd408
AD		 334 if (rdev->irq.hpd[0]) {
335 hpd1 |= S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
336 }
337 if (rdev->irq.hpd[1]) {
338 hpd2 |= S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
339 }
c010f800
JG		 340 WREG32(R_000040_GEN_INT_CNTL, tmp);
341 WREG32(R_006540_DxMODE_INT_MASK, mode_int);
dcfdd408
AD		 342 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
343 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
7ed220d7
MD		 344 return 0;
345}
346
347static inline uint32_t rs600_irq_ack(struct radeon_device *rdev, u32 *r500_disp_int)
348{
01ceae8e
JG		 349 uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS);
350 uint32_t irq_mask = ~C_000044_SW_INT;
dcfdd408 351 u32 tmp;
c010f800 352
01ceae8e 353 if (G_000044_DISPLAY_INT_STAT(irqs)) {
c010f800
JG		 354 *r500_disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS);
355 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(*r500_disp_int)) {
356 WREG32(R_006534_D1MODE_VBLANK_STATUS,
357 S_006534_D1MODE_VBLANK_ACK(1));
7ed220d7 358 }
c010f800
JG		 359 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(*r500_disp_int)) {
360 WREG32(R_006D34_D2MODE_VBLANK_STATUS,
361 S_006D34_D2MODE_VBLANK_ACK(1));
7ed220d7 362 }
dcfdd408
AD		 363 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(*r500_disp_int)) {
364 tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
365 tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(1);
366 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
367 }
368 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(*r500_disp_int)) {
369 tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
370 tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(1);
371 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
372 }
7ed220d7
MD		 373 } else {
374 *r500_disp_int = 0;
375 }
376
377 if (irqs) {
01ceae8e 378 WREG32(R_000044_GEN_INT_STATUS, irqs);
7ed220d7
MD		 379 }
380 return irqs & irq_mask;
381}
382
ac447df4
JG		 383void rs600_irq_disable(struct radeon_device *rdev)
384{
385 u32 tmp;
386
387 WREG32(R_000040_GEN_INT_CNTL, 0);
388 WREG32(R_006540_DxMODE_INT_MASK, 0);
389 /* Wait and acknowledge irq */
390 mdelay(1);
391 rs600_irq_ack(rdev, &tmp);
392}
393
7ed220d7
MD		 394int rs600_irq_process(struct radeon_device *rdev)
395{
3e5cb98d 396 uint32_t status, msi_rearm;
7ed220d7 397 uint32_t r500_disp_int;
d4877cf2 398 bool queue_hotplug = false;
7ed220d7
MD		 399
400 status = rs600_irq_ack(rdev, &r500_disp_int);
401 if (!status && !r500_disp_int) {
402 return IRQ_NONE;
403 }
404 while (status || r500_disp_int) {
405 /* SW interrupt */
43b19f16 406 if (G_000044_SW_INT(status))
7ed220d7 407 radeon_fence_process(rdev);
7ed220d7 408 /* Vertical blank interrupts */
c913e23a 409 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(r500_disp_int)) {
7ed220d7 410 drm_handle_vblank(rdev->ddev, 0);
73a6d3fc 411 wake_up(&rdev->irq.vblank_queue);
c913e23a
RM		 412 }
413 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(r500_disp_int)) {
7ed220d7 414 drm_handle_vblank(rdev->ddev, 1);
73a6d3fc 415 wake_up(&rdev->irq.vblank_queue);
c913e23a 416 }
dcfdd408 417 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(r500_disp_int)) {
d4877cf2
AD		 418 queue_hotplug = true;
419 DRM_DEBUG("HPD1\n");
dcfdd408
AD		 420 }
421 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(r500_disp_int)) {
d4877cf2
AD		 422 queue_hotplug = true;
423 DRM_DEBUG("HPD2\n");
dcfdd408 424 }
7ed220d7
MD		 425 status = rs600_irq_ack(rdev, &r500_disp_int);
426 }
d4877cf2
AD		 427 if (queue_hotplug)
428 queue_work(rdev->wq, &rdev->hotplug_work);
3e5cb98d
AD		 429 if (rdev->msi_enabled) {
430 switch (rdev->family) {
431 case CHIP_RS600:
432 case CHIP_RS690:
433 case CHIP_RS740:
434 msi_rearm = RREG32(RADEON_BUS_CNTL) & ~RS600_MSI_REARM;
435 WREG32(RADEON_BUS_CNTL, msi_rearm);
436 WREG32(RADEON_BUS_CNTL, msi_rearm | RS600_MSI_REARM);
437 break;
438 default:
439 msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN;
440 WREG32(RADEON_MSI_REARM_EN, msi_rearm);
441 WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN);
442 break;
443 }
444 }
7ed220d7
MD		 445 return IRQ_HANDLED;
446}
447
448u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc)
449{
450 if (crtc == 0)
c010f800 451 return RREG32(R_0060A4_D1CRTC_STATUS_FRAME_COUNT);
7ed220d7 452 else
c010f800 453 return RREG32(R_0068A4_D2CRTC_STATUS_FRAME_COUNT);
7ed220d7
MD		 454}
455
771fe6b9
JG		 456int rs600_mc_wait_for_idle(struct radeon_device *rdev)
457{
458 unsigned i;
771fe6b9
JG		 459
460 for (i = 0; i < rdev->usec_timeout; i++) {
c010f800 461 if (G_000000_MC_IDLE(RREG32_MC(R_000000_MC_STATUS)))
771fe6b9 462 return 0;
c010f800 463 udelay(1);
771fe6b9
JG		 464 }
465 return -1;
466}
467
771fe6b9
JG		 468void rs600_gpu_init(struct radeon_device *rdev)
469{
771fe6b9 470 r100_hdp_reset(rdev);
771fe6b9 471 r420_pipes_init(rdev);
c010f800
JG		 472 /* Wait for mc idle */
473 if (rs600_mc_wait_for_idle(rdev))
474 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
771fe6b9
JG		 475}
476
771fe6b9
JG		 477void rs600_vram_info(struct radeon_device *rdev)
478{
771fe6b9
JG		 479 rdev->mc.vram_is_ddr = true;
480 rdev->mc.vram_width = 128;
722f2943
AD		 481
482 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
483 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
484
485 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
486 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
0088dbdb
AD		 487
488 if (rdev->mc.mc_vram_size > rdev->mc.aper_size)
489 rdev->mc.mc_vram_size = rdev->mc.aper_size;
490
491 if (rdev->mc.real_vram_size > rdev->mc.aper_size)
492 rdev->mc.real_vram_size = rdev->mc.aper_size;
771fe6b9
JG		 493}
494
c93bb85b
JG		 495void rs600_bandwidth_update(struct radeon_device *rdev)
496{
497 /* FIXME: implement, should this be like rs690 ? */
498}
499
771fe6b9
JG		 500uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg)
501{
c010f800
JG		 502 WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
503 S_000070_MC_IND_CITF_ARB0(1));
504 return RREG32(R_000074_MC_IND_DATA);
771fe6b9
JG		 505}
506
507void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
508{
c010f800
JG		 509 WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
510 S_000070_MC_IND_CITF_ARB0(1) | S_000070_MC_IND_WR_EN(1));
511 WREG32(R_000074_MC_IND_DATA, v);
512}
513
514void rs600_debugfs(struct radeon_device *rdev)
515{
516 if (r100_debugfs_rbbm_init(rdev))
517 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
771fe6b9 518}
3f7dc91a 519
3bc68535 520void rs600_set_safe_registers(struct radeon_device *rdev)
3f7dc91a
DA		 521{
522 rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm;
523 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm);
3bc68535
JG		 524}
525
c010f800
JG		 526static void rs600_mc_program(struct radeon_device *rdev)
527{
528 struct rv515_mc_save save;
529
530 /* Stops all mc clients */
531 rv515_mc_stop(rdev, &save);
532
533 /* Wait for mc idle */
534 if (rs600_mc_wait_for_idle(rdev))
535 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
536
537 /* FIXME: What does AGP means for such chipset ? */
538 WREG32_MC(R_000005_MC_AGP_LOCATION, 0x0FFFFFFF);
539 WREG32_MC(R_000006_AGP_BASE, 0);
540 WREG32_MC(R_000007_AGP_BASE_2, 0);
541 /* Program MC */
542 WREG32_MC(R_000004_MC_FB_LOCATION,
543 S_000004_MC_FB_START(rdev->mc.vram_start >> 16) |
544 S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16));
545 WREG32(R_000134_HDP_FB_LOCATION,
546 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
547
548 rv515_mc_resume(rdev, &save);
549}
550
551static int rs600_startup(struct radeon_device *rdev)
552{
553 int r;
554
555 rs600_mc_program(rdev);
556 /* Resume clock */
557 rv515_clock_startup(rdev);
558 /* Initialize GPU configuration (# pipes, ...) */
559 rs600_gpu_init(rdev);
560 /* Initialize GART (initialize after TTM so we can allocate
561 * memory through TTM but finalize after TTM) */
562 r = rs600_gart_enable(rdev);
563 if (r)
564 return r;
565 /* Enable IRQ */
c010f800 566 rs600_irq_set(rdev);
cafe6609 567 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
c010f800
JG		 568 /* 1M ring buffer */
569 r = r100_cp_init(rdev, 1024 * 1024);
570 if (r) {
571 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
572 return r;
573 }
574 r = r100_wb_init(rdev);
575 if (r)
576 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
577 r = r100_ib_init(rdev);
578 if (r) {
579 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
580 return r;
581 }
582 return 0;
583}
584
585int rs600_resume(struct radeon_device *rdev)
586{
587 /* Make sur GART are not working */
588 rs600_gart_disable(rdev);
589 /* Resume clock before doing reset */
590 rv515_clock_startup(rdev);
591 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
592 if (radeon_gpu_reset(rdev)) {
593 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
594 RREG32(R_000E40_RBBM_STATUS),
595 RREG32(R_0007C0_CP_STAT));
596 }
597 /* post */
598 atom_asic_init(rdev->mode_info.atom_context);
599 /* Resume clock after posting */
600 rv515_clock_startup(rdev);
550e2d92
DA		 601 /* Initialize surface registers */
602 radeon_surface_init(rdev);
c010f800
JG		 603 return rs600_startup(rdev);
604}
605
606int rs600_suspend(struct radeon_device *rdev)
607{
608 r100_cp_disable(rdev);
609 r100_wb_disable(rdev);
ac447df4 610 rs600_irq_disable(rdev);
c010f800
JG		 611 rs600_gart_disable(rdev);
612 return 0;
613}
614
615void rs600_fini(struct radeon_device *rdev)
616{
c010f800
JG		 617 r100_cp_fini(rdev);
618 r100_wb_fini(rdev);
619 r100_ib_fini(rdev);
620 radeon_gem_fini(rdev);
621 rs600_gart_fini(rdev);
622 radeon_irq_kms_fini(rdev);
623 radeon_fence_driver_fini(rdev);
4c788679 624 radeon_bo_fini(rdev);
c010f800
JG		 625 radeon_atombios_fini(rdev);
626 kfree(rdev->bios);
627 rdev->bios = NULL;
628}
629
3bc68535
JG		 630int rs600_init(struct radeon_device *rdev)
631{
c010f800
JG		 632 int r;
633
c010f800
JG		 634 /* Disable VGA */
635 rv515_vga_render_disable(rdev);
636 /* Initialize scratch registers */
637 radeon_scratch_init(rdev);
638 /* Initialize surface registers */
639 radeon_surface_init(rdev);
640 /* BIOS */
641 if (!radeon_get_bios(rdev)) {
642 if (ASIC_IS_AVIVO(rdev))
643 return -EINVAL;
644 }
645 if (rdev->is_atom_bios) {
646 r = radeon_atombios_init(rdev);
647 if (r)
648 return r;
649 } else {
650 dev_err(rdev->dev, "Expecting atombios for RS600 GPU\n");
651 return -EINVAL;
652 }
653 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
654 if (radeon_gpu_reset(rdev)) {
655 dev_warn(rdev->dev,
656 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
657 RREG32(R_000E40_RBBM_STATUS),
658 RREG32(R_0007C0_CP_STAT));
659 }
660 /* check if cards are posted or not */
72542d77
DA		 661 if (radeon_boot_test_post_card(rdev) == false)
662 return -EINVAL;
663
c010f800
JG		 664 /* Initialize clocks */
665 radeon_get_clock_info(rdev->ddev);
7433874e
RM		 666 /* Initialize power management */
667 radeon_pm_init(rdev);
c010f800
JG		 668 /* Get vram informations */
669 rs600_vram_info(rdev);
670 /* Initialize memory controller (also test AGP) */
64bffd03 671 r = rs600_mc_init(rdev);
c010f800
JG		 672 if (r)
673 return r;
674 rs600_debugfs(rdev);
675 /* Fence driver */
676 r = radeon_fence_driver_init(rdev);
677 if (r)
678 return r;
679 r = radeon_irq_kms_init(rdev);
680 if (r)
681 return r;
682 /* Memory manager */
4c788679 683 r = radeon_bo_init(rdev);
c010f800
JG		 684 if (r)
685 return r;
686 r = rs600_gart_init(rdev);
687 if (r)
688 return r;
689 rs600_set_safe_registers(rdev);
690 rdev->accel_working = true;
691 r = rs600_startup(rdev);
692 if (r) {
693 /* Somethings want wront with the accel init stop accel */
694 dev_err(rdev->dev, "Disabling GPU acceleration\n");
c010f800
JG		 695 r100_cp_fini(rdev);
696 r100_wb_fini(rdev);
697 r100_ib_fini(rdev);
698 rs600_gart_fini(rdev);
699 radeon_irq_kms_fini(rdev);
700 rdev->accel_working = false;
701 }
3f7dc91a
DA		 702 return 0;
703}
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