[net-next-2.6.git] / drivers / gpu / drm / radeon / rs400.c

/*
 * Copyright 2008 Advanced Micro Devices, Inc.
 * Copyright 2008 Red Hat Inc.
 * Copyright 2009 Jerome Glisse.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Dave Airlie
 *          Alex Deucher
 *          Jerome Glisse
 */
#include <linux/seq_file.h>
#include <drm/drmP.h>
#include "radeon.h"
#include "rs400d.h"

/* This files gather functions specifics to : rs400,rs480 */
static int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev);

void rs400_gart_adjust_size(struct radeon_device *rdev)
{
	/* Check gart size */
	switch (rdev->mc.gtt_size/(1024*1024)) {
	case 32:
	case 64:
	case 128:
	case 256:
	case 512:
	case 1024:
	case 2048:
		break;
	default:
		DRM_ERROR("Unable to use IGP GART size %uM\n",
			  (unsigned)(rdev->mc.gtt_size >> 20));
		DRM_ERROR("Valid GART size for IGP are 32M,64M,128M,256M,512M,1G,2G\n");
		DRM_ERROR("Forcing to 32M GART size\n");
		rdev->mc.gtt_size = 32 * 1024 * 1024;
		return;
	}
	if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
		/* FIXME: RS400 & RS480 seems to have issue with GART size
		 * if 4G of system memory (needs more testing) */
		rdev->mc.gtt_size = 32 * 1024 * 1024;
		DRM_ERROR("Forcing to 32M GART size (because of ASIC bug ?)\n");
	}
}

void rs400_gart_tlb_flush(struct radeon_device *rdev)
{
	uint32_t tmp;
	unsigned int timeout = rdev->usec_timeout;

	WREG32_MC(RS480_GART_CACHE_CNTRL, RS480_GART_CACHE_INVALIDATE);
	do {
		tmp = RREG32_MC(RS480_GART_CACHE_CNTRL);
		if ((tmp & RS480_GART_CACHE_INVALIDATE) == 0)
			break;
		DRM_UDELAY(1);
		timeout--;
	} while (timeout > 0);
	WREG32_MC(RS480_GART_CACHE_CNTRL, 0);
}

int rs400_gart_init(struct radeon_device *rdev)
{
	int r;

	if (rdev->gart.table.ram.ptr) {
		WARN(1, "RS400 GART already initialized.\n");
		return 0;
	}
	/* Check gart size */
	switch(rdev->mc.gtt_size / (1024 * 1024)) {
	case 32:
	case 64:
	case 128:
	case 256:
	case 512:
	case 1024:
	case 2048:
		break;
	default:
		return -EINVAL;
	}
	/* Initialize common gart structure */
	r = radeon_gart_init(rdev);
	if (r)
		return r;
	if (rs400_debugfs_pcie_gart_info_init(rdev))
		DRM_ERROR("Failed to register debugfs file for RS400 GART !\n");
	rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
	return radeon_gart_table_ram_alloc(rdev);
}

int rs400_gart_enable(struct radeon_device *rdev)
{
	uint32_t size_reg;
	uint32_t tmp;

	radeon_gart_restore(rdev);
	tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
	tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS;
	WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp);
	/* Check gart size */
	switch(rdev->mc.gtt_size / (1024 * 1024)) {
	case 32:
		size_reg = RS480_VA_SIZE_32MB;
		break;
	case 64:
		size_reg = RS480_VA_SIZE_64MB;
		break;
	case 128:
		size_reg = RS480_VA_SIZE_128MB;
		break;
	case 256:
		size_reg = RS480_VA_SIZE_256MB;
		break;
	case 512:
		size_reg = RS480_VA_SIZE_512MB;
		break;
	case 1024:
		size_reg = RS480_VA_SIZE_1GB;
		break;
	case 2048:
		size_reg = RS480_VA_SIZE_2GB;
		break;
	default:
		return -EINVAL;
	}
	/* It should be fine to program it to max value */
	if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) {
		WREG32_MC(RS690_MCCFG_AGP_BASE, 0xFFFFFFFF);
		WREG32_MC(RS690_MCCFG_AGP_BASE_2, 0);
	} else {
		WREG32(RADEON_AGP_BASE, 0xFFFFFFFF);
		WREG32(RS480_AGP_BASE_2, 0);
	}
	tmp = REG_SET(RS690_MC_AGP_TOP, rdev->mc.gtt_end >> 16);
	tmp |= REG_SET(RS690_MC_AGP_START, rdev->mc.gtt_start >> 16);
	if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) {
		WREG32_MC(RS690_MCCFG_AGP_LOCATION, tmp);
		tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
		WREG32(RADEON_BUS_CNTL, tmp);
	} else {
		WREG32(RADEON_MC_AGP_LOCATION, tmp);
		tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
		WREG32(RADEON_BUS_CNTL, tmp);
	}
	/* Table should be in 32bits address space so ignore bits above. */
	tmp = (u32)rdev->gart.table_addr & 0xfffff000;
	tmp |= (upper_32_bits(rdev->gart.table_addr) & 0xff) << 4;

	WREG32_MC(RS480_GART_BASE, tmp);
	/* TODO: more tweaking here */
	WREG32_MC(RS480_GART_FEATURE_ID,
		  (RS480_TLB_ENABLE |
		   RS480_GTW_LAC_EN | RS480_1LEVEL_GART));
	/* Disable snooping */
	WREG32_MC(RS480_AGP_MODE_CNTL,
		  (1 << RS480_REQ_TYPE_SNOOP_SHIFT) | RS480_REQ_TYPE_SNOOP_DIS);
	/* Disable AGP mode */
	/* FIXME: according to doc we should set HIDE_MMCFG_BAR=0,
	 * AGPMODE30=0 & AGP30ENHANCED=0 in NB_CNTL */
	if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) {
		WREG32_MC(RS480_MC_MISC_CNTL,
			  (RS480_GART_INDEX_REG_EN | RS690_BLOCK_GFX_D3_EN));
	} else {
		WREG32_MC(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN);
	}
	/* Enable gart */
	WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN | size_reg));
	rs400_gart_tlb_flush(rdev);
	rdev->gart.ready = true;
	return 0;
}

void rs400_gart_disable(struct radeon_device *rdev)
{
	uint32_t tmp;

	tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
	tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS;
	WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp);
	WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
}

void rs400_gart_fini(struct radeon_device *rdev)
{
	rs400_gart_disable(rdev);
	radeon_gart_table_ram_free(rdev);
	radeon_gart_fini(rdev);
}

int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
{
	uint32_t entry;

	if (i < 0 || i > rdev->gart.num_gpu_pages) {
		return -EINVAL;
	}

	entry = (lower_32_bits(addr) & PAGE_MASK) |
		((upper_32_bits(addr) & 0xff) << 4) |
		0xc;
	entry = cpu_to_le32(entry);
	rdev->gart.table.ram.ptr[i] = entry;
	return 0;
}

int rs400_mc_wait_for_idle(struct radeon_device *rdev)
{
	unsigned i;
	uint32_t tmp;

	for (i = 0; i < rdev->usec_timeout; i++) {
		/* read MC_STATUS */
		tmp = RREG32(0x0150);
		if (tmp & (1 << 2)) {
			return 0;
		}
		DRM_UDELAY(1);
	}
	return -1;
}

void rs400_gpu_init(struct radeon_device *rdev)
{
	/* FIXME: HDP same place on rs400 ? */
	r100_hdp_reset(rdev);
	/* FIXME: is this correct ? */
	r420_pipes_init(rdev);
	if (rs400_mc_wait_for_idle(rdev)) {
		printk(KERN_WARNING "rs400: Failed to wait MC idle while "
		       "programming pipes. Bad things might happen. %08x\n", RREG32(0x150));
	}
}

void rs400_mc_init(struct radeon_device *rdev)
{
	u64 base;

	rs400_gart_adjust_size(rdev);
	rdev->mc.igp_sideport_enabled = radeon_combios_sideport_present(rdev);
	/* DDR for all card after R300 & IGP */
	rdev->mc.vram_is_ddr = true;
	rdev->mc.vram_width = 128;
	r100_vram_init_sizes(rdev);
	base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
	radeon_vram_location(rdev, &rdev->mc, base);
	radeon_gtt_location(rdev, &rdev->mc);
}

uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg)
{
	uint32_t r;

	WREG32(RS480_NB_MC_INDEX, reg & 0xff);
	r = RREG32(RS480_NB_MC_DATA);
	WREG32(RS480_NB_MC_INDEX, 0xff);
	return r;
}

void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
{
	WREG32(RS480_NB_MC_INDEX, ((reg) & 0xff) | RS480_NB_MC_IND_WR_EN);
	WREG32(RS480_NB_MC_DATA, (v));
	WREG32(RS480_NB_MC_INDEX, 0xff);
}

#if defined(CONFIG_DEBUG_FS)
static int rs400_debugfs_gart_info(struct seq_file *m, void *data)
{
	struct drm_info_node *node = (struct drm_info_node *) m->private;
	struct drm_device *dev = node->minor->dev;
	struct radeon_device *rdev = dev->dev_private;
	uint32_t tmp;

	tmp = RREG32(RADEON_HOST_PATH_CNTL);
	seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
	tmp = RREG32(RADEON_BUS_CNTL);
	seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
	tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
	seq_printf(m, "AIC_CTRL_SCRATCH 0x%08x\n", tmp);
	if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) {
		tmp = RREG32_MC(RS690_MCCFG_AGP_BASE);
		seq_printf(m, "MCCFG_AGP_BASE 0x%08x\n", tmp);
		tmp = RREG32_MC(RS690_MCCFG_AGP_BASE_2);
		seq_printf(m, "MCCFG_AGP_BASE_2 0x%08x\n", tmp);
		tmp = RREG32_MC(RS690_MCCFG_AGP_LOCATION);
		seq_printf(m, "MCCFG_AGP_LOCATION 0x%08x\n", tmp);
		tmp = RREG32_MC(0x100);
		seq_printf(m, "MCCFG_FB_LOCATION 0x%08x\n", tmp);
		tmp = RREG32(0x134);
		seq_printf(m, "HDP_FB_LOCATION 0x%08x\n", tmp);
	} else {
		tmp = RREG32(RADEON_AGP_BASE);
		seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
		tmp = RREG32(RS480_AGP_BASE_2);
		seq_printf(m, "AGP_BASE_2 0x%08x\n", tmp);
		tmp = RREG32(RADEON_MC_AGP_LOCATION);
		seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
	}
	tmp = RREG32_MC(RS480_GART_BASE);
	seq_printf(m, "GART_BASE 0x%08x\n", tmp);
	tmp = RREG32_MC(RS480_GART_FEATURE_ID);
	seq_printf(m, "GART_FEATURE_ID 0x%08x\n", tmp);
	tmp = RREG32_MC(RS480_AGP_MODE_CNTL);
	seq_printf(m, "AGP_MODE_CONTROL 0x%08x\n", tmp);
	tmp = RREG32_MC(RS480_MC_MISC_CNTL);
	seq_printf(m, "MC_MISC_CNTL 0x%08x\n", tmp);
	tmp = RREG32_MC(0x5F);
	seq_printf(m, "MC_MISC_UMA_CNTL 0x%08x\n", tmp);
	tmp = RREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE);
	seq_printf(m, "AGP_ADDRESS_SPACE_SIZE 0x%08x\n", tmp);
	tmp = RREG32_MC(RS480_GART_CACHE_CNTRL);
	seq_printf(m, "GART_CACHE_CNTRL 0x%08x\n", tmp);
	tmp = RREG32_MC(0x3B);
	seq_printf(m, "MC_GART_ERROR_ADDRESS 0x%08x\n", tmp);
	tmp = RREG32_MC(0x3C);
	seq_printf(m, "MC_GART_ERROR_ADDRESS_HI 0x%08x\n", tmp);
	tmp = RREG32_MC(0x30);
	seq_printf(m, "GART_ERROR_0 0x%08x\n", tmp);
	tmp = RREG32_MC(0x31);
	seq_printf(m, "GART_ERROR_1 0x%08x\n", tmp);
	tmp = RREG32_MC(0x32);
	seq_printf(m, "GART_ERROR_2 0x%08x\n", tmp);
	tmp = RREG32_MC(0x33);
	seq_printf(m, "GART_ERROR_3 0x%08x\n", tmp);
	tmp = RREG32_MC(0x34);
	seq_printf(m, "GART_ERROR_4 0x%08x\n", tmp);
	tmp = RREG32_MC(0x35);
	seq_printf(m, "GART_ERROR_5 0x%08x\n", tmp);
	tmp = RREG32_MC(0x36);
	seq_printf(m, "GART_ERROR_6 0x%08x\n", tmp);
	tmp = RREG32_MC(0x37);
	seq_printf(m, "GART_ERROR_7 0x%08x\n", tmp);
	return 0;
}

static struct drm_info_list rs400_gart_info_list[] = {
	{"rs400_gart_info", rs400_debugfs_gart_info, 0, NULL},
};
#endif

static int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
{
#if defined(CONFIG_DEBUG_FS)
	return radeon_debugfs_add_files(rdev, rs400_gart_info_list, 1);
#else
	return 0;
#endif
}

void rs400_mc_program(struct radeon_device *rdev)
{
	struct r100_mc_save save;

	/* Stops all mc clients */
	r100_mc_stop(rdev, &save);

	/* Wait for mc idle */
	if (rs400_mc_wait_for_idle(rdev))
		dev_warn(rdev->dev, "rs400: Wait MC idle timeout before updating MC.\n");
	WREG32(R_000148_MC_FB_LOCATION,
		S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
		S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));

	r100_mc_resume(rdev, &save);
}

static int rs400_startup(struct radeon_device *rdev)
{
	int r;

	rs400_mc_program(rdev);
	/* Resume clock */
	r300_clock_startup(rdev);
	/* Initialize GPU configuration (# pipes, ...) */
	rs400_gpu_init(rdev);
	r100_enable_bm(rdev);
	/* Initialize GART (initialize after TTM so we can allocate
	 * memory through TTM but finalize after TTM) */
	r = rs400_gart_enable(rdev);
	if (r)
		return r;
	/* Enable IRQ */
	r100_irq_set(rdev);
	rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
	/* 1M ring buffer */
	r = r100_cp_init(rdev, 1024 * 1024);
	if (r) {
		dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
		return r;
	}
	r = r100_wb_init(rdev);
	if (r)
		dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
	r = r100_ib_init(rdev);
	if (r) {
		dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
		return r;
	}
	return 0;
}

int rs400_resume(struct radeon_device *rdev)
{
	/* Make sur GART are not working */
	rs400_gart_disable(rdev);
	/* Resume clock before doing reset */
	r300_clock_startup(rdev);
	/* setup MC before calling post tables */
	rs400_mc_program(rdev);
	/* Reset gpu before posting otherwise ATOM will enter infinite loop */
	if (radeon_gpu_reset(rdev)) {
		dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
			RREG32(R_000E40_RBBM_STATUS),
			RREG32(R_0007C0_CP_STAT));
	}
	/* post */
	radeon_combios_asic_init(rdev->ddev);
	/* Resume clock after posting */
	r300_clock_startup(rdev);
	/* Initialize surface registers */
	radeon_surface_init(rdev);
	return rs400_startup(rdev);
}

int rs400_suspend(struct radeon_device *rdev)
{
	r100_cp_disable(rdev);
	r100_wb_disable(rdev);
	r100_irq_disable(rdev);
	rs400_gart_disable(rdev);
	return 0;
}

void rs400_fini(struct radeon_device *rdev)
{
	r100_cp_fini(rdev);
	r100_wb_fini(rdev);
	r100_ib_fini(rdev);
	radeon_gem_fini(rdev);
	rs400_gart_fini(rdev);
	radeon_irq_kms_fini(rdev);
	radeon_fence_driver_fini(rdev);
	radeon_bo_fini(rdev);
	radeon_atombios_fini(rdev);
	kfree(rdev->bios);
	rdev->bios = NULL;
}

int rs400_init(struct radeon_device *rdev)
{
	int r;

	/* Disable VGA */
	r100_vga_render_disable(rdev);
	/* Initialize scratch registers */
	radeon_scratch_init(rdev);
	/* Initialize surface registers */
	radeon_surface_init(rdev);
	/* TODO: disable VGA need to use VGA request */
	/* BIOS*/
	if (!radeon_get_bios(rdev)) {
		if (ASIC_IS_AVIVO(rdev))
			return -EINVAL;
	}
	if (rdev->is_atom_bios) {
		dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
		return -EINVAL;
	} else {
		r = radeon_combios_init(rdev);
		if (r)
			return r;
	}
	/* Reset gpu before posting otherwise ATOM will enter infinite loop */
	if (radeon_gpu_reset(rdev)) {
		dev_warn(rdev->dev,
			"GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
			RREG32(R_000E40_RBBM_STATUS),
			RREG32(R_0007C0_CP_STAT));
	}
	/* check if cards are posted or not */
	if (radeon_boot_test_post_card(rdev) == false)
		return -EINVAL;

	/* Initialize clocks */
	radeon_get_clock_info(rdev->ddev);
	/* Initialize power management */
	radeon_pm_init(rdev);
	/* initialize memory controller */
	rs400_mc_init(rdev);
	/* Fence driver */
	r = radeon_fence_driver_init(rdev);
	if (r)
		return r;
	r = radeon_irq_kms_init(rdev);
	if (r)
		return r;
	/* Memory manager */
	r = radeon_bo_init(rdev);
	if (r)
		return r;
	r = rs400_gart_init(rdev);
	if (r)
		return r;
	r300_set_reg_safe(rdev);
	rdev->accel_working = true;
	r = rs400_startup(rdev);
	if (r) {
		/* Somethings want wront with the accel init stop accel */
		dev_err(rdev->dev, "Disabling GPU acceleration\n");
		r100_cp_fini(rdev);
		r100_wb_fini(rdev);
		r100_ib_fini(rdev);
		rs400_gart_fini(rdev);
		radeon_irq_kms_fini(rdev);
		rdev->accel_working = false;
	}
	return 0;
}
Commit	Line	Data
771fe6b9 JG	1	/*
	2	* Copyright 2008 Advanced Micro Devices, Inc.
	3	* Copyright 2008 Red Hat Inc.
	4	* Copyright 2009 Jerome Glisse.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a
	7	* copy of this software and associated documentation files (the "Software"),
	8	* to deal in the Software without restriction, including without limitation
	9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	10	* and/or sell copies of the Software, and to permit persons to whom the
	11	* Software is furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	22	* OTHER DEALINGS IN THE SOFTWARE.
	23	*
	24	* Authors: Dave Airlie
	25	* Alex Deucher
	26	* Jerome Glisse
	27	*/
	28	#include <linux/seq_file.h>
	29	#include <drm/drmP.h>
771fe6b9	30	#include "radeon.h"
ca6ffc64	31	#include "rs400d.h"
771fe6b9	32
ca6ffc64 JG	33	/* This files gather functions specifics to : rs400,rs480 */
ca6ffc64 JG	34	static int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
771fe6b9	35
771fe6b9 JG	36	void rs400_gart_adjust_size(struct radeon_device *rdev)
	37	{
	38	/* Check gart size */
	39	switch (rdev->mc.gtt_size/(1024*1024)) {
	40	case 32:
	41	case 64:
	42	case 128:
	43	case 256:
	44	case 512:
	45	case 1024:
	46	case 2048:
	47	break;
	48	default:
	49	DRM_ERROR("Unable to use IGP GART size %uM\n",
3ce0a23d	50	(unsigned)(rdev->mc.gtt_size >> 20));
771fe6b9 JG	51	DRM_ERROR("Valid GART size for IGP are 32M,64M,128M,256M,512M,1G,2G\n");
	52	DRM_ERROR("Forcing to 32M GART size\n");
	53	rdev->mc.gtt_size = 32 * 1024 * 1024;
	54	return;
	55	}
	56	if (rdev->family == CHIP_RS400 \|\| rdev->family == CHIP_RS480) {
	57	/* FIXME: RS400 & RS480 seems to have issue with GART size
	58	* if 4G of system memory (needs more testing) */
	59	rdev->mc.gtt_size = 32 * 1024 * 1024;
	60	DRM_ERROR("Forcing to 32M GART size (because of ASIC bug ?)\n");
	61	}
	62	}
	63
	64	void rs400_gart_tlb_flush(struct radeon_device *rdev)
	65	{
	66	uint32_t tmp;
	67	unsigned int timeout = rdev->usec_timeout;
	68
	69	WREG32_MC(RS480_GART_CACHE_CNTRL, RS480_GART_CACHE_INVALIDATE);
	70	do {
	71	tmp = RREG32_MC(RS480_GART_CACHE_CNTRL);
	72	if ((tmp & RS480_GART_CACHE_INVALIDATE) == 0)
	73	break;
	74	DRM_UDELAY(1);
	75	timeout--;
	76	} while (timeout > 0);
	77	WREG32_MC(RS480_GART_CACHE_CNTRL, 0);
	78	}
	79
4aac0473	80	int rs400_gart_init(struct radeon_device *rdev)
771fe6b9	81	{
771fe6b9 JG	82	int r;
771fe6b9 JG	83
4aac0473 JG	84	if (rdev->gart.table.ram.ptr) {
	85	WARN(1, "RS400 GART already initialized.\n");
	86	return 0;
	87	}
	88	/* Check gart size */
	89	switch(rdev->mc.gtt_size / (1024 * 1024)) {
	90	case 32:
	91	case 64:
	92	case 128:
	93	case 256:
	94	case 512:
	95	case 1024:
	96	case 2048:
	97	break;
	98	default:
	99	return -EINVAL;
	100	}
771fe6b9 JG	101	/* Initialize common gart structure */
771fe6b9 JG	102	r = radeon_gart_init(rdev);
4aac0473	103	if (r)
771fe6b9	104	return r;
4aac0473	105	if (rs400_debugfs_pcie_gart_info_init(rdev))
771fe6b9	106	DRM_ERROR("Failed to register debugfs file for RS400 GART !\n");
4aac0473 JG	107	rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
	108	return radeon_gart_table_ram_alloc(rdev);
	109	}
	110
	111	int rs400_gart_enable(struct radeon_device *rdev)
	112	{
	113	uint32_t size_reg;
	114	uint32_t tmp;
771fe6b9	115
82568565	116	radeon_gart_restore(rdev);
771fe6b9 JG	117	tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
	118	tmp \|= RS690_DIS_OUT_OF_PCI_GART_ACCESS;
	119	WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp);
	120	/* Check gart size */
	121	switch(rdev->mc.gtt_size / (1024 * 1024)) {
	122	case 32:
	123	size_reg = RS480_VA_SIZE_32MB;
	124	break;
	125	case 64:
	126	size_reg = RS480_VA_SIZE_64MB;
	127	break;
	128	case 128:
	129	size_reg = RS480_VA_SIZE_128MB;
	130	break;
	131	case 256:
	132	size_reg = RS480_VA_SIZE_256MB;
	133	break;
	134	case 512:
	135	size_reg = RS480_VA_SIZE_512MB;
	136	break;
	137	case 1024:
	138	size_reg = RS480_VA_SIZE_1GB;
	139	break;
	140	case 2048:
	141	size_reg = RS480_VA_SIZE_2GB;
	142	break;
	143	default:
	144	return -EINVAL;
	145	}
771fe6b9 JG	146	/* It should be fine to program it to max value */
	147	if (rdev->family == CHIP_RS690 \|\| (rdev->family == CHIP_RS740)) {
	148	WREG32_MC(RS690_MCCFG_AGP_BASE, 0xFFFFFFFF);
	149	WREG32_MC(RS690_MCCFG_AGP_BASE_2, 0);
	150	} else {
	151	WREG32(RADEON_AGP_BASE, 0xFFFFFFFF);
	152	WREG32(RS480_AGP_BASE_2, 0);
	153	}
d594e46a JG	154	tmp = REG_SET(RS690_MC_AGP_TOP, rdev->mc.gtt_end >> 16);
d594e46a JG	155	tmp \|= REG_SET(RS690_MC_AGP_START, rdev->mc.gtt_start >> 16);
771fe6b9 JG	156	if ((rdev->family == CHIP_RS690) \|\| (rdev->family == CHIP_RS740)) {
	157	WREG32_MC(RS690_MCCFG_AGP_LOCATION, tmp);
	158	tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
	159	WREG32(RADEON_BUS_CNTL, tmp);
	160	} else {
	161	WREG32(RADEON_MC_AGP_LOCATION, tmp);
	162	tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
	163	WREG32(RADEON_BUS_CNTL, tmp);
	164	}
	165	/* Table should be in 32bits address space so ignore bits above. */
ed10f95d DA	166	tmp = (u32)rdev->gart.table_addr & 0xfffff000;
	167	tmp \|= (upper_32_bits(rdev->gart.table_addr) & 0xff) << 4;
	168
771fe6b9 JG	169	WREG32_MC(RS480_GART_BASE, tmp);
	170	/* TODO: more tweaking here */
	171	WREG32_MC(RS480_GART_FEATURE_ID,
	172	(RS480_TLB_ENABLE \|
	173	RS480_GTW_LAC_EN \| RS480_1LEVEL_GART));
	174	/* Disable snooping */
	175	WREG32_MC(RS480_AGP_MODE_CNTL,
	176	(1 << RS480_REQ_TYPE_SNOOP_SHIFT) \| RS480_REQ_TYPE_SNOOP_DIS);
	177	/* Disable AGP mode */
	178	/* FIXME: according to doc we should set HIDE_MMCFG_BAR=0,
	179	* AGPMODE30=0 & AGP30ENHANCED=0 in NB_CNTL */
	180	if ((rdev->family == CHIP_RS690) \|\| (rdev->family == CHIP_RS740)) {
	181	WREG32_MC(RS480_MC_MISC_CNTL,
	182	(RS480_GART_INDEX_REG_EN \| RS690_BLOCK_GFX_D3_EN));
	183	} else {
	184	WREG32_MC(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN);
	185	}
	186	/* Enable gart */
	187	WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN \| size_reg));
	188	rs400_gart_tlb_flush(rdev);
	189	rdev->gart.ready = true;
	190	return 0;
	191	}
	192
	193	void rs400_gart_disable(struct radeon_device *rdev)
	194	{
	195	uint32_t tmp;
	196
	197	tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
	198	tmp \|= RS690_DIS_OUT_OF_PCI_GART_ACCESS;
	199	WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp);
	200	WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
	201	}
	202
4aac0473 JG	203	void rs400_gart_fini(struct radeon_device *rdev)
	204	{
	205	rs400_gart_disable(rdev);
	206	radeon_gart_table_ram_free(rdev);
	207	radeon_gart_fini(rdev);
	208	}
	209
771fe6b9 JG	210	int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
771fe6b9 JG	211	{
ed10f95d DA	212	uint32_t entry;
ed10f95d DA	213
771fe6b9 JG	214	if (i < 0 \|\| i > rdev->gart.num_gpu_pages) {
	215	return -EINVAL;
	216	}
ed10f95d DA	217
	218	entry = (lower_32_bits(addr) & PAGE_MASK) \|
	219	((upper_32_bits(addr) & 0xff) << 4) \|
	220	0xc;
	221	entry = cpu_to_le32(entry);
	222	rdev->gart.table.ram.ptr[i] = entry;
771fe6b9 JG	223	return 0;
	224	}
	225
a17538f9 DA	226	int rs400_mc_wait_for_idle(struct radeon_device *rdev)
	227	{
	228	unsigned i;
	229	uint32_t tmp;
	230
	231	for (i = 0; i < rdev->usec_timeout; i++) {
	232	/* read MC_STATUS */
	233	tmp = RREG32(0x0150);
	234	if (tmp & (1 << 2)) {
	235	return 0;
	236	}
	237	DRM_UDELAY(1);
	238	}
	239	return -1;
	240	}
	241
771fe6b9 JG	242	void rs400_gpu_init(struct radeon_device *rdev)
	243	{
	244	/* FIXME: HDP same place on rs400 ? */
	245	r100_hdp_reset(rdev);
	246	/* FIXME: is this correct ? */
	247	r420_pipes_init(rdev);
a17538f9 DA	248	if (rs400_mc_wait_for_idle(rdev)) {
	249	printk(KERN_WARNING "rs400: Failed to wait MC idle while "
	250	"programming pipes. Bad things might happen. %08x\n", RREG32(0x150));
771fe6b9 JG	251	}
	252	}
	253
d594e46a	254	void rs400_mc_init(struct radeon_device *rdev)
771fe6b9	255	{
d594e46a JG	256	u64 base;
d594e46a JG	257
771fe6b9	258	rs400_gart_adjust_size(rdev);
d594e46a	259	rdev->mc.igp_sideport_enabled = radeon_combios_sideport_present(rdev);
771fe6b9 JG	260	/* DDR for all card after R300 & IGP */
	261	rdev->mc.vram_is_ddr = true;
	262	rdev->mc.vram_width = 128;
2a0f8918	263	r100_vram_init_sizes(rdev);
d594e46a JG	264	base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
	265	radeon_vram_location(rdev, &rdev->mc, base);
	266	radeon_gtt_location(rdev, &rdev->mc);
771fe6b9 JG	267	}
771fe6b9 JG	268
771fe6b9 JG	269	uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg)
	270	{
	271	uint32_t r;
	272
	273	WREG32(RS480_NB_MC_INDEX, reg & 0xff);
	274	r = RREG32(RS480_NB_MC_DATA);
	275	WREG32(RS480_NB_MC_INDEX, 0xff);
	276	return r;
	277	}
	278
	279	void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
	280	{
	281	WREG32(RS480_NB_MC_INDEX, ((reg) & 0xff) \| RS480_NB_MC_IND_WR_EN);
	282	WREG32(RS480_NB_MC_DATA, (v));
	283	WREG32(RS480_NB_MC_INDEX, 0xff);
	284	}
	285
771fe6b9 JG	286	#if defined(CONFIG_DEBUG_FS)
	287	static int rs400_debugfs_gart_info(struct seq_file m, void data)
	288	{
	289	struct drm_info_node node = (struct drm_info_node ) m->private;
	290	struct drm_device *dev = node->minor->dev;
	291	struct radeon_device *rdev = dev->dev_private;
	292	uint32_t tmp;
	293
	294	tmp = RREG32(RADEON_HOST_PATH_CNTL);
	295	seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
	296	tmp = RREG32(RADEON_BUS_CNTL);
	297	seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
	298	tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
	299	seq_printf(m, "AIC_CTRL_SCRATCH 0x%08x\n", tmp);
	300	if (rdev->family == CHIP_RS690 \|\| (rdev->family == CHIP_RS740)) {
	301	tmp = RREG32_MC(RS690_MCCFG_AGP_BASE);
	302	seq_printf(m, "MCCFG_AGP_BASE 0x%08x\n", tmp);
	303	tmp = RREG32_MC(RS690_MCCFG_AGP_BASE_2);
	304	seq_printf(m, "MCCFG_AGP_BASE_2 0x%08x\n", tmp);
	305	tmp = RREG32_MC(RS690_MCCFG_AGP_LOCATION);
	306	seq_printf(m, "MCCFG_AGP_LOCATION 0x%08x\n", tmp);
	307	tmp = RREG32_MC(0x100);
	308	seq_printf(m, "MCCFG_FB_LOCATION 0x%08x\n", tmp);
	309	tmp = RREG32(0x134);
	310	seq_printf(m, "HDP_FB_LOCATION 0x%08x\n", tmp);
	311	} else {
	312	tmp = RREG32(RADEON_AGP_BASE);
	313	seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
	314	tmp = RREG32(RS480_AGP_BASE_2);
	315	seq_printf(m, "AGP_BASE_2 0x%08x\n", tmp);
	316	tmp = RREG32(RADEON_MC_AGP_LOCATION);
	317	seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
	318	}
	319	tmp = RREG32_MC(RS480_GART_BASE);
	320	seq_printf(m, "GART_BASE 0x%08x\n", tmp);
	321	tmp = RREG32_MC(RS480_GART_FEATURE_ID);
	322	seq_printf(m, "GART_FEATURE_ID 0x%08x\n", tmp);
	323	tmp = RREG32_MC(RS480_AGP_MODE_CNTL);
	324	seq_printf(m, "AGP_MODE_CONTROL 0x%08x\n", tmp);
	325	tmp = RREG32_MC(RS480_MC_MISC_CNTL);
	326	seq_printf(m, "MC_MISC_CNTL 0x%08x\n", tmp);
	327	tmp = RREG32_MC(0x5F);
	328	seq_printf(m, "MC_MISC_UMA_CNTL 0x%08x\n", tmp);
	329	tmp = RREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE);
	330	seq_printf(m, "AGP_ADDRESS_SPACE_SIZE 0x%08x\n", tmp);
	331	tmp = RREG32_MC(RS480_GART_CACHE_CNTRL);
	332	seq_printf(m, "GART_CACHE_CNTRL 0x%08x\n", tmp);
	333	tmp = RREG32_MC(0x3B);
	334	seq_printf(m, "MC_GART_ERROR_ADDRESS 0x%08x\n", tmp);
	335	tmp = RREG32_MC(0x3C);
	336	seq_printf(m, "MC_GART_ERROR_ADDRESS_HI 0x%08x\n", tmp);
	337	tmp = RREG32_MC(0x30);
	338	seq_printf(m, "GART_ERROR_0 0x%08x\n", tmp);
	339	tmp = RREG32_MC(0x31);
	340	seq_printf(m, "GART_ERROR_1 0x%08x\n", tmp);
	341	tmp = RREG32_MC(0x32);
	342	seq_printf(m, "GART_ERROR_2 0x%08x\n", tmp);
	343	tmp = RREG32_MC(0x33);
	344	seq_printf(m, "GART_ERROR_3 0x%08x\n", tmp);
	345	tmp = RREG32_MC(0x34);
	346	seq_printf(m, "GART_ERROR_4 0x%08x\n", tmp);
	347	tmp = RREG32_MC(0x35);
	348	seq_printf(m, "GART_ERROR_5 0x%08x\n", tmp);
	349	tmp = RREG32_MC(0x36);
350	seq_printf(m, "GART_ERROR_6 0x%08x\n", tmp);
351	tmp = RREG32_MC(0x37);
352	seq_printf(m, "GART_ERROR_7 0x%08x\n", tmp);
353	return 0;
354	}
355
356	static struct drm_info_list rs400_gart_info_list[] = {
357	{"rs400_gart_info", rs400_debugfs_gart_info, 0, NULL},
358	};
359	#endif
360
ca6ffc64	361	static int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
771fe6b9 JG	362	{
	363	#if defined(CONFIG_DEBUG_FS)
	364	return radeon_debugfs_add_files(rdev, rs400_gart_info_list, 1);
	365	#else
	366	return 0;
	367	#endif
	368	}
ca6ffc64	369
ca6ffc64 JG	370	void rs400_mc_program(struct radeon_device *rdev)
	371	{
	372	struct r100_mc_save save;
	373
	374	/* Stops all mc clients */
	375	r100_mc_stop(rdev, &save);
	376
	377	/* Wait for mc idle */
a17538f9 DA	378	if (rs400_mc_wait_for_idle(rdev))
a17538f9 DA	379	dev_warn(rdev->dev, "rs400: Wait MC idle timeout before updating MC.\n");
ca6ffc64 JG	380	WREG32(R_000148_MC_FB_LOCATION,
	381	S_000148_MC_FB_START(rdev->mc.vram_start >> 16) \|
	382	S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
	383
	384	r100_mc_resume(rdev, &save);
	385	}
	386
	387	static int rs400_startup(struct radeon_device *rdev)
	388	{
	389	int r;
	390
	391	rs400_mc_program(rdev);
	392	/* Resume clock */
	393	r300_clock_startup(rdev);
	394	/* Initialize GPU configuration (# pipes, ...) */
	395	rs400_gpu_init(rdev);
17e15b0c	396	r100_enable_bm(rdev);
ca6ffc64 JG	397	/* Initialize GART (initialize after TTM so we can allocate
	398	* memory through TTM but finalize after TTM) */
	399	r = rs400_gart_enable(rdev);
	400	if (r)
	401	return r;
	402	/* Enable IRQ */
ca6ffc64	403	r100_irq_set(rdev);
cafe6609	404	rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
ca6ffc64 JG	405	/* 1M ring buffer */
	406	r = r100_cp_init(rdev, 1024 * 1024);
	407	if (r) {
	408	dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
	409	return r;
	410	}
	411	r = r100_wb_init(rdev);
	412	if (r)
	413	dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
	414	r = r100_ib_init(rdev);
	415	if (r) {
	416	dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
	417	return r;
	418	}
	419	return 0;
	420	}
	421
	422	int rs400_resume(struct radeon_device *rdev)
	423	{
	424	/* Make sur GART are not working */
	425	rs400_gart_disable(rdev);
	426	/* Resume clock before doing reset */
	427	r300_clock_startup(rdev);
ea1495a6 DA	428	/* setup MC before calling post tables */
ea1495a6 DA	429	rs400_mc_program(rdev);
ca6ffc64 JG	430	/* Reset gpu before posting otherwise ATOM will enter infinite loop */
	431	if (radeon_gpu_reset(rdev)) {
	432	dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
	433	RREG32(R_000E40_RBBM_STATUS),
	434	RREG32(R_0007C0_CP_STAT));
	435	}
	436	/* post */
	437	radeon_combios_asic_init(rdev->ddev);
	438	/* Resume clock after posting */
	439	r300_clock_startup(rdev);
550e2d92 DA	440	/* Initialize surface registers */
550e2d92 DA	441	radeon_surface_init(rdev);
ca6ffc64 JG	442	return rs400_startup(rdev);
	443	}
	444
	445	int rs400_suspend(struct radeon_device *rdev)
	446	{
	447	r100_cp_disable(rdev);
	448	r100_wb_disable(rdev);
	449	r100_irq_disable(rdev);
	450	rs400_gart_disable(rdev);
	451	return 0;
	452	}
	453
	454	void rs400_fini(struct radeon_device *rdev)
	455	{
ca6ffc64 JG	456	r100_cp_fini(rdev);
	457	r100_wb_fini(rdev);
	458	r100_ib_fini(rdev);
	459	radeon_gem_fini(rdev);
	460	rs400_gart_fini(rdev);
	461	radeon_irq_kms_fini(rdev);
	462	radeon_fence_driver_fini(rdev);
4c788679	463	radeon_bo_fini(rdev);
ca6ffc64 JG	464	radeon_atombios_fini(rdev);
	465	kfree(rdev->bios);
	466	rdev->bios = NULL;
	467	}
	468
	469	int rs400_init(struct radeon_device *rdev)
	470	{
	471	int r;
	472
ca6ffc64 JG	473	/* Disable VGA */
	474	r100_vga_render_disable(rdev);
	475	/* Initialize scratch registers */
	476	radeon_scratch_init(rdev);
	477	/* Initialize surface registers */
	478	radeon_surface_init(rdev);
	479	/* TODO: disable VGA need to use VGA request */
	480	/* BIOS*/
	481	if (!radeon_get_bios(rdev)) {
	482	if (ASIC_IS_AVIVO(rdev))
	483	return -EINVAL;
	484	}
	485	if (rdev->is_atom_bios) {
	486	dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
	487	return -EINVAL;
	488	} else {
	489	r = radeon_combios_init(rdev);
	490	if (r)
	491	return r;
	492	}
	493	/* Reset gpu before posting otherwise ATOM will enter infinite loop */
	494	if (radeon_gpu_reset(rdev)) {
	495	dev_warn(rdev->dev,
	496	"GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
	497	RREG32(R_000E40_RBBM_STATUS),
	498	RREG32(R_0007C0_CP_STAT));
	499	}
	500	/* check if cards are posted or not */
72542d77 DA	501	if (radeon_boot_test_post_card(rdev) == false)
	502	return -EINVAL;
	503
ca6ffc64 JG	504	/* Initialize clocks */
ca6ffc64 JG	505	radeon_get_clock_info(rdev->ddev);
6234077d RM	506	/* Initialize power management */
6234077d RM	507	radeon_pm_init(rdev);
d594e46a JG	508	/* initialize memory controller */
d594e46a JG	509	rs400_mc_init(rdev);
ca6ffc64 JG	510	/* Fence driver */
	511	r = radeon_fence_driver_init(rdev);
	512	if (r)
	513	return r;
	514	r = radeon_irq_kms_init(rdev);
	515	if (r)
	516	return r;
	517	/* Memory manager */
4c788679	518	r = radeon_bo_init(rdev);
ca6ffc64 JG	519	if (r)
	520	return r;
	521	r = rs400_gart_init(rdev);
	522	if (r)
	523	return r;
	524	r300_set_reg_safe(rdev);
	525	rdev->accel_working = true;
	526	r = rs400_startup(rdev);
	527	if (r) {
	528	/* Somethings want wront with the accel init stop accel */
	529	dev_err(rdev->dev, "Disabling GPU acceleration\n");
ca6ffc64 JG	530	r100_cp_fini(rdev);
	531	r100_wb_fini(rdev);
	532	r100_ib_fini(rdev);
	533	rs400_gart_fini(rdev);
	534	radeon_irq_kms_fini(rdev);
	535	rdev->accel_working = false;
	536	}
	537	return 0;
	538	}