[net-next-2.6.git] / drivers / gpu / drm / radeon / radeon_pm.c

/*
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Rafał Miłecki <zajec5@gmail.com>
 *          Alex Deucher <alexdeucher@gmail.com>
 */
#include "drmP.h"
#include "radeon.h"
#include "avivod.h"

#define RADEON_IDLE_LOOP_MS 100
#define RADEON_RECLOCK_DELAY_MS 200
#define RADEON_WAIT_VBLANK_TIMEOUT 200
#define RADEON_WAIT_IDLE_TIMEOUT 200

static void radeon_pm_set_clocks_locked(struct radeon_device *rdev);
static void radeon_pm_set_clocks(struct radeon_device *rdev);
static void radeon_pm_idle_work_handler(struct work_struct *work);
static int radeon_debugfs_pm_init(struct radeon_device *rdev);

static const char *pm_state_names[4] = {
	"PM_STATE_DISABLED",
	"PM_STATE_MINIMUM",
	"PM_STATE_PAUSED",
	"PM_STATE_ACTIVE"
};

static const char *pm_state_types[5] = {
	"Default",
	"Powersave",
	"Battery",
	"Balanced",
	"Performance",
};

static void radeon_print_power_mode_info(struct radeon_device *rdev)
{
	int i, j;
	bool is_default;

	DRM_INFO("%d Power State(s)\n", rdev->pm.num_power_states);
	for (i = 0; i < rdev->pm.num_power_states; i++) {
		if (rdev->pm.default_power_state == &rdev->pm.power_state[i])
			is_default = true;
		else
			is_default = false;
		DRM_INFO("State %d %s %s\n", i,
			 pm_state_types[rdev->pm.power_state[i].type],
			 is_default ? "(default)" : "");
		if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
			DRM_INFO("\t%d PCIE Lanes\n", rdev->pm.power_state[i].non_clock_info.pcie_lanes);
		DRM_INFO("\t%d Clock Mode(s)\n", rdev->pm.power_state[i].num_clock_modes);
		for (j = 0; j < rdev->pm.power_state[i].num_clock_modes; j++) {
			if (rdev->flags & RADEON_IS_IGP)
				DRM_INFO("\t\t%d engine: %d\n",
					 j,
					 rdev->pm.power_state[i].clock_info[j].sclk * 10);
			else
				DRM_INFO("\t\t%d engine/memory: %d/%d\n",
					 j,
					 rdev->pm.power_state[i].clock_info[j].sclk * 10,
					 rdev->pm.power_state[i].clock_info[j].mclk * 10);
		}
	}
}

static struct radeon_power_state * radeon_pick_power_state(struct radeon_device *rdev,
							   enum radeon_pm_state_type type)
{
	int i, j;
	enum radeon_pm_state_type wanted_types[2];
	int wanted_count;

	switch (type) {
	case POWER_STATE_TYPE_DEFAULT:
	default:
		return rdev->pm.default_power_state;
	case POWER_STATE_TYPE_POWERSAVE:
		if (rdev->flags & RADEON_IS_MOBILITY) {
			wanted_types[0] = POWER_STATE_TYPE_POWERSAVE;
			wanted_types[1] = POWER_STATE_TYPE_BATTERY;
			wanted_count = 2;
		} else {
			wanted_types[0] = POWER_STATE_TYPE_PERFORMANCE;
			wanted_count = 1;
		}
		break;
	case POWER_STATE_TYPE_BATTERY:
		if (rdev->flags & RADEON_IS_MOBILITY) {
			wanted_types[0] = POWER_STATE_TYPE_BATTERY;
			wanted_types[1] = POWER_STATE_TYPE_POWERSAVE;
			wanted_count = 2;
		} else {
			wanted_types[0] = POWER_STATE_TYPE_PERFORMANCE;
			wanted_count = 1;
		}
		break;
	case POWER_STATE_TYPE_BALANCED:
	case POWER_STATE_TYPE_PERFORMANCE:
		wanted_types[0] = type;
		wanted_count = 1;
		break;
	}

	for (i = 0; i < wanted_count; i++) {
		for (j = 0; j < rdev->pm.num_power_states; j++) {
			if (rdev->pm.power_state[j].type == wanted_types[i])
				return &rdev->pm.power_state[j];
		}
	}

	return rdev->pm.default_power_state;
}

static struct radeon_pm_clock_info * radeon_pick_clock_mode(struct radeon_device *rdev,
							    struct radeon_power_state *power_state,
							    enum radeon_pm_clock_mode_type type)
{
	switch (type) {
	case POWER_MODE_TYPE_DEFAULT:
	default:
		return power_state->default_clock_mode;
	case POWER_MODE_TYPE_LOW:
		return &power_state->clock_info[0];
	case POWER_MODE_TYPE_MID:
		if (power_state->num_clock_modes > 2)
			return &power_state->clock_info[1];
		else
			return &power_state->clock_info[0];
		break;
	case POWER_MODE_TYPE_HIGH:
		return &power_state->clock_info[power_state->num_clock_modes - 1];
	}

}

static void radeon_get_power_state(struct radeon_device *rdev,
				   enum radeon_pm_action action)
{
	switch (action) {
	case PM_ACTION_MINIMUM:
		rdev->pm.requested_power_state = radeon_pick_power_state(rdev, POWER_STATE_TYPE_BATTERY);
		rdev->pm.requested_clock_mode =
			radeon_pick_clock_mode(rdev, rdev->pm.requested_power_state, POWER_MODE_TYPE_LOW);
		break;
	case PM_ACTION_DOWNCLOCK:
		rdev->pm.requested_power_state = radeon_pick_power_state(rdev, POWER_STATE_TYPE_POWERSAVE);
		rdev->pm.requested_clock_mode =
			radeon_pick_clock_mode(rdev, rdev->pm.requested_power_state, POWER_MODE_TYPE_MID);
		break;
	case PM_ACTION_UPCLOCK:
		rdev->pm.requested_power_state = radeon_pick_power_state(rdev, POWER_STATE_TYPE_DEFAULT);
		rdev->pm.requested_clock_mode =
			radeon_pick_clock_mode(rdev, rdev->pm.requested_power_state, POWER_MODE_TYPE_HIGH);
		break;
	case PM_ACTION_NONE:
	default:
		DRM_ERROR("Requested mode for not defined action\n");
		return;
	}
	DRM_INFO("Requested: e: %d m: %d p: %d\n",
		 rdev->pm.requested_clock_mode->sclk,
		 rdev->pm.requested_clock_mode->mclk,
		 rdev->pm.requested_power_state->non_clock_info.pcie_lanes);
}

void radeon_sync_with_vblank(struct radeon_device *rdev)
{
	if (rdev->pm.active_crtcs) {
		rdev->pm.vblank_sync = false;
		wait_event_timeout(
			rdev->irq.vblank_queue, rdev->pm.vblank_sync,
			msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
	}
}

int radeon_pm_init(struct radeon_device *rdev)
{
	rdev->pm.state = PM_STATE_DISABLED;
	rdev->pm.planned_action = PM_ACTION_NONE;
	rdev->pm.downclocked = false;

	if (rdev->bios) {
		if (rdev->is_atom_bios)
			radeon_atombios_get_power_modes(rdev);
		else
			radeon_combios_get_power_modes(rdev);
		radeon_print_power_mode_info(rdev);
	}

	if (radeon_debugfs_pm_init(rdev)) {
		DRM_ERROR("Failed to register debugfs file for PM!\n");
	}

	INIT_DELAYED_WORK(&rdev->pm.idle_work, radeon_pm_idle_work_handler);

	if (radeon_dynpm != -1 && radeon_dynpm) {
		rdev->pm.state = PM_STATE_PAUSED;
		DRM_INFO("radeon: dynamic power management enabled\n");
	}

	DRM_INFO("radeon: power management initialized\n");

	return 0;
}

void radeon_pm_fini(struct radeon_device *rdev)
{
	if (rdev->pm.i2c_bus)
		radeon_i2c_destroy(rdev->pm.i2c_bus);
}

void radeon_pm_compute_clocks(struct radeon_device *rdev)
{
	struct drm_device *ddev = rdev->ddev;
	struct drm_connector *connector;
	struct radeon_crtc *radeon_crtc;
	int count = 0;

	if (rdev->pm.state == PM_STATE_DISABLED)
		return;

	mutex_lock(&rdev->pm.mutex);

	rdev->pm.active_crtcs = 0;
	list_for_each_entry(connector,
		&ddev->mode_config.connector_list, head) {
		if (connector->encoder &&
		    connector->encoder->crtc &&
		    connector->dpms != DRM_MODE_DPMS_OFF) {
			radeon_crtc = to_radeon_crtc(connector->encoder->crtc);
			rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
			++count;
		}
	}

	if (count > 1) {
		if (rdev->pm.state == PM_STATE_ACTIVE) {
			cancel_delayed_work(&rdev->pm.idle_work);

			rdev->pm.state = PM_STATE_PAUSED;
			rdev->pm.planned_action = PM_ACTION_UPCLOCK;
			if (rdev->pm.downclocked)
				radeon_pm_set_clocks(rdev);

			DRM_DEBUG("radeon: dynamic power management deactivated\n");
		}
	} else if (count == 1) {
		/* TODO: Increase clocks if needed for current mode */

		if (rdev->pm.state == PM_STATE_MINIMUM) {
			rdev->pm.state = PM_STATE_ACTIVE;
			rdev->pm.planned_action = PM_ACTION_UPCLOCK;
			radeon_pm_set_clocks(rdev);

			queue_delayed_work(rdev->wq, &rdev->pm.idle_work,
				msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
		}
		else if (rdev->pm.state == PM_STATE_PAUSED) {
			rdev->pm.state = PM_STATE_ACTIVE;
			queue_delayed_work(rdev->wq, &rdev->pm.idle_work,
				msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
			DRM_DEBUG("radeon: dynamic power management activated\n");
		}
	}
	else { /* count == 0 */
		if (rdev->pm.state != PM_STATE_MINIMUM) {
			cancel_delayed_work(&rdev->pm.idle_work);

			rdev->pm.state = PM_STATE_MINIMUM;
			rdev->pm.planned_action = PM_ACTION_MINIMUM;
			radeon_pm_set_clocks(rdev);
		}
	}

	mutex_unlock(&rdev->pm.mutex);
}

bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
{
	u32 stat_crtc = 0;
	bool in_vbl = true;

	if (ASIC_IS_DCE4(rdev)) {
		if (rdev->pm.active_crtcs & (1 << 0)) {
			stat_crtc = RREG32(EVERGREEN_CRTC_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
			if (!(stat_crtc & 1))
				in_vbl = false;
		}
		if (rdev->pm.active_crtcs & (1 << 1)) {
			stat_crtc = RREG32(EVERGREEN_CRTC_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
			if (!(stat_crtc & 1))
				in_vbl = false;
		}
		if (rdev->pm.active_crtcs & (1 << 2)) {
			stat_crtc = RREG32(EVERGREEN_CRTC_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
			if (!(stat_crtc & 1))
				in_vbl = false;
		}
		if (rdev->pm.active_crtcs & (1 << 3)) {
			stat_crtc = RREG32(EVERGREEN_CRTC_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
			if (!(stat_crtc & 1))
				in_vbl = false;
		}
		if (rdev->pm.active_crtcs & (1 << 4)) {
			stat_crtc = RREG32(EVERGREEN_CRTC_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
			if (!(stat_crtc & 1))
				in_vbl = false;
		}
		if (rdev->pm.active_crtcs & (1 << 5)) {
			stat_crtc = RREG32(EVERGREEN_CRTC_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
			if (!(stat_crtc & 1))
				in_vbl = false;
		}
	} else if (ASIC_IS_AVIVO(rdev)) {
		if (rdev->pm.active_crtcs & (1 << 0)) {
			stat_crtc = RREG32(D1CRTC_STATUS);
			if (!(stat_crtc & 1))
				in_vbl = false;
		}
		if (rdev->pm.active_crtcs & (1 << 1)) {
			stat_crtc = RREG32(D2CRTC_STATUS);
			if (!(stat_crtc & 1))
				in_vbl = false;
		}
	} else {
		if (rdev->pm.active_crtcs & (1 << 0)) {
			stat_crtc = RREG32(RADEON_CRTC_STATUS);
			if (!(stat_crtc & 1))
				in_vbl = false;
		}
		if (rdev->pm.active_crtcs & (1 << 1)) {
			stat_crtc = RREG32(RADEON_CRTC2_STATUS);
			if (!(stat_crtc & 1))
				in_vbl = false;
		}
	}
	if (in_vbl == false)
		DRM_INFO("not in vbl for pm change %08x at %s\n", stat_crtc,
			 finish ? "exit" : "entry");
	return in_vbl;
}
static void radeon_pm_set_clocks_locked(struct radeon_device *rdev)
{
	/*radeon_fence_wait_last(rdev);*/
	switch (rdev->pm.planned_action) {
	case PM_ACTION_UPCLOCK:
		rdev->pm.downclocked = false;
		break;
	case PM_ACTION_DOWNCLOCK:
		rdev->pm.downclocked = true;
		break;
	case PM_ACTION_MINIMUM:
		break;
	case PM_ACTION_NONE:
		DRM_ERROR("%s: PM_ACTION_NONE\n", __func__);
		break;
	}

	radeon_set_power_state(rdev);
	rdev->pm.planned_action = PM_ACTION_NONE;
}

static void radeon_pm_set_clocks(struct radeon_device *rdev)
{
	int i;

	radeon_get_power_state(rdev, rdev->pm.planned_action);
	mutex_lock(&rdev->cp.mutex);

	/* wait for GPU idle */
	rdev->pm.gui_idle = false;
	rdev->irq.gui_idle = true;
	radeon_irq_set(rdev);
	wait_event_interruptible_timeout(
		rdev->irq.idle_queue, rdev->pm.gui_idle,
		msecs_to_jiffies(RADEON_WAIT_IDLE_TIMEOUT));
	rdev->irq.gui_idle = false;
	radeon_irq_set(rdev);

	for (i = 0; i < rdev->num_crtc; i++) {
		if (rdev->pm.active_crtcs & (1 << i)) {
			rdev->pm.req_vblank |= (1 << i);
			drm_vblank_get(rdev->ddev, i);
		}
	}
	radeon_pm_set_clocks_locked(rdev);
	for (i = 0; i < rdev->num_crtc; i++) {
		if (rdev->pm.req_vblank & (1 << i)) {
			rdev->pm.req_vblank &= ~(1 << i);
			drm_vblank_put(rdev->ddev, i);
		}
	}

	mutex_unlock(&rdev->cp.mutex);
}

static void radeon_pm_idle_work_handler(struct work_struct *work)
{
	struct radeon_device *rdev;
	rdev = container_of(work, struct radeon_device,
				pm.idle_work.work);

	mutex_lock(&rdev->pm.mutex);
	if (rdev->pm.state == PM_STATE_ACTIVE) {
		unsigned long irq_flags;
		int not_processed = 0;

		read_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
		if (!list_empty(&rdev->fence_drv.emited)) {
			struct list_head *ptr;
			list_for_each(ptr, &rdev->fence_drv.emited) {
				/* count up to 3, that's enought info */
				if (++not_processed >= 3)
					break;
			}
		}
		read_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);

		if (not_processed >= 3) { /* should upclock */
			if (rdev->pm.planned_action == PM_ACTION_DOWNCLOCK) {
				rdev->pm.planned_action = PM_ACTION_NONE;
			} else if (rdev->pm.planned_action == PM_ACTION_NONE &&
				rdev->pm.downclocked) {
				rdev->pm.planned_action =
					PM_ACTION_UPCLOCK;
				rdev->pm.action_timeout = jiffies +
				msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
			}
		} else if (not_processed == 0) { /* should downclock */
			if (rdev->pm.planned_action == PM_ACTION_UPCLOCK) {
				rdev->pm.planned_action = PM_ACTION_NONE;
			} else if (rdev->pm.planned_action == PM_ACTION_NONE &&
				!rdev->pm.downclocked) {
				rdev->pm.planned_action =
					PM_ACTION_DOWNCLOCK;
				rdev->pm.action_timeout = jiffies +
				msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
			}
		}

		if (rdev->pm.planned_action != PM_ACTION_NONE &&
		    jiffies > rdev->pm.action_timeout) {
			radeon_pm_set_clocks(rdev);
		}
	}
	mutex_unlock(&rdev->pm.mutex);

	queue_delayed_work(rdev->wq, &rdev->pm.idle_work,
					msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
}

/*
 * Debugfs info
 */
#if defined(CONFIG_DEBUG_FS)

static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
{
	struct drm_info_node *node = (struct drm_info_node *) m->private;
	struct drm_device *dev = node->minor->dev;
	struct radeon_device *rdev = dev->dev_private;

	seq_printf(m, "state: %s\n", pm_state_names[rdev->pm.state]);
	seq_printf(m, "default engine clock: %u0 kHz\n", rdev->clock.default_sclk);
	seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
	seq_printf(m, "default memory clock: %u0 kHz\n", rdev->clock.default_mclk);
	if (rdev->asic->get_memory_clock)
		seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
	if (rdev->asic->get_pcie_lanes)
		seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));

	return 0;
}

static struct drm_info_list radeon_pm_info_list[] = {
	{"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
};
#endif

static int radeon_debugfs_pm_init(struct radeon_device *rdev)
{
#if defined(CONFIG_DEBUG_FS)
	return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));
#else
	return 0;
#endif
}
Commit	Line	Data
7433874e RM	1	/*
	2	* Permission is hereby granted, free of charge, to any person obtaining a
	3	* copy of this software and associated documentation files (the "Software"),
	4	* to deal in the Software without restriction, including without limitation
	5	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	6	* and/or sell copies of the Software, and to permit persons to whom the
	7	* Software is furnished to do so, subject to the following conditions:
	8	*
	9	* The above copyright notice and this permission notice shall be included in
	10	* all copies or substantial portions of the Software.
	11	*
	12	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	13	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	14	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	15	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	16	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	17	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	18	* OTHER DEALINGS IN THE SOFTWARE.
	19	*
	20	* Authors: Rafał Miłecki <zajec5@gmail.com>
56278a8e	21	* Alex Deucher <alexdeucher@gmail.com>
7433874e RM	22	*/
	23	#include "drmP.h"
	24	#include "radeon.h"
f735261b	25	#include "avivod.h"
7433874e	26
c913e23a RM	27	#define RADEON_IDLE_LOOP_MS 100
c913e23a RM	28	#define RADEON_RECLOCK_DELAY_MS 200
73a6d3fc	29	#define RADEON_WAIT_VBLANK_TIMEOUT 200
2031f77c	30	#define RADEON_WAIT_IDLE_TIMEOUT 200
c913e23a	31
c913e23a RM	32	static void radeon_pm_set_clocks_locked(struct radeon_device *rdev);
c913e23a RM	33	static void radeon_pm_set_clocks(struct radeon_device *rdev);
c913e23a RM	34	static void radeon_pm_idle_work_handler(struct work_struct *work);
	35	static int radeon_debugfs_pm_init(struct radeon_device *rdev);
	36
	37	static const char *pm_state_names[4] = {
	38	"PM_STATE_DISABLED",
	39	"PM_STATE_MINIMUM",
	40	"PM_STATE_PAUSED",
	41	"PM_STATE_ACTIVE"
	42	};
7433874e	43
0ec0e74f AD	44	static const char *pm_state_types[5] = {
	45	"Default",
	46	"Powersave",
	47	"Battery",
	48	"Balanced",
	49	"Performance",
	50	};
	51
56278a8e AD	52	static void radeon_print_power_mode_info(struct radeon_device *rdev)
	53	{
	54	int i, j;
	55	bool is_default;
	56
	57	DRM_INFO("%d Power State(s)\n", rdev->pm.num_power_states);
	58	for (i = 0; i < rdev->pm.num_power_states; i++) {
	59	if (rdev->pm.default_power_state == &rdev->pm.power_state[i])
	60	is_default = true;
	61	else
	62	is_default = false;
0ec0e74f AD	63	DRM_INFO("State %d %s %s\n", i,
	64	pm_state_types[rdev->pm.power_state[i].type],
	65	is_default ? "(default)" : "");
56278a8e AD	66	if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
	67	DRM_INFO("\t%d PCIE Lanes\n", rdev->pm.power_state[i].non_clock_info.pcie_lanes);
	68	DRM_INFO("\t%d Clock Mode(s)\n", rdev->pm.power_state[i].num_clock_modes);
	69	for (j = 0; j < rdev->pm.power_state[i].num_clock_modes; j++) {
	70	if (rdev->flags & RADEON_IS_IGP)
	71	DRM_INFO("\t\t%d engine: %d\n",
	72	j,
	73	rdev->pm.power_state[i].clock_info[j].sclk * 10);
	74	else
	75	DRM_INFO("\t\t%d engine/memory: %d/%d\n",
	76	j,
	77	rdev->pm.power_state[i].clock_info[j].sclk * 10,
	78	rdev->pm.power_state[i].clock_info[j].mclk * 10);
	79	}
	80	}
	81	}
	82
516d0e46 AD	83	static struct radeon_power_state * radeon_pick_power_state(struct radeon_device *rdev,
	84	enum radeon_pm_state_type type)
	85	{
bc4624ca RM	86	int i, j;
	87	enum radeon_pm_state_type wanted_types[2];
	88	int wanted_count;
516d0e46 AD	89
	90	switch (type) {
	91	case POWER_STATE_TYPE_DEFAULT:
	92	default:
	93	return rdev->pm.default_power_state;
	94	case POWER_STATE_TYPE_POWERSAVE:
08ff2a7a RM	95	if (rdev->flags & RADEON_IS_MOBILITY) {
	96	wanted_types[0] = POWER_STATE_TYPE_POWERSAVE;
	97	wanted_types[1] = POWER_STATE_TYPE_BATTERY;
	98	wanted_count = 2;
	99	} else {
	100	wanted_types[0] = POWER_STATE_TYPE_PERFORMANCE;
	101	wanted_count = 1;
	102	}
516d0e46 AD	103	break;
516d0e46 AD	104	case POWER_STATE_TYPE_BATTERY:
08ff2a7a RM	105	if (rdev->flags & RADEON_IS_MOBILITY) {
	106	wanted_types[0] = POWER_STATE_TYPE_BATTERY;
	107	wanted_types[1] = POWER_STATE_TYPE_POWERSAVE;
	108	wanted_count = 2;
	109	} else {
	110	wanted_types[0] = POWER_STATE_TYPE_PERFORMANCE;
	111	wanted_count = 1;
	112	}
516d0e46 AD	113	break;
	114	case POWER_STATE_TYPE_BALANCED:
	115	case POWER_STATE_TYPE_PERFORMANCE:
bc4624ca RM	116	wanted_types[0] = type;
bc4624ca RM	117	wanted_count = 1;
516d0e46 AD	118	break;
	119	}
	120
bc4624ca RM	121	for (i = 0; i < wanted_count; i++) {
	122	for (j = 0; j < rdev->pm.num_power_states; j++) {
	123	if (rdev->pm.power_state[j].type == wanted_types[i])
	124	return &rdev->pm.power_state[j];
	125	}
	126	}
516d0e46	127
bc4624ca	128	return rdev->pm.default_power_state;
516d0e46 AD	129	}
	130
	131	static struct radeon_pm_clock_info * radeon_pick_clock_mode(struct radeon_device *rdev,
	132	struct radeon_power_state *power_state,
	133	enum radeon_pm_clock_mode_type type)
	134	{
	135	switch (type) {
	136	case POWER_MODE_TYPE_DEFAULT:
	137	default:
	138	return power_state->default_clock_mode;
	139	case POWER_MODE_TYPE_LOW:
	140	return &power_state->clock_info[0];
	141	case POWER_MODE_TYPE_MID:
	142	if (power_state->num_clock_modes > 2)
	143	return &power_state->clock_info[1];
	144	else
	145	return &power_state->clock_info[0];
	146	break;
	147	case POWER_MODE_TYPE_HIGH:
	148	return &power_state->clock_info[power_state->num_clock_modes - 1];
	149	}
	150
	151	}
	152
	153	static void radeon_get_power_state(struct radeon_device *rdev,
	154	enum radeon_pm_action action)
	155	{
	156	switch (action) {
516d0e46 AD	157	case PM_ACTION_MINIMUM:
516d0e46 AD	158	rdev->pm.requested_power_state = radeon_pick_power_state(rdev, POWER_STATE_TYPE_BATTERY);
9038dfdf	159	rdev->pm.requested_clock_mode =
516d0e46 AD	160	radeon_pick_clock_mode(rdev, rdev->pm.requested_power_state, POWER_MODE_TYPE_LOW);
	161	break;
	162	case PM_ACTION_DOWNCLOCK:
	163	rdev->pm.requested_power_state = radeon_pick_power_state(rdev, POWER_STATE_TYPE_POWERSAVE);
9038dfdf	164	rdev->pm.requested_clock_mode =
516d0e46 AD	165	radeon_pick_clock_mode(rdev, rdev->pm.requested_power_state, POWER_MODE_TYPE_MID);
	166	break;
	167	case PM_ACTION_UPCLOCK:
	168	rdev->pm.requested_power_state = radeon_pick_power_state(rdev, POWER_STATE_TYPE_DEFAULT);
9038dfdf	169	rdev->pm.requested_clock_mode =
516d0e46 AD	170	radeon_pick_clock_mode(rdev, rdev->pm.requested_power_state, POWER_MODE_TYPE_HIGH);
516d0e46 AD	171	break;
9038dfdf RM	172	case PM_ACTION_NONE:
	173	default:
	174	DRM_ERROR("Requested mode for not defined action\n");
	175	return;
516d0e46	176	}
530079a8	177	DRM_INFO("Requested: e: %d m: %d p: %d\n",
9038dfdf RM	178	rdev->pm.requested_clock_mode->sclk,
9038dfdf RM	179	rdev->pm.requested_clock_mode->mclk,
530079a8	180	rdev->pm.requested_power_state->non_clock_info.pcie_lanes);
516d0e46 AD	181	}
516d0e46 AD	182
bae6b562	183	void radeon_sync_with_vblank(struct radeon_device *rdev)
d0d6cb81 RM	184	{
	185	if (rdev->pm.active_crtcs) {
	186	rdev->pm.vblank_sync = false;
	187	wait_event_timeout(
	188	rdev->irq.vblank_queue, rdev->pm.vblank_sync,
	189	msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
	190	}
	191	}
	192
7433874e RM	193	int radeon_pm_init(struct radeon_device *rdev)
7433874e RM	194	{
c913e23a RM	195	rdev->pm.state = PM_STATE_DISABLED;
	196	rdev->pm.planned_action = PM_ACTION_NONE;
	197	rdev->pm.downclocked = false;
c913e23a	198
56278a8e AD	199	if (rdev->bios) {
	200	if (rdev->is_atom_bios)
	201	radeon_atombios_get_power_modes(rdev);
	202	else
	203	radeon_combios_get_power_modes(rdev);
	204	radeon_print_power_mode_info(rdev);
	205	}
	206
7433874e	207	if (radeon_debugfs_pm_init(rdev)) {
c142c3e5	208	DRM_ERROR("Failed to register debugfs file for PM!\n");
7433874e RM	209	}
7433874e RM	210
c913e23a RM	211	INIT_DELAYED_WORK(&rdev->pm.idle_work, radeon_pm_idle_work_handler);
	212
	213	if (radeon_dynpm != -1 && radeon_dynpm) {
	214	rdev->pm.state = PM_STATE_PAUSED;
	215	DRM_INFO("radeon: dynamic power management enabled\n");
	216	}
	217
	218	DRM_INFO("radeon: power management initialized\n");
	219
7433874e RM	220	return 0;
	221	}
	222
29fb52ca AD	223	void radeon_pm_fini(struct radeon_device *rdev)
	224	{
	225	if (rdev->pm.i2c_bus)
	226	radeon_i2c_destroy(rdev->pm.i2c_bus);
	227	}
	228
c913e23a RM	229	void radeon_pm_compute_clocks(struct radeon_device *rdev)
	230	{
	231	struct drm_device *ddev = rdev->ddev;
	232	struct drm_connector *connector;
	233	struct radeon_crtc *radeon_crtc;
	234	int count = 0;
	235
	236	if (rdev->pm.state == PM_STATE_DISABLED)
	237	return;
	238
	239	mutex_lock(&rdev->pm.mutex);
	240
	241	rdev->pm.active_crtcs = 0;
	242	list_for_each_entry(connector,
	243	&ddev->mode_config.connector_list, head) {
	244	if (connector->encoder &&
57f50d70 AD	245	connector->encoder->crtc &&
57f50d70 AD	246	connector->dpms != DRM_MODE_DPMS_OFF) {
c913e23a RM	247	radeon_crtc = to_radeon_crtc(connector->encoder->crtc);
	248	rdev->pm.active_crtcs \|= (1 << radeon_crtc->crtc_id);
	249	++count;
	250	}
	251	}
	252
	253	if (count > 1) {
	254	if (rdev->pm.state == PM_STATE_ACTIVE) {
c913e23a RM	255	cancel_delayed_work(&rdev->pm.idle_work);
	256
	257	rdev->pm.state = PM_STATE_PAUSED;
	258	rdev->pm.planned_action = PM_ACTION_UPCLOCK;
73a6d3fc	259	if (rdev->pm.downclocked)
c913e23a RM	260	radeon_pm_set_clocks(rdev);
	261
	262	DRM_DEBUG("radeon: dynamic power management deactivated\n");
c913e23a RM	263	}
c913e23a RM	264	} else if (count == 1) {
c913e23a RM	265	/* TODO: Increase clocks if needed for current mode */
	266
	267	if (rdev->pm.state == PM_STATE_MINIMUM) {
	268	rdev->pm.state = PM_STATE_ACTIVE;
	269	rdev->pm.planned_action = PM_ACTION_UPCLOCK;
73a6d3fc	270	radeon_pm_set_clocks(rdev);
c913e23a RM	271
	272	queue_delayed_work(rdev->wq, &rdev->pm.idle_work,
	273	msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
	274	}
	275	else if (rdev->pm.state == PM_STATE_PAUSED) {
	276	rdev->pm.state = PM_STATE_ACTIVE;
	277	queue_delayed_work(rdev->wq, &rdev->pm.idle_work,
	278	msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
	279	DRM_DEBUG("radeon: dynamic power management activated\n");
	280	}
c913e23a RM	281	}
	282	else { /* count == 0 */
	283	if (rdev->pm.state != PM_STATE_MINIMUM) {
	284	cancel_delayed_work(&rdev->pm.idle_work);
	285
	286	rdev->pm.state = PM_STATE_MINIMUM;
	287	rdev->pm.planned_action = PM_ACTION_MINIMUM;
73a6d3fc	288	radeon_pm_set_clocks(rdev);
c913e23a	289	}
c913e23a	290	}
73a6d3fc RM	291
73a6d3fc RM	292	mutex_unlock(&rdev->pm.mutex);
c913e23a RM	293	}
c913e23a RM	294
bae6b562	295	bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
f735261b	296	{
bae6b562	297	u32 stat_crtc = 0;
f735261b DA	298	bool in_vbl = true;
f735261b DA	299
bae6b562 AD	300	if (ASIC_IS_DCE4(rdev)) {
	301	if (rdev->pm.active_crtcs & (1 << 0)) {
	302	stat_crtc = RREG32(EVERGREEN_CRTC_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
	303	if (!(stat_crtc & 1))
	304	in_vbl = false;
	305	}
	306	if (rdev->pm.active_crtcs & (1 << 1)) {
	307	stat_crtc = RREG32(EVERGREEN_CRTC_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
	308	if (!(stat_crtc & 1))
	309	in_vbl = false;
	310	}
	311	if (rdev->pm.active_crtcs & (1 << 2)) {
	312	stat_crtc = RREG32(EVERGREEN_CRTC_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
	313	if (!(stat_crtc & 1))
	314	in_vbl = false;
	315	}
	316	if (rdev->pm.active_crtcs & (1 << 3)) {
	317	stat_crtc = RREG32(EVERGREEN_CRTC_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
	318	if (!(stat_crtc & 1))
	319	in_vbl = false;
	320	}
	321	if (rdev->pm.active_crtcs & (1 << 4)) {
	322	stat_crtc = RREG32(EVERGREEN_CRTC_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
	323	if (!(stat_crtc & 1))
	324	in_vbl = false;
	325	}
	326	if (rdev->pm.active_crtcs & (1 << 5)) {
	327	stat_crtc = RREG32(EVERGREEN_CRTC_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
	328	if (!(stat_crtc & 1))
	329	in_vbl = false;
	330	}
	331	} else if (ASIC_IS_AVIVO(rdev)) {
	332	if (rdev->pm.active_crtcs & (1 << 0)) {
	333	stat_crtc = RREG32(D1CRTC_STATUS);
	334	if (!(stat_crtc & 1))
	335	in_vbl = false;
	336	}
	337	if (rdev->pm.active_crtcs & (1 << 1)) {
	338	stat_crtc = RREG32(D2CRTC_STATUS);
	339	if (!(stat_crtc & 1))
	340	in_vbl = false;
	341	}
	342	} else {
f735261b	343	if (rdev->pm.active_crtcs & (1 << 0)) {
bae6b562 AD	344	stat_crtc = RREG32(RADEON_CRTC_STATUS);
bae6b562 AD	345	if (!(stat_crtc & 1))
f735261b DA	346	in_vbl = false;
	347	}
	348	if (rdev->pm.active_crtcs & (1 << 1)) {
bae6b562 AD	349	stat_crtc = RREG32(RADEON_CRTC2_STATUS);
bae6b562 AD	350	if (!(stat_crtc & 1))
f735261b DA	351	in_vbl = false;
	352	}
	353	}
	354	if (in_vbl == false)
bae6b562 AD	355	DRM_INFO("not in vbl for pm change %08x at %s\n", stat_crtc,
bae6b562 AD	356	finish ? "exit" : "entry");
f735261b DA	357	return in_vbl;
f735261b DA	358	}
c913e23a RM	359	static void radeon_pm_set_clocks_locked(struct radeon_device *rdev)
	360	{
	361	/radeon_fence_wait_last(rdev);/
	362	switch (rdev->pm.planned_action) {
	363	case PM_ACTION_UPCLOCK:
c913e23a RM	364	rdev->pm.downclocked = false;
	365	break;
	366	case PM_ACTION_DOWNCLOCK:
c913e23a RM	367	rdev->pm.downclocked = true;
	368	break;
	369	case PM_ACTION_MINIMUM:
c913e23a RM	370	break;
	371	case PM_ACTION_NONE:
	372	DRM_ERROR("%s: PM_ACTION_NONE\n", __func__);
	373	break;
	374	}
f735261b	375
530079a8	376	radeon_set_power_state(rdev);
c913e23a RM	377	rdev->pm.planned_action = PM_ACTION_NONE;
	378	}
	379
	380	static void radeon_pm_set_clocks(struct radeon_device *rdev)
	381	{
8a56df63 AD	382	int i;
8a56df63 AD	383
73a6d3fc RM	384	radeon_get_power_state(rdev, rdev->pm.planned_action);
	385	mutex_lock(&rdev->cp.mutex);
	386
ef6e6cf5 AD	387	/* wait for GPU idle */
	388	rdev->pm.gui_idle = false;
	389	rdev->irq.gui_idle = true;
	390	radeon_irq_set(rdev);
	391	wait_event_interruptible_timeout(
	392	rdev->irq.idle_queue, rdev->pm.gui_idle,
	393	msecs_to_jiffies(RADEON_WAIT_IDLE_TIMEOUT));
	394	rdev->irq.gui_idle = false;
	395	radeon_irq_set(rdev);
	396
8a56df63 AD	397	for (i = 0; i < rdev->num_crtc; i++) {
	398	if (rdev->pm.active_crtcs & (1 << i)) {
	399	rdev->pm.req_vblank \|= (1 << i);
	400	drm_vblank_get(rdev->ddev, i);
	401	}
73a6d3fc	402	}
d0d6cb81	403	radeon_pm_set_clocks_locked(rdev);
8a56df63 AD	404	for (i = 0; i < rdev->num_crtc; i++) {
	405	if (rdev->pm.req_vblank & (1 << i)) {
	406	rdev->pm.req_vblank &= ~(1 << i);
	407	drm_vblank_put(rdev->ddev, i);
	408	}
c913e23a	409	}
c913e23a	410
73a6d3fc	411	mutex_unlock(&rdev->cp.mutex);
c913e23a RM	412	}
	413
	414	static void radeon_pm_idle_work_handler(struct work_struct *work)
	415	{
	416	struct radeon_device *rdev;
	417	rdev = container_of(work, struct radeon_device,
	418	pm.idle_work.work);
	419
	420	mutex_lock(&rdev->pm.mutex);
73a6d3fc	421	if (rdev->pm.state == PM_STATE_ACTIVE) {
c913e23a RM	422	unsigned long irq_flags;
	423	int not_processed = 0;
	424
	425	read_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
	426	if (!list_empty(&rdev->fence_drv.emited)) {
	427	struct list_head *ptr;
	428	list_for_each(ptr, &rdev->fence_drv.emited) {
	429	/* count up to 3, that's enought info */
	430	if (++not_processed >= 3)
	431	break;
	432	}
	433	}
	434	read_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
	435
	436	if (not_processed >= 3) { /* should upclock */
	437	if (rdev->pm.planned_action == PM_ACTION_DOWNCLOCK) {
	438	rdev->pm.planned_action = PM_ACTION_NONE;
	439	} else if (rdev->pm.planned_action == PM_ACTION_NONE &&
	440	rdev->pm.downclocked) {
	441	rdev->pm.planned_action =
	442	PM_ACTION_UPCLOCK;
	443	rdev->pm.action_timeout = jiffies +
	444	msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
	445	}
	446	} else if (not_processed == 0) { /* should downclock */
	447	if (rdev->pm.planned_action == PM_ACTION_UPCLOCK) {
	448	rdev->pm.planned_action = PM_ACTION_NONE;
	449	} else if (rdev->pm.planned_action == PM_ACTION_NONE &&
	450	!rdev->pm.downclocked) {
	451	rdev->pm.planned_action =
	452	PM_ACTION_DOWNCLOCK;
	453	rdev->pm.action_timeout = jiffies +
	454	msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
	455	}
	456	}
	457
	458	if (rdev->pm.planned_action != PM_ACTION_NONE &&
73a6d3fc RM	459	jiffies > rdev->pm.action_timeout) {
73a6d3fc RM	460	radeon_pm_set_clocks(rdev);
c913e23a RM	461	}
	462	}
	463	mutex_unlock(&rdev->pm.mutex);
	464
	465	queue_delayed_work(rdev->wq, &rdev->pm.idle_work,
	466	msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
	467	}
	468
7433874e RM	469	/*
	470	* Debugfs info
	471	*/
	472	#if defined(CONFIG_DEBUG_FS)
	473
	474	static int radeon_debugfs_pm_info(struct seq_file m, void data)
	475	{
	476	struct drm_info_node node = (struct drm_info_node ) m->private;
	477	struct drm_device *dev = node->minor->dev;
	478	struct radeon_device *rdev = dev->dev_private;
	479
c913e23a	480	seq_printf(m, "state: %s\n", pm_state_names[rdev->pm.state]);
6234077d RM	481	seq_printf(m, "default engine clock: %u0 kHz\n", rdev->clock.default_sclk);
	482	seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
	483	seq_printf(m, "default memory clock: %u0 kHz\n", rdev->clock.default_mclk);
	484	if (rdev->asic->get_memory_clock)
	485	seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
aa5120d2 RM	486	if (rdev->asic->get_pcie_lanes)
aa5120d2 RM	487	seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
7433874e RM	488
	489	return 0;
	490	}
	491
	492	static struct drm_info_list radeon_pm_info_list[] = {
	493	{"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
	494	};
	495	#endif
	496
c913e23a	497	static int radeon_debugfs_pm_init(struct radeon_device *rdev)
7433874e RM	498	{
	499	#if defined(CONFIG_DEBUG_FS)
	500	return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));
	501	#else
	502	return 0;
	503	#endif
	504	}