]> bbs.cooldavid.org Git - net-next-2.6.git/blame - drivers/gpu/drm/radeon/radeon_mode.h
git://bbs.cooldavid.org / net-next-2.6.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/radeon/kms: set proper default tv standard
[net-next-2.6.git] / drivers / gpu / drm / radeon / radeon_mode.h
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
3 * VA Linux Systems Inc., Fremont, California.
4 * Copyright 2008 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Original Authors:
25 * Kevin E. Martin, Rickard E. Faith, Alan Hourihane
26 *
27 * Kernel port Author: Dave Airlie
28 */
29
30#ifndef RADEON_MODE_H
31#define RADEON_MODE_H
32
33#include <drm_crtc.h>
34#include <drm_mode.h>
35#include <drm_edid.h>
746c1aa4 36#include <drm_dp_helper.h>
771fe6b9
JG		 37#include <linux/i2c.h>
38#include <linux/i2c-id.h>
39#include <linux/i2c-algo-bit.h>
c93bb85b
JG		 40#include "radeon_fixed.h"
41
42struct radeon_device;
771fe6b9
JG		 43
44#define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base)
45#define to_radeon_connector(x) container_of(x, struct radeon_connector, base)
46#define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base)
47#define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base)
48
49enum radeon_connector_type {
50 CONNECTOR_NONE,
51 CONNECTOR_VGA,
52 CONNECTOR_DVI_I,
53 CONNECTOR_DVI_D,
54 CONNECTOR_DVI_A,
55 CONNECTOR_STV,
56 CONNECTOR_CTV,
57 CONNECTOR_LVDS,
58 CONNECTOR_DIGITAL,
59 CONNECTOR_SCART,
60 CONNECTOR_HDMI_TYPE_A,
61 CONNECTOR_HDMI_TYPE_B,
62 CONNECTOR_0XC,
63 CONNECTOR_0XD,
64 CONNECTOR_DIN,
65 CONNECTOR_DISPLAY_PORT,
66 CONNECTOR_UNSUPPORTED
67};
68
69enum radeon_dvi_type {
70 DVI_AUTO,
71 DVI_DIGITAL,
72 DVI_ANALOG
73};
74
75enum radeon_rmx_type {
76 RMX_OFF,
77 RMX_FULL,
78 RMX_CENTER,
79 RMX_ASPECT
80};
81
82enum radeon_tv_std {
83 TV_STD_NTSC,
84 TV_STD_PAL,
85 TV_STD_PAL_M,
86 TV_STD_PAL_60,
87 TV_STD_NTSC_J,
88 TV_STD_SCART_PAL,
89 TV_STD_SECAM,
90 TV_STD_PAL_CN,
d79766fa 91 TV_STD_PAL_N,
771fe6b9
JG		 92};
93
9b9fe724
AD		 94/* radeon gpio-based i2c
95 * 1. "mask" reg and bits
96 * grabs the gpio pins for software use
97 * 0=not held 1=held
98 * 2. "a" reg and bits
99 * output pin value
100 * 0=low 1=high
101 * 3. "en" reg and bits
102 * sets the pin direction
103 * 0=input 1=output
104 * 4. "y" reg and bits
105 * input pin value
106 * 0=low 1=high
107 */
771fe6b9
JG		 108struct radeon_i2c_bus_rec {
109 bool valid;
6a93cb25
AD		 110 /* id used by atom */
111 uint8_t i2c_id;
112 /* can be used with hw i2c engine */
113 bool hw_capable;
114 /* uses multi-media i2c engine */
115 bool mm_i2c;
116 /* regs and bits */
771fe6b9
JG		 117 uint32_t mask_clk_reg;
118 uint32_t mask_data_reg;
119 uint32_t a_clk_reg;
120 uint32_t a_data_reg;
9b9fe724
AD		 121 uint32_t en_clk_reg;
122 uint32_t en_data_reg;
123 uint32_t y_clk_reg;
124 uint32_t y_data_reg;
771fe6b9
JG		 125 uint32_t mask_clk_mask;
126 uint32_t mask_data_mask;
771fe6b9
JG		 127 uint32_t a_clk_mask;
128 uint32_t a_data_mask;
9b9fe724
AD		 129 uint32_t en_clk_mask;
130 uint32_t en_data_mask;
131 uint32_t y_clk_mask;
132 uint32_t y_data_mask;
771fe6b9
JG		 133};
134
135struct radeon_tmds_pll {
136 uint32_t freq;
137 uint32_t value;
138};
139
140#define RADEON_MAX_BIOS_CONNECTOR 16
141
142#define RADEON_PLL_USE_BIOS_DIVS (1 << 0)
143#define RADEON_PLL_NO_ODD_POST_DIV (1 << 1)
144#define RADEON_PLL_USE_REF_DIV (1 << 2)
145#define RADEON_PLL_LEGACY (1 << 3)
146#define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4)
147#define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5)
148#define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6)
149#define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7)
150#define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8)
151#define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9)
152#define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10)
d0e275a9 153#define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11)
771fe6b9
JG		 154
155struct radeon_pll {
156 uint16_t reference_freq;
157 uint16_t reference_div;
158 uint32_t pll_in_min;
159 uint32_t pll_in_max;
160 uint32_t pll_out_min;
161 uint32_t pll_out_max;
162 uint16_t xclk;
163
164 uint32_t min_ref_div;
165 uint32_t max_ref_div;
166 uint32_t min_post_div;
167 uint32_t max_post_div;
168 uint32_t min_feedback_div;
169 uint32_t max_feedback_div;
170 uint32_t min_frac_feedback_div;
171 uint32_t max_frac_feedback_div;
172 uint32_t best_vco;
173};
174
175struct radeon_i2c_chan {
771fe6b9 176 struct i2c_adapter adapter;
746c1aa4
DA		 177 struct drm_device *dev;
178 union {
179 struct i2c_algo_dp_aux_data dp;
180 struct i2c_algo_bit_data bit;
181 } algo;
771fe6b9
JG		 182 struct radeon_i2c_bus_rec rec;
183};
184
185/* mostly for macs, but really any system without connector tables */
186enum radeon_connector_table {
187 CT_NONE,
188 CT_GENERIC,
189 CT_IBOOK,
190 CT_POWERBOOK_EXTERNAL,
191 CT_POWERBOOK_INTERNAL,
192 CT_POWERBOOK_VGA,
193 CT_MINI_EXTERNAL,
194 CT_MINI_INTERNAL,
195 CT_IMAC_G5_ISIGHT,
196 CT_EMAC,
197};
198
fcec570b
AD		 199enum radeon_dvo_chip {
200 DVO_SIL164,
201 DVO_SIL1178,
202};
203
771fe6b9
JG		 204struct radeon_mode_info {
205 struct atom_context *atom_context;
61c4b24b 206 struct card_info *atom_card_info;
771fe6b9
JG		 207 enum radeon_connector_table connector_table;
208 bool mode_config_initialized;
c93bb85b 209 struct radeon_crtc *crtcs[2];
445282db
DA		 210 /* DVI-I properties */
211 struct drm_property *coherent_mode_property;
212 /* DAC enable load detect */
213 struct drm_property *load_detect_property;
214 /* TV standard load detect */
215 struct drm_property *tv_std_property;
216 /* legacy TMDS PLL detect */
217 struct drm_property *tmds_pll_property;
218
c93bb85b
JG		 219};
220
4ce001ab
DA		 221#define MAX_H_CODE_TIMING_LEN 32
222#define MAX_V_CODE_TIMING_LEN 32
223
224/* need to store these as reading
225 back code tables is excessive */
226struct radeon_tv_regs {
227 uint32_t tv_uv_adr;
228 uint32_t timing_cntl;
229 uint32_t hrestart;
230 uint32_t vrestart;
231 uint32_t frestart;
232 uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN];
233 uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN];
234};
235
771fe6b9
JG		 236struct radeon_crtc {
237 struct drm_crtc base;
238 int crtc_id;
239 u16 lut_r[256], lut_g[256], lut_b[256];
240 bool enabled;
241 bool can_tile;
242 uint32_t crtc_offset;
771fe6b9
JG		 243 struct drm_gem_object *cursor_bo;
244 uint64_t cursor_addr;
245 int cursor_width;
246 int cursor_height;
4162338a 247 uint32_t legacy_display_base_addr;
c836e862 248 uint32_t legacy_cursor_offset;
c93bb85b 249 enum radeon_rmx_type rmx_type;
c93bb85b
JG		 250 fixed20_12 vsc;
251 fixed20_12 hsc;
de2103e4 252 struct drm_display_mode native_mode;
771fe6b9
JG		 253};
254
255struct radeon_encoder_primary_dac {
256 /* legacy primary dac */
257 uint32_t ps2_pdac_adj;
258};
259
260struct radeon_encoder_lvds {
261 /* legacy lvds */
262 uint16_t panel_vcc_delay;
263 uint8_t panel_pwr_delay;
264 uint8_t panel_digon_delay;
265 uint8_t panel_blon_delay;
266 uint16_t panel_ref_divider;
267 uint8_t panel_post_divider;
268 uint16_t panel_fb_divider;
269 bool use_bios_dividers;
270 uint32_t lvds_gen_cntl;
271 /* panel mode */
de2103e4 272 struct drm_display_mode native_mode;
771fe6b9
JG		 273};
274
275struct radeon_encoder_tv_dac {
276 /* legacy tv dac */
277 uint32_t ps2_tvdac_adj;
278 uint32_t ntsc_tvdac_adj;
279 uint32_t pal_tvdac_adj;
280
4ce001ab
DA		 281 int h_pos;
282 int v_pos;
283 int h_size;
284 int supported_tv_stds;
285 bool tv_on;
771fe6b9 286 enum radeon_tv_std tv_std;
4ce001ab 287 struct radeon_tv_regs tv;
771fe6b9
JG		 288};
289
290struct radeon_encoder_int_tmds {
291 /* legacy int tmds */
292 struct radeon_tmds_pll tmds_pll[4];
293};
294
fcec570b
AD		 295struct radeon_encoder_ext_tmds {
296 /* tmds over dvo */
297 struct radeon_i2c_chan *i2c_bus;
298 uint8_t slave_addr;
299 enum radeon_dvo_chip dvo_chip;
300};
301
ebbe1cb9
AD		 302/* spread spectrum */
303struct radeon_atom_ss {
304 uint16_t percentage;
305 uint8_t type;
306 uint8_t step;
307 uint8_t delay;
308 uint8_t range;
309 uint8_t refdiv;
310};
311
771fe6b9
JG		 312struct radeon_encoder_atom_dig {
313 /* atom dig */
314 bool coherent_mode;
315 int dig_block;
316 /* atom lvds */
317 uint32_t lvds_misc;
318 uint16_t panel_pwr_delay;
ebbe1cb9 319 struct radeon_atom_ss *ss;
771fe6b9 320 /* panel mode */
de2103e4 321 struct drm_display_mode native_mode;
771fe6b9
JG		 322};
323
4ce001ab
DA		 324struct radeon_encoder_atom_dac {
325 enum radeon_tv_std tv_std;
326};
327
771fe6b9
JG		 328struct radeon_encoder {
329 struct drm_encoder base;
330 uint32_t encoder_id;
331 uint32_t devices;
4ce001ab 332 uint32_t active_device;
771fe6b9
JG		 333 uint32_t flags;
334 uint32_t pixel_clock;
335 enum radeon_rmx_type rmx_type;
de2103e4 336 struct drm_display_mode native_mode;
771fe6b9 337 void *enc_priv;
dafc3bd5
CK		 338 int hdmi_offset;
339 int hdmi_audio_workaround;
340 int hdmi_buffer_status;
771fe6b9
JG		 341};
342
343struct radeon_connector_atom_dig {
344 uint32_t igp_lane_info;
345 bool linkb;
4143e919 346 /* displayport */
746c1aa4 347 struct radeon_i2c_chan *dp_i2c_bus;
1a66c95a 348 u8 dpcd[8];
4143e919 349 u8 dp_sink_type;
5801ead6
AD		 350 int dp_clock;
351 int dp_lane_count;
771fe6b9
JG		 352};
353
eed45b30
AD		 354struct radeon_gpio_rec {
355 bool valid;
356 u8 id;
357 u32 reg;
358 u32 mask;
359};
360
361enum radeon_hpd_id {
362 RADEON_HPD_NONE = 0,
363 RADEON_HPD_1,
364 RADEON_HPD_2,
365 RADEON_HPD_3,
366 RADEON_HPD_4,
367 RADEON_HPD_5,
368 RADEON_HPD_6,
369};
370
371struct radeon_hpd {
372 enum radeon_hpd_id hpd;
373 u8 plugged_state;
374 struct radeon_gpio_rec gpio;
375};
376
771fe6b9
JG		 377struct radeon_connector {
378 struct drm_connector base;
379 uint32_t connector_id;
380 uint32_t devices;
381 struct radeon_i2c_chan *ddc_bus;
0294cf4f
AD		 382 /* some systems have a an hdmi and vga port with a shared ddc line */
383 bool shared_ddc;
4ce001ab
DA		 384 bool use_digital;
385 /* we need to mind the EDID between detect
386 and get modes due to analog/digital/tvencoder */
387 struct edid *edid;
771fe6b9 388 void *con_priv;
445282db 389 bool dac_load_detect;
b75fad06 390 uint16_t connector_object_id;
eed45b30 391 struct radeon_hpd hpd;
771fe6b9
JG		 392};
393
394struct radeon_framebuffer {
395 struct drm_framebuffer base;
396 struct drm_gem_object *obj;
397};
398
d79766fa
AD		 399extern enum radeon_tv_std
400radeon_combios_get_tv_info(struct radeon_device *rdev);
401extern enum radeon_tv_std
402radeon_atombios_get_tv_info(struct radeon_device *rdev);
403
d4877cf2
AD		 404extern void radeon_connector_hotplug(struct drm_connector *connector);
405extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector);
5801ead6
AD		 406extern int radeon_dp_mode_valid_helper(struct radeon_connector *radeon_connector,
407 struct drm_display_mode *mode);
408extern void radeon_dp_set_link_config(struct drm_connector *connector,
409 struct drm_display_mode *mode);
410extern void dp_link_train(struct drm_encoder *encoder,
411 struct drm_connector *connector);
4143e919 412extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector);
9fa05c98 413extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector);
5801ead6
AD		 414extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder,
415 int action, uint8_t lane_num,
416 uint8_t lane_set);
746c1aa4
DA		 417extern int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
418 uint8_t write_byte, uint8_t *read_byte);
419
420extern struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev,
6a93cb25
AD		 421 struct radeon_i2c_bus_rec *rec,
422 const char *name);
771fe6b9
JG		 423extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
424 struct radeon_i2c_bus_rec *rec,
425 const char *name);
426extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c);
fcec570b
AD		 427extern void radeon_i2c_sw_get_byte(struct radeon_i2c_chan *i2c_bus,
428 u8 slave_addr,
429 u8 addr,
430 u8 *val);
431extern void radeon_i2c_sw_put_byte(struct radeon_i2c_chan *i2c,
432 u8 slave_addr,
433 u8 addr,
434 u8 val);
771fe6b9
JG		 435extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector);
436extern int radeon_ddc_get_modes(struct radeon_connector *radeon_connector);
437
438extern struct drm_encoder *radeon_best_encoder(struct drm_connector *connector);
439
440extern void radeon_compute_pll(struct radeon_pll *pll,
441 uint64_t freq,
442 uint32_t *dot_clock_p,
443 uint32_t *fb_div_p,
444 uint32_t *frac_fb_div_p,
445 uint32_t *ref_div_p,
446 uint32_t *post_div_p,
447 int flags);
448
b27b6375
AD		 449extern void radeon_compute_pll_avivo(struct radeon_pll *pll,
450 uint64_t freq,
451 uint32_t *dot_clock_p,
452 uint32_t *fb_div_p,
453 uint32_t *frac_fb_div_p,
454 uint32_t *ref_div_p,
455 uint32_t *post_div_p,
456 int flags);
457
1f3b6a45
DA		 458extern void radeon_setup_encoder_clones(struct drm_device *dev);
459
771fe6b9
JG		 460struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index);
461struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv);
462struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv);
463struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index);
464struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index);
465extern void atombios_external_tmds_setup(struct drm_encoder *encoder, int action);
32f48ffe 466extern void atombios_digital_setup(struct drm_encoder *encoder, int action);
771fe6b9 467extern int atombios_get_encoder_mode(struct drm_encoder *encoder);
4ce001ab 468extern void radeon_encoder_set_active_device(struct drm_encoder *encoder);
771fe6b9
JG		 469
470extern void radeon_crtc_load_lut(struct drm_crtc *crtc);
471extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
472 struct drm_framebuffer *old_fb);
473extern int atombios_crtc_mode_set(struct drm_crtc *crtc,
474 struct drm_display_mode *mode,
475 struct drm_display_mode *adjusted_mode,
476 int x, int y,
477 struct drm_framebuffer *old_fb);
478extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode);
479
480extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
481 struct drm_framebuffer *old_fb);
482extern void radeon_legacy_atom_set_surface(struct drm_crtc *crtc);
483
484extern int radeon_crtc_cursor_set(struct drm_crtc *crtc,
485 struct drm_file *file_priv,
486 uint32_t handle,
487 uint32_t width,
488 uint32_t height);
489extern int radeon_crtc_cursor_move(struct drm_crtc *crtc,
490 int x, int y);
491
492extern bool radeon_atom_get_clock_info(struct drm_device *dev);
493extern bool radeon_combios_get_clock_info(struct drm_device *dev);
494extern struct radeon_encoder_atom_dig *
495radeon_atombios_get_lvds_info(struct radeon_encoder *encoder);
fcec570b
AD		 496extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
497 struct radeon_encoder_int_tmds *tmds);
498extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
499 struct radeon_encoder_int_tmds *tmds);
500extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
501 struct radeon_encoder_int_tmds *tmds);
502extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
503 struct radeon_encoder_ext_tmds *tmds);
504extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
505 struct radeon_encoder_ext_tmds *tmds);
6fe7ac3f
AD		 506extern struct radeon_encoder_primary_dac *
507radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder);
508extern struct radeon_encoder_tv_dac *
509radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder);
771fe6b9
JG		 510extern struct radeon_encoder_lvds *
511radeon_combios_get_lvds_info(struct radeon_encoder *encoder);
771fe6b9
JG		 512extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder);
513extern struct radeon_encoder_tv_dac *
514radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder);
515extern struct radeon_encoder_primary_dac *
516radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder);
fcec570b
AD		 517extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder);
518extern void radeon_external_tmds_setup(struct drm_encoder *encoder);
771fe6b9
JG		 519extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock);
520extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev);
521extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock);
522extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev);
f657c2a7
YZ		 523extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev);
524extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev);
771fe6b9
JG		 525extern void
526radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
527extern void
528radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
529extern void
530radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
531extern void
532radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
533extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
534 u16 blue, int regno);
b8c00ac5
DA		 535extern void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
536 u16 *blue, int regno);
771fe6b9
JG		 537struct drm_framebuffer *radeon_framebuffer_create(struct drm_device *dev,
538 struct drm_mode_fb_cmd *mode_cmd,
539 struct drm_gem_object *obj);
540
541int radeonfb_probe(struct drm_device *dev);
542
543int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb);
544bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev);
545bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev);
546void radeon_atombios_init_crtc(struct drm_device *dev,
547 struct radeon_crtc *radeon_crtc);
548void radeon_legacy_init_crtc(struct drm_device *dev,
549 struct radeon_crtc *radeon_crtc);
ab1e9ea0 550extern void radeon_i2c_do_lock(struct radeon_i2c_chan *i2c, int lock_state);
771fe6b9
JG		 551
552void radeon_get_clock_info(struct drm_device *dev);
553
554extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev);
555extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev);
556
771fe6b9
JG		 557void radeon_enc_destroy(struct drm_encoder *encoder);
558void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj);
559void radeon_combios_asic_init(struct drm_device *dev);
560extern int radeon_static_clocks_init(struct drm_device *dev);
c93bb85b
JG		 561bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
562 struct drm_display_mode *mode,
563 struct drm_display_mode *adjusted_mode);
4ce001ab
DA		 564void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc);
565
566/* legacy tv */
567void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder,
568 uint32_t *h_total_disp, uint32_t *h_sync_strt_wid,
569 uint32_t *v_total_disp, uint32_t *v_sync_strt_wid);
570void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder,
571 uint32_t *htotal_cntl, uint32_t *ppll_ref_div,
572 uint32_t *ppll_div_3, uint32_t *pixclks_cntl);
573void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder,
574 uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div,
575 uint32_t *p2pll_div_0, uint32_t *pixclks_cntl);
576void radeon_legacy_tv_mode_set(struct drm_encoder *encoder,
577 struct drm_display_mode *mode,
578 struct drm_display_mode *adjusted_mode);
771fe6b9 579#endif
Clone of davem's net-next-2.6 tree