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drm/radeon/kms: add support for square microtiles on r3xx-r5xx
[net-next-2.6.git] / drivers / gpu / drm / radeon / radeon_mode.h
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
3 * VA Linux Systems Inc., Fremont, California.
4 * Copyright 2008 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Original Authors:
25 * Kevin E. Martin, Rickard E. Faith, Alan Hourihane
26 *
27 * Kernel port Author: Dave Airlie
28 */
29
30#ifndef RADEON_MODE_H
31#define RADEON_MODE_H
32
33#include <drm_crtc.h>
34#include <drm_mode.h>
35#include <drm_edid.h>
746c1aa4 36#include <drm_dp_helper.h>
771fe6b9
JG		 37#include <linux/i2c.h>
38#include <linux/i2c-id.h>
39#include <linux/i2c-algo-bit.h>
c93bb85b
JG		 40#include "radeon_fixed.h"
41
42struct radeon_device;
771fe6b9
JG		 43
44#define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base)
45#define to_radeon_connector(x) container_of(x, struct radeon_connector, base)
46#define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base)
47#define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base)
48
771fe6b9
JG		 49enum radeon_rmx_type {
50 RMX_OFF,
51 RMX_FULL,
52 RMX_CENTER,
53 RMX_ASPECT
54};
55
56enum radeon_tv_std {
57 TV_STD_NTSC,
58 TV_STD_PAL,
59 TV_STD_PAL_M,
60 TV_STD_PAL_60,
61 TV_STD_NTSC_J,
62 TV_STD_SCART_PAL,
63 TV_STD_SECAM,
64 TV_STD_PAL_CN,
d79766fa 65 TV_STD_PAL_N,
771fe6b9
JG		 66};
67
9b9fe724
AD		 68/* radeon gpio-based i2c
69 * 1. "mask" reg and bits
70 * grabs the gpio pins for software use
71 * 0=not held 1=held
72 * 2. "a" reg and bits
73 * output pin value
74 * 0=low 1=high
75 * 3. "en" reg and bits
76 * sets the pin direction
77 * 0=input 1=output
78 * 4. "y" reg and bits
79 * input pin value
80 * 0=low 1=high
81 */
771fe6b9
JG		 82struct radeon_i2c_bus_rec {
83 bool valid;
6a93cb25
AD		 84 /* id used by atom */
85 uint8_t i2c_id;
bcc1c2a1
AD		 86 /* id used by atom */
87 uint8_t hpd_id;
6a93cb25
AD		 88 /* can be used with hw i2c engine */
89 bool hw_capable;
90 /* uses multi-media i2c engine */
91 bool mm_i2c;
92 /* regs and bits */
771fe6b9
JG		 93 uint32_t mask_clk_reg;
94 uint32_t mask_data_reg;
95 uint32_t a_clk_reg;
96 uint32_t a_data_reg;
9b9fe724
AD		 97 uint32_t en_clk_reg;
98 uint32_t en_data_reg;
99 uint32_t y_clk_reg;
100 uint32_t y_data_reg;
771fe6b9
JG		 101 uint32_t mask_clk_mask;
102 uint32_t mask_data_mask;
771fe6b9
JG		 103 uint32_t a_clk_mask;
104 uint32_t a_data_mask;
9b9fe724
AD		 105 uint32_t en_clk_mask;
106 uint32_t en_data_mask;
107 uint32_t y_clk_mask;
108 uint32_t y_data_mask;
771fe6b9
JG		 109};
110
111struct radeon_tmds_pll {
112 uint32_t freq;
113 uint32_t value;
114};
115
116#define RADEON_MAX_BIOS_CONNECTOR 16
117
7c27f87d 118/* pll flags */
771fe6b9
JG		 119#define RADEON_PLL_USE_BIOS_DIVS (1 << 0)
120#define RADEON_PLL_NO_ODD_POST_DIV (1 << 1)
121#define RADEON_PLL_USE_REF_DIV (1 << 2)
122#define RADEON_PLL_LEGACY (1 << 3)
123#define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4)
124#define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5)
125#define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6)
126#define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7)
127#define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8)
128#define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9)
129#define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10)
d0e275a9 130#define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11)
fc10332b 131#define RADEON_PLL_USE_POST_DIV (1 << 12)
771fe6b9 132
7c27f87d
AD		 133/* pll algo */
134enum radeon_pll_algo {
135 PLL_ALGO_LEGACY,
136 PLL_ALGO_AVIVO
137};
138
771fe6b9 139struct radeon_pll {
fc10332b
AD		 140 /* reference frequency */
141 uint32_t reference_freq;
142
143 /* fixed dividers */
144 uint32_t reference_div;
145 uint32_t post_div;
146
147 /* pll in/out limits */
771fe6b9
JG		 148 uint32_t pll_in_min;
149 uint32_t pll_in_max;
150 uint32_t pll_out_min;
151 uint32_t pll_out_max;
fc10332b 152 uint32_t best_vco;
771fe6b9 153
fc10332b 154 /* divider limits */
771fe6b9
JG		 155 uint32_t min_ref_div;
156 uint32_t max_ref_div;
157 uint32_t min_post_div;
158 uint32_t max_post_div;
159 uint32_t min_feedback_div;
160 uint32_t max_feedback_div;
161 uint32_t min_frac_feedback_div;
162 uint32_t max_frac_feedback_div;
fc10332b
AD		 163
164 /* flags for the current clock */
165 uint32_t flags;
166
167 /* pll id */
168 uint32_t id;
7c27f87d
AD		 169 /* pll algo */
170 enum radeon_pll_algo algo;
771fe6b9
JG		 171};
172
5a6f98f5
AD		 173struct i2c_algo_radeon_data {
174 struct i2c_adapter bit_adapter;
175 struct i2c_algo_bit_data bit_data;
176};
177
771fe6b9 178struct radeon_i2c_chan {
771fe6b9 179 struct i2c_adapter adapter;
746c1aa4
DA		 180 struct drm_device *dev;
181 union {
182 struct i2c_algo_dp_aux_data dp;
5a6f98f5 183 struct i2c_algo_radeon_data radeon;
746c1aa4 184 } algo;
771fe6b9
JG		 185 struct radeon_i2c_bus_rec rec;
186};
187
188/* mostly for macs, but really any system without connector tables */
189enum radeon_connector_table {
190 CT_NONE,
191 CT_GENERIC,
192 CT_IBOOK,
193 CT_POWERBOOK_EXTERNAL,
194 CT_POWERBOOK_INTERNAL,
195 CT_POWERBOOK_VGA,
196 CT_MINI_EXTERNAL,
197 CT_MINI_INTERNAL,
198 CT_IMAC_G5_ISIGHT,
199 CT_EMAC,
200};
201
fcec570b
AD		 202enum radeon_dvo_chip {
203 DVO_SIL164,
204 DVO_SIL1178,
205};
206
771fe6b9
JG		 207struct radeon_mode_info {
208 struct atom_context *atom_context;
61c4b24b 209 struct card_info *atom_card_info;
771fe6b9
JG		 210 enum radeon_connector_table connector_table;
211 bool mode_config_initialized;
bcc1c2a1 212 struct radeon_crtc *crtcs[6];
445282db
DA		 213 /* DVI-I properties */
214 struct drm_property *coherent_mode_property;
215 /* DAC enable load detect */
216 struct drm_property *load_detect_property;
217 /* TV standard load detect */
218 struct drm_property *tv_std_property;
219 /* legacy TMDS PLL detect */
220 struct drm_property *tmds_pll_property;
3c537889
AD		 221 /* hardcoded DFP edid from BIOS */
222 struct edid *bios_hardcoded_edid;
c93bb85b
JG		 223};
224
4ce001ab
DA		 225#define MAX_H_CODE_TIMING_LEN 32
226#define MAX_V_CODE_TIMING_LEN 32
227
228/* need to store these as reading
229 back code tables is excessive */
230struct radeon_tv_regs {
231 uint32_t tv_uv_adr;
232 uint32_t timing_cntl;
233 uint32_t hrestart;
234 uint32_t vrestart;
235 uint32_t frestart;
236 uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN];
237 uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN];
238};
239
771fe6b9
JG		 240struct radeon_crtc {
241 struct drm_crtc base;
242 int crtc_id;
243 u16 lut_r[256], lut_g[256], lut_b[256];
244 bool enabled;
245 bool can_tile;
246 uint32_t crtc_offset;
771fe6b9
JG		 247 struct drm_gem_object *cursor_bo;
248 uint64_t cursor_addr;
249 int cursor_width;
250 int cursor_height;
4162338a 251 uint32_t legacy_display_base_addr;
c836e862 252 uint32_t legacy_cursor_offset;
c93bb85b 253 enum radeon_rmx_type rmx_type;
c93bb85b
JG		 254 fixed20_12 vsc;
255 fixed20_12 hsc;
de2103e4 256 struct drm_display_mode native_mode;
bcc1c2a1 257 int pll_id;
771fe6b9
JG		 258};
259
260struct radeon_encoder_primary_dac {
261 /* legacy primary dac */
262 uint32_t ps2_pdac_adj;
263};
264
265struct radeon_encoder_lvds {
266 /* legacy lvds */
267 uint16_t panel_vcc_delay;
268 uint8_t panel_pwr_delay;
269 uint8_t panel_digon_delay;
270 uint8_t panel_blon_delay;
271 uint16_t panel_ref_divider;
272 uint8_t panel_post_divider;
273 uint16_t panel_fb_divider;
274 bool use_bios_dividers;
275 uint32_t lvds_gen_cntl;
276 /* panel mode */
de2103e4 277 struct drm_display_mode native_mode;
771fe6b9
JG		 278};
279
280struct radeon_encoder_tv_dac {
281 /* legacy tv dac */
282 uint32_t ps2_tvdac_adj;
283 uint32_t ntsc_tvdac_adj;
284 uint32_t pal_tvdac_adj;
285
4ce001ab
DA		 286 int h_pos;
287 int v_pos;
288 int h_size;
289 int supported_tv_stds;
290 bool tv_on;
771fe6b9 291 enum radeon_tv_std tv_std;
4ce001ab 292 struct radeon_tv_regs tv;
771fe6b9
JG		 293};
294
295struct radeon_encoder_int_tmds {
296 /* legacy int tmds */
297 struct radeon_tmds_pll tmds_pll[4];
298};
299
fcec570b
AD		 300struct radeon_encoder_ext_tmds {
301 /* tmds over dvo */
302 struct radeon_i2c_chan *i2c_bus;
303 uint8_t slave_addr;
304 enum radeon_dvo_chip dvo_chip;
305};
306
ebbe1cb9
AD		 307/* spread spectrum */
308struct radeon_atom_ss {
309 uint16_t percentage;
310 uint8_t type;
311 uint8_t step;
312 uint8_t delay;
313 uint8_t range;
314 uint8_t refdiv;
315};
316
771fe6b9
JG		 317struct radeon_encoder_atom_dig {
318 /* atom dig */
319 bool coherent_mode;
f28cf339 320 int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB */
771fe6b9
JG		 321 /* atom lvds */
322 uint32_t lvds_misc;
323 uint16_t panel_pwr_delay;
7c27f87d 324 enum radeon_pll_algo pll_algo;
ebbe1cb9 325 struct radeon_atom_ss *ss;
771fe6b9 326 /* panel mode */
de2103e4 327 struct drm_display_mode native_mode;
771fe6b9
JG		 328};
329
4ce001ab
DA		 330struct radeon_encoder_atom_dac {
331 enum radeon_tv_std tv_std;
332};
333
771fe6b9
JG		 334struct radeon_encoder {
335 struct drm_encoder base;
336 uint32_t encoder_id;
337 uint32_t devices;
4ce001ab 338 uint32_t active_device;
771fe6b9
JG		 339 uint32_t flags;
340 uint32_t pixel_clock;
341 enum radeon_rmx_type rmx_type;
de2103e4 342 struct drm_display_mode native_mode;
771fe6b9 343 void *enc_priv;
dafc3bd5
CK		 344 int hdmi_offset;
345 int hdmi_audio_workaround;
346 int hdmi_buffer_status;
771fe6b9
JG		 347};
348
349struct radeon_connector_atom_dig {
350 uint32_t igp_lane_info;
351 bool linkb;
4143e919 352 /* displayport */
746c1aa4 353 struct radeon_i2c_chan *dp_i2c_bus;
1a66c95a 354 u8 dpcd[8];
4143e919 355 u8 dp_sink_type;
5801ead6
AD		 356 int dp_clock;
357 int dp_lane_count;
771fe6b9
JG		 358};
359
eed45b30
AD		 360struct radeon_gpio_rec {
361 bool valid;
362 u8 id;
363 u32 reg;
364 u32 mask;
365};
366
367enum radeon_hpd_id {
368 RADEON_HPD_NONE = 0,
369 RADEON_HPD_1,
370 RADEON_HPD_2,
371 RADEON_HPD_3,
372 RADEON_HPD_4,
373 RADEON_HPD_5,
374 RADEON_HPD_6,
375};
376
377struct radeon_hpd {
378 enum radeon_hpd_id hpd;
379 u8 plugged_state;
380 struct radeon_gpio_rec gpio;
381};
382
771fe6b9
JG		 383struct radeon_connector {
384 struct drm_connector base;
385 uint32_t connector_id;
386 uint32_t devices;
387 struct radeon_i2c_chan *ddc_bus;
0294cf4f
AD		 388 /* some systems have a an hdmi and vga port with a shared ddc line */
389 bool shared_ddc;
4ce001ab
DA		 390 bool use_digital;
391 /* we need to mind the EDID between detect
392 and get modes due to analog/digital/tvencoder */
393 struct edid *edid;
771fe6b9 394 void *con_priv;
445282db 395 bool dac_load_detect;
b75fad06 396 uint16_t connector_object_id;
eed45b30 397 struct radeon_hpd hpd;
771fe6b9
JG		 398};
399
400struct radeon_framebuffer {
401 struct drm_framebuffer base;
402 struct drm_gem_object *obj;
403};
404
d79766fa
AD		 405extern enum radeon_tv_std
406radeon_combios_get_tv_info(struct radeon_device *rdev);
407extern enum radeon_tv_std
408radeon_atombios_get_tv_info(struct radeon_device *rdev);
409
d4877cf2
AD		 410extern void radeon_connector_hotplug(struct drm_connector *connector);
411extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector);
5801ead6
AD		 412extern int radeon_dp_mode_valid_helper(struct radeon_connector *radeon_connector,
413 struct drm_display_mode *mode);
414extern void radeon_dp_set_link_config(struct drm_connector *connector,
415 struct drm_display_mode *mode);
416extern void dp_link_train(struct drm_encoder *encoder,
417 struct drm_connector *connector);
4143e919 418extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector);
9fa05c98 419extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector);
bcc1c2a1 420extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action);
5801ead6
AD		 421extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder,
422 int action, uint8_t lane_num,
423 uint8_t lane_set);
746c1aa4
DA		 424extern int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
425 uint8_t write_byte, uint8_t *read_byte);
426
427extern struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev,
6a93cb25
AD		 428 struct radeon_i2c_bus_rec *rec,
429 const char *name);
771fe6b9
JG		 430extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
431 struct radeon_i2c_bus_rec *rec,
432 const char *name);
433extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c);
5a6f98f5
AD		 434extern void radeon_i2c_destroy_dp(struct radeon_i2c_chan *i2c);
435extern void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus,
436 u8 slave_addr,
437 u8 addr,
438 u8 *val);
439extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c,
440 u8 slave_addr,
441 u8 addr,
442 u8 val);
771fe6b9
JG		 443extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector);
444extern int radeon_ddc_get_modes(struct radeon_connector *radeon_connector);
445
446extern struct drm_encoder *radeon_best_encoder(struct drm_connector *connector);
447
448extern void radeon_compute_pll(struct radeon_pll *pll,
449 uint64_t freq,
450 uint32_t *dot_clock_p,
451 uint32_t *fb_div_p,
452 uint32_t *frac_fb_div_p,
453 uint32_t *ref_div_p,
fc10332b 454 uint32_t *post_div_p);
771fe6b9 455
1f3b6a45
DA		 456extern void radeon_setup_encoder_clones(struct drm_device *dev);
457
771fe6b9
JG		 458struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index);
459struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv);
460struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv);
461struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index);
462struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index);
463extern void atombios_external_tmds_setup(struct drm_encoder *encoder, int action);
32f48ffe 464extern void atombios_digital_setup(struct drm_encoder *encoder, int action);
771fe6b9 465extern int atombios_get_encoder_mode(struct drm_encoder *encoder);
4ce001ab 466extern void radeon_encoder_set_active_device(struct drm_encoder *encoder);
771fe6b9
JG		 467
468extern void radeon_crtc_load_lut(struct drm_crtc *crtc);
469extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
470 struct drm_framebuffer *old_fb);
471extern int atombios_crtc_mode_set(struct drm_crtc *crtc,
472 struct drm_display_mode *mode,
473 struct drm_display_mode *adjusted_mode,
474 int x, int y,
475 struct drm_framebuffer *old_fb);
476extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode);
477
478extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
479 struct drm_framebuffer *old_fb);
771fe6b9
JG		 480
481extern int radeon_crtc_cursor_set(struct drm_crtc *crtc,
482 struct drm_file *file_priv,
483 uint32_t handle,
484 uint32_t width,
485 uint32_t height);
486extern int radeon_crtc_cursor_move(struct drm_crtc *crtc,
487 int x, int y);
488
3c537889
AD		 489extern bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev);
490extern struct edid *
491radeon_combios_get_hardcoded_edid(struct radeon_device *rdev);
771fe6b9
JG		 492extern bool radeon_atom_get_clock_info(struct drm_device *dev);
493extern bool radeon_combios_get_clock_info(struct drm_device *dev);
494extern struct radeon_encoder_atom_dig *
495radeon_atombios_get_lvds_info(struct radeon_encoder *encoder);
fcec570b
AD		 496extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
497 struct radeon_encoder_int_tmds *tmds);
498extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
499 struct radeon_encoder_int_tmds *tmds);
500extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
501 struct radeon_encoder_int_tmds *tmds);
502extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
503 struct radeon_encoder_ext_tmds *tmds);
504extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
505 struct radeon_encoder_ext_tmds *tmds);
6fe7ac3f
AD		 506extern struct radeon_encoder_primary_dac *
507radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder);
508extern struct radeon_encoder_tv_dac *
509radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder);
771fe6b9
JG		 510extern struct radeon_encoder_lvds *
511radeon_combios_get_lvds_info(struct radeon_encoder *encoder);
771fe6b9
JG		 512extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder);
513extern struct radeon_encoder_tv_dac *
514radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder);
515extern struct radeon_encoder_primary_dac *
516radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder);
fcec570b
AD		 517extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder);
518extern void radeon_external_tmds_setup(struct drm_encoder *encoder);
771fe6b9
JG		 519extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock);
520extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev);
521extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock);
522extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev);
f657c2a7
YZ		 523extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev);
524extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev);
771fe6b9
JG		 525extern void
526radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
527extern void
528radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
529extern void
530radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
531extern void
532radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
533extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
534 u16 blue, int regno);
b8c00ac5
DA		 535extern void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
536 u16 *blue, int regno);
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JG		 537struct drm_framebuffer *radeon_framebuffer_create(struct drm_device *dev,
538 struct drm_mode_fb_cmd *mode_cmd,
539 struct drm_gem_object *obj);
540
541int radeonfb_probe(struct drm_device *dev);
542
543int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb);
544bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev);
545bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev);
546void radeon_atombios_init_crtc(struct drm_device *dev,
547 struct radeon_crtc *radeon_crtc);
548void radeon_legacy_init_crtc(struct drm_device *dev,
549 struct radeon_crtc *radeon_crtc);
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JG		 550
551void radeon_get_clock_info(struct drm_device *dev);
552
553extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev);
554extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev);
555
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JG		 556void radeon_enc_destroy(struct drm_encoder *encoder);
557void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj);
558void radeon_combios_asic_init(struct drm_device *dev);
559extern int radeon_static_clocks_init(struct drm_device *dev);
c93bb85b
JG		 560bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
561 struct drm_display_mode *mode,
562 struct drm_display_mode *adjusted_mode);
4ce001ab
DA		 563void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc);
564
565/* legacy tv */
566void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder,
567 uint32_t *h_total_disp, uint32_t *h_sync_strt_wid,
568 uint32_t *v_total_disp, uint32_t *v_sync_strt_wid);
569void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder,
570 uint32_t *htotal_cntl, uint32_t *ppll_ref_div,
571 uint32_t *ppll_div_3, uint32_t *pixclks_cntl);
572void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder,
573 uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div,
574 uint32_t *p2pll_div_0, uint32_t *pixclks_cntl);
575void radeon_legacy_tv_mode_set(struct drm_encoder *encoder,
576 struct drm_display_mode *mode,
577 struct drm_display_mode *adjusted_mode);
771fe6b9 578#endif
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