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radeon: Enable memory reclocking on r100-500
[net-next-2.6.git] / drivers / gpu / drm / radeon / radeon_mode.h
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
3 * VA Linux Systems Inc., Fremont, California.
4 * Copyright 2008 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Original Authors:
25 * Kevin E. Martin, Rickard E. Faith, Alan Hourihane
26 *
27 * Kernel port Author: Dave Airlie
28 */
29
30#ifndef RADEON_MODE_H
31#define RADEON_MODE_H
32
33#include <drm_crtc.h>
34#include <drm_mode.h>
35#include <drm_edid.h>
746c1aa4 36#include <drm_dp_helper.h>
771fe6b9
JG		 37#include <linux/i2c.h>
38#include <linux/i2c-id.h>
39#include <linux/i2c-algo-bit.h>
c93bb85b
JG		 40#include "radeon_fixed.h"
41
38651674 42struct radeon_bo;
c93bb85b 43struct radeon_device;
771fe6b9
JG		 44
45#define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base)
46#define to_radeon_connector(x) container_of(x, struct radeon_connector, base)
47#define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base)
48#define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base)
49
771fe6b9
JG		 50enum radeon_rmx_type {
51 RMX_OFF,
52 RMX_FULL,
53 RMX_CENTER,
54 RMX_ASPECT
55};
56
57enum radeon_tv_std {
58 TV_STD_NTSC,
59 TV_STD_PAL,
60 TV_STD_PAL_M,
61 TV_STD_PAL_60,
62 TV_STD_NTSC_J,
63 TV_STD_SCART_PAL,
64 TV_STD_SECAM,
65 TV_STD_PAL_CN,
d79766fa 66 TV_STD_PAL_N,
771fe6b9
JG		 67};
68
9b9fe724
AD		 69/* radeon gpio-based i2c
70 * 1. "mask" reg and bits
71 * grabs the gpio pins for software use
72 * 0=not held 1=held
73 * 2. "a" reg and bits
74 * output pin value
75 * 0=low 1=high
76 * 3. "en" reg and bits
77 * sets the pin direction
78 * 0=input 1=output
79 * 4. "y" reg and bits
80 * input pin value
81 * 0=low 1=high
82 */
771fe6b9
JG		 83struct radeon_i2c_bus_rec {
84 bool valid;
6a93cb25
AD		 85 /* id used by atom */
86 uint8_t i2c_id;
bcc1c2a1
AD		 87 /* id used by atom */
88 uint8_t hpd_id;
6a93cb25
AD		 89 /* can be used with hw i2c engine */
90 bool hw_capable;
91 /* uses multi-media i2c engine */
92 bool mm_i2c;
93 /* regs and bits */
771fe6b9
JG		 94 uint32_t mask_clk_reg;
95 uint32_t mask_data_reg;
96 uint32_t a_clk_reg;
97 uint32_t a_data_reg;
9b9fe724
AD		 98 uint32_t en_clk_reg;
99 uint32_t en_data_reg;
100 uint32_t y_clk_reg;
101 uint32_t y_data_reg;
771fe6b9
JG		 102 uint32_t mask_clk_mask;
103 uint32_t mask_data_mask;
771fe6b9
JG		 104 uint32_t a_clk_mask;
105 uint32_t a_data_mask;
9b9fe724
AD		 106 uint32_t en_clk_mask;
107 uint32_t en_data_mask;
108 uint32_t y_clk_mask;
109 uint32_t y_data_mask;
771fe6b9
JG		 110};
111
112struct radeon_tmds_pll {
113 uint32_t freq;
114 uint32_t value;
115};
116
117#define RADEON_MAX_BIOS_CONNECTOR 16
118
7c27f87d 119/* pll flags */
771fe6b9
JG		 120#define RADEON_PLL_USE_BIOS_DIVS (1 << 0)
121#define RADEON_PLL_NO_ODD_POST_DIV (1 << 1)
122#define RADEON_PLL_USE_REF_DIV (1 << 2)
123#define RADEON_PLL_LEGACY (1 << 3)
124#define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4)
125#define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5)
126#define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6)
127#define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7)
128#define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8)
129#define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9)
130#define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10)
d0e275a9 131#define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11)
fc10332b 132#define RADEON_PLL_USE_POST_DIV (1 << 12)
86cb2bbf 133#define RADEON_PLL_IS_LCD (1 << 13)
771fe6b9 134
7c27f87d
AD		 135/* pll algo */
136enum radeon_pll_algo {
137 PLL_ALGO_LEGACY,
383be5d1 138 PLL_ALGO_NEW
7c27f87d
AD		 139};
140
771fe6b9 141struct radeon_pll {
fc10332b
AD		 142 /* reference frequency */
143 uint32_t reference_freq;
144
145 /* fixed dividers */
146 uint32_t reference_div;
147 uint32_t post_div;
148
149 /* pll in/out limits */
771fe6b9
JG		 150 uint32_t pll_in_min;
151 uint32_t pll_in_max;
152 uint32_t pll_out_min;
153 uint32_t pll_out_max;
86cb2bbf
AD		 154 uint32_t lcd_pll_out_min;
155 uint32_t lcd_pll_out_max;
fc10332b 156 uint32_t best_vco;
771fe6b9 157
fc10332b 158 /* divider limits */
771fe6b9
JG		 159 uint32_t min_ref_div;
160 uint32_t max_ref_div;
161 uint32_t min_post_div;
162 uint32_t max_post_div;
163 uint32_t min_feedback_div;
164 uint32_t max_feedback_div;
165 uint32_t min_frac_feedback_div;
166 uint32_t max_frac_feedback_div;
fc10332b
AD		 167
168 /* flags for the current clock */
169 uint32_t flags;
170
171 /* pll id */
172 uint32_t id;
7c27f87d
AD		 173 /* pll algo */
174 enum radeon_pll_algo algo;
771fe6b9
JG		 175};
176
177struct radeon_i2c_chan {
771fe6b9 178 struct i2c_adapter adapter;
746c1aa4
DA		 179 struct drm_device *dev;
180 union {
ac1aade6 181 struct i2c_algo_bit_data bit;
746c1aa4 182 struct i2c_algo_dp_aux_data dp;
746c1aa4 183 } algo;
771fe6b9
JG		 184 struct radeon_i2c_bus_rec rec;
185};
186
187/* mostly for macs, but really any system without connector tables */
188enum radeon_connector_table {
189 CT_NONE,
190 CT_GENERIC,
191 CT_IBOOK,
192 CT_POWERBOOK_EXTERNAL,
193 CT_POWERBOOK_INTERNAL,
194 CT_POWERBOOK_VGA,
195 CT_MINI_EXTERNAL,
196 CT_MINI_INTERNAL,
197 CT_IMAC_G5_ISIGHT,
198 CT_EMAC,
199};
200
fcec570b
AD		 201enum radeon_dvo_chip {
202 DVO_SIL164,
203 DVO_SIL1178,
204};
205
8be48d92 206struct radeon_fbdev;
38651674 207
771fe6b9
JG		 208struct radeon_mode_info {
209 struct atom_context *atom_context;
61c4b24b 210 struct card_info *atom_card_info;
771fe6b9
JG		 211 enum radeon_connector_table connector_table;
212 bool mode_config_initialized;
bcc1c2a1 213 struct radeon_crtc *crtcs[6];
445282db
DA		 214 /* DVI-I properties */
215 struct drm_property *coherent_mode_property;
216 /* DAC enable load detect */
217 struct drm_property *load_detect_property;
218 /* TV standard load detect */
219 struct drm_property *tv_std_property;
220 /* legacy TMDS PLL detect */
221 struct drm_property *tmds_pll_property;
3c537889
AD		 222 /* hardcoded DFP edid from BIOS */
223 struct edid *bios_hardcoded_edid;
38651674
DA		 224
225 /* pointer to fbdev info structure */
8be48d92 226 struct radeon_fbdev *rfbdev;
c93bb85b
JG		 227};
228
4ce001ab
DA		 229#define MAX_H_CODE_TIMING_LEN 32
230#define MAX_V_CODE_TIMING_LEN 32
231
232/* need to store these as reading
233 back code tables is excessive */
234struct radeon_tv_regs {
235 uint32_t tv_uv_adr;
236 uint32_t timing_cntl;
237 uint32_t hrestart;
238 uint32_t vrestart;
239 uint32_t frestart;
240 uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN];
241 uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN];
242};
243
771fe6b9
JG		 244struct radeon_crtc {
245 struct drm_crtc base;
246 int crtc_id;
247 u16 lut_r[256], lut_g[256], lut_b[256];
248 bool enabled;
249 bool can_tile;
250 uint32_t crtc_offset;
771fe6b9
JG		 251 struct drm_gem_object *cursor_bo;
252 uint64_t cursor_addr;
253 int cursor_width;
254 int cursor_height;
4162338a 255 uint32_t legacy_display_base_addr;
c836e862 256 uint32_t legacy_cursor_offset;
c93bb85b 257 enum radeon_rmx_type rmx_type;
c93bb85b
JG		 258 fixed20_12 vsc;
259 fixed20_12 hsc;
de2103e4 260 struct drm_display_mode native_mode;
bcc1c2a1 261 int pll_id;
771fe6b9
JG		 262};
263
264struct radeon_encoder_primary_dac {
265 /* legacy primary dac */
266 uint32_t ps2_pdac_adj;
267};
268
269struct radeon_encoder_lvds {
270 /* legacy lvds */
271 uint16_t panel_vcc_delay;
272 uint8_t panel_pwr_delay;
273 uint8_t panel_digon_delay;
274 uint8_t panel_blon_delay;
275 uint16_t panel_ref_divider;
276 uint8_t panel_post_divider;
277 uint16_t panel_fb_divider;
278 bool use_bios_dividers;
279 uint32_t lvds_gen_cntl;
280 /* panel mode */
de2103e4 281 struct drm_display_mode native_mode;
771fe6b9
JG		 282};
283
284struct radeon_encoder_tv_dac {
285 /* legacy tv dac */
286 uint32_t ps2_tvdac_adj;
287 uint32_t ntsc_tvdac_adj;
288 uint32_t pal_tvdac_adj;
289
4ce001ab
DA		 290 int h_pos;
291 int v_pos;
292 int h_size;
293 int supported_tv_stds;
294 bool tv_on;
771fe6b9 295 enum radeon_tv_std tv_std;
4ce001ab 296 struct radeon_tv_regs tv;
771fe6b9
JG		 297};
298
299struct radeon_encoder_int_tmds {
300 /* legacy int tmds */
301 struct radeon_tmds_pll tmds_pll[4];
302};
303
fcec570b
AD		 304struct radeon_encoder_ext_tmds {
305 /* tmds over dvo */
306 struct radeon_i2c_chan *i2c_bus;
307 uint8_t slave_addr;
308 enum radeon_dvo_chip dvo_chip;
309};
310
ebbe1cb9
AD		 311/* spread spectrum */
312struct radeon_atom_ss {
313 uint16_t percentage;
314 uint8_t type;
315 uint8_t step;
316 uint8_t delay;
317 uint8_t range;
318 uint8_t refdiv;
319};
320
771fe6b9
JG		 321struct radeon_encoder_atom_dig {
322 /* atom dig */
323 bool coherent_mode;
f28cf339 324 int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB */
771fe6b9
JG		 325 /* atom lvds */
326 uint32_t lvds_misc;
327 uint16_t panel_pwr_delay;
7c27f87d 328 enum radeon_pll_algo pll_algo;
ebbe1cb9 329 struct radeon_atom_ss *ss;
771fe6b9 330 /* panel mode */
de2103e4 331 struct drm_display_mode native_mode;
771fe6b9
JG		 332};
333
4ce001ab
DA		 334struct radeon_encoder_atom_dac {
335 enum radeon_tv_std tv_std;
336};
337
771fe6b9
JG		 338struct radeon_encoder {
339 struct drm_encoder base;
340 uint32_t encoder_id;
341 uint32_t devices;
4ce001ab 342 uint32_t active_device;
771fe6b9
JG		 343 uint32_t flags;
344 uint32_t pixel_clock;
345 enum radeon_rmx_type rmx_type;
de2103e4 346 struct drm_display_mode native_mode;
771fe6b9 347 void *enc_priv;
58bd0863 348 int audio_polling_active;
dafc3bd5 349 int hdmi_offset;
808032ee 350 int hdmi_config_offset;
dafc3bd5
CK		 351 int hdmi_audio_workaround;
352 int hdmi_buffer_status;
771fe6b9
JG		 353};
354
355struct radeon_connector_atom_dig {
356 uint32_t igp_lane_info;
357 bool linkb;
4143e919 358 /* displayport */
746c1aa4 359 struct radeon_i2c_chan *dp_i2c_bus;
1a66c95a 360 u8 dpcd[8];
4143e919 361 u8 dp_sink_type;
5801ead6
AD		 362 int dp_clock;
363 int dp_lane_count;
771fe6b9
JG		 364};
365
eed45b30
AD		 366struct radeon_gpio_rec {
367 bool valid;
368 u8 id;
369 u32 reg;
370 u32 mask;
371};
372
373enum radeon_hpd_id {
374 RADEON_HPD_NONE = 0,
375 RADEON_HPD_1,
376 RADEON_HPD_2,
377 RADEON_HPD_3,
378 RADEON_HPD_4,
379 RADEON_HPD_5,
380 RADEON_HPD_6,
381};
382
383struct radeon_hpd {
384 enum radeon_hpd_id hpd;
385 u8 plugged_state;
386 struct radeon_gpio_rec gpio;
387};
388
771fe6b9
JG		 389struct radeon_connector {
390 struct drm_connector base;
391 uint32_t connector_id;
392 uint32_t devices;
393 struct radeon_i2c_chan *ddc_bus;
0294cf4f
AD		 394 /* some systems have a an hdmi and vga port with a shared ddc line */
395 bool shared_ddc;
4ce001ab
DA		 396 bool use_digital;
397 /* we need to mind the EDID between detect
398 and get modes due to analog/digital/tvencoder */
399 struct edid *edid;
771fe6b9 400 void *con_priv;
445282db 401 bool dac_load_detect;
b75fad06 402 uint16_t connector_object_id;
eed45b30 403 struct radeon_hpd hpd;
771fe6b9
JG		 404};
405
406struct radeon_framebuffer {
407 struct drm_framebuffer base;
408 struct drm_gem_object *obj;
409};
410
d79766fa
AD		 411extern enum radeon_tv_std
412radeon_combios_get_tv_info(struct radeon_device *rdev);
413extern enum radeon_tv_std
414radeon_atombios_get_tv_info(struct radeon_device *rdev);
415
d4877cf2
AD		 416extern void radeon_connector_hotplug(struct drm_connector *connector);
417extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector);
5801ead6
AD		 418extern int radeon_dp_mode_valid_helper(struct radeon_connector *radeon_connector,
419 struct drm_display_mode *mode);
420extern void radeon_dp_set_link_config(struct drm_connector *connector,
421 struct drm_display_mode *mode);
422extern void dp_link_train(struct drm_encoder *encoder,
423 struct drm_connector *connector);
4143e919 424extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector);
9fa05c98 425extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector);
bcc1c2a1 426extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action);
5801ead6
AD		 427extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder,
428 int action, uint8_t lane_num,
429 uint8_t lane_set);
746c1aa4
DA		 430extern int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
431 uint8_t write_byte, uint8_t *read_byte);
432
433extern struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev,
6a93cb25
AD		 434 struct radeon_i2c_bus_rec *rec,
435 const char *name);
771fe6b9
JG		 436extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
437 struct radeon_i2c_bus_rec *rec,
438 const char *name);
439extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c);
5a6f98f5
AD		 440extern void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus,
441 u8 slave_addr,
442 u8 addr,
443 u8 *val);
444extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c,
445 u8 slave_addr,
446 u8 addr,
447 u8 val);
771fe6b9
JG		 448extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector);
449extern int radeon_ddc_get_modes(struct radeon_connector *radeon_connector);
450
451extern struct drm_encoder *radeon_best_encoder(struct drm_connector *connector);
452
453extern void radeon_compute_pll(struct radeon_pll *pll,
454 uint64_t freq,
455 uint32_t *dot_clock_p,
456 uint32_t *fb_div_p,
457 uint32_t *frac_fb_div_p,
458 uint32_t *ref_div_p,
fc10332b 459 uint32_t *post_div_p);
771fe6b9 460
1f3b6a45
DA		 461extern void radeon_setup_encoder_clones(struct drm_device *dev);
462
771fe6b9
JG		 463struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index);
464struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv);
465struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv);
466struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index);
467struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index);
468extern void atombios_external_tmds_setup(struct drm_encoder *encoder, int action);
32f48ffe 469extern void atombios_digital_setup(struct drm_encoder *encoder, int action);
771fe6b9 470extern int atombios_get_encoder_mode(struct drm_encoder *encoder);
4ce001ab 471extern void radeon_encoder_set_active_device(struct drm_encoder *encoder);
771fe6b9
JG		 472
473extern void radeon_crtc_load_lut(struct drm_crtc *crtc);
474extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
475 struct drm_framebuffer *old_fb);
476extern int atombios_crtc_mode_set(struct drm_crtc *crtc,
477 struct drm_display_mode *mode,
478 struct drm_display_mode *adjusted_mode,
479 int x, int y,
480 struct drm_framebuffer *old_fb);
481extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode);
482
483extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
484 struct drm_framebuffer *old_fb);
771fe6b9
JG		 485
486extern int radeon_crtc_cursor_set(struct drm_crtc *crtc,
487 struct drm_file *file_priv,
488 uint32_t handle,
489 uint32_t width,
490 uint32_t height);
491extern int radeon_crtc_cursor_move(struct drm_crtc *crtc,
492 int x, int y);
493
3c537889
AD		 494extern bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev);
495extern struct edid *
496radeon_combios_get_hardcoded_edid(struct radeon_device *rdev);
771fe6b9
JG		 497extern bool radeon_atom_get_clock_info(struct drm_device *dev);
498extern bool radeon_combios_get_clock_info(struct drm_device *dev);
499extern struct radeon_encoder_atom_dig *
500radeon_atombios_get_lvds_info(struct radeon_encoder *encoder);
fcec570b
AD		 501extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
502 struct radeon_encoder_int_tmds *tmds);
503extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
504 struct radeon_encoder_int_tmds *tmds);
505extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
506 struct radeon_encoder_int_tmds *tmds);
507extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
508 struct radeon_encoder_ext_tmds *tmds);
509extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
510 struct radeon_encoder_ext_tmds *tmds);
6fe7ac3f
AD		 511extern struct radeon_encoder_primary_dac *
512radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder);
513extern struct radeon_encoder_tv_dac *
514radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder);
771fe6b9
JG		 515extern struct radeon_encoder_lvds *
516radeon_combios_get_lvds_info(struct radeon_encoder *encoder);
771fe6b9
JG		 517extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder);
518extern struct radeon_encoder_tv_dac *
519radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder);
520extern struct radeon_encoder_primary_dac *
521radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder);
fcec570b
AD		 522extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder);
523extern void radeon_external_tmds_setup(struct drm_encoder *encoder);
771fe6b9
JG		 524extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock);
525extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev);
526extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock);
527extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev);
f657c2a7
YZ		 528extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev);
529extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev);
771fe6b9
JG		 530extern void
531radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
532extern void
533radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
534extern void
535radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
536extern void
537radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
538extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
539 u16 blue, int regno);
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DA		 540extern void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
541 u16 *blue, int regno);
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DA		 542void radeon_framebuffer_init(struct drm_device *dev,
543 struct radeon_framebuffer *rfb,
544 struct drm_mode_fb_cmd *mode_cmd,
545 struct drm_gem_object *obj);
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JG		 546
547int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb);
548bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev);
549bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev);
550void radeon_atombios_init_crtc(struct drm_device *dev,
551 struct radeon_crtc *radeon_crtc);
552void radeon_legacy_init_crtc(struct drm_device *dev,
553 struct radeon_crtc *radeon_crtc);
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JG		 554
555void radeon_get_clock_info(struct drm_device *dev);
556
557extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev);
558extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev);
559
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JG		 560void radeon_enc_destroy(struct drm_encoder *encoder);
561void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj);
562void radeon_combios_asic_init(struct drm_device *dev);
563extern int radeon_static_clocks_init(struct drm_device *dev);
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JG		 564bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
565 struct drm_display_mode *mode,
566 struct drm_display_mode *adjusted_mode);
4ce001ab
DA		 567void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc);
568
569/* legacy tv */
570void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder,
571 uint32_t *h_total_disp, uint32_t *h_sync_strt_wid,
572 uint32_t *v_total_disp, uint32_t *v_sync_strt_wid);
573void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder,
574 uint32_t *htotal_cntl, uint32_t *ppll_ref_div,
575 uint32_t *ppll_div_3, uint32_t *pixclks_cntl);
576void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder,
577 uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div,
578 uint32_t *p2pll_div_0, uint32_t *pixclks_cntl);
579void radeon_legacy_tv_mode_set(struct drm_encoder *encoder,
580 struct drm_display_mode *mode,
581 struct drm_display_mode *adjusted_mode);
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DA		 582
583/* fbdev layer */
584int radeon_fbdev_init(struct radeon_device *rdev);
585void radeon_fbdev_fini(struct radeon_device *rdev);
586void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state);
587int radeon_fbdev_total_size(struct radeon_device *rdev);
588bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj);
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DA		 589
590void radeon_fb_output_poll_changed(struct radeon_device *rdev);
771fe6b9 591#endif
Clone of davem's net-next-2.6 tree