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drm/radeon/kms: don't fail if we fail to init GPU acceleration
[net-next-2.6.git] / drivers / gpu / drm / radeon / radeon_kms.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include "drmP.h"
29#include "drm_sarea.h"
30#include "radeon.h"
31#include "radeon_drm.h"
32
33
34/*
35 * Driver load/unload
36 */
37int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
38{
39 struct radeon_device *rdev;
40 int r;
41
42 rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL);
43 if (rdev == NULL) {
44 return -ENOMEM;
45 }
46 dev->dev_private = (void *)rdev;
47
48 /* update BUS flag */
49 if (drm_device_is_agp(dev)) {
50 flags |= RADEON_IS_AGP;
51 } else if (drm_device_is_pcie(dev)) {
52 flags |= RADEON_IS_PCIE;
53 } else {
54 flags |= RADEON_IS_PCI;
55 }
56
6cf8a3f5
JG		 57 /* radeon_device_init should report only fatal error
58 * like memory allocation failure or iomapping failure,
59 * or memory manager initialization failure, it must
60 * properly initialize the GPU MC controller and permit
61 * VRAM allocation
62 */
771fe6b9
JG		 63 r = radeon_device_init(rdev, dev, dev->pdev, flags);
64 if (r) {
6cf8a3f5
JG		 65 DRM_ERROR("Fatal error while trying to initialize radeon.\n");
66 return r;
67 }
68 /* Again modeset_init should fail only on fatal error
69 * otherwise it should provide enough functionalities
70 * for shadowfb to run
71 */
72 r = radeon_modeset_init(rdev);
73 if (r) {
771fe6b9
JG		 74 return r;
75 }
76 return 0;
77}
78
79int radeon_driver_unload_kms(struct drm_device *dev)
80{
81 struct radeon_device *rdev = dev->dev_private;
82
6cf8a3f5
JG		 83 if (rdev == NULL)
84 return 0;
85 radeon_modeset_fini(rdev);
771fe6b9
JG		 86 radeon_device_fini(rdev);
87 kfree(rdev);
88 dev->dev_private = NULL;
89 return 0;
90}
91
92
93/*
94 * Userspace get informations ioctl
95 */
96int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
97{
98 struct radeon_device *rdev = dev->dev_private;
99 struct drm_radeon_info *info;
100 uint32_t *value_ptr;
101 uint32_t value;
102
103 info = data;
104 value_ptr = (uint32_t *)((unsigned long)info->value);
105 switch (info->request) {
106 case RADEON_INFO_DEVICE_ID:
107 value = dev->pci_device;
108 break;
109 case RADEON_INFO_NUM_GB_PIPES:
110 value = rdev->num_gb_pipes;
111 break;
f779b3e5
AD		 112 case RADEON_INFO_NUM_Z_PIPES:
113 value = rdev->num_z_pipes;
114 break;
733289c2
JG		 115 case RADEON_INFO_ACCEL_WORKING:
116 value = rdev->accel_working;
117 break;
771fe6b9
JG		 118 default:
119 DRM_DEBUG("Invalid request %d\n", info->request);
120 return -EINVAL;
121 }
122 if (DRM_COPY_TO_USER(value_ptr, &value, sizeof(uint32_t))) {
123 DRM_ERROR("copy_to_user\n");
124 return -EFAULT;
125 }
126 return 0;
127}
128
129
130/*
131 * Outdated mess for old drm with Xorg being in charge (void function now).
132 */
133int radeon_driver_firstopen_kms(struct drm_device *dev)
134{
135 return 0;
136}
137
138
139void radeon_driver_lastclose_kms(struct drm_device *dev)
140{
141}
142
143int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
144{
145 return 0;
146}
147
148void radeon_driver_postclose_kms(struct drm_device *dev,
149 struct drm_file *file_priv)
150{
151}
152
153void radeon_driver_preclose_kms(struct drm_device *dev,
154 struct drm_file *file_priv)
155{
156}
157
158
159/*
160 * VBlank related functions.
161 */
162u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc)
163{
7ed220d7
MD		 164 struct radeon_device *rdev = dev->dev_private;
165
166 if (crtc < 0 || crtc > 1) {
167 DRM_ERROR("Invalid crtc %d\n", crtc);
168 return -EINVAL;
169 }
170
171 return radeon_get_vblank_counter(rdev, crtc);
771fe6b9
JG		 172}
173
174int radeon_enable_vblank_kms(struct drm_device *dev, int crtc)
175{
7ed220d7
MD		 176 struct radeon_device *rdev = dev->dev_private;
177
178 if (crtc < 0 || crtc > 1) {
179 DRM_ERROR("Invalid crtc %d\n", crtc);
180 return -EINVAL;
181 }
182
183 rdev->irq.crtc_vblank_int[crtc] = true;
184
185 return radeon_irq_set(rdev);
771fe6b9
JG		 186}
187
188void radeon_disable_vblank_kms(struct drm_device *dev, int crtc)
189{
7ed220d7
MD		 190 struct radeon_device *rdev = dev->dev_private;
191
192 if (crtc < 0 || crtc > 1) {
193 DRM_ERROR("Invalid crtc %d\n", crtc);
194 return;
195 }
196
197 rdev->irq.crtc_vblank_int[crtc] = false;
198
199 radeon_irq_set(rdev);
771fe6b9
JG		 200}
201
202
203/*
204 * For multiple master (like multiple X).
205 */
206struct drm_radeon_master_private {
207 drm_local_map_t *sarea;
208 drm_radeon_sarea_t *sarea_priv;
209};
210
211int radeon_master_create_kms(struct drm_device *dev, struct drm_master *master)
212{
213 struct drm_radeon_master_private *master_priv;
214 unsigned long sareapage;
215 int ret;
216
9a298b2a 217 master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
771fe6b9
JG		 218 if (master_priv == NULL) {
219 return -ENOMEM;
220 }
221 /* prebuild the SAREA */
222 sareapage = max_t(unsigned long, SAREA_MAX, PAGE_SIZE);
223 ret = drm_addmap(dev, 0, sareapage, _DRM_SHM,
3b47883d 224 _DRM_CONTAINS_LOCK,
771fe6b9
JG		 225 &master_priv->sarea);
226 if (ret) {
227 DRM_ERROR("SAREA setup failed\n");
228 return ret;
229 }
230 master_priv->sarea_priv = master_priv->sarea->handle + sizeof(struct drm_sarea);
231 master_priv->sarea_priv->pfCurrentPage = 0;
232 master->driver_priv = master_priv;
233 return 0;
234}
235
236void radeon_master_destroy_kms(struct drm_device *dev,
237 struct drm_master *master)
238{
239 struct drm_radeon_master_private *master_priv = master->driver_priv;
240
241 if (master_priv == NULL) {
242 return;
243 }
244 if (master_priv->sarea) {
245 drm_rmmap_locked(dev, master_priv->sarea);
246 }
9a298b2a 247 kfree(master_priv);
771fe6b9
JG		 248 master->driver_priv = NULL;
249}
250
251
252/*
253 * IOCTL.
254 */
255int radeon_dma_ioctl_kms(struct drm_device *dev, void *data,
256 struct drm_file *file_priv)
257{
258 /* Not valid in KMS. */
259 return -EINVAL;
260}
261
262#define KMS_INVALID_IOCTL(name) \
263int name(struct drm_device *dev, void *data, struct drm_file *file_priv)\
264{ \
265 DRM_ERROR("invalid ioctl with kms %s\n", __func__); \
266 return -EINVAL; \
267}
268
269/*
270 * All these ioctls are invalid in kms world.
271 */
272KMS_INVALID_IOCTL(radeon_cp_init_kms)
273KMS_INVALID_IOCTL(radeon_cp_start_kms)
274KMS_INVALID_IOCTL(radeon_cp_stop_kms)
275KMS_INVALID_IOCTL(radeon_cp_reset_kms)
276KMS_INVALID_IOCTL(radeon_cp_idle_kms)
277KMS_INVALID_IOCTL(radeon_cp_resume_kms)
278KMS_INVALID_IOCTL(radeon_engine_reset_kms)
279KMS_INVALID_IOCTL(radeon_fullscreen_kms)
280KMS_INVALID_IOCTL(radeon_cp_swap_kms)
281KMS_INVALID_IOCTL(radeon_cp_clear_kms)
282KMS_INVALID_IOCTL(radeon_cp_vertex_kms)
283KMS_INVALID_IOCTL(radeon_cp_indices_kms)
284KMS_INVALID_IOCTL(radeon_cp_texture_kms)
285KMS_INVALID_IOCTL(radeon_cp_stipple_kms)
286KMS_INVALID_IOCTL(radeon_cp_indirect_kms)
287KMS_INVALID_IOCTL(radeon_cp_vertex2_kms)
288KMS_INVALID_IOCTL(radeon_cp_cmdbuf_kms)
289KMS_INVALID_IOCTL(radeon_cp_getparam_kms)
290KMS_INVALID_IOCTL(radeon_cp_flip_kms)
291KMS_INVALID_IOCTL(radeon_mem_alloc_kms)
292KMS_INVALID_IOCTL(radeon_mem_free_kms)
293KMS_INVALID_IOCTL(radeon_mem_init_heap_kms)
294KMS_INVALID_IOCTL(radeon_irq_emit_kms)
295KMS_INVALID_IOCTL(radeon_irq_wait_kms)
296KMS_INVALID_IOCTL(radeon_cp_setparam_kms)
297KMS_INVALID_IOCTL(radeon_surface_alloc_kms)
298KMS_INVALID_IOCTL(radeon_surface_free_kms)
299
300
301struct drm_ioctl_desc radeon_ioctls_kms[] = {
302 DRM_IOCTL_DEF(DRM_RADEON_CP_INIT, radeon_cp_init_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
303 DRM_IOCTL_DEF(DRM_RADEON_CP_START, radeon_cp_start_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
304 DRM_IOCTL_DEF(DRM_RADEON_CP_STOP, radeon_cp_stop_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
305 DRM_IOCTL_DEF(DRM_RADEON_CP_RESET, radeon_cp_reset_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
306 DRM_IOCTL_DEF(DRM_RADEON_CP_IDLE, radeon_cp_idle_kms, DRM_AUTH),
307 DRM_IOCTL_DEF(DRM_RADEON_CP_RESUME, radeon_cp_resume_kms, DRM_AUTH),
308 DRM_IOCTL_DEF(DRM_RADEON_RESET, radeon_engine_reset_kms, DRM_AUTH),
309 DRM_IOCTL_DEF(DRM_RADEON_FULLSCREEN, radeon_fullscreen_kms, DRM_AUTH),
310 DRM_IOCTL_DEF(DRM_RADEON_SWAP, radeon_cp_swap_kms, DRM_AUTH),
311 DRM_IOCTL_DEF(DRM_RADEON_CLEAR, radeon_cp_clear_kms, DRM_AUTH),
312 DRM_IOCTL_DEF(DRM_RADEON_VERTEX, radeon_cp_vertex_kms, DRM_AUTH),
313 DRM_IOCTL_DEF(DRM_RADEON_INDICES, radeon_cp_indices_kms, DRM_AUTH),
314 DRM_IOCTL_DEF(DRM_RADEON_TEXTURE, radeon_cp_texture_kms, DRM_AUTH),
315 DRM_IOCTL_DEF(DRM_RADEON_STIPPLE, radeon_cp_stipple_kms, DRM_AUTH),
316 DRM_IOCTL_DEF(DRM_RADEON_INDIRECT, radeon_cp_indirect_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
317 DRM_IOCTL_DEF(DRM_RADEON_VERTEX2, radeon_cp_vertex2_kms, DRM_AUTH),
318 DRM_IOCTL_DEF(DRM_RADEON_CMDBUF, radeon_cp_cmdbuf_kms, DRM_AUTH),
319 DRM_IOCTL_DEF(DRM_RADEON_GETPARAM, radeon_cp_getparam_kms, DRM_AUTH),
320 DRM_IOCTL_DEF(DRM_RADEON_FLIP, radeon_cp_flip_kms, DRM_AUTH),
321 DRM_IOCTL_DEF(DRM_RADEON_ALLOC, radeon_mem_alloc_kms, DRM_AUTH),
322 DRM_IOCTL_DEF(DRM_RADEON_FREE, radeon_mem_free_kms, DRM_AUTH),
323 DRM_IOCTL_DEF(DRM_RADEON_INIT_HEAP, radeon_mem_init_heap_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
324 DRM_IOCTL_DEF(DRM_RADEON_IRQ_EMIT, radeon_irq_emit_kms, DRM_AUTH),
325 DRM_IOCTL_DEF(DRM_RADEON_IRQ_WAIT, radeon_irq_wait_kms, DRM_AUTH),
326 DRM_IOCTL_DEF(DRM_RADEON_SETPARAM, radeon_cp_setparam_kms, DRM_AUTH),
327 DRM_IOCTL_DEF(DRM_RADEON_SURF_ALLOC, radeon_surface_alloc_kms, DRM_AUTH),
328 DRM_IOCTL_DEF(DRM_RADEON_SURF_FREE, radeon_surface_free_kms, DRM_AUTH),
329 /* KMS */
330 DRM_IOCTL_DEF(DRM_RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH),
331 DRM_IOCTL_DEF(DRM_RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH),
332 DRM_IOCTL_DEF(DRM_RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH),
333 DRM_IOCTL_DEF(DRM_RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH),
334 DRM_IOCTL_DEF(DRM_RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH),
335 DRM_IOCTL_DEF(DRM_RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH),
336 DRM_IOCTL_DEF(DRM_RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH),
337 DRM_IOCTL_DEF(DRM_RADEON_CS, radeon_cs_ioctl, DRM_AUTH),
338 DRM_IOCTL_DEF(DRM_RADEON_INFO, radeon_info_ioctl, DRM_AUTH),
e024e110
DA		 339 DRM_IOCTL_DEF(DRM_RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH),
340 DRM_IOCTL_DEF(DRM_RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH),
e3b2415e 341 DRM_IOCTL_DEF(DRM_RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH),
771fe6b9
JG		 342};
343int radeon_max_kms_ioctl = DRM_ARRAY_SIZE(radeon_ioctls_kms);
Clone of davem's net-next-2.6 tree