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771fe6b9 JG |
1 | /* |
2 | * Copyright 2009 Jerome Glisse. | |
3 | * All Rights Reserved. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the | |
7 | * "Software"), to deal in the Software without restriction, including | |
8 | * without limitation the rights to use, copy, modify, merge, publish, | |
9 | * distribute, sub license, and/or sell copies of the Software, and to | |
10 | * permit persons to whom the Software is furnished to do so, subject to | |
11 | * the following conditions: | |
12 | * | |
13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
14 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
15 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL | |
16 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, | |
17 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR | |
18 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE | |
19 | * USE OR OTHER DEALINGS IN THE SOFTWARE. | |
20 | * | |
21 | * The above copyright notice and this permission notice (including the | |
22 | * next paragraph) shall be included in all copies or substantial portions | |
23 | * of the Software. | |
24 | * | |
25 | */ | |
26 | /* | |
27 | * Authors: | |
28 | * Jerome Glisse <glisse@freedesktop.org> | |
29 | * Dave Airlie | |
30 | */ | |
31 | #include <linux/seq_file.h> | |
32 | #include <asm/atomic.h> | |
33 | #include <linux/wait.h> | |
34 | #include <linux/list.h> | |
35 | #include <linux/kref.h> | |
5a0e3ad6 | 36 | #include <linux/slab.h> |
771fe6b9 JG |
37 | #include "drmP.h" |
38 | #include "drm.h" | |
39 | #include "radeon_reg.h" | |
40 | #include "radeon.h" | |
41 | ||
42 | int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence) | |
43 | { | |
44 | unsigned long irq_flags; | |
45 | ||
46 | write_lock_irqsave(&rdev->fence_drv.lock, irq_flags); | |
47 | if (fence->emited) { | |
48 | write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags); | |
49 | return 0; | |
50 | } | |
51 | fence->seq = atomic_add_return(1, &rdev->fence_drv.seq); | |
52 | if (!rdev->cp.ready) { | |
53 | /* FIXME: cp is not running assume everythings is done right | |
54 | * away | |
55 | */ | |
56 | WREG32(rdev->fence_drv.scratch_reg, fence->seq); | |
3ce0a23d | 57 | } else |
771fe6b9 | 58 | radeon_fence_ring_emit(rdev, fence); |
3ce0a23d | 59 | |
771fe6b9 | 60 | fence->emited = true; |
771fe6b9 JG |
61 | list_del(&fence->list); |
62 | list_add_tail(&fence->list, &rdev->fence_drv.emited); | |
63 | write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags); | |
64 | return 0; | |
65 | } | |
66 | ||
67 | static bool radeon_fence_poll_locked(struct radeon_device *rdev) | |
68 | { | |
69 | struct radeon_fence *fence; | |
70 | struct list_head *i, *n; | |
71 | uint32_t seq; | |
72 | bool wake = false; | |
225758d8 | 73 | unsigned long cjiffies; |
771fe6b9 | 74 | |
724c80e1 | 75 | if (rdev->wb.enabled) { |
d0f8a854 AD |
76 | u32 scratch_index; |
77 | if (rdev->wb.use_event) | |
78 | scratch_index = R600_WB_EVENT_OFFSET + rdev->fence_drv.scratch_reg - rdev->scratch.reg_base; | |
79 | else | |
80 | scratch_index = RADEON_WB_SCRATCH_OFFSET + rdev->fence_drv.scratch_reg - rdev->scratch.reg_base; | |
724c80e1 AD |
81 | seq = rdev->wb.wb[scratch_index/4]; |
82 | } else | |
83 | seq = RREG32(rdev->fence_drv.scratch_reg); | |
225758d8 JG |
84 | if (seq != rdev->fence_drv.last_seq) { |
85 | rdev->fence_drv.last_seq = seq; | |
86 | rdev->fence_drv.last_jiffies = jiffies; | |
87 | rdev->fence_drv.last_timeout = RADEON_FENCE_JIFFIES_TIMEOUT; | |
88 | } else { | |
89 | cjiffies = jiffies; | |
90 | if (time_after(cjiffies, rdev->fence_drv.last_jiffies)) { | |
91 | cjiffies -= rdev->fence_drv.last_jiffies; | |
92 | if (time_after(rdev->fence_drv.last_timeout, cjiffies)) { | |
93 | /* update the timeout */ | |
94 | rdev->fence_drv.last_timeout -= cjiffies; | |
95 | } else { | |
96 | /* the 500ms timeout is elapsed we should test | |
97 | * for GPU lockup | |
98 | */ | |
99 | rdev->fence_drv.last_timeout = 1; | |
100 | } | |
101 | } else { | |
102 | /* wrap around update last jiffies, we will just wait | |
103 | * a little longer | |
104 | */ | |
105 | rdev->fence_drv.last_jiffies = cjiffies; | |
106 | } | |
107 | return false; | |
108 | } | |
771fe6b9 JG |
109 | n = NULL; |
110 | list_for_each(i, &rdev->fence_drv.emited) { | |
111 | fence = list_entry(i, struct radeon_fence, list); | |
112 | if (fence->seq == seq) { | |
113 | n = i; | |
114 | break; | |
115 | } | |
116 | } | |
117 | /* all fence previous to this one are considered as signaled */ | |
118 | if (n) { | |
119 | i = n; | |
120 | do { | |
121 | n = i->prev; | |
122 | list_del(i); | |
123 | list_add_tail(i, &rdev->fence_drv.signaled); | |
124 | fence = list_entry(i, struct radeon_fence, list); | |
125 | fence->signaled = true; | |
126 | i = n; | |
127 | } while (i != &rdev->fence_drv.emited); | |
128 | wake = true; | |
129 | } | |
130 | return wake; | |
131 | } | |
132 | ||
133 | static void radeon_fence_destroy(struct kref *kref) | |
134 | { | |
135 | unsigned long irq_flags; | |
136 | struct radeon_fence *fence; | |
137 | ||
138 | fence = container_of(kref, struct radeon_fence, kref); | |
139 | write_lock_irqsave(&fence->rdev->fence_drv.lock, irq_flags); | |
140 | list_del(&fence->list); | |
141 | fence->emited = false; | |
142 | write_unlock_irqrestore(&fence->rdev->fence_drv.lock, irq_flags); | |
143 | kfree(fence); | |
144 | } | |
145 | ||
146 | int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence) | |
147 | { | |
148 | unsigned long irq_flags; | |
149 | ||
150 | *fence = kmalloc(sizeof(struct radeon_fence), GFP_KERNEL); | |
151 | if ((*fence) == NULL) { | |
152 | return -ENOMEM; | |
153 | } | |
154 | kref_init(&((*fence)->kref)); | |
155 | (*fence)->rdev = rdev; | |
156 | (*fence)->emited = false; | |
157 | (*fence)->signaled = false; | |
158 | (*fence)->seq = 0; | |
159 | INIT_LIST_HEAD(&(*fence)->list); | |
160 | ||
161 | write_lock_irqsave(&rdev->fence_drv.lock, irq_flags); | |
162 | list_add_tail(&(*fence)->list, &rdev->fence_drv.created); | |
163 | write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags); | |
164 | return 0; | |
165 | } | |
166 | ||
167 | ||
168 | bool radeon_fence_signaled(struct radeon_fence *fence) | |
169 | { | |
771fe6b9 JG |
170 | unsigned long irq_flags; |
171 | bool signaled = false; | |
172 | ||
3655d54a | 173 | if (!fence) |
771fe6b9 | 174 | return true; |
3655d54a DJ |
175 | |
176 | if (fence->rdev->gpu_lockup) | |
771fe6b9 | 177 | return true; |
3655d54a | 178 | |
771fe6b9 JG |
179 | write_lock_irqsave(&fence->rdev->fence_drv.lock, irq_flags); |
180 | signaled = fence->signaled; | |
181 | /* if we are shuting down report all fence as signaled */ | |
182 | if (fence->rdev->shutdown) { | |
183 | signaled = true; | |
184 | } | |
185 | if (!fence->emited) { | |
186 | WARN(1, "Querying an unemited fence : %p !\n", fence); | |
187 | signaled = true; | |
188 | } | |
189 | if (!signaled) { | |
190 | radeon_fence_poll_locked(fence->rdev); | |
191 | signaled = fence->signaled; | |
192 | } | |
193 | write_unlock_irqrestore(&fence->rdev->fence_drv.lock, irq_flags); | |
194 | return signaled; | |
195 | } | |
196 | ||
3ce0a23d | 197 | int radeon_fence_wait(struct radeon_fence *fence, bool intr) |
771fe6b9 JG |
198 | { |
199 | struct radeon_device *rdev; | |
225758d8 JG |
200 | unsigned long irq_flags, timeout; |
201 | u32 seq; | |
771fe6b9 JG |
202 | int r; |
203 | ||
771fe6b9 JG |
204 | if (fence == NULL) { |
205 | WARN(1, "Querying an invalid fence : %p !\n", fence); | |
206 | return 0; | |
207 | } | |
208 | rdev = fence->rdev; | |
209 | if (radeon_fence_signaled(fence)) { | |
210 | return 0; | |
211 | } | |
225758d8 | 212 | timeout = rdev->fence_drv.last_timeout; |
771fe6b9 | 213 | retry: |
225758d8 JG |
214 | /* save current sequence used to check for GPU lockup */ |
215 | seq = rdev->fence_drv.last_seq; | |
3ce0a23d | 216 | if (intr) { |
1614f8b1 | 217 | radeon_irq_kms_sw_irq_get(rdev); |
771fe6b9 JG |
218 | r = wait_event_interruptible_timeout(rdev->fence_drv.queue, |
219 | radeon_fence_signaled(fence), timeout); | |
1614f8b1 | 220 | radeon_irq_kms_sw_irq_put(rdev); |
90aca4d2 | 221 | if (unlikely(r < 0)) { |
5cc6fbab | 222 | return r; |
90aca4d2 | 223 | } |
771fe6b9 | 224 | } else { |
1614f8b1 | 225 | radeon_irq_kms_sw_irq_get(rdev); |
771fe6b9 JG |
226 | r = wait_event_timeout(rdev->fence_drv.queue, |
227 | radeon_fence_signaled(fence), timeout); | |
1614f8b1 | 228 | radeon_irq_kms_sw_irq_put(rdev); |
771fe6b9 JG |
229 | } |
230 | if (unlikely(!radeon_fence_signaled(fence))) { | |
225758d8 JG |
231 | /* we were interrupted for some reason and fence isn't |
232 | * isn't signaled yet, resume wait | |
233 | */ | |
234 | if (r) { | |
235 | timeout = r; | |
236 | goto retry; | |
771fe6b9 | 237 | } |
225758d8 JG |
238 | /* don't protect read access to rdev->fence_drv.last_seq |
239 | * if we experiencing a lockup the value doesn't change | |
240 | */ | |
241 | if (seq == rdev->fence_drv.last_seq && radeon_gpu_is_lockup(rdev)) { | |
242 | /* good news we believe it's a lockup */ | |
90aca4d2 | 243 | WARN(1, "GPU lockup (waiting for 0x%08X last fence id 0x%08X)\n", fence->seq, seq); |
225758d8 JG |
244 | /* FIXME: what should we do ? marking everyone |
245 | * as signaled for now | |
246 | */ | |
90aca4d2 | 247 | rdev->gpu_lockup = true; |
90aca4d2 JG |
248 | r = radeon_gpu_reset(rdev); |
249 | if (r) | |
250 | return r; | |
a1e9ada3 | 251 | WREG32(rdev->fence_drv.scratch_reg, fence->seq); |
90aca4d2 | 252 | rdev->gpu_lockup = false; |
771fe6b9 | 253 | } |
225758d8 JG |
254 | timeout = RADEON_FENCE_JIFFIES_TIMEOUT; |
255 | write_lock_irqsave(&rdev->fence_drv.lock, irq_flags); | |
256 | rdev->fence_drv.last_timeout = RADEON_FENCE_JIFFIES_TIMEOUT; | |
257 | rdev->fence_drv.last_jiffies = jiffies; | |
258 | write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags); | |
771fe6b9 JG |
259 | goto retry; |
260 | } | |
771fe6b9 JG |
261 | return 0; |
262 | } | |
263 | ||
264 | int radeon_fence_wait_next(struct radeon_device *rdev) | |
265 | { | |
266 | unsigned long irq_flags; | |
267 | struct radeon_fence *fence; | |
268 | int r; | |
269 | ||
270 | if (rdev->gpu_lockup) { | |
271 | return 0; | |
272 | } | |
273 | write_lock_irqsave(&rdev->fence_drv.lock, irq_flags); | |
274 | if (list_empty(&rdev->fence_drv.emited)) { | |
275 | write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags); | |
276 | return 0; | |
277 | } | |
278 | fence = list_entry(rdev->fence_drv.emited.next, | |
279 | struct radeon_fence, list); | |
280 | radeon_fence_ref(fence); | |
281 | write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags); | |
282 | r = radeon_fence_wait(fence, false); | |
283 | radeon_fence_unref(&fence); | |
284 | return r; | |
285 | } | |
286 | ||
287 | int radeon_fence_wait_last(struct radeon_device *rdev) | |
288 | { | |
289 | unsigned long irq_flags; | |
290 | struct radeon_fence *fence; | |
291 | int r; | |
292 | ||
293 | if (rdev->gpu_lockup) { | |
294 | return 0; | |
295 | } | |
296 | write_lock_irqsave(&rdev->fence_drv.lock, irq_flags); | |
297 | if (list_empty(&rdev->fence_drv.emited)) { | |
298 | write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags); | |
299 | return 0; | |
300 | } | |
301 | fence = list_entry(rdev->fence_drv.emited.prev, | |
302 | struct radeon_fence, list); | |
303 | radeon_fence_ref(fence); | |
304 | write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags); | |
305 | r = radeon_fence_wait(fence, false); | |
306 | radeon_fence_unref(&fence); | |
307 | return r; | |
308 | } | |
309 | ||
310 | struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence) | |
311 | { | |
312 | kref_get(&fence->kref); | |
313 | return fence; | |
314 | } | |
315 | ||
316 | void radeon_fence_unref(struct radeon_fence **fence) | |
317 | { | |
318 | struct radeon_fence *tmp = *fence; | |
319 | ||
320 | *fence = NULL; | |
321 | if (tmp) { | |
322 | kref_put(&tmp->kref, &radeon_fence_destroy); | |
323 | } | |
324 | } | |
325 | ||
326 | void radeon_fence_process(struct radeon_device *rdev) | |
327 | { | |
328 | unsigned long irq_flags; | |
329 | bool wake; | |
330 | ||
331 | write_lock_irqsave(&rdev->fence_drv.lock, irq_flags); | |
332 | wake = radeon_fence_poll_locked(rdev); | |
333 | write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags); | |
334 | if (wake) { | |
335 | wake_up_all(&rdev->fence_drv.queue); | |
336 | } | |
337 | } | |
338 | ||
339 | int radeon_fence_driver_init(struct radeon_device *rdev) | |
340 | { | |
341 | unsigned long irq_flags; | |
342 | int r; | |
343 | ||
344 | write_lock_irqsave(&rdev->fence_drv.lock, irq_flags); | |
345 | r = radeon_scratch_get(rdev, &rdev->fence_drv.scratch_reg); | |
346 | if (r) { | |
0a0c7596 | 347 | dev_err(rdev->dev, "fence failed to get scratch register\n"); |
771fe6b9 JG |
348 | write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags); |
349 | return r; | |
350 | } | |
351 | WREG32(rdev->fence_drv.scratch_reg, 0); | |
352 | atomic_set(&rdev->fence_drv.seq, 0); | |
353 | INIT_LIST_HEAD(&rdev->fence_drv.created); | |
354 | INIT_LIST_HEAD(&rdev->fence_drv.emited); | |
355 | INIT_LIST_HEAD(&rdev->fence_drv.signaled); | |
771fe6b9 | 356 | init_waitqueue_head(&rdev->fence_drv.queue); |
0a0c7596 | 357 | rdev->fence_drv.initialized = true; |
771fe6b9 JG |
358 | write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags); |
359 | if (radeon_debugfs_fence_init(rdev)) { | |
0a0c7596 | 360 | dev_err(rdev->dev, "fence debugfs file creation failed\n"); |
771fe6b9 JG |
361 | } |
362 | return 0; | |
363 | } | |
364 | ||
365 | void radeon_fence_driver_fini(struct radeon_device *rdev) | |
366 | { | |
367 | unsigned long irq_flags; | |
368 | ||
0a0c7596 JG |
369 | if (!rdev->fence_drv.initialized) |
370 | return; | |
771fe6b9 JG |
371 | wake_up_all(&rdev->fence_drv.queue); |
372 | write_lock_irqsave(&rdev->fence_drv.lock, irq_flags); | |
373 | radeon_scratch_free(rdev, rdev->fence_drv.scratch_reg); | |
374 | write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags); | |
0a0c7596 | 375 | rdev->fence_drv.initialized = false; |
771fe6b9 JG |
376 | } |
377 | ||
378 | ||
379 | /* | |
380 | * Fence debugfs | |
381 | */ | |
382 | #if defined(CONFIG_DEBUG_FS) | |
383 | static int radeon_debugfs_fence_info(struct seq_file *m, void *data) | |
384 | { | |
385 | struct drm_info_node *node = (struct drm_info_node *)m->private; | |
386 | struct drm_device *dev = node->minor->dev; | |
387 | struct radeon_device *rdev = dev->dev_private; | |
388 | struct radeon_fence *fence; | |
389 | ||
390 | seq_printf(m, "Last signaled fence 0x%08X\n", | |
391 | RREG32(rdev->fence_drv.scratch_reg)); | |
392 | if (!list_empty(&rdev->fence_drv.emited)) { | |
393 | fence = list_entry(rdev->fence_drv.emited.prev, | |
394 | struct radeon_fence, list); | |
395 | seq_printf(m, "Last emited fence %p with 0x%08X\n", | |
396 | fence, fence->seq); | |
397 | } | |
398 | return 0; | |
399 | } | |
400 | ||
401 | static struct drm_info_list radeon_debugfs_fence_list[] = { | |
402 | {"radeon_fence_info", &radeon_debugfs_fence_info, 0, NULL}, | |
403 | }; | |
404 | #endif | |
405 | ||
406 | int radeon_debugfs_fence_init(struct radeon_device *rdev) | |
407 | { | |
408 | #if defined(CONFIG_DEBUG_FS) | |
409 | return radeon_debugfs_add_files(rdev, radeon_debugfs_fence_list, 1); | |
410 | #else | |
411 | return 0; | |
412 | #endif | |
413 | } |