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Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6
[net-next-2.6.git] / drivers / gpu / drm / radeon / radeon_encoders.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26#include "drmP.h"
27#include "drm_crtc_helper.h"
28#include "radeon_drm.h"
29#include "radeon.h"
30#include "atom.h"
31
32extern int atom_debug;
33
5a9bcacc
AD		 34/* evil but including atombios.h is much worse */
35bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
36 struct drm_display_mode *mode);
37
1f3b6a45
DA		 38static uint32_t radeon_encoder_clones(struct drm_encoder *encoder)
39{
40 struct drm_device *dev = encoder->dev;
41 struct radeon_device *rdev = dev->dev_private;
42 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
43 struct drm_encoder *clone_encoder;
44 uint32_t index_mask = 0;
45 int count;
46
47 /* DIG routing gets problematic */
48 if (rdev->family >= CHIP_R600)
49 return index_mask;
50 /* LVDS/TV are too wacky */
51 if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
52 return index_mask;
53 /* DVO requires 2x ppll clocks depending on tmds chip */
54 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT)
55 return index_mask;
bcc1c2a1 56
1f3b6a45
DA		 57 count = -1;
58 list_for_each_entry(clone_encoder, &dev->mode_config.encoder_list, head) {
59 struct radeon_encoder *radeon_clone = to_radeon_encoder(clone_encoder);
60 count++;
61
62 if (clone_encoder == encoder)
63 continue;
64 if (radeon_clone->devices & (ATOM_DEVICE_LCD_SUPPORT))
65 continue;
66 if (radeon_clone->devices & ATOM_DEVICE_DFP2_SUPPORT)
67 continue;
68 else
69 index_mask |= (1 << count);
70 }
71 return index_mask;
72}
73
74void radeon_setup_encoder_clones(struct drm_device *dev)
75{
76 struct drm_encoder *encoder;
77
78 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
79 encoder->possible_clones = radeon_encoder_clones(encoder);
80 }
81}
82
771fe6b9 83uint32_t
5137ee94 84radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device, uint8_t dac)
771fe6b9
JG		 85{
86 struct radeon_device *rdev = dev->dev_private;
87 uint32_t ret = 0;
88
89 switch (supported_device) {
90 case ATOM_DEVICE_CRT1_SUPPORT:
91 case ATOM_DEVICE_TV1_SUPPORT:
92 case ATOM_DEVICE_TV2_SUPPORT:
93 case ATOM_DEVICE_CRT2_SUPPORT:
94 case ATOM_DEVICE_CV_SUPPORT:
95 switch (dac) {
96 case 1: /* dac a */
97 if ((rdev->family == CHIP_RS300) ||
98 (rdev->family == CHIP_RS400) ||
99 (rdev->family == CHIP_RS480))
5137ee94 100 ret = ENCODER_INTERNAL_DAC2_ENUM_ID1;
771fe6b9 101 else if (ASIC_IS_AVIVO(rdev))
5137ee94 102 ret = ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1;
771fe6b9 103 else
5137ee94 104 ret = ENCODER_INTERNAL_DAC1_ENUM_ID1;
771fe6b9
JG		 105 break;
106 case 2: /* dac b */
107 if (ASIC_IS_AVIVO(rdev))
5137ee94 108 ret = ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1;
771fe6b9
JG		 109 else {
110 /*if (rdev->family == CHIP_R200)
5137ee94 111 ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
771fe6b9 112 else*/
5137ee94 113 ret = ENCODER_INTERNAL_DAC2_ENUM_ID1;
771fe6b9
JG		 114 }
115 break;
116 case 3: /* external dac */
117 if (ASIC_IS_AVIVO(rdev))
5137ee94 118 ret = ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1;
771fe6b9 119 else
5137ee94 120 ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
771fe6b9
JG		 121 break;
122 }
123 break;
124 case ATOM_DEVICE_LCD1_SUPPORT:
125 if (ASIC_IS_AVIVO(rdev))
5137ee94 126 ret = ENCODER_INTERNAL_LVTM1_ENUM_ID1;
771fe6b9 127 else
5137ee94 128 ret = ENCODER_INTERNAL_LVDS_ENUM_ID1;
771fe6b9
JG		 129 break;
130 case ATOM_DEVICE_DFP1_SUPPORT:
131 if ((rdev->family == CHIP_RS300) ||
132 (rdev->family == CHIP_RS400) ||
133 (rdev->family == CHIP_RS480))
5137ee94 134 ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
771fe6b9 135 else if (ASIC_IS_AVIVO(rdev))
5137ee94 136 ret = ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1;
771fe6b9 137 else
5137ee94 138 ret = ENCODER_INTERNAL_TMDS1_ENUM_ID1;
771fe6b9
JG		 139 break;
140 case ATOM_DEVICE_LCD2_SUPPORT:
141 case ATOM_DEVICE_DFP2_SUPPORT:
142 if ((rdev->family == CHIP_RS600) ||
143 (rdev->family == CHIP_RS690) ||
144 (rdev->family == CHIP_RS740))
5137ee94 145 ret = ENCODER_INTERNAL_DDI_ENUM_ID1;
771fe6b9 146 else if (ASIC_IS_AVIVO(rdev))
5137ee94 147 ret = ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1;
771fe6b9 148 else
5137ee94 149 ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
771fe6b9
JG		 150 break;
151 case ATOM_DEVICE_DFP3_SUPPORT:
5137ee94 152 ret = ENCODER_INTERNAL_LVTM1_ENUM_ID1;
771fe6b9
JG		 153 break;
154 }
155
156 return ret;
157}
158
f28cf339
DA		 159static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder)
160{
161 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
162 switch (radeon_encoder->encoder_id) {
163 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
164 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
165 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
166 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
167 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
168 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
169 case ENCODER_OBJECT_ID_INTERNAL_DDI:
170 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
171 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
172 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
173 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
174 return true;
175 default:
176 return false;
177 }
178}
771fe6b9
JG		 179void
180radeon_link_encoder_connector(struct drm_device *dev)
181{
182 struct drm_connector *connector;
183 struct radeon_connector *radeon_connector;
184 struct drm_encoder *encoder;
185 struct radeon_encoder *radeon_encoder;
186
187 /* walk the list and link encoders to connectors */
188 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
189 radeon_connector = to_radeon_connector(connector);
190 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
191 radeon_encoder = to_radeon_encoder(encoder);
192 if (radeon_encoder->devices & radeon_connector->devices)
193 drm_mode_connector_attach_encoder(connector, encoder);
194 }
195 }
196}
197
4ce001ab
DA		 198void radeon_encoder_set_active_device(struct drm_encoder *encoder)
199{
200 struct drm_device *dev = encoder->dev;
201 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
202 struct drm_connector *connector;
203
204 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
205 if (connector->encoder == encoder) {
206 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
207 radeon_encoder->active_device = radeon_encoder->devices & radeon_connector->devices;
d9fdaafb 208 DRM_DEBUG_KMS("setting active device to %08x from %08x %08x for encoder %d\n",
f641e51e
DA		 209 radeon_encoder->active_device, radeon_encoder->devices,
210 radeon_connector->devices, encoder->encoder_type);
4ce001ab
DA		 211 }
212 }
213}
214
5b1714d3 215struct drm_connector *
771fe6b9
JG		 216radeon_get_connector_for_encoder(struct drm_encoder *encoder)
217{
218 struct drm_device *dev = encoder->dev;
219 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
220 struct drm_connector *connector;
221 struct radeon_connector *radeon_connector;
222
223 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
224 radeon_connector = to_radeon_connector(connector);
43c33ed8 225 if (radeon_encoder->active_device & radeon_connector->devices)
771fe6b9
JG		 226 return connector;
227 }
228 return NULL;
229}
230
3515387b
AD		 231void radeon_panel_mode_fixup(struct drm_encoder *encoder,
232 struct drm_display_mode *adjusted_mode)
233{
234 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
235 struct drm_device *dev = encoder->dev;
236 struct radeon_device *rdev = dev->dev_private;
237 struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
238 unsigned hblank = native_mode->htotal - native_mode->hdisplay;
239 unsigned vblank = native_mode->vtotal - native_mode->vdisplay;
240 unsigned hover = native_mode->hsync_start - native_mode->hdisplay;
241 unsigned vover = native_mode->vsync_start - native_mode->vdisplay;
242 unsigned hsync_width = native_mode->hsync_end - native_mode->hsync_start;
243 unsigned vsync_width = native_mode->vsync_end - native_mode->vsync_start;
244
245 adjusted_mode->clock = native_mode->clock;
246 adjusted_mode->flags = native_mode->flags;
247
248 if (ASIC_IS_AVIVO(rdev)) {
249 adjusted_mode->hdisplay = native_mode->hdisplay;
250 adjusted_mode->vdisplay = native_mode->vdisplay;
251 }
252
253 adjusted_mode->htotal = native_mode->hdisplay + hblank;
254 adjusted_mode->hsync_start = native_mode->hdisplay + hover;
255 adjusted_mode->hsync_end = adjusted_mode->hsync_start + hsync_width;
256
257 adjusted_mode->vtotal = native_mode->vdisplay + vblank;
258 adjusted_mode->vsync_start = native_mode->vdisplay + vover;
259 adjusted_mode->vsync_end = adjusted_mode->vsync_start + vsync_width;
260
261 drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
262
263 if (ASIC_IS_AVIVO(rdev)) {
264 adjusted_mode->crtc_hdisplay = native_mode->hdisplay;
265 adjusted_mode->crtc_vdisplay = native_mode->vdisplay;
266 }
267
268 adjusted_mode->crtc_htotal = adjusted_mode->crtc_hdisplay + hblank;
269 adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hdisplay + hover;
270 adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_start + hsync_width;
271
272 adjusted_mode->crtc_vtotal = adjusted_mode->crtc_vdisplay + vblank;
273 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + vover;
274 adjusted_mode->crtc_vsync_end = adjusted_mode->crtc_vsync_start + vsync_width;
275
276}
277
771fe6b9
JG		 278static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
279 struct drm_display_mode *mode,
280 struct drm_display_mode *adjusted_mode)
281{
771fe6b9 282 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
5a9bcacc
AD		 283 struct drm_device *dev = encoder->dev;
284 struct radeon_device *rdev = dev->dev_private;
771fe6b9 285
8c2a6d73
AD		 286 /* set the active encoder to connector routing */
287 radeon_encoder_set_active_device(encoder);
771fe6b9
JG		 288 drm_mode_set_crtcinfo(adjusted_mode, 0);
289
771fe6b9
JG		 290 /* hw bug */
291 if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
292 && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
293 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
294
80297e87 295 /* get the native mode for LVDS */
3515387b
AD		 296 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
297 radeon_panel_mode_fixup(encoder, adjusted_mode);
80297e87
AD		 298
299 /* get the native mode for TV */
ceefedd8 300 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
5a9bcacc
AD		 301 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
302 if (tv_dac) {
303 if (tv_dac->tv_std == TV_STD_NTSC ||
304 tv_dac->tv_std == TV_STD_NTSC_J ||
305 tv_dac->tv_std == TV_STD_PAL_M)
306 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
307 else
308 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
309 }
310 }
311
5801ead6 312 if (ASIC_IS_DCE3(rdev) &&
9f998ad7 313 (radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT))) {
5801ead6
AD		 314 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
315 radeon_dp_set_link_config(connector, mode);
316 }
317
771fe6b9
JG		 318 return true;
319}
320
321static void
322atombios_dac_setup(struct drm_encoder *encoder, int action)
323{
324 struct drm_device *dev = encoder->dev;
325 struct radeon_device *rdev = dev->dev_private;
326 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
327 DAC_ENCODER_CONTROL_PS_ALLOCATION args;
affd8589 328 int index = 0;
445282db 329 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
445282db 330
771fe6b9
JG		 331 memset(&args, 0, sizeof(args));
332
333 switch (radeon_encoder->encoder_id) {
334 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
335 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
336 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
771fe6b9
JG		 337 break;
338 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
339 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
340 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
771fe6b9
JG		 341 break;
342 }
343
344 args.ucAction = action;
345
4ce001ab 346 if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
771fe6b9 347 args.ucDacStandard = ATOM_DAC1_PS2;
4ce001ab 348 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
771fe6b9
JG		 349 args.ucDacStandard = ATOM_DAC1_CV;
350 else {
affd8589 351 switch (dac_info->tv_std) {
771fe6b9
JG		 352 case TV_STD_PAL:
353 case TV_STD_PAL_M:
354 case TV_STD_SCART_PAL:
355 case TV_STD_SECAM:
356 case TV_STD_PAL_CN:
357 args.ucDacStandard = ATOM_DAC1_PAL;
358 break;
359 case TV_STD_NTSC:
360 case TV_STD_NTSC_J:
361 case TV_STD_PAL_60:
362 default:
363 args.ucDacStandard = ATOM_DAC1_NTSC;
364 break;
365 }
366 }
367 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
368
369 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
370
371}
372
373static void
374atombios_tv_setup(struct drm_encoder *encoder, int action)
375{
376 struct drm_device *dev = encoder->dev;
377 struct radeon_device *rdev = dev->dev_private;
378 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
379 TV_ENCODER_CONTROL_PS_ALLOCATION args;
380 int index = 0;
445282db 381 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
445282db 382
771fe6b9
JG		 383 memset(&args, 0, sizeof(args));
384
385 index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
386
387 args.sTVEncoder.ucAction = action;
388
4ce001ab 389 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
771fe6b9
JG		 390 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
391 else {
affd8589 392 switch (dac_info->tv_std) {
771fe6b9
JG		 393 case TV_STD_NTSC:
394 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
395 break;
396 case TV_STD_PAL:
397 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
398 break;
399 case TV_STD_PAL_M:
400 args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
401 break;
402 case TV_STD_PAL_60:
403 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
404 break;
405 case TV_STD_NTSC_J:
406 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
407 break;
408 case TV_STD_SCART_PAL:
409 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
410 break;
411 case TV_STD_SECAM:
412 args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
413 break;
414 case TV_STD_PAL_CN:
415 args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
416 break;
417 default:
418 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
419 break;
420 }
421 }
422
423 args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
424
425 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
426
427}
428
429void
430atombios_external_tmds_setup(struct drm_encoder *encoder, int action)
431{
432 struct drm_device *dev = encoder->dev;
433 struct radeon_device *rdev = dev->dev_private;
434 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
435 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION args;
436 int index = 0;
437
438 memset(&args, 0, sizeof(args));
439
440 index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
441
442 args.sXTmdsEncoder.ucEnable = action;
443
444 if (radeon_encoder->pixel_clock > 165000)
445 args.sXTmdsEncoder.ucMisc = PANEL_ENCODER_MISC_DUAL;
446
447 /*if (pScrn->rgbBits == 8)*/
448 args.sXTmdsEncoder.ucMisc |= (1 << 1);
449
450 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
451
452}
453
454static void
455atombios_ddia_setup(struct drm_encoder *encoder, int action)
456{
457 struct drm_device *dev = encoder->dev;
458 struct radeon_device *rdev = dev->dev_private;
459 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
460 DVO_ENCODER_CONTROL_PS_ALLOCATION args;
461 int index = 0;
462
463 memset(&args, 0, sizeof(args));
464
465 index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
466
467 args.sDVOEncoder.ucAction = action;
468 args.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
469
470 if (radeon_encoder->pixel_clock > 165000)
471 args.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute = PANEL_ENCODER_MISC_DUAL;
472
473 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
474
475}
476
477union lvds_encoder_control {
478 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1;
479 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
480};
481
32f48ffe 482void
771fe6b9
JG		 483atombios_digital_setup(struct drm_encoder *encoder, int action)
484{
485 struct drm_device *dev = encoder->dev;
486 struct radeon_device *rdev = dev->dev_private;
487 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
9ae47867 488 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
771fe6b9
JG		 489 union lvds_encoder_control args;
490 int index = 0;
dafc3bd5 491 int hdmi_detected = 0;
771fe6b9 492 uint8_t frev, crev;
771fe6b9 493
4aab97e8 494 if (!dig)
771fe6b9
JG		 495 return;
496
9ae47867 497 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
dafc3bd5
CK		 498 hdmi_detected = 1;
499
771fe6b9
JG		 500 memset(&args, 0, sizeof(args));
501
502 switch (radeon_encoder->encoder_id) {
503 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
504 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
505 break;
506 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
507 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
508 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
509 break;
510 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
511 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
512 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
513 else
514 index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
515 break;
516 }
517
a084e6ee
AD		 518 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
519 return;
771fe6b9
JG		 520
521 switch (frev) {
522 case 1:
523 case 2:
524 switch (crev) {
525 case 1:
526 args.v1.ucMisc = 0;
527 args.v1.ucAction = action;
dafc3bd5 528 if (hdmi_detected)
771fe6b9
JG		 529 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
530 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
531 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
ba032a58 532 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
771fe6b9 533 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
ba032a58 534 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
771fe6b9
JG		 535 args.v1.ucMisc |= (1 << 1);
536 } else {
5137ee94 537 if (dig->linkb)
771fe6b9
JG		 538 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
539 if (radeon_encoder->pixel_clock > 165000)
540 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
541 /*if (pScrn->rgbBits == 8) */
542 args.v1.ucMisc |= (1 << 1);
543 }
544 break;
545 case 2:
546 case 3:
547 args.v2.ucMisc = 0;
548 args.v2.ucAction = action;
549 if (crev == 3) {
550 if (dig->coherent_mode)
551 args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
552 }
dafc3bd5 553 if (hdmi_detected)
771fe6b9
JG		 554 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
555 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
556 args.v2.ucTruncate = 0;
557 args.v2.ucSpatial = 0;
558 args.v2.ucTemporal = 0;
559 args.v2.ucFRC = 0;
560 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
ba032a58 561 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
771fe6b9 562 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
ba032a58 563 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) {
771fe6b9 564 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
ba032a58 565 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
771fe6b9
JG		 566 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
567 }
ba032a58 568 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) {
771fe6b9 569 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
ba032a58 570 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
771fe6b9 571 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
ba032a58 572 if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
771fe6b9
JG		 573 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
574 }
575 } else {
5137ee94 576 if (dig->linkb)
771fe6b9
JG		 577 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
578 if (radeon_encoder->pixel_clock > 165000)
579 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
580 }
581 break;
582 default:
583 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
584 break;
585 }
586 break;
587 default:
588 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
589 break;
590 }
591
592 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
771fe6b9
JG		 593}
594
595int
596atombios_get_encoder_mode(struct drm_encoder *encoder)
597{
d033af87
AD		 598 struct drm_device *dev = encoder->dev;
599 struct radeon_device *rdev = dev->dev_private;
771fe6b9
JG		 600 struct drm_connector *connector;
601 struct radeon_connector *radeon_connector;
9ae47867 602 struct radeon_connector_atom_dig *dig_connector;
771fe6b9
JG		 603
604 connector = radeon_get_connector_for_encoder(encoder);
605 if (!connector)
606 return 0;
607
608 radeon_connector = to_radeon_connector(connector);
609
610 switch (connector->connector_type) {
611 case DRM_MODE_CONNECTOR_DVII:
705af9c7 612 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
d033af87
AD		 613 if (drm_detect_hdmi_monitor(radeon_connector->edid)) {
614 /* fix me */
615 if (ASIC_IS_DCE4(rdev))
616 return ATOM_ENCODER_MODE_DVI;
617 else
618 return ATOM_ENCODER_MODE_HDMI;
619 } else if (radeon_connector->use_digital)
771fe6b9
JG		 620 return ATOM_ENCODER_MODE_DVI;
621 else
622 return ATOM_ENCODER_MODE_CRT;
623 break;
624 case DRM_MODE_CONNECTOR_DVID:
625 case DRM_MODE_CONNECTOR_HDMIA:
771fe6b9 626 default:
d033af87
AD		 627 if (drm_detect_hdmi_monitor(radeon_connector->edid)) {
628 /* fix me */
629 if (ASIC_IS_DCE4(rdev))
630 return ATOM_ENCODER_MODE_DVI;
631 else
632 return ATOM_ENCODER_MODE_HDMI;
633 } else
771fe6b9
JG		 634 return ATOM_ENCODER_MODE_DVI;
635 break;
636 case DRM_MODE_CONNECTOR_LVDS:
637 return ATOM_ENCODER_MODE_LVDS;
638 break;
639 case DRM_MODE_CONNECTOR_DisplayPort:
196c58d2 640 case DRM_MODE_CONNECTOR_eDP:
9ae47867
AD		 641 dig_connector = radeon_connector->con_priv;
642 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
643 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
f92a8b67 644 return ATOM_ENCODER_MODE_DP;
d033af87
AD		 645 else if (drm_detect_hdmi_monitor(radeon_connector->edid)) {
646 /* fix me */
647 if (ASIC_IS_DCE4(rdev))
648 return ATOM_ENCODER_MODE_DVI;
649 else
650 return ATOM_ENCODER_MODE_HDMI;
651 } else
771fe6b9
JG		 652 return ATOM_ENCODER_MODE_DVI;
653 break;
a5899fcc
AD		 654 case DRM_MODE_CONNECTOR_DVIA:
655 case DRM_MODE_CONNECTOR_VGA:
771fe6b9
JG		 656 return ATOM_ENCODER_MODE_CRT;
657 break;
a5899fcc
AD		 658 case DRM_MODE_CONNECTOR_Composite:
659 case DRM_MODE_CONNECTOR_SVIDEO:
660 case DRM_MODE_CONNECTOR_9PinDIN:
771fe6b9
JG		 661 /* fix me */
662 return ATOM_ENCODER_MODE_TV;
663 /*return ATOM_ENCODER_MODE_CV;*/
664 break;
665 }
666}
667
1a66c95a
AD		 668/*
669 * DIG Encoder/Transmitter Setup
670 *
671 * DCE 3.0/3.1
672 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
673 * Supports up to 3 digital outputs
674 * - 2 DIG encoder blocks.
675 * DIG1 can drive UNIPHY link A or link B
676 * DIG2 can drive UNIPHY link B or LVTMA
677 *
678 * DCE 3.2
679 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
680 * Supports up to 5 digital outputs
681 * - 2 DIG encoder blocks.
682 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
683 *
bcc1c2a1
AD		 684 * DCE 4.0
685 * - 3 DIG transmitter blocks UNPHY0/1/2 (links A and B).
686 * Supports up to 6 digital outputs
687 * - 6 DIG encoder blocks.
688 * - DIG to PHY mapping is hardcoded
689 * DIG1 drives UNIPHY0 link A, A+B
690 * DIG2 drives UNIPHY0 link B
691 * DIG3 drives UNIPHY1 link A, A+B
692 * DIG4 drives UNIPHY1 link B
693 * DIG5 drives UNIPHY2 link A, A+B
694 * DIG6 drives UNIPHY2 link B
695 *
1a66c95a
AD		 696 * Routing
697 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
698 * Examples:
699 * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI
700 * crtc1 -> dig1 -> UNIPHY0 link B -> DP
701 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS
702 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI
703 */
bcc1c2a1
AD		 704
705union dig_encoder_control {
706 DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
707 DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
708 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
709};
710
711void
771fe6b9
JG		 712atombios_dig_encoder_setup(struct drm_encoder *encoder, int action)
713{
714 struct drm_device *dev = encoder->dev;
715 struct radeon_device *rdev = dev->dev_private;
716 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
9ae47867 717 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
4aab97e8 718 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
bcc1c2a1 719 union dig_encoder_control args;
d9c9fe36 720 int index = 0;
771fe6b9 721 uint8_t frev, crev;
4aab97e8
AD		 722 int dp_clock = 0;
723 int dp_lane_count = 0;
724
725 if (connector) {
726 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
727 struct radeon_connector_atom_dig *dig_connector =
728 radeon_connector->con_priv;
771fe6b9 729
4aab97e8
AD		 730 dp_clock = dig_connector->dp_clock;
731 dp_lane_count = dig_connector->dp_lane_count;
732 }
733
734 /* no dig encoder assigned */
735 if (dig->dig_encoder == -1)
771fe6b9
JG		 736 return;
737
771fe6b9
JG		 738 memset(&args, 0, sizeof(args));
739
bcc1c2a1
AD		 740 if (ASIC_IS_DCE4(rdev))
741 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
742 else {
743 if (dig->dig_encoder)
744 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
745 else
746 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
747 }
771fe6b9 748
a084e6ee
AD		 749 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
750 return;
771fe6b9 751
bcc1c2a1
AD		 752 args.v1.ucAction = action;
753 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
754 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
771fe6b9 755
bcc1c2a1 756 if (args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) {
4aab97e8 757 if (dp_clock == 270000)
bcc1c2a1 758 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
4aab97e8 759 args.v1.ucLaneNum = dp_lane_count;
bcc1c2a1
AD		 760 } else if (radeon_encoder->pixel_clock > 165000)
761 args.v1.ucLaneNum = 8;
762 else
763 args.v1.ucLaneNum = 4;
764
765 if (ASIC_IS_DCE4(rdev)) {
766 args.v3.acConfig.ucDigSel = dig->dig_encoder;
767 args.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR;
768 } else {
771fe6b9
JG		 769 switch (radeon_encoder->encoder_id) {
770 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
bcc1c2a1 771 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
771fe6b9
JG		 772 break;
773 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
bcc1c2a1
AD		 774 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
775 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
771fe6b9
JG		 776 break;
777 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
bcc1c2a1 778 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
771fe6b9
JG		 779 break;
780 }
5137ee94 781 if (dig->linkb)
bcc1c2a1
AD		 782 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
783 else
784 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
771fe6b9
JG		 785 }
786
771fe6b9
JG		 787 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
788
789}
790
791union dig_transmitter_control {
792 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
793 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
bcc1c2a1 794 DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
771fe6b9
JG		 795};
796
5801ead6 797void
1a66c95a 798atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
771fe6b9
JG		 799{
800 struct drm_device *dev = encoder->dev;
801 struct radeon_device *rdev = dev->dev_private;
802 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
9ae47867 803 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
4aab97e8 804 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
771fe6b9 805 union dig_transmitter_control args;
d9c9fe36 806 int index = 0;
771fe6b9 807 uint8_t frev, crev;
f92a8b67 808 bool is_dp = false;
bcc1c2a1 809 int pll_id = 0;
4aab97e8
AD		 810 int dp_clock = 0;
811 int dp_lane_count = 0;
812 int connector_object_id = 0;
813 int igp_lane_info = 0;
814
815 if (connector) {
816 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
817 struct radeon_connector_atom_dig *dig_connector =
818 radeon_connector->con_priv;
819
820 dp_clock = dig_connector->dp_clock;
821 dp_lane_count = dig_connector->dp_lane_count;
822 connector_object_id =
823 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
824 igp_lane_info = dig_connector->igp_lane_info;
825 }
771fe6b9 826
4aab97e8
AD		 827 /* no dig encoder assigned */
828 if (dig->dig_encoder == -1)
771fe6b9
JG		 829 return;
830
f92a8b67
AD		 831 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP)
832 is_dp = true;
833
771fe6b9
JG		 834 memset(&args, 0, sizeof(args));
835
4aab97e8
AD		 836 switch (radeon_encoder->encoder_id) {
837 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
838 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
839 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
771fe6b9 840 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
4aab97e8
AD		 841 break;
842 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
843 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
844 break;
771fe6b9
JG		 845 }
846
a084e6ee
AD		 847 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
848 return;
771fe6b9
JG		 849
850 args.v1.ucAction = action;
f95a9f0b 851 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
4aab97e8 852 args.v1.usInitInfo = connector_object_id;
1a66c95a
AD		 853 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
854 args.v1.asMode.ucLaneSel = lane_num;
855 args.v1.asMode.ucLaneSet = lane_set;
f95a9f0b 856 } else {
f92a8b67
AD		 857 if (is_dp)
858 args.v1.usPixelClock =
4aab97e8 859 cpu_to_le16(dp_clock / 10);
f92a8b67 860 else if (radeon_encoder->pixel_clock > 165000)
f95a9f0b
AD		 861 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
862 else
863 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
864 }
bcc1c2a1
AD		 865 if (ASIC_IS_DCE4(rdev)) {
866 if (is_dp)
4aab97e8 867 args.v3.ucLaneNum = dp_lane_count;
bcc1c2a1
AD		 868 else if (radeon_encoder->pixel_clock > 165000)
869 args.v3.ucLaneNum = 8;
870 else
871 args.v3.ucLaneNum = 4;
872
5137ee94 873 if (dig->linkb) {
bcc1c2a1
AD		 874 args.v3.acConfig.ucLinkSel = 1;
875 args.v3.acConfig.ucEncoderSel = 1;
876 }
877
878 /* Select the PLL for the PHY
879 * DP PHY should be clocked from external src if there is
880 * one.
881 */
882 if (encoder->crtc) {
883 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
884 pll_id = radeon_crtc->pll_id;
885 }
886 if (is_dp && rdev->clock.dp_extclk)
887 args.v3.acConfig.ucRefClkSource = 2; /* external src */
888 else
889 args.v3.acConfig.ucRefClkSource = pll_id;
890
891 switch (radeon_encoder->encoder_id) {
892 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
893 args.v3.acConfig.ucTransmitterSel = 0;
bcc1c2a1
AD		 894 break;
895 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
896 args.v3.acConfig.ucTransmitterSel = 1;
bcc1c2a1
AD		 897 break;
898 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
899 args.v3.acConfig.ucTransmitterSel = 2;
bcc1c2a1
AD		 900 break;
901 }
902
903 if (is_dp)
904 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
905 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
906 if (dig->coherent_mode)
907 args.v3.acConfig.fCoherentMode = 1;
b317a9ce
AD		 908 if (radeon_encoder->pixel_clock > 165000)
909 args.v3.acConfig.fDualLinkConnector = 1;
bcc1c2a1
AD		 910 }
911 } else if (ASIC_IS_DCE32(rdev)) {
d9c9fe36 912 args.v2.acConfig.ucEncoderSel = dig->dig_encoder;
5137ee94 913 if (dig->linkb)
1a66c95a 914 args.v2.acConfig.ucLinkSel = 1;
771fe6b9
JG		 915
916 switch (radeon_encoder->encoder_id) {
917 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
918 args.v2.acConfig.ucTransmitterSel = 0;
771fe6b9
JG		 919 break;
920 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
921 args.v2.acConfig.ucTransmitterSel = 1;
771fe6b9
JG		 922 break;
923 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
924 args.v2.acConfig.ucTransmitterSel = 2;
771fe6b9
JG		 925 break;
926 }
927
f92a8b67
AD		 928 if (is_dp)
929 args.v2.acConfig.fCoherentMode = 1;
930 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
771fe6b9
JG		 931 if (dig->coherent_mode)
932 args.v2.acConfig.fCoherentMode = 1;
b317a9ce
AD		 933 if (radeon_encoder->pixel_clock > 165000)
934 args.v2.acConfig.fDualLinkConnector = 1;
771fe6b9
JG		 935 }
936 } else {
937 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
771fe6b9 938
f28cf339
DA		 939 if (dig->dig_encoder)
940 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
941 else
942 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
943
d9c9fe36
AD		 944 if ((rdev->flags & RADEON_IS_IGP) &&
945 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
946 if (is_dp || (radeon_encoder->pixel_clock <= 165000)) {
4aab97e8 947 if (igp_lane_info & 0x1)
d9c9fe36 948 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
4aab97e8 949 else if (igp_lane_info & 0x2)
d9c9fe36 950 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
4aab97e8 951 else if (igp_lane_info & 0x4)
d9c9fe36 952 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
4aab97e8 953 else if (igp_lane_info & 0x8)
d9c9fe36
AD		 954 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
955 } else {
4aab97e8 956 if (igp_lane_info & 0x3)
d9c9fe36 957 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
4aab97e8 958 else if (igp_lane_info & 0xc)
d9c9fe36 959 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
771fe6b9 960 }
771fe6b9
JG		 961 }
962
5137ee94 963 if (dig->linkb)
1a66c95a
AD		 964 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
965 else
966 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
967
f92a8b67
AD		 968 if (is_dp)
969 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
970 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
771fe6b9
JG		 971 if (dig->coherent_mode)
972 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
d9c9fe36
AD		 973 if (radeon_encoder->pixel_clock > 165000)
974 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
771fe6b9
JG		 975 }
976 }
977
978 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
771fe6b9
JG		 979}
980
771fe6b9
JG		 981static void
982atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
983{
984 struct drm_device *dev = encoder->dev;
985 struct radeon_device *rdev = dev->dev_private;
986 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
987 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
988 ENABLE_YUV_PS_ALLOCATION args;
989 int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
990 uint32_t temp, reg;
991
992 memset(&args, 0, sizeof(args));
993
994 if (rdev->family >= CHIP_R600)
995 reg = R600_BIOS_3_SCRATCH;
996 else
997 reg = RADEON_BIOS_3_SCRATCH;
998
999 /* XXX: fix up scratch reg handling */
1000 temp = RREG32(reg);
4ce001ab 1001 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
771fe6b9
JG		 1002 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
1003 (radeon_crtc->crtc_id << 18)));
4ce001ab 1004 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
771fe6b9
JG		 1005 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
1006 else
1007 WREG32(reg, 0);
1008
1009 if (enable)
1010 args.ucEnable = ATOM_ENABLE;
1011 args.ucCRTC = radeon_crtc->crtc_id;
1012
1013 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1014
1015 WREG32(reg, temp);
1016}
1017
771fe6b9
JG		 1018static void
1019radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1020{
1021 struct drm_device *dev = encoder->dev;
1022 struct radeon_device *rdev = dev->dev_private;
1023 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1024 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1025 int index = 0;
1026 bool is_dig = false;
1027
1028 memset(&args, 0, sizeof(args));
1029
d9fdaafb 1030 DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
f641e51e
DA		 1031 radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1032 radeon_encoder->active_device);
771fe6b9
JG		 1033 switch (radeon_encoder->encoder_id) {
1034 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1035 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1036 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1037 break;
1038 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1039 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1040 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1041 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1042 is_dig = true;
1043 break;
1044 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1045 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1046 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1047 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1048 break;
1049 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1050 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1051 break;
1052 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1053 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1054 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1055 else
1056 index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1057 break;
1058 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1059 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
8c2a6d73 1060 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
771fe6b9 1061 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
8c2a6d73 1062 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
771fe6b9
JG		 1063 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1064 else
1065 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1066 break;
1067 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1068 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
8c2a6d73 1069 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
771fe6b9 1070 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
8c2a6d73 1071 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
771fe6b9
JG		 1072 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1073 else
1074 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1075 break;
1076 }
1077
1078 if (is_dig) {
1079 switch (mode) {
1080 case DRM_MODE_DPMS_ON:
e13b2ac1 1081 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
fb668c2f 1082 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) {
58682f10 1083 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
fb668c2f 1084
58682f10 1085 dp_link_train(encoder, connector);
fb668c2f
AD		 1086 if (ASIC_IS_DCE4(rdev))
1087 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON);
58682f10 1088 }
771fe6b9
JG		 1089 break;
1090 case DRM_MODE_DPMS_STANDBY:
1091 case DRM_MODE_DPMS_SUSPEND:
1092 case DRM_MODE_DPMS_OFF:
e13b2ac1 1093 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
fb668c2f
AD		 1094 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) {
1095 if (ASIC_IS_DCE4(rdev))
1096 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF);
1097 }
771fe6b9
JG		 1098 break;
1099 }
1100 } else {
1101 switch (mode) {
1102 case DRM_MODE_DPMS_ON:
1103 args.ucAction = ATOM_ENABLE;
1104 break;
1105 case DRM_MODE_DPMS_STANDBY:
1106 case DRM_MODE_DPMS_SUSPEND:
1107 case DRM_MODE_DPMS_OFF:
1108 args.ucAction = ATOM_DISABLE;
1109 break;
1110 }
1111 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1112 }
1113 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
c913e23a 1114
771fe6b9
JG		 1115}
1116
9ae47867 1117union crtc_source_param {
771fe6b9
JG		 1118 SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1119 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1120};
1121
1122static void
1123atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1124{
1125 struct drm_device *dev = encoder->dev;
1126 struct radeon_device *rdev = dev->dev_private;
1127 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1128 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
9ae47867 1129 union crtc_source_param args;
771fe6b9
JG		 1130 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1131 uint8_t frev, crev;
f28cf339 1132 struct radeon_encoder_atom_dig *dig;
771fe6b9
JG		 1133
1134 memset(&args, 0, sizeof(args));
1135
a084e6ee
AD		 1136 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1137 return;
771fe6b9
JG		 1138
1139 switch (frev) {
1140 case 1:
1141 switch (crev) {
1142 case 1:
1143 default:
1144 if (ASIC_IS_AVIVO(rdev))
1145 args.v1.ucCRTC = radeon_crtc->crtc_id;
1146 else {
1147 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1148 args.v1.ucCRTC = radeon_crtc->crtc_id;
1149 } else {
1150 args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1151 }
1152 }
1153 switch (radeon_encoder->encoder_id) {
1154 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1155 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1156 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1157 break;
1158 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1159 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1160 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1161 args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1162 else
1163 args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1164 break;
1165 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1166 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1167 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1168 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1169 break;
1170 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1171 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
4ce001ab 1172 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
771fe6b9 1173 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
4ce001ab 1174 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
771fe6b9
JG		 1175 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1176 else
1177 args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1178 break;
1179 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1180 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
4ce001ab 1181 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
771fe6b9 1182 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
4ce001ab 1183 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
771fe6b9
JG		 1184 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1185 else
1186 args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1187 break;
1188 }
1189 break;
1190 case 2:
1191 args.v2.ucCRTC = radeon_crtc->crtc_id;
1192 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1193 switch (radeon_encoder->encoder_id) {
1194 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1195 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1196 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
f28cf339
DA		 1197 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1198 dig = radeon_encoder->enc_priv;
bcc1c2a1
AD		 1199 switch (dig->dig_encoder) {
1200 case 0:
f28cf339 1201 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
bcc1c2a1
AD		 1202 break;
1203 case 1:
1204 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1205 break;
1206 case 2:
1207 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1208 break;
1209 case 3:
1210 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1211 break;
1212 case 4:
1213 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1214 break;
1215 case 5:
1216 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1217 break;
1218 }
771fe6b9
JG		 1219 break;
1220 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1221 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1222 break;
771fe6b9 1223 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
4ce001ab 1224 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
771fe6b9 1225 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
4ce001ab 1226 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
771fe6b9
JG		 1227 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1228 else
1229 args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1230 break;
1231 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
4ce001ab 1232 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
771fe6b9 1233 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
4ce001ab 1234 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
771fe6b9
JG		 1235 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1236 else
1237 args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1238 break;
1239 }
1240 break;
1241 }
1242 break;
1243 default:
1244 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1245 break;
1246 }
1247
1248 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
267364ac
AD		 1249
1250 /* update scratch regs with new routing */
1251 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
771fe6b9
JG		 1252}
1253
1254static void
1255atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1256 struct drm_display_mode *mode)
1257{
1258 struct drm_device *dev = encoder->dev;
1259 struct radeon_device *rdev = dev->dev_private;
1260 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1261 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1262
1263 /* Funky macbooks */
1264 if ((dev->pdev->device == 0x71C5) &&
1265 (dev->pdev->subsystem_vendor == 0x106b) &&
1266 (dev->pdev->subsystem_device == 0x0080)) {
1267 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1268 uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1269
1270 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
1271 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
1272
1273 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
1274 }
1275 }
1276
1277 /* set scaler clears this on some chips */
bcc1c2a1 1278 /* XXX check DCE4 */
ceefedd8
AD		 1279 if (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))) {
1280 if (ASIC_IS_AVIVO(rdev) && (mode->flags & DRM_MODE_FLAG_INTERLACE))
1281 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1282 AVIVO_D1MODE_INTERLEAVE_EN);
1283 }
771fe6b9
JG		 1284}
1285
f28cf339
DA		 1286static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
1287{
1288 struct drm_device *dev = encoder->dev;
1289 struct radeon_device *rdev = dev->dev_private;
1290 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1291 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1292 struct drm_encoder *test_encoder;
1293 struct radeon_encoder_atom_dig *dig;
1294 uint32_t dig_enc_in_use = 0;
bcc1c2a1
AD		 1295
1296 if (ASIC_IS_DCE4(rdev)) {
5137ee94 1297 dig = radeon_encoder->enc_priv;
bcc1c2a1
AD		 1298 switch (radeon_encoder->encoder_id) {
1299 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
5137ee94 1300 if (dig->linkb)
bcc1c2a1
AD		 1301 return 1;
1302 else
1303 return 0;
1304 break;
1305 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
5137ee94 1306 if (dig->linkb)
bcc1c2a1
AD		 1307 return 3;
1308 else
1309 return 2;
1310 break;
1311 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
5137ee94 1312 if (dig->linkb)
bcc1c2a1
AD		 1313 return 5;
1314 else
1315 return 4;
1316 break;
1317 }
1318 }
1319
f28cf339
DA		 1320 /* on DCE32 and encoder can driver any block so just crtc id */
1321 if (ASIC_IS_DCE32(rdev)) {
1322 return radeon_crtc->crtc_id;
1323 }
1324
1325 /* on DCE3 - LVTMA can only be driven by DIGB */
1326 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1327 struct radeon_encoder *radeon_test_encoder;
1328
1329 if (encoder == test_encoder)
1330 continue;
1331
1332 if (!radeon_encoder_is_digital(test_encoder))
1333 continue;
1334
1335 radeon_test_encoder = to_radeon_encoder(test_encoder);
1336 dig = radeon_test_encoder->enc_priv;
1337
1338 if (dig->dig_encoder >= 0)
1339 dig_enc_in_use |= (1 << dig->dig_encoder);
1340 }
1341
1342 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
1343 if (dig_enc_in_use & 0x2)
1344 DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
1345 return 1;
1346 }
1347 if (!(dig_enc_in_use & 1))
1348 return 0;
1349 return 1;
1350}
1351
771fe6b9
JG		 1352static void
1353radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1354 struct drm_display_mode *mode,
1355 struct drm_display_mode *adjusted_mode)
1356{
1357 struct drm_device *dev = encoder->dev;
1358 struct radeon_device *rdev = dev->dev_private;
1359 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
771fe6b9 1360
771fe6b9
JG		 1361 radeon_encoder->pixel_clock = adjusted_mode->clock;
1362
c6f8505e 1363 if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
4ce001ab 1364 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
771fe6b9
JG		 1365 atombios_yuv_setup(encoder, true);
1366 else
1367 atombios_yuv_setup(encoder, false);
1368 }
1369
1370 switch (radeon_encoder->encoder_id) {
1371 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1372 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1373 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1374 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1375 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
1376 break;
1377 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1378 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1379 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1380 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
bcc1c2a1
AD		 1381 if (ASIC_IS_DCE4(rdev)) {
1382 /* disable the transmitter */
1383 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1384 /* setup and enable the encoder */
1385 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP);
1386
1387 /* init and enable the transmitter */
1388 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
1389 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1390 } else {
1391 /* disable the encoder and transmitter */
1392 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1393 atombios_dig_encoder_setup(encoder, ATOM_DISABLE);
1394
1395 /* setup and enable the encoder and transmitter */
1396 atombios_dig_encoder_setup(encoder, ATOM_ENABLE);
1397 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
1398 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1399 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1400 }
771fe6b9
JG		 1401 break;
1402 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1403 atombios_ddia_setup(encoder, ATOM_ENABLE);
1404 break;
1405 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1406 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1407 atombios_external_tmds_setup(encoder, ATOM_ENABLE);
1408 break;
1409 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1410 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1411 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1412 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1413 atombios_dac_setup(encoder, ATOM_ENABLE);
d3a67a43
AD		 1414 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
1415 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1416 atombios_tv_setup(encoder, ATOM_ENABLE);
1417 else
1418 atombios_tv_setup(encoder, ATOM_DISABLE);
1419 }
771fe6b9
JG		 1420 break;
1421 }
1422 atombios_apply_encoder_quirks(encoder, adjusted_mode);
dafc3bd5 1423
2cd6218c
RM		 1424 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
1425 r600_hdmi_enable(encoder);
bcc1c2a1 1426 r600_hdmi_setmode(encoder, adjusted_mode);
2cd6218c 1427 }
771fe6b9
JG		 1428}
1429
1430static bool
4ce001ab 1431atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
771fe6b9
JG		 1432{
1433 struct drm_device *dev = encoder->dev;
1434 struct radeon_device *rdev = dev->dev_private;
1435 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
4ce001ab 1436 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
771fe6b9
JG		 1437
1438 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
1439 ATOM_DEVICE_CV_SUPPORT |
1440 ATOM_DEVICE_CRT_SUPPORT)) {
1441 DAC_LOAD_DETECTION_PS_ALLOCATION args;
1442 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
1443 uint8_t frev, crev;
1444
1445 memset(&args, 0, sizeof(args));
1446
a084e6ee
AD		 1447 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1448 return false;
771fe6b9
JG		 1449
1450 args.sDacload.ucMisc = 0;
1451
1452 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
1453 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
1454 args.sDacload.ucDacType = ATOM_DAC_A;
1455 else
1456 args.sDacload.ucDacType = ATOM_DAC_B;
1457
4ce001ab 1458 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
771fe6b9 1459 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
4ce001ab 1460 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
771fe6b9 1461 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
4ce001ab 1462 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
771fe6b9
JG		 1463 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
1464 if (crev >= 3)
1465 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
4ce001ab 1466 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
771fe6b9
JG		 1467 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
1468 if (crev >= 3)
1469 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1470 }
1471
1472 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1473
1474 return true;
1475 } else
1476 return false;
1477}
1478
1479static enum drm_connector_status
1480radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1481{
1482 struct drm_device *dev = encoder->dev;
1483 struct radeon_device *rdev = dev->dev_private;
1484 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
4ce001ab 1485 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
771fe6b9
JG		 1486 uint32_t bios_0_scratch;
1487
4ce001ab 1488 if (!atombios_dac_load_detect(encoder, connector)) {
d9fdaafb 1489 DRM_DEBUG_KMS("detect returned false \n");
771fe6b9
JG		 1490 return connector_status_unknown;
1491 }
1492
1493 if (rdev->family >= CHIP_R600)
1494 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
1495 else
1496 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
1497
d9fdaafb 1498 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
4ce001ab 1499 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
771fe6b9
JG		 1500 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
1501 return connector_status_connected;
4ce001ab
DA		 1502 }
1503 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
771fe6b9
JG		 1504 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
1505 return connector_status_connected;
4ce001ab
DA		 1506 }
1507 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
771fe6b9
JG		 1508 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
1509 return connector_status_connected;
4ce001ab
DA		 1510 }
1511 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
771fe6b9
JG		 1512 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
1513 return connector_status_connected; /* CTV */
1514 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
1515 return connector_status_connected; /* STV */
1516 }
1517 return connector_status_disconnected;
1518}
1519
1520static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
1521{
267364ac 1522 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
fb939dfc 1523 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
267364ac
AD		 1524
1525 if (radeon_encoder->active_device &
1526 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) {
1527 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1528 if (dig)
1529 dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
1530 }
1531
771fe6b9
JG		 1532 radeon_atom_output_lock(encoder, true);
1533 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
267364ac 1534
fb939dfc
AD		 1535 /* select the clock/data port if it uses a router */
1536 if (connector) {
1537 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1538 if (radeon_connector->router.cd_valid)
1539 radeon_router_select_cd_port(radeon_connector);
1540 }
1541
267364ac
AD		 1542 /* this is needed for the pll/ss setup to work correctly in some cases */
1543 atombios_set_encoder_crtc_source(encoder);
771fe6b9
JG		 1544}
1545
1546static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
1547{
1548 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
1549 radeon_atom_output_lock(encoder, false);
1550}
1551
4ce001ab
DA		 1552static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
1553{
aa961391
AD		 1554 struct drm_device *dev = encoder->dev;
1555 struct radeon_device *rdev = dev->dev_private;
4ce001ab 1556 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
f28cf339 1557 struct radeon_encoder_atom_dig *dig;
a0ae5864
AD		 1558
1559 /* check for pre-DCE3 cards with shared encoders;
1560 * can't really use the links individually, so don't disable
1561 * the encoder if it's in use by another connector
1562 */
1563 if (!ASIC_IS_DCE3(rdev)) {
1564 struct drm_encoder *other_encoder;
1565 struct radeon_encoder *other_radeon_encoder;
1566
1567 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
1568 other_radeon_encoder = to_radeon_encoder(other_encoder);
1569 if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) &&
1570 drm_helper_encoder_in_use(other_encoder))
1571 goto disable_done;
1572 }
1573 }
1574
4ce001ab 1575 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
f28cf339 1576
aa961391
AD		 1577 switch (radeon_encoder->encoder_id) {
1578 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1579 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1580 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1581 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1582 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE);
1583 break;
1584 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1585 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1586 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1587 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1588 if (ASIC_IS_DCE4(rdev))
1589 /* disable the transmitter */
1590 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1591 else {
1592 /* disable the encoder and transmitter */
1593 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1594 atombios_dig_encoder_setup(encoder, ATOM_DISABLE);
1595 }
1596 break;
1597 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1598 atombios_ddia_setup(encoder, ATOM_DISABLE);
1599 break;
1600 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1601 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1602 atombios_external_tmds_setup(encoder, ATOM_DISABLE);
1603 break;
1604 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1605 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1606 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1607 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1608 atombios_dac_setup(encoder, ATOM_DISABLE);
8bf3aae6 1609 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
aa961391
AD		 1610 atombios_tv_setup(encoder, ATOM_DISABLE);
1611 break;
1612 }
1613
a0ae5864 1614disable_done:
f28cf339 1615 if (radeon_encoder_is_digital(encoder)) {
2cd6218c
RM		 1616 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
1617 r600_hdmi_disable(encoder);
f28cf339
DA		 1618 dig = radeon_encoder->enc_priv;
1619 dig->dig_encoder = -1;
1620 }
4ce001ab
DA		 1621 radeon_encoder->active_device = 0;
1622}
1623
771fe6b9
JG		 1624static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
1625 .dpms = radeon_atom_encoder_dpms,
1626 .mode_fixup = radeon_atom_mode_fixup,
1627 .prepare = radeon_atom_encoder_prepare,
1628 .mode_set = radeon_atom_encoder_mode_set,
1629 .commit = radeon_atom_encoder_commit,
4ce001ab 1630 .disable = radeon_atom_encoder_disable,
771fe6b9
JG		 1631 /* no detect for TMDS/LVDS yet */
1632};
1633
1634static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
1635 .dpms = radeon_atom_encoder_dpms,
1636 .mode_fixup = radeon_atom_mode_fixup,
1637 .prepare = radeon_atom_encoder_prepare,
1638 .mode_set = radeon_atom_encoder_mode_set,
1639 .commit = radeon_atom_encoder_commit,
1640 .detect = radeon_atom_dac_detect,
1641};
1642
1643void radeon_enc_destroy(struct drm_encoder *encoder)
1644{
1645 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1646 kfree(radeon_encoder->enc_priv);
1647 drm_encoder_cleanup(encoder);
1648 kfree(radeon_encoder);
1649}
1650
1651static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
1652 .destroy = radeon_enc_destroy,
1653};
1654
4ce001ab
DA		 1655struct radeon_encoder_atom_dac *
1656radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
1657{
affd8589
AD		 1658 struct drm_device *dev = radeon_encoder->base.dev;
1659 struct radeon_device *rdev = dev->dev_private;
4ce001ab
DA		 1660 struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
1661
1662 if (!dac)
1663 return NULL;
1664
affd8589 1665 dac->tv_std = radeon_atombios_get_tv_info(rdev);
4ce001ab
DA		 1666 return dac;
1667}
1668
771fe6b9
JG		 1669struct radeon_encoder_atom_dig *
1670radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
1671{
5137ee94 1672 int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
771fe6b9
JG		 1673 struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1674
1675 if (!dig)
1676 return NULL;
1677
1678 /* coherent mode by default */
1679 dig->coherent_mode = true;
f28cf339 1680 dig->dig_encoder = -1;
771fe6b9 1681
5137ee94
AD		 1682 if (encoder_enum == 2)
1683 dig->linkb = true;
1684 else
1685 dig->linkb = false;
1686
771fe6b9
JG		 1687 return dig;
1688}
1689
1690void
5137ee94 1691radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum, uint32_t supported_device)
771fe6b9 1692{
dfee5614 1693 struct radeon_device *rdev = dev->dev_private;
771fe6b9
JG		 1694 struct drm_encoder *encoder;
1695 struct radeon_encoder *radeon_encoder;
1696
1697 /* see if we already added it */
1698 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1699 radeon_encoder = to_radeon_encoder(encoder);
5137ee94 1700 if (radeon_encoder->encoder_enum == encoder_enum) {
771fe6b9
JG		 1701 radeon_encoder->devices |= supported_device;
1702 return;
1703 }
1704
1705 }
1706
1707 /* add a new one */
1708 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
1709 if (!radeon_encoder)
1710 return;
1711
1712 encoder = &radeon_encoder->base;
bcc1c2a1
AD		 1713 switch (rdev->num_crtc) {
1714 case 1:
dfee5614 1715 encoder->possible_crtcs = 0x1;
bcc1c2a1
AD		 1716 break;
1717 case 2:
1718 default:
dfee5614 1719 encoder->possible_crtcs = 0x3;
bcc1c2a1
AD		 1720 break;
1721 case 6:
1722 encoder->possible_crtcs = 0x3f;
1723 break;
1724 }
771fe6b9
JG		 1725
1726 radeon_encoder->enc_priv = NULL;
1727
5137ee94
AD		 1728 radeon_encoder->encoder_enum = encoder_enum;
1729 radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
771fe6b9 1730 radeon_encoder->devices = supported_device;
c93bb85b 1731 radeon_encoder->rmx_type = RMX_OFF;
5b1714d3 1732 radeon_encoder->underscan_type = UNDERSCAN_OFF;
771fe6b9
JG		 1733
1734 switch (radeon_encoder->encoder_id) {
1735 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1736 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1737 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1738 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1739 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1740 radeon_encoder->rmx_type = RMX_FULL;
1741 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
1742 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1743 } else {
1744 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
1745 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
430f70d5
AD		 1746 if (ASIC_IS_AVIVO(rdev))
1747 radeon_encoder->underscan_type = UNDERSCAN_AUTO;
771fe6b9
JG		 1748 }
1749 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
1750 break;
1751 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1752 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
affd8589 1753 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
771fe6b9
JG		 1754 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
1755 break;
1756 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1757 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1758 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1759 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
4ce001ab 1760 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
771fe6b9
JG		 1761 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
1762 break;
1763 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1764 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1765 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1766 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1767 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1768 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1769 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
60d15f55
AD		 1770 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1771 radeon_encoder->rmx_type = RMX_FULL;
1772 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
1773 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1774 } else {
1775 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
1776 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
430f70d5
AD		 1777 if (ASIC_IS_AVIVO(rdev))
1778 radeon_encoder->underscan_type = UNDERSCAN_AUTO;
60d15f55 1779 }
771fe6b9
JG		 1780 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
1781 break;
1782 }
1783}
Clone of davem's net-next-2.6 tree