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drm/radeon/kms/atom: rework crtc modeset
[net-next-2.6.git] / drivers / gpu / drm / radeon / radeon_encoders.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26#include "drmP.h"
27#include "drm_crtc_helper.h"
28#include "radeon_drm.h"
29#include "radeon.h"
30#include "atom.h"
31
32extern int atom_debug;
33
5a9bcacc
AD		 34/* evil but including atombios.h is much worse */
35bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
36 struct drm_display_mode *mode);
37
771fe6b9
JG		 38uint32_t
39radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device, uint8_t dac)
40{
41 struct radeon_device *rdev = dev->dev_private;
42 uint32_t ret = 0;
43
44 switch (supported_device) {
45 case ATOM_DEVICE_CRT1_SUPPORT:
46 case ATOM_DEVICE_TV1_SUPPORT:
47 case ATOM_DEVICE_TV2_SUPPORT:
48 case ATOM_DEVICE_CRT2_SUPPORT:
49 case ATOM_DEVICE_CV_SUPPORT:
50 switch (dac) {
51 case 1: /* dac a */
52 if ((rdev->family == CHIP_RS300) ||
53 (rdev->family == CHIP_RS400) ||
54 (rdev->family == CHIP_RS480))
55 ret = ENCODER_OBJECT_ID_INTERNAL_DAC2;
56 else if (ASIC_IS_AVIVO(rdev))
57 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1;
58 else
59 ret = ENCODER_OBJECT_ID_INTERNAL_DAC1;
60 break;
61 case 2: /* dac b */
62 if (ASIC_IS_AVIVO(rdev))
63 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2;
64 else {
65 /*if (rdev->family == CHIP_R200)
66 ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
67 else*/
68 ret = ENCODER_OBJECT_ID_INTERNAL_DAC2;
69 }
70 break;
71 case 3: /* external dac */
72 if (ASIC_IS_AVIVO(rdev))
73 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1;
74 else
75 ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
76 break;
77 }
78 break;
79 case ATOM_DEVICE_LCD1_SUPPORT:
80 if (ASIC_IS_AVIVO(rdev))
81 ret = ENCODER_OBJECT_ID_INTERNAL_LVTM1;
82 else
83 ret = ENCODER_OBJECT_ID_INTERNAL_LVDS;
84 break;
85 case ATOM_DEVICE_DFP1_SUPPORT:
86 if ((rdev->family == CHIP_RS300) ||
87 (rdev->family == CHIP_RS400) ||
88 (rdev->family == CHIP_RS480))
89 ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
90 else if (ASIC_IS_AVIVO(rdev))
91 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1;
92 else
93 ret = ENCODER_OBJECT_ID_INTERNAL_TMDS1;
94 break;
95 case ATOM_DEVICE_LCD2_SUPPORT:
96 case ATOM_DEVICE_DFP2_SUPPORT:
97 if ((rdev->family == CHIP_RS600) ||
98 (rdev->family == CHIP_RS690) ||
99 (rdev->family == CHIP_RS740))
100 ret = ENCODER_OBJECT_ID_INTERNAL_DDI;
101 else if (ASIC_IS_AVIVO(rdev))
102 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1;
103 else
104 ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
105 break;
106 case ATOM_DEVICE_DFP3_SUPPORT:
107 ret = ENCODER_OBJECT_ID_INTERNAL_LVTM1;
108 break;
109 }
110
111 return ret;
112}
113
114void
115radeon_link_encoder_connector(struct drm_device *dev)
116{
117 struct drm_connector *connector;
118 struct radeon_connector *radeon_connector;
119 struct drm_encoder *encoder;
120 struct radeon_encoder *radeon_encoder;
121
122 /* walk the list and link encoders to connectors */
123 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
124 radeon_connector = to_radeon_connector(connector);
125 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
126 radeon_encoder = to_radeon_encoder(encoder);
127 if (radeon_encoder->devices & radeon_connector->devices)
128 drm_mode_connector_attach_encoder(connector, encoder);
129 }
130 }
131}
132
4ce001ab
DA		 133void radeon_encoder_set_active_device(struct drm_encoder *encoder)
134{
135 struct drm_device *dev = encoder->dev;
136 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
137 struct drm_connector *connector;
138
139 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
140 if (connector->encoder == encoder) {
141 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
142 radeon_encoder->active_device = radeon_encoder->devices & radeon_connector->devices;
f641e51e
DA		 143 DRM_DEBUG("setting active device to %08x from %08x %08x for encoder %d\n",
144 radeon_encoder->active_device, radeon_encoder->devices,
145 radeon_connector->devices, encoder->encoder_type);
4ce001ab
DA		 146 }
147 }
148}
149
771fe6b9
JG		 150static struct drm_connector *
151radeon_get_connector_for_encoder(struct drm_encoder *encoder)
152{
153 struct drm_device *dev = encoder->dev;
154 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
155 struct drm_connector *connector;
156 struct radeon_connector *radeon_connector;
157
158 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
159 radeon_connector = to_radeon_connector(connector);
160 if (radeon_encoder->devices & radeon_connector->devices)
161 return connector;
162 }
163 return NULL;
164}
165
166/* used for both atom and legacy */
167void radeon_rmx_mode_fixup(struct drm_encoder *encoder,
168 struct drm_display_mode *mode,
169 struct drm_display_mode *adjusted_mode)
170{
171 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
172 struct drm_device *dev = encoder->dev;
173 struct radeon_device *rdev = dev->dev_private;
174 struct radeon_native_mode *native_mode = &radeon_encoder->native_mode;
175
176 if (mode->hdisplay < native_mode->panel_xres ||
177 mode->vdisplay < native_mode->panel_yres) {
771fe6b9
JG		 178 if (ASIC_IS_AVIVO(rdev)) {
179 adjusted_mode->hdisplay = native_mode->panel_xres;
180 adjusted_mode->vdisplay = native_mode->panel_yres;
181 adjusted_mode->htotal = native_mode->panel_xres + native_mode->hblank;
182 adjusted_mode->hsync_start = native_mode->panel_xres + native_mode->hoverplus;
183 adjusted_mode->hsync_end = adjusted_mode->hsync_start + native_mode->hsync_width;
184 adjusted_mode->vtotal = native_mode->panel_yres + native_mode->vblank;
185 adjusted_mode->vsync_start = native_mode->panel_yres + native_mode->voverplus;
186 adjusted_mode->vsync_end = adjusted_mode->vsync_start + native_mode->vsync_width;
187 /* update crtc values */
188 drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
189 /* adjust crtc values */
190 adjusted_mode->crtc_hdisplay = native_mode->panel_xres;
191 adjusted_mode->crtc_vdisplay = native_mode->panel_yres;
192 adjusted_mode->crtc_htotal = adjusted_mode->crtc_hdisplay + native_mode->hblank;
193 adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hdisplay + native_mode->hoverplus;
194 adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_start + native_mode->hsync_width;
195 adjusted_mode->crtc_vtotal = adjusted_mode->crtc_vdisplay + native_mode->vblank;
196 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + native_mode->voverplus;
197 adjusted_mode->crtc_vsync_end = adjusted_mode->crtc_vsync_start + native_mode->vsync_width;
198 } else {
199 adjusted_mode->htotal = native_mode->panel_xres + native_mode->hblank;
200 adjusted_mode->hsync_start = native_mode->panel_xres + native_mode->hoverplus;
201 adjusted_mode->hsync_end = adjusted_mode->hsync_start + native_mode->hsync_width;
202 adjusted_mode->vtotal = native_mode->panel_yres + native_mode->vblank;
203 adjusted_mode->vsync_start = native_mode->panel_yres + native_mode->voverplus;
204 adjusted_mode->vsync_end = adjusted_mode->vsync_start + native_mode->vsync_width;
205 /* update crtc values */
206 drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
207 /* adjust crtc values */
208 adjusted_mode->crtc_htotal = adjusted_mode->crtc_hdisplay + native_mode->hblank;
209 adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hdisplay + native_mode->hoverplus;
210 adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_start + native_mode->hsync_width;
211 adjusted_mode->crtc_vtotal = adjusted_mode->crtc_vdisplay + native_mode->vblank;
212 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + native_mode->voverplus;
213 adjusted_mode->crtc_vsync_end = adjusted_mode->crtc_vsync_start + native_mode->vsync_width;
214 }
215 adjusted_mode->flags = native_mode->flags;
216 adjusted_mode->clock = native_mode->dotclock;
217 }
218}
219
c93bb85b 220
771fe6b9
JG		 221static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
222 struct drm_display_mode *mode,
223 struct drm_display_mode *adjusted_mode)
224{
771fe6b9 225 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
5a9bcacc
AD		 226 struct drm_device *dev = encoder->dev;
227 struct radeon_device *rdev = dev->dev_private;
771fe6b9 228
771fe6b9
JG		 229 drm_mode_set_crtcinfo(adjusted_mode, 0);
230
231 if (radeon_encoder->rmx_type != RMX_OFF)
232 radeon_rmx_mode_fixup(encoder, mode, adjusted_mode);
233
234 /* hw bug */
235 if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
236 && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
237 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
238
5a9bcacc
AD		 239 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
240 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
241 if (tv_dac) {
242 if (tv_dac->tv_std == TV_STD_NTSC ||
243 tv_dac->tv_std == TV_STD_NTSC_J ||
244 tv_dac->tv_std == TV_STD_PAL_M)
245 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
246 else
247 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
248 }
249 }
250
771fe6b9
JG		 251 return true;
252}
253
254static void
255atombios_dac_setup(struct drm_encoder *encoder, int action)
256{
257 struct drm_device *dev = encoder->dev;
258 struct radeon_device *rdev = dev->dev_private;
259 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
260 DAC_ENCODER_CONTROL_PS_ALLOCATION args;
261 int index = 0, num = 0;
445282db 262 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
771fe6b9
JG		 263 enum radeon_tv_std tv_std = TV_STD_NTSC;
264
445282db
DA		 265 if (dac_info->tv_std)
266 tv_std = dac_info->tv_std;
267
771fe6b9
JG		 268 memset(&args, 0, sizeof(args));
269
270 switch (radeon_encoder->encoder_id) {
271 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
272 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
273 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
274 num = 1;
275 break;
276 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
277 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
278 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
279 num = 2;
280 break;
281 }
282
283 args.ucAction = action;
284
4ce001ab 285 if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
771fe6b9 286 args.ucDacStandard = ATOM_DAC1_PS2;
4ce001ab 287 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
771fe6b9
JG		 288 args.ucDacStandard = ATOM_DAC1_CV;
289 else {
290 switch (tv_std) {
291 case TV_STD_PAL:
292 case TV_STD_PAL_M:
293 case TV_STD_SCART_PAL:
294 case TV_STD_SECAM:
295 case TV_STD_PAL_CN:
296 args.ucDacStandard = ATOM_DAC1_PAL;
297 break;
298 case TV_STD_NTSC:
299 case TV_STD_NTSC_J:
300 case TV_STD_PAL_60:
301 default:
302 args.ucDacStandard = ATOM_DAC1_NTSC;
303 break;
304 }
305 }
306 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
307
308 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
309
310}
311
312static void
313atombios_tv_setup(struct drm_encoder *encoder, int action)
314{
315 struct drm_device *dev = encoder->dev;
316 struct radeon_device *rdev = dev->dev_private;
317 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
318 TV_ENCODER_CONTROL_PS_ALLOCATION args;
319 int index = 0;
445282db 320 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
771fe6b9
JG		 321 enum radeon_tv_std tv_std = TV_STD_NTSC;
322
445282db
DA		 323 if (dac_info->tv_std)
324 tv_std = dac_info->tv_std;
325
771fe6b9
JG		 326 memset(&args, 0, sizeof(args));
327
328 index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
329
330 args.sTVEncoder.ucAction = action;
331
4ce001ab 332 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
771fe6b9
JG		 333 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
334 else {
335 switch (tv_std) {
336 case TV_STD_NTSC:
337 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
338 break;
339 case TV_STD_PAL:
340 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
341 break;
342 case TV_STD_PAL_M:
343 args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
344 break;
345 case TV_STD_PAL_60:
346 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
347 break;
348 case TV_STD_NTSC_J:
349 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
350 break;
351 case TV_STD_SCART_PAL:
352 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
353 break;
354 case TV_STD_SECAM:
355 args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
356 break;
357 case TV_STD_PAL_CN:
358 args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
359 break;
360 default:
361 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
362 break;
363 }
364 }
365
366 args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
367
368 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
369
370}
371
372void
373atombios_external_tmds_setup(struct drm_encoder *encoder, int action)
374{
375 struct drm_device *dev = encoder->dev;
376 struct radeon_device *rdev = dev->dev_private;
377 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
378 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION args;
379 int index = 0;
380
381 memset(&args, 0, sizeof(args));
382
383 index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
384
385 args.sXTmdsEncoder.ucEnable = action;
386
387 if (radeon_encoder->pixel_clock > 165000)
388 args.sXTmdsEncoder.ucMisc = PANEL_ENCODER_MISC_DUAL;
389
390 /*if (pScrn->rgbBits == 8)*/
391 args.sXTmdsEncoder.ucMisc |= (1 << 1);
392
393 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
394
395}
396
397static void
398atombios_ddia_setup(struct drm_encoder *encoder, int action)
399{
400 struct drm_device *dev = encoder->dev;
401 struct radeon_device *rdev = dev->dev_private;
402 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
403 DVO_ENCODER_CONTROL_PS_ALLOCATION args;
404 int index = 0;
405
406 memset(&args, 0, sizeof(args));
407
408 index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
409
410 args.sDVOEncoder.ucAction = action;
411 args.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
412
413 if (radeon_encoder->pixel_clock > 165000)
414 args.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute = PANEL_ENCODER_MISC_DUAL;
415
416 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
417
418}
419
420union lvds_encoder_control {
421 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1;
422 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
423};
424
425static void
426atombios_digital_setup(struct drm_encoder *encoder, int action)
427{
428 struct drm_device *dev = encoder->dev;
429 struct radeon_device *rdev = dev->dev_private;
430 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
431 union lvds_encoder_control args;
432 int index = 0;
433 uint8_t frev, crev;
434 struct radeon_encoder_atom_dig *dig;
435 struct drm_connector *connector;
436 struct radeon_connector *radeon_connector;
437 struct radeon_connector_atom_dig *dig_connector;
438
439 connector = radeon_get_connector_for_encoder(encoder);
440 if (!connector)
441 return;
442
443 radeon_connector = to_radeon_connector(connector);
444
445 if (!radeon_encoder->enc_priv)
446 return;
447
448 dig = radeon_encoder->enc_priv;
449
450 if (!radeon_connector->con_priv)
451 return;
452
453 dig_connector = radeon_connector->con_priv;
454
455 memset(&args, 0, sizeof(args));
456
457 switch (radeon_encoder->encoder_id) {
458 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
459 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
460 break;
461 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
462 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
463 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
464 break;
465 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
466 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
467 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
468 else
469 index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
470 break;
471 }
472
473 atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
474
475 switch (frev) {
476 case 1:
477 case 2:
478 switch (crev) {
479 case 1:
480 args.v1.ucMisc = 0;
481 args.v1.ucAction = action;
482 if (drm_detect_hdmi_monitor((struct edid *)connector->edid_blob_ptr))
483 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
484 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
485 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
486 if (dig->lvds_misc & (1 << 0))
487 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
488 if (dig->lvds_misc & (1 << 1))
489 args.v1.ucMisc |= (1 << 1);
490 } else {
491 if (dig_connector->linkb)
492 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
493 if (radeon_encoder->pixel_clock > 165000)
494 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
495 /*if (pScrn->rgbBits == 8) */
496 args.v1.ucMisc |= (1 << 1);
497 }
498 break;
499 case 2:
500 case 3:
501 args.v2.ucMisc = 0;
502 args.v2.ucAction = action;
503 if (crev == 3) {
504 if (dig->coherent_mode)
505 args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
506 }
507 if (drm_detect_hdmi_monitor((struct edid *)connector->edid_blob_ptr))
508 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
509 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
510 args.v2.ucTruncate = 0;
511 args.v2.ucSpatial = 0;
512 args.v2.ucTemporal = 0;
513 args.v2.ucFRC = 0;
514 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
515 if (dig->lvds_misc & (1 << 0))
516 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
517 if (dig->lvds_misc & (1 << 5)) {
518 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
519 if (dig->lvds_misc & (1 << 1))
520 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
521 }
522 if (dig->lvds_misc & (1 << 6)) {
523 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
524 if (dig->lvds_misc & (1 << 1))
525 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
526 if (((dig->lvds_misc >> 2) & 0x3) == 2)
527 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
528 }
529 } else {
530 if (dig_connector->linkb)
531 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
532 if (radeon_encoder->pixel_clock > 165000)
533 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
534 }
535 break;
536 default:
537 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
538 break;
539 }
540 break;
541 default:
542 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
543 break;
544 }
545
546 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
547
548}
549
550int
551atombios_get_encoder_mode(struct drm_encoder *encoder)
552{
553 struct drm_connector *connector;
554 struct radeon_connector *radeon_connector;
555
556 connector = radeon_get_connector_for_encoder(encoder);
557 if (!connector)
558 return 0;
559
560 radeon_connector = to_radeon_connector(connector);
561
562 switch (connector->connector_type) {
563 case DRM_MODE_CONNECTOR_DVII:
705af9c7 564 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
771fe6b9
JG		 565 if (drm_detect_hdmi_monitor((struct edid *)connector->edid_blob_ptr))
566 return ATOM_ENCODER_MODE_HDMI;
567 else if (radeon_connector->use_digital)
568 return ATOM_ENCODER_MODE_DVI;
569 else
570 return ATOM_ENCODER_MODE_CRT;
571 break;
572 case DRM_MODE_CONNECTOR_DVID:
573 case DRM_MODE_CONNECTOR_HDMIA:
771fe6b9
JG		 574 default:
575 if (drm_detect_hdmi_monitor((struct edid *)connector->edid_blob_ptr))
576 return ATOM_ENCODER_MODE_HDMI;
577 else
578 return ATOM_ENCODER_MODE_DVI;
579 break;
580 case DRM_MODE_CONNECTOR_LVDS:
581 return ATOM_ENCODER_MODE_LVDS;
582 break;
583 case DRM_MODE_CONNECTOR_DisplayPort:
584 /*if (radeon_output->MonType == MT_DP)
585 return ATOM_ENCODER_MODE_DP;
586 else*/
587 if (drm_detect_hdmi_monitor((struct edid *)connector->edid_blob_ptr))
588 return ATOM_ENCODER_MODE_HDMI;
589 else
590 return ATOM_ENCODER_MODE_DVI;
591 break;
592 case CONNECTOR_DVI_A:
593 case CONNECTOR_VGA:
594 return ATOM_ENCODER_MODE_CRT;
595 break;
596 case CONNECTOR_STV:
597 case CONNECTOR_CTV:
598 case CONNECTOR_DIN:
599 /* fix me */
600 return ATOM_ENCODER_MODE_TV;
601 /*return ATOM_ENCODER_MODE_CV;*/
602 break;
603 }
604}
605
606static void
607atombios_dig_encoder_setup(struct drm_encoder *encoder, int action)
608{
609 struct drm_device *dev = encoder->dev;
610 struct radeon_device *rdev = dev->dev_private;
611 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
612 DIG_ENCODER_CONTROL_PS_ALLOCATION args;
613 int index = 0, num = 0;
614 uint8_t frev, crev;
615 struct radeon_encoder_atom_dig *dig;
616 struct drm_connector *connector;
617 struct radeon_connector *radeon_connector;
618 struct radeon_connector_atom_dig *dig_connector;
619
620 connector = radeon_get_connector_for_encoder(encoder);
621 if (!connector)
622 return;
623
624 radeon_connector = to_radeon_connector(connector);
625
626 if (!radeon_connector->con_priv)
627 return;
628
629 dig_connector = radeon_connector->con_priv;
630
631 if (!radeon_encoder->enc_priv)
632 return;
633
634 dig = radeon_encoder->enc_priv;
635
636 memset(&args, 0, sizeof(args));
637
638 if (ASIC_IS_DCE32(rdev)) {
639 if (dig->dig_block)
640 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
641 else
642 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
643 num = dig->dig_block + 1;
644 } else {
645 switch (radeon_encoder->encoder_id) {
646 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
647 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
648 num = 1;
649 break;
650 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
651 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
652 num = 2;
653 break;
654 }
655 }
656
657 atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
658
659 args.ucAction = action;
660 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
661
662 if (ASIC_IS_DCE32(rdev)) {
663 switch (radeon_encoder->encoder_id) {
664 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
665 args.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
666 break;
667 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
668 args.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
669 break;
670 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
671 args.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
672 break;
673 }
674 } else {
675 switch (radeon_encoder->encoder_id) {
676 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
677 args.ucConfig = ATOM_ENCODER_CONFIG_TRANSMITTER1;
678 break;
679 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
680 args.ucConfig = ATOM_ENCODER_CONFIG_TRANSMITTER2;
681 break;
682 }
683 }
684
685 if (radeon_encoder->pixel_clock > 165000) {
686 args.ucConfig |= ATOM_ENCODER_CONFIG_LINKA_B;
687 args.ucLaneNum = 8;
688 } else {
689 if (dig_connector->linkb)
690 args.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
691 else
692 args.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
693 args.ucLaneNum = 4;
694 }
695
696 args.ucEncoderMode = atombios_get_encoder_mode(encoder);
697
698 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
699
700}
701
702union dig_transmitter_control {
703 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
704 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
705};
706
707static void
708atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action)
709{
710 struct drm_device *dev = encoder->dev;
711 struct radeon_device *rdev = dev->dev_private;
712 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
713 union dig_transmitter_control args;
714 int index = 0, num = 0;
715 uint8_t frev, crev;
716 struct radeon_encoder_atom_dig *dig;
717 struct drm_connector *connector;
718 struct radeon_connector *radeon_connector;
719 struct radeon_connector_atom_dig *dig_connector;
720
721 connector = radeon_get_connector_for_encoder(encoder);
722 if (!connector)
723 return;
724
725 radeon_connector = to_radeon_connector(connector);
726
727 if (!radeon_encoder->enc_priv)
728 return;
729
730 dig = radeon_encoder->enc_priv;
731
732 if (!radeon_connector->con_priv)
733 return;
734
735 dig_connector = radeon_connector->con_priv;
736
737 memset(&args, 0, sizeof(args));
738
739 if (ASIC_IS_DCE32(rdev))
740 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
741 else {
742 switch (radeon_encoder->encoder_id) {
743 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
744 index = GetIndexIntoMasterTable(COMMAND, DIG1TransmitterControl);
745 break;
746 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
747 index = GetIndexIntoMasterTable(COMMAND, DIG2TransmitterControl);
748 break;
749 }
750 }
751
752 atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
753
754 args.v1.ucAction = action;
755
756 if (ASIC_IS_DCE32(rdev)) {
757 if (radeon_encoder->pixel_clock > 165000) {
758 args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock * 10 * 2) / 100);
759 args.v2.acConfig.fDualLinkConnector = 1;
760 } else {
761 args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock * 10 * 4) / 100);
762 }
763 if (dig->dig_block)
764 args.v2.acConfig.ucEncoderSel = 1;
765
766 switch (radeon_encoder->encoder_id) {
767 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
768 args.v2.acConfig.ucTransmitterSel = 0;
769 num = 0;
770 break;
771 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
772 args.v2.acConfig.ucTransmitterSel = 1;
773 num = 1;
774 break;
775 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
776 args.v2.acConfig.ucTransmitterSel = 2;
777 num = 2;
778 break;
779 }
780
781 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
782 if (dig->coherent_mode)
783 args.v2.acConfig.fCoherentMode = 1;
784 }
785 } else {
786 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
787 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock) / 10);
788
789 switch (radeon_encoder->encoder_id) {
790 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
791 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
792 if (rdev->flags & RADEON_IS_IGP) {
793 if (radeon_encoder->pixel_clock > 165000) {
794 args.v1.ucConfig |= (ATOM_TRANSMITTER_CONFIG_8LANE_LINK |
795 ATOM_TRANSMITTER_CONFIG_LINKA_B);
796 if (dig_connector->igp_lane_info & 0x3)
797 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
798 else if (dig_connector->igp_lane_info & 0xc)
799 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
800 } else {
801 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
802 if (dig_connector->igp_lane_info & 0x1)
803 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
804 else if (dig_connector->igp_lane_info & 0x2)
805 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
806 else if (dig_connector->igp_lane_info & 0x4)
807 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
808 else if (dig_connector->igp_lane_info & 0x8)
809 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
810 }
811 } else {
812 if (radeon_encoder->pixel_clock > 165000)
813 args.v1.ucConfig |= (ATOM_TRANSMITTER_CONFIG_8LANE_LINK |
814 ATOM_TRANSMITTER_CONFIG_LINKA_B |
815 ATOM_TRANSMITTER_CONFIG_LANE_0_7);
816 else {
817 if (dig_connector->linkb)
818 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB | ATOM_TRANSMITTER_CONFIG_LANE_0_3;
819 else
820 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA | ATOM_TRANSMITTER_CONFIG_LANE_0_3;
821 }
822 }
823 break;
824 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
825 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
826 if (radeon_encoder->pixel_clock > 165000)
827 args.v1.ucConfig |= (ATOM_TRANSMITTER_CONFIG_8LANE_LINK |
828 ATOM_TRANSMITTER_CONFIG_LINKA_B |
829 ATOM_TRANSMITTER_CONFIG_LANE_0_7);
830 else {
831 if (dig_connector->linkb)
832 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB | ATOM_TRANSMITTER_CONFIG_LANE_0_3;
833 else
834 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA | ATOM_TRANSMITTER_CONFIG_LANE_0_3;
835 }
836 break;
837 }
838
839 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
840 if (dig->coherent_mode)
841 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
842 }
843 }
844
845 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
846
847}
848
771fe6b9
JG		 849static void
850atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
851{
852 struct drm_device *dev = encoder->dev;
853 struct radeon_device *rdev = dev->dev_private;
854 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
855 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
856 ENABLE_YUV_PS_ALLOCATION args;
857 int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
858 uint32_t temp, reg;
859
860 memset(&args, 0, sizeof(args));
861
862 if (rdev->family >= CHIP_R600)
863 reg = R600_BIOS_3_SCRATCH;
864 else
865 reg = RADEON_BIOS_3_SCRATCH;
866
867 /* XXX: fix up scratch reg handling */
868 temp = RREG32(reg);
4ce001ab 869 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
771fe6b9
JG		 870 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
871 (radeon_crtc->crtc_id << 18)));
4ce001ab 872 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
771fe6b9
JG		 873 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
874 else
875 WREG32(reg, 0);
876
877 if (enable)
878 args.ucEnable = ATOM_ENABLE;
879 args.ucCRTC = radeon_crtc->crtc_id;
880
881 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
882
883 WREG32(reg, temp);
884}
885
771fe6b9
JG		 886static void
887radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
888{
889 struct drm_device *dev = encoder->dev;
890 struct radeon_device *rdev = dev->dev_private;
891 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
892 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
893 int index = 0;
894 bool is_dig = false;
4ce001ab 895 int devices;
771fe6b9
JG		 896
897 memset(&args, 0, sizeof(args));
898
4ce001ab
DA		 899 /* on DPMS off we have no idea if active device is meaningful */
900 if (mode != DRM_MODE_DPMS_ON && !radeon_encoder->active_device)
901 devices = radeon_encoder->devices;
902 else
903 devices = radeon_encoder->active_device;
904
f641e51e
DA		 905 DRM_DEBUG("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
906 radeon_encoder->encoder_id, mode, radeon_encoder->devices,
907 radeon_encoder->active_device);
771fe6b9
JG		 908 switch (radeon_encoder->encoder_id) {
909 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
910 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
911 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
912 break;
913 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
914 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
915 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
916 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
917 is_dig = true;
918 break;
919 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
920 case ENCODER_OBJECT_ID_INTERNAL_DDI:
921 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
922 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
923 break;
924 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
925 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
926 break;
927 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
928 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
929 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
930 else
931 index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
932 break;
933 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
934 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
4ce001ab 935 if (devices & (ATOM_DEVICE_TV_SUPPORT))
771fe6b9 936 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
4ce001ab 937 else if (devices & (ATOM_DEVICE_CV_SUPPORT))
771fe6b9
JG		 938 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
939 else
940 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
941 break;
942 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
943 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
4ce001ab 944 if (devices & (ATOM_DEVICE_TV_SUPPORT))
771fe6b9 945 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
4ce001ab 946 else if (devices & (ATOM_DEVICE_CV_SUPPORT))
771fe6b9
JG		 947 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
948 else
949 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
950 break;
951 }
952
953 if (is_dig) {
954 switch (mode) {
955 case DRM_MODE_DPMS_ON:
956 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE);
957 break;
958 case DRM_MODE_DPMS_STANDBY:
959 case DRM_MODE_DPMS_SUSPEND:
960 case DRM_MODE_DPMS_OFF:
961 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE);
962 break;
963 }
964 } else {
965 switch (mode) {
966 case DRM_MODE_DPMS_ON:
967 args.ucAction = ATOM_ENABLE;
968 break;
969 case DRM_MODE_DPMS_STANDBY:
970 case DRM_MODE_DPMS_SUSPEND:
971 case DRM_MODE_DPMS_OFF:
972 args.ucAction = ATOM_DISABLE;
973 break;
974 }
975 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
976 }
977 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
978}
979
980union crtc_sourc_param {
981 SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
982 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
983};
984
985static void
986atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
987{
988 struct drm_device *dev = encoder->dev;
989 struct radeon_device *rdev = dev->dev_private;
990 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
991 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
992 union crtc_sourc_param args;
993 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
994 uint8_t frev, crev;
995
996 memset(&args, 0, sizeof(args));
997
998 atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
999
1000 switch (frev) {
1001 case 1:
1002 switch (crev) {
1003 case 1:
1004 default:
1005 if (ASIC_IS_AVIVO(rdev))
1006 args.v1.ucCRTC = radeon_crtc->crtc_id;
1007 else {
1008 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1009 args.v1.ucCRTC = radeon_crtc->crtc_id;
1010 } else {
1011 args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1012 }
1013 }
1014 switch (radeon_encoder->encoder_id) {
1015 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1016 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1017 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1018 break;
1019 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1020 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1021 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1022 args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1023 else
1024 args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1025 break;
1026 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1027 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1028 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1029 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1030 break;
1031 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1032 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
4ce001ab 1033 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
771fe6b9 1034 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
4ce001ab 1035 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
771fe6b9
JG		 1036 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1037 else
1038 args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1039 break;
1040 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1041 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
4ce001ab 1042 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
771fe6b9 1043 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
4ce001ab 1044 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
771fe6b9
JG		 1045 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1046 else
1047 args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1048 break;
1049 }
1050 break;
1051 case 2:
1052 args.v2.ucCRTC = radeon_crtc->crtc_id;
1053 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1054 switch (radeon_encoder->encoder_id) {
1055 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1056 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1057 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1058 if (ASIC_IS_DCE32(rdev)) {
1059 if (radeon_crtc->crtc_id)
1060 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1061 else
1062 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1063 } else
1064 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1065 break;
1066 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1067 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1068 break;
1069 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1070 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1071 break;
1072 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
4ce001ab 1073 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
771fe6b9 1074 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
4ce001ab 1075 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
771fe6b9
JG		 1076 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1077 else
1078 args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1079 break;
1080 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
4ce001ab 1081 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
771fe6b9 1082 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
4ce001ab 1083 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
771fe6b9
JG		 1084 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1085 else
1086 args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1087 break;
1088 }
1089 break;
1090 }
1091 break;
1092 default:
1093 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1094 break;
1095 }
1096
1097 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1098
1099}
1100
1101static void
1102atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1103 struct drm_display_mode *mode)
1104{
1105 struct drm_device *dev = encoder->dev;
1106 struct radeon_device *rdev = dev->dev_private;
1107 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1108 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1109
1110 /* Funky macbooks */
1111 if ((dev->pdev->device == 0x71C5) &&
1112 (dev->pdev->subsystem_vendor == 0x106b) &&
1113 (dev->pdev->subsystem_device == 0x0080)) {
1114 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1115 uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1116
1117 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
1118 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
1119
1120 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
1121 }
1122 }
1123
1124 /* set scaler clears this on some chips */
1125 if (ASIC_IS_AVIVO(rdev) && (mode->flags & DRM_MODE_FLAG_INTERLACE))
1126 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, AVIVO_D1MODE_INTERLEAVE_EN);
1127}
1128
1129static void
1130radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1131 struct drm_display_mode *mode,
1132 struct drm_display_mode *adjusted_mode)
1133{
1134 struct drm_device *dev = encoder->dev;
1135 struct radeon_device *rdev = dev->dev_private;
1136 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1137 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1138
1139 if (radeon_encoder->enc_priv) {
1140 struct radeon_encoder_atom_dig *dig;
1141
1142 dig = radeon_encoder->enc_priv;
1143 dig->dig_block = radeon_crtc->crtc_id;
1144 }
1145 radeon_encoder->pixel_clock = adjusted_mode->clock;
1146
1147 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
771fe6b9
JG		 1148 atombios_set_encoder_crtc_source(encoder);
1149
1150 if (ASIC_IS_AVIVO(rdev)) {
4ce001ab 1151 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
771fe6b9
JG		 1152 atombios_yuv_setup(encoder, true);
1153 else
1154 atombios_yuv_setup(encoder, false);
1155 }
1156
1157 switch (radeon_encoder->encoder_id) {
1158 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1159 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1160 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1161 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1162 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
1163 break;
1164 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1165 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1166 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1167 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1168 /* disable the encoder and transmitter */
1169 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE);
1170 atombios_dig_encoder_setup(encoder, ATOM_DISABLE);
1171
1172 /* setup and enable the encoder and transmitter */
1173 atombios_dig_encoder_setup(encoder, ATOM_ENABLE);
1174 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP);
1175 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE);
1176 break;
1177 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1178 atombios_ddia_setup(encoder, ATOM_ENABLE);
1179 break;
1180 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1181 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1182 atombios_external_tmds_setup(encoder, ATOM_ENABLE);
1183 break;
1184 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1185 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1186 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1187 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1188 atombios_dac_setup(encoder, ATOM_ENABLE);
4ce001ab 1189 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
771fe6b9
JG		 1190 atombios_tv_setup(encoder, ATOM_ENABLE);
1191 break;
1192 }
1193 atombios_apply_encoder_quirks(encoder, adjusted_mode);
1194}
1195
1196static bool
4ce001ab 1197atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
771fe6b9
JG		 1198{
1199 struct drm_device *dev = encoder->dev;
1200 struct radeon_device *rdev = dev->dev_private;
1201 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
4ce001ab 1202 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
771fe6b9
JG		 1203
1204 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
1205 ATOM_DEVICE_CV_SUPPORT |
1206 ATOM_DEVICE_CRT_SUPPORT)) {
1207 DAC_LOAD_DETECTION_PS_ALLOCATION args;
1208 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
1209 uint8_t frev, crev;
1210
1211 memset(&args, 0, sizeof(args));
1212
1213 atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
1214
1215 args.sDacload.ucMisc = 0;
1216
1217 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
1218 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
1219 args.sDacload.ucDacType = ATOM_DAC_A;
1220 else
1221 args.sDacload.ucDacType = ATOM_DAC_B;
1222
4ce001ab 1223 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
771fe6b9 1224 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
4ce001ab 1225 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
771fe6b9 1226 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
4ce001ab 1227 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
771fe6b9
JG		 1228 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
1229 if (crev >= 3)
1230 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
4ce001ab 1231 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
771fe6b9
JG		 1232 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
1233 if (crev >= 3)
1234 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1235 }
1236
1237 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1238
1239 return true;
1240 } else
1241 return false;
1242}
1243
1244static enum drm_connector_status
1245radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1246{
1247 struct drm_device *dev = encoder->dev;
1248 struct radeon_device *rdev = dev->dev_private;
1249 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
4ce001ab 1250 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
771fe6b9
JG		 1251 uint32_t bios_0_scratch;
1252
4ce001ab 1253 if (!atombios_dac_load_detect(encoder, connector)) {
771fe6b9
JG		 1254 DRM_DEBUG("detect returned false \n");
1255 return connector_status_unknown;
1256 }
1257
1258 if (rdev->family >= CHIP_R600)
1259 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
1260 else
1261 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
1262
4ce001ab
DA		 1263 DRM_DEBUG("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
1264 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
771fe6b9
JG		 1265 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
1266 return connector_status_connected;
4ce001ab
DA		 1267 }
1268 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
771fe6b9
JG		 1269 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
1270 return connector_status_connected;
4ce001ab
DA		 1271 }
1272 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
771fe6b9
JG		 1273 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
1274 return connector_status_connected;
4ce001ab
DA		 1275 }
1276 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
771fe6b9
JG		 1277 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
1278 return connector_status_connected; /* CTV */
1279 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
1280 return connector_status_connected; /* STV */
1281 }
1282 return connector_status_disconnected;
1283}
1284
1285static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
1286{
1287 radeon_atom_output_lock(encoder, true);
1288 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
4ce001ab
DA		 1289
1290 radeon_encoder_set_active_device(encoder);
771fe6b9
JG		 1291}
1292
1293static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
1294{
1295 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
1296 radeon_atom_output_lock(encoder, false);
1297}
1298
4ce001ab
DA		 1299static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
1300{
1301 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1302 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
4ce001ab
DA		 1303 radeon_encoder->active_device = 0;
1304}
1305
771fe6b9
JG		 1306static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
1307 .dpms = radeon_atom_encoder_dpms,
1308 .mode_fixup = radeon_atom_mode_fixup,
1309 .prepare = radeon_atom_encoder_prepare,
1310 .mode_set = radeon_atom_encoder_mode_set,
1311 .commit = radeon_atom_encoder_commit,
4ce001ab 1312 .disable = radeon_atom_encoder_disable,
771fe6b9
JG		 1313 /* no detect for TMDS/LVDS yet */
1314};
1315
1316static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
1317 .dpms = radeon_atom_encoder_dpms,
1318 .mode_fixup = radeon_atom_mode_fixup,
1319 .prepare = radeon_atom_encoder_prepare,
1320 .mode_set = radeon_atom_encoder_mode_set,
1321 .commit = radeon_atom_encoder_commit,
1322 .detect = radeon_atom_dac_detect,
1323};
1324
1325void radeon_enc_destroy(struct drm_encoder *encoder)
1326{
1327 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1328 kfree(radeon_encoder->enc_priv);
1329 drm_encoder_cleanup(encoder);
1330 kfree(radeon_encoder);
1331}
1332
1333static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
1334 .destroy = radeon_enc_destroy,
1335};
1336
4ce001ab
DA		 1337struct radeon_encoder_atom_dac *
1338radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
1339{
1340 struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
1341
1342 if (!dac)
1343 return NULL;
1344
1345 dac->tv_std = TV_STD_NTSC;
1346 return dac;
1347}
1348
771fe6b9
JG		 1349struct radeon_encoder_atom_dig *
1350radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
1351{
1352 struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1353
1354 if (!dig)
1355 return NULL;
1356
1357 /* coherent mode by default */
1358 dig->coherent_mode = true;
1359
1360 return dig;
1361}
1362
1363void
1364radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t supported_device)
1365{
dfee5614 1366 struct radeon_device *rdev = dev->dev_private;
771fe6b9
JG		 1367 struct drm_encoder *encoder;
1368 struct radeon_encoder *radeon_encoder;
1369
1370 /* see if we already added it */
1371 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1372 radeon_encoder = to_radeon_encoder(encoder);
1373 if (radeon_encoder->encoder_id == encoder_id) {
1374 radeon_encoder->devices |= supported_device;
1375 return;
1376 }
1377
1378 }
1379
1380 /* add a new one */
1381 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
1382 if (!radeon_encoder)
1383 return;
1384
1385 encoder = &radeon_encoder->base;
dfee5614
DA		 1386 if (rdev->flags & RADEON_SINGLE_CRTC)
1387 encoder->possible_crtcs = 0x1;
1388 else
1389 encoder->possible_crtcs = 0x3;
771fe6b9
JG		 1390 encoder->possible_clones = 0;
1391
1392 radeon_encoder->enc_priv = NULL;
1393
1394 radeon_encoder->encoder_id = encoder_id;
1395 radeon_encoder->devices = supported_device;
c93bb85b 1396 radeon_encoder->rmx_type = RMX_OFF;
771fe6b9
JG		 1397
1398 switch (radeon_encoder->encoder_id) {
1399 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1400 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1401 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1402 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1403 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1404 radeon_encoder->rmx_type = RMX_FULL;
1405 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
1406 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1407 } else {
1408 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
1409 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
1410 }
1411 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
1412 break;
1413 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1414 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
1415 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
1416 break;
1417 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1418 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1419 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1420 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
4ce001ab 1421 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
771fe6b9
JG		 1422 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
1423 break;
1424 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1425 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1426 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1427 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1428 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1429 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1430 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
60d15f55
AD		 1431 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1432 radeon_encoder->rmx_type = RMX_FULL;
1433 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
1434 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1435 } else {
1436 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
1437 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
1438 }
771fe6b9
JG		 1439 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
1440 break;
1441 }
1442}
Clone of davem's net-next-2.6 tree