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drm/radeon/kms/atom: clean up dig atom handling
[net-next-2.6.git] / drivers / gpu / drm / radeon / radeon_encoders.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26#include "drmP.h"
27#include "drm_crtc_helper.h"
28#include "radeon_drm.h"
29#include "radeon.h"
30#include "atom.h"
31
32extern int atom_debug;
33
5a9bcacc
AD		 34/* evil but including atombios.h is much worse */
35bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
36 struct drm_display_mode *mode);
37
1f3b6a45
DA		 38static uint32_t radeon_encoder_clones(struct drm_encoder *encoder)
39{
40 struct drm_device *dev = encoder->dev;
41 struct radeon_device *rdev = dev->dev_private;
42 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
43 struct drm_encoder *clone_encoder;
44 uint32_t index_mask = 0;
45 int count;
46
47 /* DIG routing gets problematic */
48 if (rdev->family >= CHIP_R600)
49 return index_mask;
50 /* LVDS/TV are too wacky */
51 if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
52 return index_mask;
53 /* DVO requires 2x ppll clocks depending on tmds chip */
54 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT)
55 return index_mask;
bcc1c2a1 56
1f3b6a45
DA		 57 count = -1;
58 list_for_each_entry(clone_encoder, &dev->mode_config.encoder_list, head) {
59 struct radeon_encoder *radeon_clone = to_radeon_encoder(clone_encoder);
60 count++;
61
62 if (clone_encoder == encoder)
63 continue;
64 if (radeon_clone->devices & (ATOM_DEVICE_LCD_SUPPORT))
65 continue;
66 if (radeon_clone->devices & ATOM_DEVICE_DFP2_SUPPORT)
67 continue;
68 else
69 index_mask |= (1 << count);
70 }
71 return index_mask;
72}
73
74void radeon_setup_encoder_clones(struct drm_device *dev)
75{
76 struct drm_encoder *encoder;
77
78 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
79 encoder->possible_clones = radeon_encoder_clones(encoder);
80 }
81}
82
771fe6b9 83uint32_t
5137ee94 84radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device, uint8_t dac)
771fe6b9
JG		 85{
86 struct radeon_device *rdev = dev->dev_private;
87 uint32_t ret = 0;
88
89 switch (supported_device) {
90 case ATOM_DEVICE_CRT1_SUPPORT:
91 case ATOM_DEVICE_TV1_SUPPORT:
92 case ATOM_DEVICE_TV2_SUPPORT:
93 case ATOM_DEVICE_CRT2_SUPPORT:
94 case ATOM_DEVICE_CV_SUPPORT:
95 switch (dac) {
96 case 1: /* dac a */
97 if ((rdev->family == CHIP_RS300) ||
98 (rdev->family == CHIP_RS400) ||
99 (rdev->family == CHIP_RS480))
5137ee94 100 ret = ENCODER_INTERNAL_DAC2_ENUM_ID1;
771fe6b9 101 else if (ASIC_IS_AVIVO(rdev))
5137ee94 102 ret = ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1;
771fe6b9 103 else
5137ee94 104 ret = ENCODER_INTERNAL_DAC1_ENUM_ID1;
771fe6b9
JG		 105 break;
106 case 2: /* dac b */
107 if (ASIC_IS_AVIVO(rdev))
5137ee94 108 ret = ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1;
771fe6b9
JG		 109 else {
110 /*if (rdev->family == CHIP_R200)
5137ee94 111 ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
771fe6b9 112 else*/
5137ee94 113 ret = ENCODER_INTERNAL_DAC2_ENUM_ID1;
771fe6b9
JG		 114 }
115 break;
116 case 3: /* external dac */
117 if (ASIC_IS_AVIVO(rdev))
5137ee94 118 ret = ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1;
771fe6b9 119 else
5137ee94 120 ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
771fe6b9
JG		 121 break;
122 }
123 break;
124 case ATOM_DEVICE_LCD1_SUPPORT:
125 if (ASIC_IS_AVIVO(rdev))
5137ee94 126 ret = ENCODER_INTERNAL_LVTM1_ENUM_ID1;
771fe6b9 127 else
5137ee94 128 ret = ENCODER_INTERNAL_LVDS_ENUM_ID1;
771fe6b9
JG		 129 break;
130 case ATOM_DEVICE_DFP1_SUPPORT:
131 if ((rdev->family == CHIP_RS300) ||
132 (rdev->family == CHIP_RS400) ||
133 (rdev->family == CHIP_RS480))
5137ee94 134 ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
771fe6b9 135 else if (ASIC_IS_AVIVO(rdev))
5137ee94 136 ret = ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1;
771fe6b9 137 else
5137ee94 138 ret = ENCODER_INTERNAL_TMDS1_ENUM_ID1;
771fe6b9
JG		 139 break;
140 case ATOM_DEVICE_LCD2_SUPPORT:
141 case ATOM_DEVICE_DFP2_SUPPORT:
142 if ((rdev->family == CHIP_RS600) ||
143 (rdev->family == CHIP_RS690) ||
144 (rdev->family == CHIP_RS740))
5137ee94 145 ret = ENCODER_INTERNAL_DDI_ENUM_ID1;
771fe6b9 146 else if (ASIC_IS_AVIVO(rdev))
5137ee94 147 ret = ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1;
771fe6b9 148 else
5137ee94 149 ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
771fe6b9
JG		 150 break;
151 case ATOM_DEVICE_DFP3_SUPPORT:
5137ee94 152 ret = ENCODER_INTERNAL_LVTM1_ENUM_ID1;
771fe6b9
JG		 153 break;
154 }
155
156 return ret;
157}
158
f28cf339
DA		 159static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder)
160{
161 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
162 switch (radeon_encoder->encoder_id) {
163 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
164 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
165 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
166 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
167 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
168 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
169 case ENCODER_OBJECT_ID_INTERNAL_DDI:
170 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
171 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
172 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
173 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
174 return true;
175 default:
176 return false;
177 }
178}
771fe6b9
JG		 179void
180radeon_link_encoder_connector(struct drm_device *dev)
181{
182 struct drm_connector *connector;
183 struct radeon_connector *radeon_connector;
184 struct drm_encoder *encoder;
185 struct radeon_encoder *radeon_encoder;
186
187 /* walk the list and link encoders to connectors */
188 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
189 radeon_connector = to_radeon_connector(connector);
190 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
191 radeon_encoder = to_radeon_encoder(encoder);
192 if (radeon_encoder->devices & radeon_connector->devices)
193 drm_mode_connector_attach_encoder(connector, encoder);
194 }
195 }
196}
197
4ce001ab
DA		 198void radeon_encoder_set_active_device(struct drm_encoder *encoder)
199{
200 struct drm_device *dev = encoder->dev;
201 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
202 struct drm_connector *connector;
203
204 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
205 if (connector->encoder == encoder) {
206 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
207 radeon_encoder->active_device = radeon_encoder->devices & radeon_connector->devices;
d9fdaafb 208 DRM_DEBUG_KMS("setting active device to %08x from %08x %08x for encoder %d\n",
f641e51e
DA		 209 radeon_encoder->active_device, radeon_encoder->devices,
210 radeon_connector->devices, encoder->encoder_type);
4ce001ab
DA		 211 }
212 }
213}
214
5b1714d3 215struct drm_connector *
771fe6b9
JG		 216radeon_get_connector_for_encoder(struct drm_encoder *encoder)
217{
218 struct drm_device *dev = encoder->dev;
219 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
220 struct drm_connector *connector;
221 struct radeon_connector *radeon_connector;
222
223 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
224 radeon_connector = to_radeon_connector(connector);
43c33ed8 225 if (radeon_encoder->active_device & radeon_connector->devices)
771fe6b9
JG		 226 return connector;
227 }
228 return NULL;
229}
230
3515387b
AD		 231void radeon_panel_mode_fixup(struct drm_encoder *encoder,
232 struct drm_display_mode *adjusted_mode)
233{
234 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
235 struct drm_device *dev = encoder->dev;
236 struct radeon_device *rdev = dev->dev_private;
237 struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
238 unsigned hblank = native_mode->htotal - native_mode->hdisplay;
239 unsigned vblank = native_mode->vtotal - native_mode->vdisplay;
240 unsigned hover = native_mode->hsync_start - native_mode->hdisplay;
241 unsigned vover = native_mode->vsync_start - native_mode->vdisplay;
242 unsigned hsync_width = native_mode->hsync_end - native_mode->hsync_start;
243 unsigned vsync_width = native_mode->vsync_end - native_mode->vsync_start;
244
245 adjusted_mode->clock = native_mode->clock;
246 adjusted_mode->flags = native_mode->flags;
247
248 if (ASIC_IS_AVIVO(rdev)) {
249 adjusted_mode->hdisplay = native_mode->hdisplay;
250 adjusted_mode->vdisplay = native_mode->vdisplay;
251 }
252
253 adjusted_mode->htotal = native_mode->hdisplay + hblank;
254 adjusted_mode->hsync_start = native_mode->hdisplay + hover;
255 adjusted_mode->hsync_end = adjusted_mode->hsync_start + hsync_width;
256
257 adjusted_mode->vtotal = native_mode->vdisplay + vblank;
258 adjusted_mode->vsync_start = native_mode->vdisplay + vover;
259 adjusted_mode->vsync_end = adjusted_mode->vsync_start + vsync_width;
260
261 drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
262
263 if (ASIC_IS_AVIVO(rdev)) {
264 adjusted_mode->crtc_hdisplay = native_mode->hdisplay;
265 adjusted_mode->crtc_vdisplay = native_mode->vdisplay;
266 }
267
268 adjusted_mode->crtc_htotal = adjusted_mode->crtc_hdisplay + hblank;
269 adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hdisplay + hover;
270 adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_start + hsync_width;
271
272 adjusted_mode->crtc_vtotal = adjusted_mode->crtc_vdisplay + vblank;
273 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + vover;
274 adjusted_mode->crtc_vsync_end = adjusted_mode->crtc_vsync_start + vsync_width;
275
276}
277
771fe6b9
JG		 278static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
279 struct drm_display_mode *mode,
280 struct drm_display_mode *adjusted_mode)
281{
771fe6b9 282 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
5a9bcacc
AD		 283 struct drm_device *dev = encoder->dev;
284 struct radeon_device *rdev = dev->dev_private;
771fe6b9 285
8c2a6d73
AD		 286 /* set the active encoder to connector routing */
287 radeon_encoder_set_active_device(encoder);
771fe6b9
JG		 288 drm_mode_set_crtcinfo(adjusted_mode, 0);
289
771fe6b9
JG		 290 /* hw bug */
291 if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
292 && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
293 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
294
80297e87 295 /* get the native mode for LVDS */
3515387b
AD		 296 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
297 radeon_panel_mode_fixup(encoder, adjusted_mode);
80297e87
AD		 298
299 /* get the native mode for TV */
ceefedd8 300 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
5a9bcacc
AD		 301 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
302 if (tv_dac) {
303 if (tv_dac->tv_std == TV_STD_NTSC ||
304 tv_dac->tv_std == TV_STD_NTSC_J ||
305 tv_dac->tv_std == TV_STD_PAL_M)
306 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
307 else
308 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
309 }
310 }
311
5801ead6 312 if (ASIC_IS_DCE3(rdev) &&
9f998ad7 313 (radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT))) {
5801ead6
AD		 314 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
315 radeon_dp_set_link_config(connector, mode);
316 }
317
771fe6b9
JG		 318 return true;
319}
320
321static void
322atombios_dac_setup(struct drm_encoder *encoder, int action)
323{
324 struct drm_device *dev = encoder->dev;
325 struct radeon_device *rdev = dev->dev_private;
326 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
327 DAC_ENCODER_CONTROL_PS_ALLOCATION args;
affd8589 328 int index = 0;
445282db 329 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
445282db 330
771fe6b9
JG		 331 memset(&args, 0, sizeof(args));
332
333 switch (radeon_encoder->encoder_id) {
334 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
335 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
336 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
771fe6b9
JG		 337 break;
338 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
339 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
340 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
771fe6b9
JG		 341 break;
342 }
343
344 args.ucAction = action;
345
4ce001ab 346 if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
771fe6b9 347 args.ucDacStandard = ATOM_DAC1_PS2;
4ce001ab 348 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
771fe6b9
JG		 349 args.ucDacStandard = ATOM_DAC1_CV;
350 else {
affd8589 351 switch (dac_info->tv_std) {
771fe6b9
JG		 352 case TV_STD_PAL:
353 case TV_STD_PAL_M:
354 case TV_STD_SCART_PAL:
355 case TV_STD_SECAM:
356 case TV_STD_PAL_CN:
357 args.ucDacStandard = ATOM_DAC1_PAL;
358 break;
359 case TV_STD_NTSC:
360 case TV_STD_NTSC_J:
361 case TV_STD_PAL_60:
362 default:
363 args.ucDacStandard = ATOM_DAC1_NTSC;
364 break;
365 }
366 }
367 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
368
369 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
370
371}
372
373static void
374atombios_tv_setup(struct drm_encoder *encoder, int action)
375{
376 struct drm_device *dev = encoder->dev;
377 struct radeon_device *rdev = dev->dev_private;
378 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
379 TV_ENCODER_CONTROL_PS_ALLOCATION args;
380 int index = 0;
445282db 381 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
445282db 382
771fe6b9
JG		 383 memset(&args, 0, sizeof(args));
384
385 index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
386
387 args.sTVEncoder.ucAction = action;
388
4ce001ab 389 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
771fe6b9
JG		 390 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
391 else {
affd8589 392 switch (dac_info->tv_std) {
771fe6b9
JG		 393 case TV_STD_NTSC:
394 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
395 break;
396 case TV_STD_PAL:
397 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
398 break;
399 case TV_STD_PAL_M:
400 args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
401 break;
402 case TV_STD_PAL_60:
403 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
404 break;
405 case TV_STD_NTSC_J:
406 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
407 break;
408 case TV_STD_SCART_PAL:
409 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
410 break;
411 case TV_STD_SECAM:
412 args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
413 break;
414 case TV_STD_PAL_CN:
415 args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
416 break;
417 default:
418 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
419 break;
420 }
421 }
422
423 args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
424
425 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
426
427}
428
429void
430atombios_external_tmds_setup(struct drm_encoder *encoder, int action)
431{
432 struct drm_device *dev = encoder->dev;
433 struct radeon_device *rdev = dev->dev_private;
434 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
435 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION args;
436 int index = 0;
437
438 memset(&args, 0, sizeof(args));
439
440 index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
441
442 args.sXTmdsEncoder.ucEnable = action;
443
444 if (radeon_encoder->pixel_clock > 165000)
445 args.sXTmdsEncoder.ucMisc = PANEL_ENCODER_MISC_DUAL;
446
447 /*if (pScrn->rgbBits == 8)*/
448 args.sXTmdsEncoder.ucMisc |= (1 << 1);
449
450 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
451
452}
453
454static void
455atombios_ddia_setup(struct drm_encoder *encoder, int action)
456{
457 struct drm_device *dev = encoder->dev;
458 struct radeon_device *rdev = dev->dev_private;
459 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
460 DVO_ENCODER_CONTROL_PS_ALLOCATION args;
461 int index = 0;
462
463 memset(&args, 0, sizeof(args));
464
465 index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
466
467 args.sDVOEncoder.ucAction = action;
468 args.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
469
470 if (radeon_encoder->pixel_clock > 165000)
471 args.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute = PANEL_ENCODER_MISC_DUAL;
472
473 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
474
475}
476
477union lvds_encoder_control {
478 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1;
479 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
480};
481
32f48ffe 482void
771fe6b9
JG		 483atombios_digital_setup(struct drm_encoder *encoder, int action)
484{
485 struct drm_device *dev = encoder->dev;
486 struct radeon_device *rdev = dev->dev_private;
487 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
9ae47867 488 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
771fe6b9
JG		 489 union lvds_encoder_control args;
490 int index = 0;
dafc3bd5 491 int hdmi_detected = 0;
771fe6b9 492 uint8_t frev, crev;
771fe6b9 493
4aab97e8 494 if (!dig)
771fe6b9
JG		 495 return;
496
9ae47867 497 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
dafc3bd5
CK		 498 hdmi_detected = 1;
499
771fe6b9
JG		 500 memset(&args, 0, sizeof(args));
501
502 switch (radeon_encoder->encoder_id) {
503 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
504 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
505 break;
506 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
507 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
508 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
509 break;
510 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
511 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
512 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
513 else
514 index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
515 break;
516 }
517
a084e6ee
AD		 518 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
519 return;
771fe6b9
JG		 520
521 switch (frev) {
522 case 1:
523 case 2:
524 switch (crev) {
525 case 1:
526 args.v1.ucMisc = 0;
527 args.v1.ucAction = action;
dafc3bd5 528 if (hdmi_detected)
771fe6b9
JG		 529 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
530 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
531 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
edc664e3 532 if (dig->lvds_misc & ATOM_PANEL_MISC_DUAL)
771fe6b9 533 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
edc664e3 534 if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB)
771fe6b9
JG		 535 args.v1.ucMisc |= (1 << 1);
536 } else {
5137ee94 537 if (dig->linkb)
771fe6b9
JG		 538 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
539 if (radeon_encoder->pixel_clock > 165000)
540 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
541 /*if (pScrn->rgbBits == 8) */
542 args.v1.ucMisc |= (1 << 1);
543 }
544 break;
545 case 2:
546 case 3:
547 args.v2.ucMisc = 0;
548 args.v2.ucAction = action;
549 if (crev == 3) {
550 if (dig->coherent_mode)
551 args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
552 }
dafc3bd5 553 if (hdmi_detected)
771fe6b9
JG		 554 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
555 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
556 args.v2.ucTruncate = 0;
557 args.v2.ucSpatial = 0;
558 args.v2.ucTemporal = 0;
559 args.v2.ucFRC = 0;
560 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
edc664e3 561 if (dig->lvds_misc & ATOM_PANEL_MISC_DUAL)
771fe6b9 562 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
edc664e3 563 if (dig->lvds_misc & ATOM_PANEL_MISC_SPATIAL) {
771fe6b9 564 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
edc664e3 565 if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB)
771fe6b9
JG		 566 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
567 }
edc664e3 568 if (dig->lvds_misc & ATOM_PANEL_MISC_TEMPORAL) {
771fe6b9 569 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
edc664e3 570 if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB)
771fe6b9 571 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
edc664e3 572 if (((dig->lvds_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
771fe6b9
JG		 573 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
574 }
575 } else {
5137ee94 576 if (dig->linkb)
771fe6b9
JG		 577 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
578 if (radeon_encoder->pixel_clock > 165000)
579 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
580 }
581 break;
582 default:
583 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
584 break;
585 }
586 break;
587 default:
588 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
589 break;
590 }
591
592 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
771fe6b9
JG		 593}
594
595int
596atombios_get_encoder_mode(struct drm_encoder *encoder)
597{
598 struct drm_connector *connector;
599 struct radeon_connector *radeon_connector;
9ae47867 600 struct radeon_connector_atom_dig *dig_connector;
771fe6b9
JG		 601
602 connector = radeon_get_connector_for_encoder(encoder);
603 if (!connector)
604 return 0;
605
606 radeon_connector = to_radeon_connector(connector);
607
608 switch (connector->connector_type) {
609 case DRM_MODE_CONNECTOR_DVII:
705af9c7 610 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
0294cf4f 611 if (drm_detect_hdmi_monitor(radeon_connector->edid))
771fe6b9
JG		 612 return ATOM_ENCODER_MODE_HDMI;
613 else if (radeon_connector->use_digital)
614 return ATOM_ENCODER_MODE_DVI;
615 else
616 return ATOM_ENCODER_MODE_CRT;
617 break;
618 case DRM_MODE_CONNECTOR_DVID:
619 case DRM_MODE_CONNECTOR_HDMIA:
771fe6b9 620 default:
0294cf4f 621 if (drm_detect_hdmi_monitor(radeon_connector->edid))
771fe6b9
JG		 622 return ATOM_ENCODER_MODE_HDMI;
623 else
624 return ATOM_ENCODER_MODE_DVI;
625 break;
626 case DRM_MODE_CONNECTOR_LVDS:
627 return ATOM_ENCODER_MODE_LVDS;
628 break;
629 case DRM_MODE_CONNECTOR_DisplayPort:
196c58d2 630 case DRM_MODE_CONNECTOR_eDP:
9ae47867
AD		 631 dig_connector = radeon_connector->con_priv;
632 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
633 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
f92a8b67
AD		 634 return ATOM_ENCODER_MODE_DP;
635 else if (drm_detect_hdmi_monitor(radeon_connector->edid))
771fe6b9
JG		 636 return ATOM_ENCODER_MODE_HDMI;
637 else
638 return ATOM_ENCODER_MODE_DVI;
639 break;
a5899fcc
AD		 640 case DRM_MODE_CONNECTOR_DVIA:
641 case DRM_MODE_CONNECTOR_VGA:
771fe6b9
JG		 642 return ATOM_ENCODER_MODE_CRT;
643 break;
a5899fcc
AD		 644 case DRM_MODE_CONNECTOR_Composite:
645 case DRM_MODE_CONNECTOR_SVIDEO:
646 case DRM_MODE_CONNECTOR_9PinDIN:
771fe6b9
JG		 647 /* fix me */
648 return ATOM_ENCODER_MODE_TV;
649 /*return ATOM_ENCODER_MODE_CV;*/
650 break;
651 }
652}
653
1a66c95a
AD		 654/*
655 * DIG Encoder/Transmitter Setup
656 *
657 * DCE 3.0/3.1
658 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
659 * Supports up to 3 digital outputs
660 * - 2 DIG encoder blocks.
661 * DIG1 can drive UNIPHY link A or link B
662 * DIG2 can drive UNIPHY link B or LVTMA
663 *
664 * DCE 3.2
665 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
666 * Supports up to 5 digital outputs
667 * - 2 DIG encoder blocks.
668 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
669 *
bcc1c2a1
AD		 670 * DCE 4.0
671 * - 3 DIG transmitter blocks UNPHY0/1/2 (links A and B).
672 * Supports up to 6 digital outputs
673 * - 6 DIG encoder blocks.
674 * - DIG to PHY mapping is hardcoded
675 * DIG1 drives UNIPHY0 link A, A+B
676 * DIG2 drives UNIPHY0 link B
677 * DIG3 drives UNIPHY1 link A, A+B
678 * DIG4 drives UNIPHY1 link B
679 * DIG5 drives UNIPHY2 link A, A+B
680 * DIG6 drives UNIPHY2 link B
681 *
1a66c95a
AD		 682 * Routing
683 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
684 * Examples:
685 * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI
686 * crtc1 -> dig1 -> UNIPHY0 link B -> DP
687 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS
688 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI
689 */
bcc1c2a1
AD		 690
691union dig_encoder_control {
692 DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
693 DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
694 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
695};
696
697void
771fe6b9
JG		 698atombios_dig_encoder_setup(struct drm_encoder *encoder, int action)
699{
700 struct drm_device *dev = encoder->dev;
701 struct radeon_device *rdev = dev->dev_private;
702 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
9ae47867 703 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
4aab97e8 704 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
bcc1c2a1 705 union dig_encoder_control args;
d9c9fe36 706 int index = 0;
771fe6b9 707 uint8_t frev, crev;
4aab97e8
AD		 708 int dp_clock = 0;
709 int dp_lane_count = 0;
710
711 if (connector) {
712 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
713 struct radeon_connector_atom_dig *dig_connector =
714 radeon_connector->con_priv;
771fe6b9 715
4aab97e8
AD		 716 dp_clock = dig_connector->dp_clock;
717 dp_lane_count = dig_connector->dp_lane_count;
718 }
719
720 /* no dig encoder assigned */
721 if (dig->dig_encoder == -1)
771fe6b9
JG		 722 return;
723
771fe6b9
JG		 724 memset(&args, 0, sizeof(args));
725
bcc1c2a1
AD		 726 if (ASIC_IS_DCE4(rdev))
727 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
728 else {
729 if (dig->dig_encoder)
730 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
731 else
732 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
733 }
771fe6b9 734
a084e6ee
AD		 735 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
736 return;
771fe6b9 737
bcc1c2a1
AD		 738 args.v1.ucAction = action;
739 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
740 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
771fe6b9 741
bcc1c2a1 742 if (args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) {
4aab97e8 743 if (dp_clock == 270000)
bcc1c2a1 744 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
4aab97e8 745 args.v1.ucLaneNum = dp_lane_count;
bcc1c2a1
AD		 746 } else if (radeon_encoder->pixel_clock > 165000)
747 args.v1.ucLaneNum = 8;
748 else
749 args.v1.ucLaneNum = 4;
750
751 if (ASIC_IS_DCE4(rdev)) {
752 args.v3.acConfig.ucDigSel = dig->dig_encoder;
753 args.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR;
754 } else {
771fe6b9
JG		 755 switch (radeon_encoder->encoder_id) {
756 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
bcc1c2a1 757 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
771fe6b9
JG		 758 break;
759 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
bcc1c2a1
AD		 760 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
761 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
771fe6b9
JG		 762 break;
763 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
bcc1c2a1 764 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
771fe6b9
JG		 765 break;
766 }
5137ee94 767 if (dig->linkb)
bcc1c2a1
AD		 768 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
769 else
770 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
771fe6b9
JG		 771 }
772
771fe6b9
JG		 773 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
774
775}
776
777union dig_transmitter_control {
778 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
779 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
bcc1c2a1 780 DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
771fe6b9
JG		 781};
782
5801ead6 783void
1a66c95a 784atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
771fe6b9
JG		 785{
786 struct drm_device *dev = encoder->dev;
787 struct radeon_device *rdev = dev->dev_private;
788 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
9ae47867 789 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
4aab97e8 790 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
771fe6b9 791 union dig_transmitter_control args;
d9c9fe36 792 int index = 0;
771fe6b9 793 uint8_t frev, crev;
f92a8b67 794 bool is_dp = false;
bcc1c2a1 795 int pll_id = 0;
4aab97e8
AD		 796 int dp_clock = 0;
797 int dp_lane_count = 0;
798 int connector_object_id = 0;
799 int igp_lane_info = 0;
800
801 if (connector) {
802 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
803 struct radeon_connector_atom_dig *dig_connector =
804 radeon_connector->con_priv;
805
806 dp_clock = dig_connector->dp_clock;
807 dp_lane_count = dig_connector->dp_lane_count;
808 connector_object_id =
809 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
810 igp_lane_info = dig_connector->igp_lane_info;
811 }
771fe6b9 812
4aab97e8
AD		 813 /* no dig encoder assigned */
814 if (dig->dig_encoder == -1)
771fe6b9
JG		 815 return;
816
f92a8b67
AD		 817 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP)
818 is_dp = true;
819
771fe6b9
JG		 820 memset(&args, 0, sizeof(args));
821
4aab97e8
AD		 822 switch (radeon_encoder->encoder_id) {
823 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
824 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
825 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
771fe6b9 826 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
4aab97e8
AD		 827 break;
828 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
829 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
830 break;
771fe6b9
JG		 831 }
832
a084e6ee
AD		 833 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
834 return;
771fe6b9
JG		 835
836 args.v1.ucAction = action;
f95a9f0b 837 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
4aab97e8 838 args.v1.usInitInfo = connector_object_id;
1a66c95a
AD		 839 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
840 args.v1.asMode.ucLaneSel = lane_num;
841 args.v1.asMode.ucLaneSet = lane_set;
f95a9f0b 842 } else {
f92a8b67
AD		 843 if (is_dp)
844 args.v1.usPixelClock =
4aab97e8 845 cpu_to_le16(dp_clock / 10);
f92a8b67 846 else if (radeon_encoder->pixel_clock > 165000)
f95a9f0b
AD		 847 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
848 else
849 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
850 }
bcc1c2a1
AD		 851 if (ASIC_IS_DCE4(rdev)) {
852 if (is_dp)
4aab97e8 853 args.v3.ucLaneNum = dp_lane_count;
bcc1c2a1
AD		 854 else if (radeon_encoder->pixel_clock > 165000)
855 args.v3.ucLaneNum = 8;
856 else
857 args.v3.ucLaneNum = 4;
858
5137ee94 859 if (dig->linkb) {
bcc1c2a1
AD		 860 args.v3.acConfig.ucLinkSel = 1;
861 args.v3.acConfig.ucEncoderSel = 1;
862 }
863
864 /* Select the PLL for the PHY
865 * DP PHY should be clocked from external src if there is
866 * one.
867 */
868 if (encoder->crtc) {
869 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
870 pll_id = radeon_crtc->pll_id;
871 }
872 if (is_dp && rdev->clock.dp_extclk)
873 args.v3.acConfig.ucRefClkSource = 2; /* external src */
874 else
875 args.v3.acConfig.ucRefClkSource = pll_id;
876
877 switch (radeon_encoder->encoder_id) {
878 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
879 args.v3.acConfig.ucTransmitterSel = 0;
bcc1c2a1
AD		 880 break;
881 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
882 args.v3.acConfig.ucTransmitterSel = 1;
bcc1c2a1
AD		 883 break;
884 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
885 args.v3.acConfig.ucTransmitterSel = 2;
bcc1c2a1
AD		 886 break;
887 }
888
889 if (is_dp)
890 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
891 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
892 if (dig->coherent_mode)
893 args.v3.acConfig.fCoherentMode = 1;
b317a9ce
AD		 894 if (radeon_encoder->pixel_clock > 165000)
895 args.v3.acConfig.fDualLinkConnector = 1;
bcc1c2a1
AD		 896 }
897 } else if (ASIC_IS_DCE32(rdev)) {
d9c9fe36 898 args.v2.acConfig.ucEncoderSel = dig->dig_encoder;
5137ee94 899 if (dig->linkb)
1a66c95a 900 args.v2.acConfig.ucLinkSel = 1;
771fe6b9
JG		 901
902 switch (radeon_encoder->encoder_id) {
903 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
904 args.v2.acConfig.ucTransmitterSel = 0;
771fe6b9
JG		 905 break;
906 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
907 args.v2.acConfig.ucTransmitterSel = 1;
771fe6b9
JG		 908 break;
909 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
910 args.v2.acConfig.ucTransmitterSel = 2;
771fe6b9
JG		 911 break;
912 }
913
f92a8b67
AD		 914 if (is_dp)
915 args.v2.acConfig.fCoherentMode = 1;
916 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
771fe6b9
JG		 917 if (dig->coherent_mode)
918 args.v2.acConfig.fCoherentMode = 1;
b317a9ce
AD		 919 if (radeon_encoder->pixel_clock > 165000)
920 args.v2.acConfig.fDualLinkConnector = 1;
771fe6b9
JG		 921 }
922 } else {
923 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
771fe6b9 924
f28cf339
DA		 925 if (dig->dig_encoder)
926 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
927 else
928 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
929
d9c9fe36
AD		 930 if ((rdev->flags & RADEON_IS_IGP) &&
931 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
932 if (is_dp || (radeon_encoder->pixel_clock <= 165000)) {
4aab97e8 933 if (igp_lane_info & 0x1)
d9c9fe36 934 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
4aab97e8 935 else if (igp_lane_info & 0x2)
d9c9fe36 936 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
4aab97e8 937 else if (igp_lane_info & 0x4)
d9c9fe36 938 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
4aab97e8 939 else if (igp_lane_info & 0x8)
d9c9fe36
AD		 940 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
941 } else {
4aab97e8 942 if (igp_lane_info & 0x3)
d9c9fe36 943 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
4aab97e8 944 else if (igp_lane_info & 0xc)
d9c9fe36 945 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
771fe6b9 946 }
771fe6b9
JG		 947 }
948
5137ee94 949 if (dig->linkb)
1a66c95a
AD		 950 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
951 else
952 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
953
f92a8b67
AD		 954 if (is_dp)
955 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
956 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
771fe6b9
JG		 957 if (dig->coherent_mode)
958 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
d9c9fe36
AD		 959 if (radeon_encoder->pixel_clock > 165000)
960 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
771fe6b9
JG		 961 }
962 }
963
964 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
771fe6b9
JG		 965}
966
771fe6b9
JG		 967static void
968atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
969{
970 struct drm_device *dev = encoder->dev;
971 struct radeon_device *rdev = dev->dev_private;
972 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
973 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
974 ENABLE_YUV_PS_ALLOCATION args;
975 int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
976 uint32_t temp, reg;
977
978 memset(&args, 0, sizeof(args));
979
980 if (rdev->family >= CHIP_R600)
981 reg = R600_BIOS_3_SCRATCH;
982 else
983 reg = RADEON_BIOS_3_SCRATCH;
984
985 /* XXX: fix up scratch reg handling */
986 temp = RREG32(reg);
4ce001ab 987 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
771fe6b9
JG		 988 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
989 (radeon_crtc->crtc_id << 18)));
4ce001ab 990 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
771fe6b9
JG		 991 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
992 else
993 WREG32(reg, 0);
994
995 if (enable)
996 args.ucEnable = ATOM_ENABLE;
997 args.ucCRTC = radeon_crtc->crtc_id;
998
999 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1000
1001 WREG32(reg, temp);
1002}
1003
771fe6b9
JG		 1004static void
1005radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1006{
1007 struct drm_device *dev = encoder->dev;
1008 struct radeon_device *rdev = dev->dev_private;
1009 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1010 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1011 int index = 0;
1012 bool is_dig = false;
1013
1014 memset(&args, 0, sizeof(args));
1015
d9fdaafb 1016 DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
f641e51e
DA		 1017 radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1018 radeon_encoder->active_device);
771fe6b9
JG		 1019 switch (radeon_encoder->encoder_id) {
1020 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1021 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1022 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1023 break;
1024 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1025 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1026 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1027 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1028 is_dig = true;
1029 break;
1030 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1031 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1032 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1033 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1034 break;
1035 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1036 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1037 break;
1038 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1039 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1040 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1041 else
1042 index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1043 break;
1044 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1045 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
8c2a6d73 1046 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
771fe6b9 1047 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
8c2a6d73 1048 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
771fe6b9
JG		 1049 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1050 else
1051 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1052 break;
1053 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1054 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
8c2a6d73 1055 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
771fe6b9 1056 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
8c2a6d73 1057 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
771fe6b9
JG		 1058 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1059 else
1060 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1061 break;
1062 }
1063
1064 if (is_dig) {
1065 switch (mode) {
1066 case DRM_MODE_DPMS_ON:
e13b2ac1 1067 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
fb668c2f 1068 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) {
58682f10 1069 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
fb668c2f 1070
58682f10 1071 dp_link_train(encoder, connector);
fb668c2f
AD		 1072 if (ASIC_IS_DCE4(rdev))
1073 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON);
58682f10 1074 }
771fe6b9
JG		 1075 break;
1076 case DRM_MODE_DPMS_STANDBY:
1077 case DRM_MODE_DPMS_SUSPEND:
1078 case DRM_MODE_DPMS_OFF:
e13b2ac1 1079 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
fb668c2f
AD		 1080 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) {
1081 if (ASIC_IS_DCE4(rdev))
1082 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF);
1083 }
771fe6b9
JG		 1084 break;
1085 }
1086 } else {
1087 switch (mode) {
1088 case DRM_MODE_DPMS_ON:
1089 args.ucAction = ATOM_ENABLE;
1090 break;
1091 case DRM_MODE_DPMS_STANDBY:
1092 case DRM_MODE_DPMS_SUSPEND:
1093 case DRM_MODE_DPMS_OFF:
1094 args.ucAction = ATOM_DISABLE;
1095 break;
1096 }
1097 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1098 }
1099 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
c913e23a 1100
771fe6b9
JG		 1101}
1102
9ae47867 1103union crtc_source_param {
771fe6b9
JG		 1104 SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1105 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1106};
1107
1108static void
1109atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1110{
1111 struct drm_device *dev = encoder->dev;
1112 struct radeon_device *rdev = dev->dev_private;
1113 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1114 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
9ae47867 1115 union crtc_source_param args;
771fe6b9
JG		 1116 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1117 uint8_t frev, crev;
f28cf339 1118 struct radeon_encoder_atom_dig *dig;
771fe6b9
JG		 1119
1120 memset(&args, 0, sizeof(args));
1121
a084e6ee
AD		 1122 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1123 return;
771fe6b9
JG		 1124
1125 switch (frev) {
1126 case 1:
1127 switch (crev) {
1128 case 1:
1129 default:
1130 if (ASIC_IS_AVIVO(rdev))
1131 args.v1.ucCRTC = radeon_crtc->crtc_id;
1132 else {
1133 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1134 args.v1.ucCRTC = radeon_crtc->crtc_id;
1135 } else {
1136 args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1137 }
1138 }
1139 switch (radeon_encoder->encoder_id) {
1140 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1141 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1142 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1143 break;
1144 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1145 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1146 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1147 args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1148 else
1149 args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1150 break;
1151 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1152 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1153 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1154 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1155 break;
1156 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1157 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
4ce001ab 1158 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
771fe6b9 1159 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
4ce001ab 1160 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
771fe6b9
JG		 1161 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1162 else
1163 args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1164 break;
1165 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1166 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
4ce001ab 1167 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
771fe6b9 1168 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
4ce001ab 1169 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
771fe6b9
JG		 1170 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1171 else
1172 args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1173 break;
1174 }
1175 break;
1176 case 2:
1177 args.v2.ucCRTC = radeon_crtc->crtc_id;
1178 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1179 switch (radeon_encoder->encoder_id) {
1180 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1181 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1182 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
f28cf339
DA		 1183 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1184 dig = radeon_encoder->enc_priv;
bcc1c2a1
AD		 1185 switch (dig->dig_encoder) {
1186 case 0:
f28cf339 1187 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
bcc1c2a1
AD		 1188 break;
1189 case 1:
1190 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1191 break;
1192 case 2:
1193 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1194 break;
1195 case 3:
1196 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1197 break;
1198 case 4:
1199 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1200 break;
1201 case 5:
1202 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1203 break;
1204 }
771fe6b9
JG		 1205 break;
1206 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1207 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1208 break;
771fe6b9 1209 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
4ce001ab 1210 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
771fe6b9 1211 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
4ce001ab 1212 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
771fe6b9
JG		 1213 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1214 else
1215 args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1216 break;
1217 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
4ce001ab 1218 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
771fe6b9 1219 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
4ce001ab 1220 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
771fe6b9
JG		 1221 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1222 else
1223 args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1224 break;
1225 }
1226 break;
1227 }
1228 break;
1229 default:
1230 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1231 break;
1232 }
1233
1234 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
267364ac
AD		 1235
1236 /* update scratch regs with new routing */
1237 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
771fe6b9
JG		 1238}
1239
1240static void
1241atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1242 struct drm_display_mode *mode)
1243{
1244 struct drm_device *dev = encoder->dev;
1245 struct radeon_device *rdev = dev->dev_private;
1246 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1247 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1248
1249 /* Funky macbooks */
1250 if ((dev->pdev->device == 0x71C5) &&
1251 (dev->pdev->subsystem_vendor == 0x106b) &&
1252 (dev->pdev->subsystem_device == 0x0080)) {
1253 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1254 uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1255
1256 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
1257 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
1258
1259 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
1260 }
1261 }
1262
1263 /* set scaler clears this on some chips */
bcc1c2a1 1264 /* XXX check DCE4 */
ceefedd8
AD		 1265 if (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))) {
1266 if (ASIC_IS_AVIVO(rdev) && (mode->flags & DRM_MODE_FLAG_INTERLACE))
1267 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1268 AVIVO_D1MODE_INTERLEAVE_EN);
1269 }
771fe6b9
JG		 1270}
1271
f28cf339
DA		 1272static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
1273{
1274 struct drm_device *dev = encoder->dev;
1275 struct radeon_device *rdev = dev->dev_private;
1276 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1277 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1278 struct drm_encoder *test_encoder;
1279 struct radeon_encoder_atom_dig *dig;
1280 uint32_t dig_enc_in_use = 0;
bcc1c2a1
AD		 1281
1282 if (ASIC_IS_DCE4(rdev)) {
5137ee94 1283 dig = radeon_encoder->enc_priv;
bcc1c2a1
AD		 1284 switch (radeon_encoder->encoder_id) {
1285 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
5137ee94 1286 if (dig->linkb)
bcc1c2a1
AD		 1287 return 1;
1288 else
1289 return 0;
1290 break;
1291 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
5137ee94 1292 if (dig->linkb)
bcc1c2a1
AD		 1293 return 3;
1294 else
1295 return 2;
1296 break;
1297 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
5137ee94 1298 if (dig->linkb)
bcc1c2a1
AD		 1299 return 5;
1300 else
1301 return 4;
1302 break;
1303 }
1304 }
1305
f28cf339
DA		 1306 /* on DCE32 and encoder can driver any block so just crtc id */
1307 if (ASIC_IS_DCE32(rdev)) {
1308 return radeon_crtc->crtc_id;
1309 }
1310
1311 /* on DCE3 - LVTMA can only be driven by DIGB */
1312 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1313 struct radeon_encoder *radeon_test_encoder;
1314
1315 if (encoder == test_encoder)
1316 continue;
1317
1318 if (!radeon_encoder_is_digital(test_encoder))
1319 continue;
1320
1321 radeon_test_encoder = to_radeon_encoder(test_encoder);
1322 dig = radeon_test_encoder->enc_priv;
1323
1324 if (dig->dig_encoder >= 0)
1325 dig_enc_in_use |= (1 << dig->dig_encoder);
1326 }
1327
1328 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
1329 if (dig_enc_in_use & 0x2)
1330 DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
1331 return 1;
1332 }
1333 if (!(dig_enc_in_use & 1))
1334 return 0;
1335 return 1;
1336}
1337
771fe6b9
JG		 1338static void
1339radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1340 struct drm_display_mode *mode,
1341 struct drm_display_mode *adjusted_mode)
1342{
1343 struct drm_device *dev = encoder->dev;
1344 struct radeon_device *rdev = dev->dev_private;
1345 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
771fe6b9 1346
771fe6b9
JG		 1347 radeon_encoder->pixel_clock = adjusted_mode->clock;
1348
c6f8505e 1349 if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
4ce001ab 1350 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
771fe6b9
JG		 1351 atombios_yuv_setup(encoder, true);
1352 else
1353 atombios_yuv_setup(encoder, false);
1354 }
1355
1356 switch (radeon_encoder->encoder_id) {
1357 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1358 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1359 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1360 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1361 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
1362 break;
1363 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1364 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1365 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1366 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
bcc1c2a1
AD		 1367 if (ASIC_IS_DCE4(rdev)) {
1368 /* disable the transmitter */
1369 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1370 /* setup and enable the encoder */
1371 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP);
1372
1373 /* init and enable the transmitter */
1374 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
1375 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1376 } else {
1377 /* disable the encoder and transmitter */
1378 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1379 atombios_dig_encoder_setup(encoder, ATOM_DISABLE);
1380
1381 /* setup and enable the encoder and transmitter */
1382 atombios_dig_encoder_setup(encoder, ATOM_ENABLE);
1383 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
1384 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1385 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1386 }
771fe6b9
JG		 1387 break;
1388 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1389 atombios_ddia_setup(encoder, ATOM_ENABLE);
1390 break;
1391 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1392 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1393 atombios_external_tmds_setup(encoder, ATOM_ENABLE);
1394 break;
1395 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1396 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1397 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1398 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1399 atombios_dac_setup(encoder, ATOM_ENABLE);
d3a67a43
AD		 1400 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
1401 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1402 atombios_tv_setup(encoder, ATOM_ENABLE);
1403 else
1404 atombios_tv_setup(encoder, ATOM_DISABLE);
1405 }
771fe6b9
JG		 1406 break;
1407 }
1408 atombios_apply_encoder_quirks(encoder, adjusted_mode);
dafc3bd5 1409
2cd6218c
RM		 1410 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
1411 r600_hdmi_enable(encoder);
bcc1c2a1 1412 r600_hdmi_setmode(encoder, adjusted_mode);
2cd6218c 1413 }
771fe6b9
JG		 1414}
1415
1416static bool
4ce001ab 1417atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
771fe6b9
JG		 1418{
1419 struct drm_device *dev = encoder->dev;
1420 struct radeon_device *rdev = dev->dev_private;
1421 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
4ce001ab 1422 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
771fe6b9
JG		 1423
1424 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
1425 ATOM_DEVICE_CV_SUPPORT |
1426 ATOM_DEVICE_CRT_SUPPORT)) {
1427 DAC_LOAD_DETECTION_PS_ALLOCATION args;
1428 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
1429 uint8_t frev, crev;
1430
1431 memset(&args, 0, sizeof(args));
1432
a084e6ee
AD		 1433 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1434 return false;
771fe6b9
JG		 1435
1436 args.sDacload.ucMisc = 0;
1437
1438 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
1439 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
1440 args.sDacload.ucDacType = ATOM_DAC_A;
1441 else
1442 args.sDacload.ucDacType = ATOM_DAC_B;
1443
4ce001ab 1444 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
771fe6b9 1445 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
4ce001ab 1446 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
771fe6b9 1447 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
4ce001ab 1448 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
771fe6b9
JG		 1449 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
1450 if (crev >= 3)
1451 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
4ce001ab 1452 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
771fe6b9
JG		 1453 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
1454 if (crev >= 3)
1455 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1456 }
1457
1458 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1459
1460 return true;
1461 } else
1462 return false;
1463}
1464
1465static enum drm_connector_status
1466radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1467{
1468 struct drm_device *dev = encoder->dev;
1469 struct radeon_device *rdev = dev->dev_private;
1470 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
4ce001ab 1471 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
771fe6b9
JG		 1472 uint32_t bios_0_scratch;
1473
4ce001ab 1474 if (!atombios_dac_load_detect(encoder, connector)) {
d9fdaafb 1475 DRM_DEBUG_KMS("detect returned false \n");
771fe6b9
JG		 1476 return connector_status_unknown;
1477 }
1478
1479 if (rdev->family >= CHIP_R600)
1480 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
1481 else
1482 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
1483
d9fdaafb 1484 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
4ce001ab 1485 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
771fe6b9
JG		 1486 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
1487 return connector_status_connected;
4ce001ab
DA		 1488 }
1489 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
771fe6b9
JG		 1490 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
1491 return connector_status_connected;
4ce001ab
DA		 1492 }
1493 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
771fe6b9
JG		 1494 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
1495 return connector_status_connected;
4ce001ab
DA		 1496 }
1497 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
771fe6b9
JG		 1498 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
1499 return connector_status_connected; /* CTV */
1500 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
1501 return connector_status_connected; /* STV */
1502 }
1503 return connector_status_disconnected;
1504}
1505
1506static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
1507{
267364ac
AD		 1508 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1509
1510 if (radeon_encoder->active_device &
1511 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) {
1512 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1513 if (dig)
1514 dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
1515 }
1516
771fe6b9
JG		 1517 radeon_atom_output_lock(encoder, true);
1518 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
267364ac
AD		 1519
1520 /* this is needed for the pll/ss setup to work correctly in some cases */
1521 atombios_set_encoder_crtc_source(encoder);
771fe6b9
JG		 1522}
1523
1524static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
1525{
1526 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
1527 radeon_atom_output_lock(encoder, false);
1528}
1529
4ce001ab
DA		 1530static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
1531{
aa961391
AD		 1532 struct drm_device *dev = encoder->dev;
1533 struct radeon_device *rdev = dev->dev_private;
4ce001ab 1534 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
f28cf339 1535 struct radeon_encoder_atom_dig *dig;
4ce001ab 1536 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
f28cf339 1537
aa961391
AD		 1538 switch (radeon_encoder->encoder_id) {
1539 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1540 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1541 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1542 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1543 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE);
1544 break;
1545 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1546 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1547 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1548 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1549 if (ASIC_IS_DCE4(rdev))
1550 /* disable the transmitter */
1551 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1552 else {
1553 /* disable the encoder and transmitter */
1554 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1555 atombios_dig_encoder_setup(encoder, ATOM_DISABLE);
1556 }
1557 break;
1558 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1559 atombios_ddia_setup(encoder, ATOM_DISABLE);
1560 break;
1561 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1562 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1563 atombios_external_tmds_setup(encoder, ATOM_DISABLE);
1564 break;
1565 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1566 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1567 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1568 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1569 atombios_dac_setup(encoder, ATOM_DISABLE);
8bf3aae6 1570 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
aa961391
AD		 1571 atombios_tv_setup(encoder, ATOM_DISABLE);
1572 break;
1573 }
1574
f28cf339 1575 if (radeon_encoder_is_digital(encoder)) {
2cd6218c
RM		 1576 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
1577 r600_hdmi_disable(encoder);
f28cf339
DA		 1578 dig = radeon_encoder->enc_priv;
1579 dig->dig_encoder = -1;
1580 }
4ce001ab
DA		 1581 radeon_encoder->active_device = 0;
1582}
1583
771fe6b9
JG		 1584static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
1585 .dpms = radeon_atom_encoder_dpms,
1586 .mode_fixup = radeon_atom_mode_fixup,
1587 .prepare = radeon_atom_encoder_prepare,
1588 .mode_set = radeon_atom_encoder_mode_set,
1589 .commit = radeon_atom_encoder_commit,
4ce001ab 1590 .disable = radeon_atom_encoder_disable,
771fe6b9
JG		 1591 /* no detect for TMDS/LVDS yet */
1592};
1593
1594static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
1595 .dpms = radeon_atom_encoder_dpms,
1596 .mode_fixup = radeon_atom_mode_fixup,
1597 .prepare = radeon_atom_encoder_prepare,
1598 .mode_set = radeon_atom_encoder_mode_set,
1599 .commit = radeon_atom_encoder_commit,
1600 .detect = radeon_atom_dac_detect,
1601};
1602
1603void radeon_enc_destroy(struct drm_encoder *encoder)
1604{
1605 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1606 kfree(radeon_encoder->enc_priv);
1607 drm_encoder_cleanup(encoder);
1608 kfree(radeon_encoder);
1609}
1610
1611static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
1612 .destroy = radeon_enc_destroy,
1613};
1614
4ce001ab
DA		 1615struct radeon_encoder_atom_dac *
1616radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
1617{
affd8589
AD		 1618 struct drm_device *dev = radeon_encoder->base.dev;
1619 struct radeon_device *rdev = dev->dev_private;
4ce001ab
DA		 1620 struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
1621
1622 if (!dac)
1623 return NULL;
1624
affd8589 1625 dac->tv_std = radeon_atombios_get_tv_info(rdev);
4ce001ab
DA		 1626 return dac;
1627}
1628
771fe6b9
JG		 1629struct radeon_encoder_atom_dig *
1630radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
1631{
5137ee94 1632 int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
771fe6b9
JG		 1633 struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1634
1635 if (!dig)
1636 return NULL;
1637
1638 /* coherent mode by default */
1639 dig->coherent_mode = true;
f28cf339 1640 dig->dig_encoder = -1;
771fe6b9 1641
5137ee94
AD		 1642 if (encoder_enum == 2)
1643 dig->linkb = true;
1644 else
1645 dig->linkb = false;
1646
771fe6b9
JG		 1647 return dig;
1648}
1649
1650void
5137ee94 1651radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum, uint32_t supported_device)
771fe6b9 1652{
dfee5614 1653 struct radeon_device *rdev = dev->dev_private;
771fe6b9
JG		 1654 struct drm_encoder *encoder;
1655 struct radeon_encoder *radeon_encoder;
1656
1657 /* see if we already added it */
1658 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1659 radeon_encoder = to_radeon_encoder(encoder);
5137ee94 1660 if (radeon_encoder->encoder_enum == encoder_enum) {
771fe6b9
JG		 1661 radeon_encoder->devices |= supported_device;
1662 return;
1663 }
1664
1665 }
1666
1667 /* add a new one */
1668 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
1669 if (!radeon_encoder)
1670 return;
1671
1672 encoder = &radeon_encoder->base;
bcc1c2a1
AD		 1673 switch (rdev->num_crtc) {
1674 case 1:
dfee5614 1675 encoder->possible_crtcs = 0x1;
bcc1c2a1
AD		 1676 break;
1677 case 2:
1678 default:
dfee5614 1679 encoder->possible_crtcs = 0x3;
bcc1c2a1
AD		 1680 break;
1681 case 6:
1682 encoder->possible_crtcs = 0x3f;
1683 break;
1684 }
771fe6b9
JG		 1685
1686 radeon_encoder->enc_priv = NULL;
1687
5137ee94
AD		 1688 radeon_encoder->encoder_enum = encoder_enum;
1689 radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
771fe6b9 1690 radeon_encoder->devices = supported_device;
c93bb85b 1691 radeon_encoder->rmx_type = RMX_OFF;
5b1714d3 1692 radeon_encoder->underscan_type = UNDERSCAN_OFF;
771fe6b9
JG		 1693
1694 switch (radeon_encoder->encoder_id) {
1695 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1696 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1697 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1698 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1699 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1700 radeon_encoder->rmx_type = RMX_FULL;
1701 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
1702 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1703 } else {
1704 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
1705 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
430f70d5
AD		 1706 if (ASIC_IS_AVIVO(rdev))
1707 radeon_encoder->underscan_type = UNDERSCAN_AUTO;
771fe6b9
JG		 1708 }
1709 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
1710 break;
1711 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1712 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
affd8589 1713 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
771fe6b9
JG		 1714 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
1715 break;
1716 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1717 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1718 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1719 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
4ce001ab 1720 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
771fe6b9
JG		 1721 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
1722 break;
1723 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1724 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1725 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1726 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1727 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1728 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1729 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
60d15f55
AD		 1730 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1731 radeon_encoder->rmx_type = RMX_FULL;
1732 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
1733 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1734 } else {
1735 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
1736 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
430f70d5
AD		 1737 if (ASIC_IS_AVIVO(rdev))
1738 radeon_encoder->underscan_type = UNDERSCAN_AUTO;
60d15f55 1739 }
771fe6b9
JG		 1740 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
1741 break;
1742 }
1743}
Clone of davem's net-next-2.6 tree