]> bbs.cooldavid.org Git - net-next-2.6.git/blame - drivers/gpu/drm/radeon/radeon_display.c
git://bbs.cooldavid.org / net-next-2.6.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/ttm: fix memory leak noticed by kmemleak.
[net-next-2.6.git] / drivers / gpu / drm / radeon / radeon_display.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26#include "drmP.h"
27#include "radeon_drm.h"
28#include "radeon.h"
29
30#include "atom.h"
31#include <asm/div64.h>
32
33#include "drm_crtc_helper.h"
34#include "drm_edid.h"
35
36static int radeon_ddc_dump(struct drm_connector *connector);
37
38static void avivo_crtc_load_lut(struct drm_crtc *crtc)
39{
40 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
41 struct drm_device *dev = crtc->dev;
42 struct radeon_device *rdev = dev->dev_private;
43 int i;
44
45 DRM_DEBUG("%d\n", radeon_crtc->crtc_id);
46 WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
47
48 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
49 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
50 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
51
52 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
53 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
54 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
55
56 WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
57 WREG32(AVIVO_DC_LUT_RW_MODE, 0);
58 WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
59
60 WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
61 for (i = 0; i < 256; i++) {
62 WREG32(AVIVO_DC_LUT_30_COLOR,
63 (radeon_crtc->lut_r[i] << 20) |
64 (radeon_crtc->lut_g[i] << 10) |
65 (radeon_crtc->lut_b[i] << 0));
66 }
67
68 WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id);
69}
70
71static void legacy_crtc_load_lut(struct drm_crtc *crtc)
72{
73 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
74 struct drm_device *dev = crtc->dev;
75 struct radeon_device *rdev = dev->dev_private;
76 int i;
77 uint32_t dac2_cntl;
78
79 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
80 if (radeon_crtc->crtc_id == 0)
81 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
82 else
83 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;
84 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
85
86 WREG8(RADEON_PALETTE_INDEX, 0);
87 for (i = 0; i < 256; i++) {
88 WREG32(RADEON_PALETTE_30_DATA,
89 (radeon_crtc->lut_r[i] << 20) |
90 (radeon_crtc->lut_g[i] << 10) |
91 (radeon_crtc->lut_b[i] << 0));
92 }
93}
94
95void radeon_crtc_load_lut(struct drm_crtc *crtc)
96{
97 struct drm_device *dev = crtc->dev;
98 struct radeon_device *rdev = dev->dev_private;
99
100 if (!crtc->enabled)
101 return;
102
103 if (ASIC_IS_AVIVO(rdev))
104 avivo_crtc_load_lut(crtc);
105 else
106 legacy_crtc_load_lut(crtc);
107}
108
b8c00ac5 109/** Sets the color ramps on behalf of fbcon */
771fe6b9
JG		 110void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
111 u16 blue, int regno)
112{
113 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
114
771fe6b9
JG		 115 radeon_crtc->lut_r[regno] = red >> 6;
116 radeon_crtc->lut_g[regno] = green >> 6;
117 radeon_crtc->lut_b[regno] = blue >> 6;
118}
119
b8c00ac5
DA		 120/** Gets the color ramps on behalf of fbcon */
121void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
122 u16 *blue, int regno)
123{
124 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
125
126 *red = radeon_crtc->lut_r[regno] << 6;
127 *green = radeon_crtc->lut_g[regno] << 6;
128 *blue = radeon_crtc->lut_b[regno] << 6;
129}
130
771fe6b9
JG		 131static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
132 u16 *blue, uint32_t size)
133{
134 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
b8c00ac5 135 int i;
771fe6b9
JG		 136
137 if (size != 256) {
138 return;
139 }
771fe6b9 140
b8c00ac5
DA		 141 /* userspace palettes are always correct as is */
142 for (i = 0; i < 256; i++) {
143 radeon_crtc->lut_r[i] = red[i] >> 6;
144 radeon_crtc->lut_g[i] = green[i] >> 6;
145 radeon_crtc->lut_b[i] = blue[i] >> 6;
771fe6b9 146 }
771fe6b9
JG		 147 radeon_crtc_load_lut(crtc);
148}
149
150static void radeon_crtc_destroy(struct drm_crtc *crtc)
151{
152 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
153
771fe6b9
JG		 154 drm_crtc_cleanup(crtc);
155 kfree(radeon_crtc);
156}
157
158static const struct drm_crtc_funcs radeon_crtc_funcs = {
159 .cursor_set = radeon_crtc_cursor_set,
160 .cursor_move = radeon_crtc_cursor_move,
161 .gamma_set = radeon_crtc_gamma_set,
162 .set_config = drm_crtc_helper_set_config,
163 .destroy = radeon_crtc_destroy,
164};
165
166static void radeon_crtc_init(struct drm_device *dev, int index)
167{
168 struct radeon_device *rdev = dev->dev_private;
169 struct radeon_crtc *radeon_crtc;
170 int i;
171
172 radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
173 if (radeon_crtc == NULL)
174 return;
175
176 drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
177
178 drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
179 radeon_crtc->crtc_id = index;
c93bb85b 180 rdev->mode_info.crtcs[index] = radeon_crtc;
771fe6b9 181
785b93ef 182#if 0
771fe6b9
JG		 183 radeon_crtc->mode_set.crtc = &radeon_crtc->base;
184 radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
185 radeon_crtc->mode_set.num_connectors = 0;
785b93ef 186#endif
771fe6b9
JG		 187
188 for (i = 0; i < 256; i++) {
189 radeon_crtc->lut_r[i] = i << 2;
190 radeon_crtc->lut_g[i] = i << 2;
191 radeon_crtc->lut_b[i] = i << 2;
192 }
193
194 if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))
195 radeon_atombios_init_crtc(dev, radeon_crtc);
196 else
197 radeon_legacy_init_crtc(dev, radeon_crtc);
198}
199
200static const char *encoder_names[34] = {
201 "NONE",
202 "INTERNAL_LVDS",
203 "INTERNAL_TMDS1",
204 "INTERNAL_TMDS2",
205 "INTERNAL_DAC1",
206 "INTERNAL_DAC2",
207 "INTERNAL_SDVOA",
208 "INTERNAL_SDVOB",
209 "SI170B",
210 "CH7303",
211 "CH7301",
212 "INTERNAL_DVO1",
213 "EXTERNAL_SDVOA",
214 "EXTERNAL_SDVOB",
215 "TITFP513",
216 "INTERNAL_LVTM1",
217 "VT1623",
218 "HDMI_SI1930",
219 "HDMI_INTERNAL",
220 "INTERNAL_KLDSCP_TMDS1",
221 "INTERNAL_KLDSCP_DVO1",
222 "INTERNAL_KLDSCP_DAC1",
223 "INTERNAL_KLDSCP_DAC2",
224 "SI178",
225 "MVPU_FPGA",
226 "INTERNAL_DDI",
227 "VT1625",
228 "HDMI_SI1932",
229 "DP_AN9801",
230 "DP_DP501",
231 "INTERNAL_UNIPHY",
232 "INTERNAL_KLDSCP_LVTMA",
233 "INTERNAL_UNIPHY1",
234 "INTERNAL_UNIPHY2",
235};
236
237static const char *connector_names[13] = {
238 "Unknown",
239 "VGA",
240 "DVI-I",
241 "DVI-D",
242 "DVI-A",
243 "Composite",
244 "S-video",
245 "LVDS",
246 "Component",
247 "DIN",
248 "DisplayPort",
249 "HDMI-A",
250 "HDMI-B",
251};
252
eed45b30
AD		 253static const char *hpd_names[7] = {
254 "NONE",
255 "HPD1",
256 "HPD2",
257 "HPD3",
258 "HPD4",
259 "HPD5",
260 "HPD6",
261};
262
771fe6b9
JG		 263static void radeon_print_display_setup(struct drm_device *dev)
264{
265 struct drm_connector *connector;
266 struct radeon_connector *radeon_connector;
267 struct drm_encoder *encoder;
268 struct radeon_encoder *radeon_encoder;
269 uint32_t devices;
270 int i = 0;
271
272 DRM_INFO("Radeon Display Connectors\n");
273 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
274 radeon_connector = to_radeon_connector(connector);
275 DRM_INFO("Connector %d:\n", i);
276 DRM_INFO(" %s\n", connector_names[connector->connector_type]);
eed45b30
AD		 277 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
278 DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]);
771fe6b9
JG		 279 if (radeon_connector->ddc_bus)
280 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
281 radeon_connector->ddc_bus->rec.mask_clk_reg,
282 radeon_connector->ddc_bus->rec.mask_data_reg,
283 radeon_connector->ddc_bus->rec.a_clk_reg,
284 radeon_connector->ddc_bus->rec.a_data_reg,
9b9fe724
AD		 285 radeon_connector->ddc_bus->rec.en_clk_reg,
286 radeon_connector->ddc_bus->rec.en_data_reg,
287 radeon_connector->ddc_bus->rec.y_clk_reg,
288 radeon_connector->ddc_bus->rec.y_data_reg);
771fe6b9
JG		 289 DRM_INFO(" Encoders:\n");
290 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
291 radeon_encoder = to_radeon_encoder(encoder);
292 devices = radeon_encoder->devices & radeon_connector->devices;
293 if (devices) {
294 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
295 DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);
296 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
297 DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);
298 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
299 DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);
300 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
301 DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);
302 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
303 DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);
304 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
305 DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);
306 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
307 DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
308 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
309 DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
310 if (devices & ATOM_DEVICE_TV1_SUPPORT)
311 DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
312 if (devices & ATOM_DEVICE_CV_SUPPORT)
313 DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]);
314 }
315 }
316 i++;
317 }
318}
319
4ce001ab 320static bool radeon_setup_enc_conn(struct drm_device *dev)
771fe6b9
JG		 321{
322 struct radeon_device *rdev = dev->dev_private;
323 struct drm_connector *drm_connector;
324 bool ret = false;
325
326 if (rdev->bios) {
327 if (rdev->is_atom_bios) {
328 if (rdev->family >= CHIP_R600)
329 ret = radeon_get_atom_connector_info_from_object_table(dev);
330 else
331 ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
332 } else
333 ret = radeon_get_legacy_connector_info_from_bios(dev);
334 } else {
335 if (!ASIC_IS_AVIVO(rdev))
336 ret = radeon_get_legacy_connector_info_from_table(dev);
337 }
338 if (ret) {
1f3b6a45 339 radeon_setup_encoder_clones(dev);
771fe6b9
JG		 340 radeon_print_display_setup(dev);
341 list_for_each_entry(drm_connector, &dev->mode_config.connector_list, head)
342 radeon_ddc_dump(drm_connector);
343 }
344
345 return ret;
346}
347
348int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
349{
771fe6b9
JG		 350 int ret = 0;
351
746c1aa4
DA		 352 if (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
353 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
9fa05c98
AD		 354 if (dig->dp_i2c_bus)
355 radeon_connector->edid = drm_get_edid(&radeon_connector->base, &dig->dp_i2c_bus->adapter);
746c1aa4 356 }
771fe6b9
JG		 357 if (!radeon_connector->ddc_bus)
358 return -1;
4ce001ab 359 if (!radeon_connector->edid) {
ab1e9ea0 360 radeon_i2c_do_lock(radeon_connector->ddc_bus, 1);
0294cf4f 361 radeon_connector->edid = drm_get_edid(&radeon_connector->base, &radeon_connector->ddc_bus->adapter);
ab1e9ea0 362 radeon_i2c_do_lock(radeon_connector->ddc_bus, 0);
0294cf4f
AD		 363 }
364
365 if (radeon_connector->edid) {
366 drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid);
367 ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid);
771fe6b9
JG		 368 return ret;
369 }
370 drm_mode_connector_update_edid_property(&radeon_connector->base, NULL);
42dea5dd 371 return 0;
771fe6b9
JG		 372}
373
374static int radeon_ddc_dump(struct drm_connector *connector)
375{
376 struct edid *edid;
377 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
378 int ret = 0;
379
380 if (!radeon_connector->ddc_bus)
381 return -1;
ab1e9ea0 382 radeon_i2c_do_lock(radeon_connector->ddc_bus, 1);
771fe6b9 383 edid = drm_get_edid(connector, &radeon_connector->ddc_bus->adapter);
ab1e9ea0 384 radeon_i2c_do_lock(radeon_connector->ddc_bus, 0);
771fe6b9
JG		 385 if (edid) {
386 kfree(edid);
387 }
388 return ret;
389}
390
391static inline uint32_t radeon_div(uint64_t n, uint32_t d)
392{
393 uint64_t mod;
394
395 n += d / 2;
396
397 mod = do_div(n, d);
398 return n;
399}
400
401void radeon_compute_pll(struct radeon_pll *pll,
402 uint64_t freq,
403 uint32_t *dot_clock_p,
404 uint32_t *fb_div_p,
405 uint32_t *frac_fb_div_p,
406 uint32_t *ref_div_p,
407 uint32_t *post_div_p,
408 int flags)
409{
410 uint32_t min_ref_div = pll->min_ref_div;
411 uint32_t max_ref_div = pll->max_ref_div;
412 uint32_t min_fractional_feed_div = 0;
413 uint32_t max_fractional_feed_div = 0;
414 uint32_t best_vco = pll->best_vco;
415 uint32_t best_post_div = 1;
416 uint32_t best_ref_div = 1;
417 uint32_t best_feedback_div = 1;
418 uint32_t best_frac_feedback_div = 0;
419 uint32_t best_freq = -1;
420 uint32_t best_error = 0xffffffff;
421 uint32_t best_vco_diff = 1;
422 uint32_t post_div;
423
424 DRM_DEBUG("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
425 freq = freq * 1000;
426
427 if (flags & RADEON_PLL_USE_REF_DIV)
428 min_ref_div = max_ref_div = pll->reference_div;
429 else {
430 while (min_ref_div < max_ref_div-1) {
431 uint32_t mid = (min_ref_div + max_ref_div) / 2;
432 uint32_t pll_in = pll->reference_freq / mid;
433 if (pll_in < pll->pll_in_min)
434 max_ref_div = mid;
435 else if (pll_in > pll->pll_in_max)
436 min_ref_div = mid;
437 else
438 break;
439 }
440 }
441
442 if (flags & RADEON_PLL_USE_FRAC_FB_DIV) {
443 min_fractional_feed_div = pll->min_frac_feedback_div;
444 max_fractional_feed_div = pll->max_frac_feedback_div;
445 }
446
447 for (post_div = pll->min_post_div; post_div <= pll->max_post_div; ++post_div) {
448 uint32_t ref_div;
449
450 if ((flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
451 continue;
452
453 /* legacy radeons only have a few post_divs */
454 if (flags & RADEON_PLL_LEGACY) {
455 if ((post_div == 5) ||
456 (post_div == 7) ||
457 (post_div == 9) ||
458 (post_div == 10) ||
459 (post_div == 11) ||
460 (post_div == 13) ||
461 (post_div == 14) ||
462 (post_div == 15))
463 continue;
464 }
465
466 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
467 uint32_t feedback_div, current_freq = 0, error, vco_diff;
468 uint32_t pll_in = pll->reference_freq / ref_div;
469 uint32_t min_feed_div = pll->min_feedback_div;
470 uint32_t max_feed_div = pll->max_feedback_div + 1;
471
472 if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
473 continue;
474
475 while (min_feed_div < max_feed_div) {
476 uint32_t vco;
477 uint32_t min_frac_feed_div = min_fractional_feed_div;
478 uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
479 uint32_t frac_feedback_div;
480 uint64_t tmp;
481
482 feedback_div = (min_feed_div + max_feed_div) / 2;
483
484 tmp = (uint64_t)pll->reference_freq * feedback_div;
485 vco = radeon_div(tmp, ref_div);
486
487 if (vco < pll->pll_out_min) {
488 min_feed_div = feedback_div + 1;
489 continue;
490 } else if (vco > pll->pll_out_max) {
491 max_feed_div = feedback_div;
492 continue;
493 }
494
495 while (min_frac_feed_div < max_frac_feed_div) {
496 frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
497 tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
498 tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
499 current_freq = radeon_div(tmp, ref_div * post_div);
500
d0e275a9
AD		 501 if (flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
502 error = freq - current_freq;
503 error = error < 0 ? 0xffffffff : error;
504 } else
505 error = abs(current_freq - freq);
771fe6b9
JG		 506 vco_diff = abs(vco - best_vco);
507
508 if ((best_vco == 0 && error < best_error) ||
509 (best_vco != 0 &&
510 (error < best_error - 100 ||
511 (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
512 best_post_div = post_div;
513 best_ref_div = ref_div;
514 best_feedback_div = feedback_div;
515 best_frac_feedback_div = frac_feedback_div;
516 best_freq = current_freq;
517 best_error = error;
518 best_vco_diff = vco_diff;
519 } else if (current_freq == freq) {
520 if (best_freq == -1) {
521 best_post_div = post_div;
522 best_ref_div = ref_div;
523 best_feedback_div = feedback_div;
524 best_frac_feedback_div = frac_feedback_div;
525 best_freq = current_freq;
526 best_error = error;
527 best_vco_diff = vco_diff;
528 } else if (((flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
529 ((flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
530 ((flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
531 ((flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
532 ((flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
533 ((flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
534 best_post_div = post_div;
535 best_ref_div = ref_div;
536 best_feedback_div = feedback_div;
537 best_frac_feedback_div = frac_feedback_div;
538 best_freq = current_freq;
539 best_error = error;
540 best_vco_diff = vco_diff;
541 }
542 }
543 if (current_freq < freq)
544 min_frac_feed_div = frac_feedback_div + 1;
545 else
546 max_frac_feed_div = frac_feedback_div;
547 }
548 if (current_freq < freq)
549 min_feed_div = feedback_div + 1;
550 else
551 max_feed_div = feedback_div;
552 }
553 }
554 }
555
556 *dot_clock_p = best_freq / 10000;
557 *fb_div_p = best_feedback_div;
558 *frac_fb_div_p = best_frac_feedback_div;
559 *ref_div_p = best_ref_div;
560 *post_div_p = best_post_div;
561}
562
563static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
564{
565 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
566 struct drm_device *dev = fb->dev;
567
568 if (fb->fbdev)
569 radeonfb_remove(dev, fb);
570
571 if (radeon_fb->obj) {
572 radeon_gem_object_unpin(radeon_fb->obj);
573 mutex_lock(&dev->struct_mutex);
574 drm_gem_object_unreference(radeon_fb->obj);
575 mutex_unlock(&dev->struct_mutex);
576 }
577 drm_framebuffer_cleanup(fb);
578 kfree(radeon_fb);
579}
580
581static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb,
582 struct drm_file *file_priv,
583 unsigned int *handle)
584{
585 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
586
587 return drm_gem_handle_create(file_priv, radeon_fb->obj, handle);
588}
589
590static const struct drm_framebuffer_funcs radeon_fb_funcs = {
591 .destroy = radeon_user_framebuffer_destroy,
592 .create_handle = radeon_user_framebuffer_create_handle,
593};
594
595struct drm_framebuffer *
596radeon_framebuffer_create(struct drm_device *dev,
597 struct drm_mode_fb_cmd *mode_cmd,
598 struct drm_gem_object *obj)
599{
600 struct radeon_framebuffer *radeon_fb;
601
602 radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL);
603 if (radeon_fb == NULL) {
604 return NULL;
605 }
606 drm_framebuffer_init(dev, &radeon_fb->base, &radeon_fb_funcs);
607 drm_helper_mode_fill_fb_struct(&radeon_fb->base, mode_cmd);
608 radeon_fb->obj = obj;
609 return &radeon_fb->base;
610}
611
612static struct drm_framebuffer *
613radeon_user_framebuffer_create(struct drm_device *dev,
614 struct drm_file *file_priv,
615 struct drm_mode_fb_cmd *mode_cmd)
616{
617 struct drm_gem_object *obj;
618
619 obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handle);
620
621 return radeon_framebuffer_create(dev, mode_cmd, obj);
622}
623
624static const struct drm_mode_config_funcs radeon_mode_funcs = {
625 .fb_create = radeon_user_framebuffer_create,
626 .fb_changed = radeonfb_probe,
627};
628
445282db
DA		 629struct drm_prop_enum_list {
630 int type;
631 char *name;
632};
633
634static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
635{ { 0, "driver" },
636 { 1, "bios" },
637};
638
639static struct drm_prop_enum_list radeon_tv_std_enum_list[] =
640{ { TV_STD_NTSC, "ntsc" },
641 { TV_STD_PAL, "pal" },
642 { TV_STD_PAL_M, "pal-m" },
643 { TV_STD_PAL_60, "pal-60" },
644 { TV_STD_NTSC_J, "ntsc-j" },
645 { TV_STD_SCART_PAL, "scart-pal" },
646 { TV_STD_PAL_CN, "pal-cn" },
647 { TV_STD_SECAM, "secam" },
648};
649
650int radeon_modeset_create_props(struct radeon_device *rdev)
651{
652 int i, sz;
653
654 if (rdev->is_atom_bios) {
655 rdev->mode_info.coherent_mode_property =
656 drm_property_create(rdev->ddev,
657 DRM_MODE_PROP_RANGE,
658 "coherent", 2);
659 if (!rdev->mode_info.coherent_mode_property)
660 return -ENOMEM;
661
662 rdev->mode_info.coherent_mode_property->values[0] = 0;
663 rdev->mode_info.coherent_mode_property->values[0] = 1;
664 }
665
666 if (!ASIC_IS_AVIVO(rdev)) {
667 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
668 rdev->mode_info.tmds_pll_property =
669 drm_property_create(rdev->ddev,
670 DRM_MODE_PROP_ENUM,
671 "tmds_pll", sz);
672 for (i = 0; i < sz; i++) {
673 drm_property_add_enum(rdev->mode_info.tmds_pll_property,
674 i,
675 radeon_tmds_pll_enum_list[i].type,
676 radeon_tmds_pll_enum_list[i].name);
677 }
678 }
679
680 rdev->mode_info.load_detect_property =
681 drm_property_create(rdev->ddev,
682 DRM_MODE_PROP_RANGE,
683 "load detection", 2);
684 if (!rdev->mode_info.load_detect_property)
685 return -ENOMEM;
686 rdev->mode_info.load_detect_property->values[0] = 0;
687 rdev->mode_info.load_detect_property->values[0] = 1;
688
689 drm_mode_create_scaling_mode_property(rdev->ddev);
690
691 sz = ARRAY_SIZE(radeon_tv_std_enum_list);
692 rdev->mode_info.tv_std_property =
693 drm_property_create(rdev->ddev,
694 DRM_MODE_PROP_ENUM,
695 "tv standard", sz);
696 for (i = 0; i < sz; i++) {
697 drm_property_add_enum(rdev->mode_info.tv_std_property,
698 i,
699 radeon_tv_std_enum_list[i].type,
700 radeon_tv_std_enum_list[i].name);
701 }
702
703 return 0;
704}
705
771fe6b9
JG		 706int radeon_modeset_init(struct radeon_device *rdev)
707{
708 int num_crtc = 2, i;
709 int ret;
710
711 drm_mode_config_init(rdev->ddev);
712 rdev->mode_info.mode_config_initialized = true;
713
714 rdev->ddev->mode_config.funcs = (void *)&radeon_mode_funcs;
715
716 if (ASIC_IS_AVIVO(rdev)) {
717 rdev->ddev->mode_config.max_width = 8192;
718 rdev->ddev->mode_config.max_height = 8192;
719 } else {
720 rdev->ddev->mode_config.max_width = 4096;
721 rdev->ddev->mode_config.max_height = 4096;
722 }
723
724 rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
725
445282db
DA		 726 ret = radeon_modeset_create_props(rdev);
727 if (ret) {
728 return ret;
729 }
dfee5614
DA		 730
731 if (rdev->flags & RADEON_SINGLE_CRTC)
732 num_crtc = 1;
733
734 /* allocate crtcs */
771fe6b9
JG		 735 for (i = 0; i < num_crtc; i++) {
736 radeon_crtc_init(rdev->ddev, i);
737 }
738
739 /* okay we should have all the bios connectors */
740 ret = radeon_setup_enc_conn(rdev->ddev);
741 if (!ret) {
742 return ret;
743 }
d4877cf2
AD		 744 /* initialize hpd */
745 radeon_hpd_init(rdev);
771fe6b9
JG		 746 drm_helper_initial_config(rdev->ddev);
747 return 0;
748}
749
750void radeon_modeset_fini(struct radeon_device *rdev)
751{
752 if (rdev->mode_info.mode_config_initialized) {
d4877cf2 753 radeon_hpd_fini(rdev);
771fe6b9
JG		 754 drm_mode_config_cleanup(rdev->ddev);
755 rdev->mode_info.mode_config_initialized = false;
756 }
757}
758
c93bb85b
JG		 759bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
760 struct drm_display_mode *mode,
761 struct drm_display_mode *adjusted_mode)
771fe6b9 762{
c93bb85b
JG		 763 struct drm_device *dev = crtc->dev;
764 struct drm_encoder *encoder;
765 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
766 struct radeon_encoder *radeon_encoder;
767 bool first = true;
771fe6b9 768
c93bb85b
JG		 769 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
770 radeon_encoder = to_radeon_encoder(encoder);
771 if (encoder->crtc != crtc)
772 continue;
773 if (first) {
80297e87
AD		 774 /* set scaling */
775 if (radeon_encoder->rmx_type == RMX_OFF)
776 radeon_crtc->rmx_type = RMX_OFF;
777 else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay ||
778 mode->vdisplay < radeon_encoder->native_mode.vdisplay)
779 radeon_crtc->rmx_type = radeon_encoder->rmx_type;
780 else
781 radeon_crtc->rmx_type = RMX_OFF;
782 /* copy native mode */
c93bb85b 783 memcpy(&radeon_crtc->native_mode,
80297e87 784 &radeon_encoder->native_mode,
de2103e4 785 sizeof(struct drm_display_mode));
c93bb85b
JG		 786 first = false;
787 } else {
788 if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
789 /* WARNING: Right now this can't happen but
790 * in the future we need to check that scaling
791 * are consistent accross different encoder
792 * (ie all encoder can work with the same
793 * scaling).
794 */
795 DRM_ERROR("Scaling not consistent accross encoder.\n");
796 return false;
797 }
771fe6b9
JG		 798 }
799 }
c93bb85b
JG		 800 if (radeon_crtc->rmx_type != RMX_OFF) {
801 fixed20_12 a, b;
802 a.full = rfixed_const(crtc->mode.vdisplay);
de2103e4 803 b.full = rfixed_const(radeon_crtc->native_mode.hdisplay);
c93bb85b
JG		 804 radeon_crtc->vsc.full = rfixed_div(a, b);
805 a.full = rfixed_const(crtc->mode.hdisplay);
de2103e4 806 b.full = rfixed_const(radeon_crtc->native_mode.vdisplay);
c93bb85b 807 radeon_crtc->hsc.full = rfixed_div(a, b);
771fe6b9 808 } else {
c93bb85b
JG		 809 radeon_crtc->vsc.full = rfixed_const(1);
810 radeon_crtc->hsc.full = rfixed_const(1);
771fe6b9 811 }
c93bb85b 812 return true;
771fe6b9 813}
Clone of davem's net-next-2.6 tree