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drm/radeon/kms: add workaround for rn50/rv100 servers
[net-next-2.6.git] / drivers / gpu / drm / radeon / radeon_display.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26#include "drmP.h"
27#include "radeon_drm.h"
28#include "radeon.h"
29
30#include "atom.h"
31#include <asm/div64.h>
32
33#include "drm_crtc_helper.h"
34#include "drm_edid.h"
35
36static int radeon_ddc_dump(struct drm_connector *connector);
37
38static void avivo_crtc_load_lut(struct drm_crtc *crtc)
39{
40 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
41 struct drm_device *dev = crtc->dev;
42 struct radeon_device *rdev = dev->dev_private;
43 int i;
44
45 DRM_DEBUG("%d\n", radeon_crtc->crtc_id);
46 WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
47
48 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
49 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
50 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
51
52 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
53 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
54 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
55
56 WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
57 WREG32(AVIVO_DC_LUT_RW_MODE, 0);
58 WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
59
60 WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
61 for (i = 0; i < 256; i++) {
62 WREG32(AVIVO_DC_LUT_30_COLOR,
63 (radeon_crtc->lut_r[i] << 20) |
64 (radeon_crtc->lut_g[i] << 10) |
65 (radeon_crtc->lut_b[i] << 0));
66 }
67
68 WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id);
69}
70
71static void legacy_crtc_load_lut(struct drm_crtc *crtc)
72{
73 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
74 struct drm_device *dev = crtc->dev;
75 struct radeon_device *rdev = dev->dev_private;
76 int i;
77 uint32_t dac2_cntl;
78
79 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
80 if (radeon_crtc->crtc_id == 0)
81 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
82 else
83 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;
84 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
85
86 WREG8(RADEON_PALETTE_INDEX, 0);
87 for (i = 0; i < 256; i++) {
88 WREG32(RADEON_PALETTE_30_DATA,
89 (radeon_crtc->lut_r[i] << 20) |
90 (radeon_crtc->lut_g[i] << 10) |
91 (radeon_crtc->lut_b[i] << 0));
92 }
93}
94
95void radeon_crtc_load_lut(struct drm_crtc *crtc)
96{
97 struct drm_device *dev = crtc->dev;
98 struct radeon_device *rdev = dev->dev_private;
99
100 if (!crtc->enabled)
101 return;
102
103 if (ASIC_IS_AVIVO(rdev))
104 avivo_crtc_load_lut(crtc);
105 else
106 legacy_crtc_load_lut(crtc);
107}
108
b8c00ac5 109/** Sets the color ramps on behalf of fbcon */
771fe6b9
JG		 110void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
111 u16 blue, int regno)
112{
113 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
114
771fe6b9
JG		 115 radeon_crtc->lut_r[regno] = red >> 6;
116 radeon_crtc->lut_g[regno] = green >> 6;
117 radeon_crtc->lut_b[regno] = blue >> 6;
118}
119
b8c00ac5
DA		 120/** Gets the color ramps on behalf of fbcon */
121void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
122 u16 *blue, int regno)
123{
124 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
125
126 *red = radeon_crtc->lut_r[regno] << 6;
127 *green = radeon_crtc->lut_g[regno] << 6;
128 *blue = radeon_crtc->lut_b[regno] << 6;
129}
130
771fe6b9
JG		 131static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
132 u16 *blue, uint32_t size)
133{
134 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
b8c00ac5 135 int i;
771fe6b9
JG		 136
137 if (size != 256) {
138 return;
139 }
771fe6b9 140
b8c00ac5
DA		 141 /* userspace palettes are always correct as is */
142 for (i = 0; i < 256; i++) {
143 radeon_crtc->lut_r[i] = red[i] >> 6;
144 radeon_crtc->lut_g[i] = green[i] >> 6;
145 radeon_crtc->lut_b[i] = blue[i] >> 6;
771fe6b9 146 }
771fe6b9
JG		 147 radeon_crtc_load_lut(crtc);
148}
149
150static void radeon_crtc_destroy(struct drm_crtc *crtc)
151{
152 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
153
771fe6b9
JG		 154 drm_crtc_cleanup(crtc);
155 kfree(radeon_crtc);
156}
157
158static const struct drm_crtc_funcs radeon_crtc_funcs = {
159 .cursor_set = radeon_crtc_cursor_set,
160 .cursor_move = radeon_crtc_cursor_move,
161 .gamma_set = radeon_crtc_gamma_set,
162 .set_config = drm_crtc_helper_set_config,
163 .destroy = radeon_crtc_destroy,
164};
165
166static void radeon_crtc_init(struct drm_device *dev, int index)
167{
168 struct radeon_device *rdev = dev->dev_private;
169 struct radeon_crtc *radeon_crtc;
170 int i;
171
172 radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
173 if (radeon_crtc == NULL)
174 return;
175
176 drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
177
178 drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
179 radeon_crtc->crtc_id = index;
c93bb85b 180 rdev->mode_info.crtcs[index] = radeon_crtc;
771fe6b9 181
785b93ef 182#if 0
771fe6b9
JG		 183 radeon_crtc->mode_set.crtc = &radeon_crtc->base;
184 radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
185 radeon_crtc->mode_set.num_connectors = 0;
785b93ef 186#endif
771fe6b9
JG		 187
188 for (i = 0; i < 256; i++) {
189 radeon_crtc->lut_r[i] = i << 2;
190 radeon_crtc->lut_g[i] = i << 2;
191 radeon_crtc->lut_b[i] = i << 2;
192 }
193
194 if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))
195 radeon_atombios_init_crtc(dev, radeon_crtc);
196 else
197 radeon_legacy_init_crtc(dev, radeon_crtc);
198}
199
200static const char *encoder_names[34] = {
201 "NONE",
202 "INTERNAL_LVDS",
203 "INTERNAL_TMDS1",
204 "INTERNAL_TMDS2",
205 "INTERNAL_DAC1",
206 "INTERNAL_DAC2",
207 "INTERNAL_SDVOA",
208 "INTERNAL_SDVOB",
209 "SI170B",
210 "CH7303",
211 "CH7301",
212 "INTERNAL_DVO1",
213 "EXTERNAL_SDVOA",
214 "EXTERNAL_SDVOB",
215 "TITFP513",
216 "INTERNAL_LVTM1",
217 "VT1623",
218 "HDMI_SI1930",
219 "HDMI_INTERNAL",
220 "INTERNAL_KLDSCP_TMDS1",
221 "INTERNAL_KLDSCP_DVO1",
222 "INTERNAL_KLDSCP_DAC1",
223 "INTERNAL_KLDSCP_DAC2",
224 "SI178",
225 "MVPU_FPGA",
226 "INTERNAL_DDI",
227 "VT1625",
228 "HDMI_SI1932",
229 "DP_AN9801",
230 "DP_DP501",
231 "INTERNAL_UNIPHY",
232 "INTERNAL_KLDSCP_LVTMA",
233 "INTERNAL_UNIPHY1",
234 "INTERNAL_UNIPHY2",
235};
236
196c58d2 237static const char *connector_names[15] = {
771fe6b9
JG		 238 "Unknown",
239 "VGA",
240 "DVI-I",
241 "DVI-D",
242 "DVI-A",
243 "Composite",
244 "S-video",
245 "LVDS",
246 "Component",
247 "DIN",
248 "DisplayPort",
249 "HDMI-A",
250 "HDMI-B",
196c58d2
AD		 251 "TV",
252 "eDP",
771fe6b9
JG		 253};
254
eed45b30
AD		 255static const char *hpd_names[7] = {
256 "NONE",
257 "HPD1",
258 "HPD2",
259 "HPD3",
260 "HPD4",
261 "HPD5",
262 "HPD6",
263};
264
771fe6b9
JG		 265static void radeon_print_display_setup(struct drm_device *dev)
266{
267 struct drm_connector *connector;
268 struct radeon_connector *radeon_connector;
269 struct drm_encoder *encoder;
270 struct radeon_encoder *radeon_encoder;
271 uint32_t devices;
272 int i = 0;
273
274 DRM_INFO("Radeon Display Connectors\n");
275 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
276 radeon_connector = to_radeon_connector(connector);
277 DRM_INFO("Connector %d:\n", i);
278 DRM_INFO(" %s\n", connector_names[connector->connector_type]);
eed45b30
AD		 279 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
280 DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]);
771fe6b9
JG		 281 if (radeon_connector->ddc_bus)
282 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
283 radeon_connector->ddc_bus->rec.mask_clk_reg,
284 radeon_connector->ddc_bus->rec.mask_data_reg,
285 radeon_connector->ddc_bus->rec.a_clk_reg,
286 radeon_connector->ddc_bus->rec.a_data_reg,
9b9fe724
AD		 287 radeon_connector->ddc_bus->rec.en_clk_reg,
288 radeon_connector->ddc_bus->rec.en_data_reg,
289 radeon_connector->ddc_bus->rec.y_clk_reg,
290 radeon_connector->ddc_bus->rec.y_data_reg);
771fe6b9
JG		 291 DRM_INFO(" Encoders:\n");
292 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
293 radeon_encoder = to_radeon_encoder(encoder);
294 devices = radeon_encoder->devices & radeon_connector->devices;
295 if (devices) {
296 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
297 DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);
298 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
299 DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);
300 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
301 DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);
302 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
303 DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);
304 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
305 DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);
306 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
307 DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);
308 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
309 DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
310 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
311 DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
312 if (devices & ATOM_DEVICE_TV1_SUPPORT)
313 DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
314 if (devices & ATOM_DEVICE_CV_SUPPORT)
315 DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]);
316 }
317 }
318 i++;
319 }
320}
321
4ce001ab 322static bool radeon_setup_enc_conn(struct drm_device *dev)
771fe6b9
JG		 323{
324 struct radeon_device *rdev = dev->dev_private;
325 struct drm_connector *drm_connector;
326 bool ret = false;
327
328 if (rdev->bios) {
329 if (rdev->is_atom_bios) {
330 if (rdev->family >= CHIP_R600)
331 ret = radeon_get_atom_connector_info_from_object_table(dev);
332 else
333 ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
b9597a1c 334 } else {
771fe6b9 335 ret = radeon_get_legacy_connector_info_from_bios(dev);
b9597a1c
AD		 336 if (ret == false)
337 ret = radeon_get_legacy_connector_info_from_table(dev);
338 }
771fe6b9
JG		 339 } else {
340 if (!ASIC_IS_AVIVO(rdev))
341 ret = radeon_get_legacy_connector_info_from_table(dev);
342 }
343 if (ret) {
1f3b6a45 344 radeon_setup_encoder_clones(dev);
771fe6b9
JG		 345 radeon_print_display_setup(dev);
346 list_for_each_entry(drm_connector, &dev->mode_config.connector_list, head)
347 radeon_ddc_dump(drm_connector);
348 }
349
350 return ret;
351}
352
353int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
354{
771fe6b9
JG		 355 int ret = 0;
356
196c58d2
AD		 357 if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
358 (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) {
746c1aa4 359 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
7a15cbd4
DA		 360 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
361 dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && dig->dp_i2c_bus)
9fa05c98 362 radeon_connector->edid = drm_get_edid(&radeon_connector->base, &dig->dp_i2c_bus->adapter);
746c1aa4 363 }
771fe6b9
JG		 364 if (!radeon_connector->ddc_bus)
365 return -1;
4ce001ab 366 if (!radeon_connector->edid) {
0294cf4f 367 radeon_connector->edid = drm_get_edid(&radeon_connector->base, &radeon_connector->ddc_bus->adapter);
0294cf4f
AD		 368 }
369
370 if (radeon_connector->edid) {
371 drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid);
372 ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid);
771fe6b9
JG		 373 return ret;
374 }
375 drm_mode_connector_update_edid_property(&radeon_connector->base, NULL);
42dea5dd 376 return 0;
771fe6b9
JG		 377}
378
379static int radeon_ddc_dump(struct drm_connector *connector)
380{
381 struct edid *edid;
382 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
383 int ret = 0;
384
385 if (!radeon_connector->ddc_bus)
386 return -1;
771fe6b9 387 edid = drm_get_edid(connector, &radeon_connector->ddc_bus->adapter);
771fe6b9
JG		 388 if (edid) {
389 kfree(edid);
390 }
391 return ret;
392}
393
394static inline uint32_t radeon_div(uint64_t n, uint32_t d)
395{
396 uint64_t mod;
397
398 n += d / 2;
399
400 mod = do_div(n, d);
401 return n;
402}
403
404void radeon_compute_pll(struct radeon_pll *pll,
405 uint64_t freq,
406 uint32_t *dot_clock_p,
407 uint32_t *fb_div_p,
408 uint32_t *frac_fb_div_p,
409 uint32_t *ref_div_p,
fc10332b 410 uint32_t *post_div_p)
771fe6b9
JG		 411{
412 uint32_t min_ref_div = pll->min_ref_div;
413 uint32_t max_ref_div = pll->max_ref_div;
fc10332b
AD		 414 uint32_t min_post_div = pll->min_post_div;
415 uint32_t max_post_div = pll->max_post_div;
771fe6b9
JG		 416 uint32_t min_fractional_feed_div = 0;
417 uint32_t max_fractional_feed_div = 0;
418 uint32_t best_vco = pll->best_vco;
419 uint32_t best_post_div = 1;
420 uint32_t best_ref_div = 1;
421 uint32_t best_feedback_div = 1;
422 uint32_t best_frac_feedback_div = 0;
423 uint32_t best_freq = -1;
424 uint32_t best_error = 0xffffffff;
425 uint32_t best_vco_diff = 1;
426 uint32_t post_div;
427
428 DRM_DEBUG("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
429 freq = freq * 1000;
430
fc10332b 431 if (pll->flags & RADEON_PLL_USE_REF_DIV)
771fe6b9
JG		 432 min_ref_div = max_ref_div = pll->reference_div;
433 else {
434 while (min_ref_div < max_ref_div-1) {
435 uint32_t mid = (min_ref_div + max_ref_div) / 2;
436 uint32_t pll_in = pll->reference_freq / mid;
437 if (pll_in < pll->pll_in_min)
438 max_ref_div = mid;
439 else if (pll_in > pll->pll_in_max)
440 min_ref_div = mid;
441 else
442 break;
443 }
444 }
445
fc10332b
AD		 446 if (pll->flags & RADEON_PLL_USE_POST_DIV)
447 min_post_div = max_post_div = pll->post_div;
448
449 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
771fe6b9
JG		 450 min_fractional_feed_div = pll->min_frac_feedback_div;
451 max_fractional_feed_div = pll->max_frac_feedback_div;
452 }
453
fc10332b 454 for (post_div = min_post_div; post_div <= max_post_div; ++post_div) {
771fe6b9
JG		 455 uint32_t ref_div;
456
fc10332b 457 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
771fe6b9
JG		 458 continue;
459
460 /* legacy radeons only have a few post_divs */
fc10332b 461 if (pll->flags & RADEON_PLL_LEGACY) {
771fe6b9
JG		 462 if ((post_div == 5) ||
463 (post_div == 7) ||
464 (post_div == 9) ||
465 (post_div == 10) ||
466 (post_div == 11) ||
467 (post_div == 13) ||
468 (post_div == 14) ||
469 (post_div == 15))
470 continue;
471 }
472
473 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
474 uint32_t feedback_div, current_freq = 0, error, vco_diff;
475 uint32_t pll_in = pll->reference_freq / ref_div;
476 uint32_t min_feed_div = pll->min_feedback_div;
477 uint32_t max_feed_div = pll->max_feedback_div + 1;
478
479 if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
480 continue;
481
482 while (min_feed_div < max_feed_div) {
483 uint32_t vco;
484 uint32_t min_frac_feed_div = min_fractional_feed_div;
485 uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
486 uint32_t frac_feedback_div;
487 uint64_t tmp;
488
489 feedback_div = (min_feed_div + max_feed_div) / 2;
490
491 tmp = (uint64_t)pll->reference_freq * feedback_div;
492 vco = radeon_div(tmp, ref_div);
493
494 if (vco < pll->pll_out_min) {
495 min_feed_div = feedback_div + 1;
496 continue;
497 } else if (vco > pll->pll_out_max) {
498 max_feed_div = feedback_div;
499 continue;
500 }
501
502 while (min_frac_feed_div < max_frac_feed_div) {
503 frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
504 tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
505 tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
506 current_freq = radeon_div(tmp, ref_div * post_div);
507
fc10332b 508 if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
d0e275a9
AD		 509 error = freq - current_freq;
510 error = error < 0 ? 0xffffffff : error;
511 } else
512 error = abs(current_freq - freq);
771fe6b9
JG		 513 vco_diff = abs(vco - best_vco);
514
515 if ((best_vco == 0 && error < best_error) ||
516 (best_vco != 0 &&
517 (error < best_error - 100 ||
518 (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
519 best_post_div = post_div;
520 best_ref_div = ref_div;
521 best_feedback_div = feedback_div;
522 best_frac_feedback_div = frac_feedback_div;
523 best_freq = current_freq;
524 best_error = error;
525 best_vco_diff = vco_diff;
526 } else if (current_freq == freq) {
527 if (best_freq == -1) {
528 best_post_div = post_div;
529 best_ref_div = ref_div;
530 best_feedback_div = feedback_div;
531 best_frac_feedback_div = frac_feedback_div;
532 best_freq = current_freq;
533 best_error = error;
534 best_vco_diff = vco_diff;
fc10332b
AD		 535 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
536 ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
537 ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
538 ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
539 ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
540 ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
771fe6b9
JG		 541 best_post_div = post_div;
542 best_ref_div = ref_div;
543 best_feedback_div = feedback_div;
544 best_frac_feedback_div = frac_feedback_div;
545 best_freq = current_freq;
546 best_error = error;
547 best_vco_diff = vco_diff;
548 }
549 }
550 if (current_freq < freq)
551 min_frac_feed_div = frac_feedback_div + 1;
552 else
553 max_frac_feed_div = frac_feedback_div;
554 }
555 if (current_freq < freq)
556 min_feed_div = feedback_div + 1;
557 else
558 max_feed_div = feedback_div;
559 }
560 }
561 }
562
563 *dot_clock_p = best_freq / 10000;
564 *fb_div_p = best_feedback_div;
565 *frac_fb_div_p = best_frac_feedback_div;
566 *ref_div_p = best_ref_div;
567 *post_div_p = best_post_div;
568}
569
b27b6375
AD		 570void radeon_compute_pll_avivo(struct radeon_pll *pll,
571 uint64_t freq,
572 uint32_t *dot_clock_p,
573 uint32_t *fb_div_p,
574 uint32_t *frac_fb_div_p,
575 uint32_t *ref_div_p,
fc10332b 576 uint32_t *post_div_p)
b27b6375
AD		 577{
578 fixed20_12 m, n, frac_n, p, f_vco, f_pclk, best_freq;
579 fixed20_12 pll_out_max, pll_out_min;
580 fixed20_12 pll_in_max, pll_in_min;
581 fixed20_12 reference_freq;
582 fixed20_12 error, ffreq, a, b;
583
584 pll_out_max.full = rfixed_const(pll->pll_out_max);
585 pll_out_min.full = rfixed_const(pll->pll_out_min);
586 pll_in_max.full = rfixed_const(pll->pll_in_max);
587 pll_in_min.full = rfixed_const(pll->pll_in_min);
588 reference_freq.full = rfixed_const(pll->reference_freq);
589 do_div(freq, 10);
590 ffreq.full = rfixed_const(freq);
591 error.full = rfixed_const(100 * 100);
592
593 /* max p */
594 p.full = rfixed_div(pll_out_max, ffreq);
595 p.full = rfixed_floor(p);
596
597 /* min m */
598 m.full = rfixed_div(reference_freq, pll_in_max);
599 m.full = rfixed_ceil(m);
600
601 while (1) {
602 n.full = rfixed_div(ffreq, reference_freq);
603 n.full = rfixed_mul(n, m);
604 n.full = rfixed_mul(n, p);
605
606 f_vco.full = rfixed_div(n, m);
607 f_vco.full = rfixed_mul(f_vco, reference_freq);
608
609 f_pclk.full = rfixed_div(f_vco, p);
610
611 if (f_pclk.full > ffreq.full)
612 error.full = f_pclk.full - ffreq.full;
613 else
614 error.full = ffreq.full - f_pclk.full;
615 error.full = rfixed_div(error, f_pclk);
616 a.full = rfixed_const(100 * 100);
617 error.full = rfixed_mul(error, a);
618
619 a.full = rfixed_mul(m, p);
620 a.full = rfixed_div(n, a);
621 best_freq.full = rfixed_mul(reference_freq, a);
622
623 if (rfixed_trunc(error) < 25)
624 break;
625
626 a.full = rfixed_const(1);
627 m.full = m.full + a.full;
628 a.full = rfixed_div(reference_freq, m);
629 if (a.full >= pll_in_min.full)
630 continue;
631
632 m.full = rfixed_div(reference_freq, pll_in_max);
633 m.full = rfixed_ceil(m);
634 a.full= rfixed_const(1);
635 p.full = p.full - a.full;
636 a.full = rfixed_mul(p, ffreq);
637 if (a.full >= pll_out_min.full)
638 continue;
639 else {
640 DRM_ERROR("Unable to find pll dividers\n");
641 break;
642 }
643 }
644
645 a.full = rfixed_const(10);
646 b.full = rfixed_mul(n, a);
647
648 frac_n.full = rfixed_floor(n);
649 frac_n.full = rfixed_mul(frac_n, a);
650 frac_n.full = b.full - frac_n.full;
651
652 *dot_clock_p = rfixed_trunc(best_freq);
653 *fb_div_p = rfixed_trunc(n);
654 *frac_fb_div_p = rfixed_trunc(frac_n);
655 *ref_div_p = rfixed_trunc(m);
656 *post_div_p = rfixed_trunc(p);
657
658 DRM_DEBUG("%u %d.%d, %d, %d\n", *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p, *ref_div_p, *post_div_p);
659}
660
771fe6b9
JG		 661static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
662{
663 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
664 struct drm_device *dev = fb->dev;
665
666 if (fb->fbdev)
667 radeonfb_remove(dev, fb);
668
669 if (radeon_fb->obj) {
771fe6b9
JG		 670 mutex_lock(&dev->struct_mutex);
671 drm_gem_object_unreference(radeon_fb->obj);
672 mutex_unlock(&dev->struct_mutex);
673 }
674 drm_framebuffer_cleanup(fb);
675 kfree(radeon_fb);
676}
677
678static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb,
679 struct drm_file *file_priv,
680 unsigned int *handle)
681{
682 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
683
684 return drm_gem_handle_create(file_priv, radeon_fb->obj, handle);
685}
686
687static const struct drm_framebuffer_funcs radeon_fb_funcs = {
688 .destroy = radeon_user_framebuffer_destroy,
689 .create_handle = radeon_user_framebuffer_create_handle,
690};
691
692struct drm_framebuffer *
693radeon_framebuffer_create(struct drm_device *dev,
694 struct drm_mode_fb_cmd *mode_cmd,
695 struct drm_gem_object *obj)
696{
697 struct radeon_framebuffer *radeon_fb;
698
699 radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL);
700 if (radeon_fb == NULL) {
701 return NULL;
702 }
703 drm_framebuffer_init(dev, &radeon_fb->base, &radeon_fb_funcs);
704 drm_helper_mode_fill_fb_struct(&radeon_fb->base, mode_cmd);
705 radeon_fb->obj = obj;
706 return &radeon_fb->base;
707}
708
709static struct drm_framebuffer *
710radeon_user_framebuffer_create(struct drm_device *dev,
711 struct drm_file *file_priv,
712 struct drm_mode_fb_cmd *mode_cmd)
713{
714 struct drm_gem_object *obj;
715
716 obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handle);
7e71c9e2
JG		 717 if (obj == NULL) {
718 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
719 "can't create framebuffer\n", mode_cmd->handle);
720 return NULL;
721 }
771fe6b9
JG		 722 return radeon_framebuffer_create(dev, mode_cmd, obj);
723}
724
725static const struct drm_mode_config_funcs radeon_mode_funcs = {
726 .fb_create = radeon_user_framebuffer_create,
727 .fb_changed = radeonfb_probe,
728};
729
445282db
DA		 730struct drm_prop_enum_list {
731 int type;
732 char *name;
733};
734
735static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
736{ { 0, "driver" },
737 { 1, "bios" },
738};
739
740static struct drm_prop_enum_list radeon_tv_std_enum_list[] =
741{ { TV_STD_NTSC, "ntsc" },
742 { TV_STD_PAL, "pal" },
743 { TV_STD_PAL_M, "pal-m" },
744 { TV_STD_PAL_60, "pal-60" },
745 { TV_STD_NTSC_J, "ntsc-j" },
746 { TV_STD_SCART_PAL, "scart-pal" },
747 { TV_STD_PAL_CN, "pal-cn" },
748 { TV_STD_SECAM, "secam" },
749};
750
d79766fa 751static int radeon_modeset_create_props(struct radeon_device *rdev)
445282db
DA		 752{
753 int i, sz;
754
755 if (rdev->is_atom_bios) {
756 rdev->mode_info.coherent_mode_property =
757 drm_property_create(rdev->ddev,
758 DRM_MODE_PROP_RANGE,
759 "coherent", 2);
760 if (!rdev->mode_info.coherent_mode_property)
761 return -ENOMEM;
762
763 rdev->mode_info.coherent_mode_property->values[0] = 0;
390d0bbe 764 rdev->mode_info.coherent_mode_property->values[1] = 1;
445282db
DA		 765 }
766
767 if (!ASIC_IS_AVIVO(rdev)) {
768 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
769 rdev->mode_info.tmds_pll_property =
770 drm_property_create(rdev->ddev,
771 DRM_MODE_PROP_ENUM,
772 "tmds_pll", sz);
773 for (i = 0; i < sz; i++) {
774 drm_property_add_enum(rdev->mode_info.tmds_pll_property,
775 i,
776 radeon_tmds_pll_enum_list[i].type,
777 radeon_tmds_pll_enum_list[i].name);
778 }
779 }
780
781 rdev->mode_info.load_detect_property =
782 drm_property_create(rdev->ddev,
783 DRM_MODE_PROP_RANGE,
784 "load detection", 2);
785 if (!rdev->mode_info.load_detect_property)
786 return -ENOMEM;
787 rdev->mode_info.load_detect_property->values[0] = 0;
390d0bbe 788 rdev->mode_info.load_detect_property->values[1] = 1;
445282db
DA		 789
790 drm_mode_create_scaling_mode_property(rdev->ddev);
791
792 sz = ARRAY_SIZE(radeon_tv_std_enum_list);
793 rdev->mode_info.tv_std_property =
794 drm_property_create(rdev->ddev,
795 DRM_MODE_PROP_ENUM,
796 "tv standard", sz);
797 for (i = 0; i < sz; i++) {
798 drm_property_add_enum(rdev->mode_info.tv_std_property,
799 i,
800 radeon_tv_std_enum_list[i].type,
801 radeon_tv_std_enum_list[i].name);
802 }
803
804 return 0;
805}
806
771fe6b9
JG		 807int radeon_modeset_init(struct radeon_device *rdev)
808{
809 int num_crtc = 2, i;
810 int ret;
811
812 drm_mode_config_init(rdev->ddev);
813 rdev->mode_info.mode_config_initialized = true;
814
815 rdev->ddev->mode_config.funcs = (void *)&radeon_mode_funcs;
816
817 if (ASIC_IS_AVIVO(rdev)) {
818 rdev->ddev->mode_config.max_width = 8192;
819 rdev->ddev->mode_config.max_height = 8192;
820 } else {
821 rdev->ddev->mode_config.max_width = 4096;
822 rdev->ddev->mode_config.max_height = 4096;
823 }
824
825 rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
826
445282db
DA		 827 ret = radeon_modeset_create_props(rdev);
828 if (ret) {
829 return ret;
830 }
dfee5614
DA		 831
832 if (rdev->flags & RADEON_SINGLE_CRTC)
833 num_crtc = 1;
834
835 /* allocate crtcs */
771fe6b9
JG		 836 for (i = 0; i < num_crtc; i++) {
837 radeon_crtc_init(rdev->ddev, i);
838 }
839
840 /* okay we should have all the bios connectors */
841 ret = radeon_setup_enc_conn(rdev->ddev);
842 if (!ret) {
843 return ret;
844 }
d4877cf2
AD		 845 /* initialize hpd */
846 radeon_hpd_init(rdev);
771fe6b9
JG		 847 drm_helper_initial_config(rdev->ddev);
848 return 0;
849}
850
851void radeon_modeset_fini(struct radeon_device *rdev)
852{
853 if (rdev->mode_info.mode_config_initialized) {
d4877cf2 854 radeon_hpd_fini(rdev);
771fe6b9
JG		 855 drm_mode_config_cleanup(rdev->ddev);
856 rdev->mode_info.mode_config_initialized = false;
857 }
858}
859
c93bb85b
JG		 860bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
861 struct drm_display_mode *mode,
862 struct drm_display_mode *adjusted_mode)
771fe6b9 863{
c93bb85b
JG		 864 struct drm_device *dev = crtc->dev;
865 struct drm_encoder *encoder;
866 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
867 struct radeon_encoder *radeon_encoder;
868 bool first = true;
771fe6b9 869
c93bb85b
JG		 870 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
871 radeon_encoder = to_radeon_encoder(encoder);
872 if (encoder->crtc != crtc)
873 continue;
874 if (first) {
80297e87
AD		 875 /* set scaling */
876 if (radeon_encoder->rmx_type == RMX_OFF)
877 radeon_crtc->rmx_type = RMX_OFF;
878 else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay ||
879 mode->vdisplay < radeon_encoder->native_mode.vdisplay)
880 radeon_crtc->rmx_type = radeon_encoder->rmx_type;
881 else
882 radeon_crtc->rmx_type = RMX_OFF;
883 /* copy native mode */
c93bb85b 884 memcpy(&radeon_crtc->native_mode,
80297e87 885 &radeon_encoder->native_mode,
de2103e4 886 sizeof(struct drm_display_mode));
c93bb85b
JG		 887 first = false;
888 } else {
889 if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
890 /* WARNING: Right now this can't happen but
891 * in the future we need to check that scaling
892 * are consistent accross different encoder
893 * (ie all encoder can work with the same
894 * scaling).
895 */
896 DRM_ERROR("Scaling not consistent accross encoder.\n");
897 return false;
898 }
771fe6b9
JG		 899 }
900 }
c93bb85b
JG		 901 if (radeon_crtc->rmx_type != RMX_OFF) {
902 fixed20_12 a, b;
903 a.full = rfixed_const(crtc->mode.vdisplay);
de2103e4 904 b.full = rfixed_const(radeon_crtc->native_mode.hdisplay);
c93bb85b
JG		 905 radeon_crtc->vsc.full = rfixed_div(a, b);
906 a.full = rfixed_const(crtc->mode.hdisplay);
de2103e4 907 b.full = rfixed_const(radeon_crtc->native_mode.vdisplay);
c93bb85b 908 radeon_crtc->hsc.full = rfixed_div(a, b);
771fe6b9 909 } else {
c93bb85b
JG		 910 radeon_crtc->vsc.full = rfixed_const(1);
911 radeon_crtc->hsc.full = rfixed_const(1);
771fe6b9 912 }
c93bb85b 913 return true;
771fe6b9 914}
Clone of davem's net-next-2.6 tree