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drm/radeon/kms: fix typo in quirks
[net-next-2.6.git] / drivers / gpu / drm / radeon / radeon_device.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include <linux/console.h>
29#include <drm/drmP.h>
30#include <drm/drm_crtc_helper.h>
31#include <drm/radeon_drm.h>
32#include "radeon_reg.h"
33#include "radeon.h"
34#include "radeon_asic.h"
35#include "atom.h"
36
b1e3a6d1
MD		 37/*
38 * Clear GPU surface registers.
39 */
3ce0a23d 40void radeon_surface_init(struct radeon_device *rdev)
b1e3a6d1
MD		 41{
42 /* FIXME: check this out */
43 if (rdev->family < CHIP_R600) {
44 int i;
45
46 for (i = 0; i < 8; i++) {
47 WREG32(RADEON_SURFACE0_INFO +
48 i * (RADEON_SURFACE1_INFO - RADEON_SURFACE0_INFO),
49 0);
50 }
e024e110
DA		 51 /* enable surfaces */
52 WREG32(RADEON_SURFACE_CNTL, 0);
b1e3a6d1
MD		 53 }
54}
55
771fe6b9
JG		 56/*
57 * GPU scratch registers helpers function.
58 */
3ce0a23d 59void radeon_scratch_init(struct radeon_device *rdev)
771fe6b9
JG		 60{
61 int i;
62
63 /* FIXME: check this out */
64 if (rdev->family < CHIP_R300) {
65 rdev->scratch.num_reg = 5;
66 } else {
67 rdev->scratch.num_reg = 7;
68 }
69 for (i = 0; i < rdev->scratch.num_reg; i++) {
70 rdev->scratch.free[i] = true;
71 rdev->scratch.reg[i] = RADEON_SCRATCH_REG0 + (i * 4);
72 }
73}
74
75int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg)
76{
77 int i;
78
79 for (i = 0; i < rdev->scratch.num_reg; i++) {
80 if (rdev->scratch.free[i]) {
81 rdev->scratch.free[i] = false;
82 *reg = rdev->scratch.reg[i];
83 return 0;
84 }
85 }
86 return -EINVAL;
87}
88
89void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
90{
91 int i;
92
93 for (i = 0; i < rdev->scratch.num_reg; i++) {
94 if (rdev->scratch.reg[i] == reg) {
95 rdev->scratch.free[i] = true;
96 return;
97 }
98 }
99}
100
101/*
102 * MC common functions
103 */
104int radeon_mc_setup(struct radeon_device *rdev)
105{
106 uint32_t tmp;
107
108 /* Some chips have an "issue" with the memory controller, the
109 * location must be aligned to the size. We just align it down,
110 * too bad if we walk over the top of system memory, we don't
111 * use DMA without a remapped anyway.
112 * Affected chips are rv280, all r3xx, and all r4xx, but not IGP
113 */
114 /* FGLRX seems to setup like this, VRAM a 0, then GART.
115 */
116 /*
117 * Note: from R6xx the address space is 40bits but here we only
118 * use 32bits (still have to see a card which would exhaust 4G
119 * address space).
120 */
121 if (rdev->mc.vram_location != 0xFFFFFFFFUL) {
122 /* vram location was already setup try to put gtt after
123 * if it fits */
7a50f01a 124 tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size;
771fe6b9
JG		 125 tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1);
126 if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) {
127 rdev->mc.gtt_location = tmp;
128 } else {
129 if (rdev->mc.gtt_size >= rdev->mc.vram_location) {
130 printk(KERN_ERR "[drm] GTT too big to fit "
131 "before or after vram location.\n");
132 return -EINVAL;
133 }
134 rdev->mc.gtt_location = 0;
135 }
136 } else if (rdev->mc.gtt_location != 0xFFFFFFFFUL) {
137 /* gtt location was already setup try to put vram before
138 * if it fits */
7a50f01a 139 if (rdev->mc.mc_vram_size < rdev->mc.gtt_location) {
771fe6b9
JG		 140 rdev->mc.vram_location = 0;
141 } else {
142 tmp = rdev->mc.gtt_location + rdev->mc.gtt_size;
7a50f01a
DA		 143 tmp += (rdev->mc.mc_vram_size - 1);
144 tmp &= ~(rdev->mc.mc_vram_size - 1);
145 if ((0xFFFFFFFFUL - tmp) >= rdev->mc.mc_vram_size) {
771fe6b9
JG		 146 rdev->mc.vram_location = tmp;
147 } else {
148 printk(KERN_ERR "[drm] vram too big to fit "
149 "before or after GTT location.\n");
150 return -EINVAL;
151 }
152 }
153 } else {
154 rdev->mc.vram_location = 0;
17332925
DA		 155 tmp = rdev->mc.mc_vram_size;
156 tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1);
157 rdev->mc.gtt_location = tmp;
771fe6b9 158 }
3ce0a23d 159 DRM_INFO("radeon: VRAM %uM\n", (unsigned)(rdev->mc.mc_vram_size >> 20));
771fe6b9 160 DRM_INFO("radeon: VRAM from 0x%08X to 0x%08X\n",
3ce0a23d
JG		 161 (unsigned)rdev->mc.vram_location,
162 (unsigned)(rdev->mc.vram_location + rdev->mc.mc_vram_size - 1));
163 DRM_INFO("radeon: GTT %uM\n", (unsigned)(rdev->mc.gtt_size >> 20));
771fe6b9 164 DRM_INFO("radeon: GTT from 0x%08X to 0x%08X\n",
3ce0a23d
JG		 165 (unsigned)rdev->mc.gtt_location,
166 (unsigned)(rdev->mc.gtt_location + rdev->mc.gtt_size - 1));
771fe6b9
JG		 167 return 0;
168}
169
170
171/*
172 * GPU helpers function.
173 */
174static bool radeon_card_posted(struct radeon_device *rdev)
175{
176 uint32_t reg;
177
178 /* first check CRTCs */
179 if (ASIC_IS_AVIVO(rdev)) {
180 reg = RREG32(AVIVO_D1CRTC_CONTROL) |
181 RREG32(AVIVO_D2CRTC_CONTROL);
182 if (reg & AVIVO_CRTC_EN) {
183 return true;
184 }
185 } else {
186 reg = RREG32(RADEON_CRTC_GEN_CNTL) |
187 RREG32(RADEON_CRTC2_GEN_CNTL);
188 if (reg & RADEON_CRTC_EN) {
189 return true;
190 }
191 }
192
193 /* then check MEM_SIZE, in case the crtcs are off */
194 if (rdev->family >= CHIP_R600)
195 reg = RREG32(R600_CONFIG_MEMSIZE);
196 else
197 reg = RREG32(RADEON_CONFIG_MEMSIZE);
198
199 if (reg)
200 return true;
201
202 return false;
203
204}
205
3ce0a23d
JG		 206int radeon_dummy_page_init(struct radeon_device *rdev)
207{
208 rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
209 if (rdev->dummy_page.page == NULL)
210 return -ENOMEM;
211 rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page,
212 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
213 if (!rdev->dummy_page.addr) {
214 __free_page(rdev->dummy_page.page);
215 rdev->dummy_page.page = NULL;
216 return -ENOMEM;
217 }
218 return 0;
219}
220
221void radeon_dummy_page_fini(struct radeon_device *rdev)
222{
223 if (rdev->dummy_page.page == NULL)
224 return;
225 pci_unmap_page(rdev->pdev, rdev->dummy_page.addr,
226 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
227 __free_page(rdev->dummy_page.page);
228 rdev->dummy_page.page = NULL;
229}
230
771fe6b9
JG		 231
232/*
233 * Registers accessors functions.
234 */
235uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
236{
237 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
238 BUG_ON(1);
239 return 0;
240}
241
242void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
243{
244 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
245 reg, v);
246 BUG_ON(1);
247}
248
249void radeon_register_accessor_init(struct radeon_device *rdev)
250{
771fe6b9
JG		 251 rdev->mc_rreg = &radeon_invalid_rreg;
252 rdev->mc_wreg = &radeon_invalid_wreg;
253 rdev->pll_rreg = &radeon_invalid_rreg;
254 rdev->pll_wreg = &radeon_invalid_wreg;
771fe6b9
JG		 255 rdev->pciep_rreg = &radeon_invalid_rreg;
256 rdev->pciep_wreg = &radeon_invalid_wreg;
257
258 /* Don't change order as we are overridding accessor. */
259 if (rdev->family < CHIP_RV515) {
de1b2898
DA		 260 rdev->pcie_reg_mask = 0xff;
261 } else {
262 rdev->pcie_reg_mask = 0x7ff;
771fe6b9
JG		 263 }
264 /* FIXME: not sure here */
265 if (rdev->family <= CHIP_R580) {
266 rdev->pll_rreg = &r100_pll_rreg;
267 rdev->pll_wreg = &r100_pll_wreg;
268 }
905b6822
JG		 269 if (rdev->family >= CHIP_R420) {
270 rdev->mc_rreg = &r420_mc_rreg;
271 rdev->mc_wreg = &r420_mc_wreg;
272 }
771fe6b9
JG		 273 if (rdev->family >= CHIP_RV515) {
274 rdev->mc_rreg = &rv515_mc_rreg;
275 rdev->mc_wreg = &rv515_mc_wreg;
276 }
277 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
278 rdev->mc_rreg = &rs400_mc_rreg;
279 rdev->mc_wreg = &rs400_mc_wreg;
280 }
281 if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
282 rdev->mc_rreg = &rs690_mc_rreg;
283 rdev->mc_wreg = &rs690_mc_wreg;
284 }
285 if (rdev->family == CHIP_RS600) {
286 rdev->mc_rreg = &rs600_mc_rreg;
287 rdev->mc_wreg = &rs600_mc_wreg;
288 }
289 if (rdev->family >= CHIP_R600) {
290 rdev->pciep_rreg = &r600_pciep_rreg;
291 rdev->pciep_wreg = &r600_pciep_wreg;
292 }
293}
294
295
296/*
297 * ASIC
298 */
299int radeon_asic_init(struct radeon_device *rdev)
300{
301 radeon_register_accessor_init(rdev);
302 switch (rdev->family) {
303 case CHIP_R100:
304 case CHIP_RV100:
305 case CHIP_RS100:
306 case CHIP_RV200:
307 case CHIP_RS200:
308 case CHIP_R200:
309 case CHIP_RV250:
310 case CHIP_RS300:
311 case CHIP_RV280:
312 rdev->asic = &r100_asic;
313 break;
314 case CHIP_R300:
315 case CHIP_R350:
316 case CHIP_RV350:
317 case CHIP_RV380:
318 rdev->asic = &r300_asic;
319 break;
320 case CHIP_R420:
321 case CHIP_R423:
322 case CHIP_RV410:
323 rdev->asic = &r420_asic;
324 break;
325 case CHIP_RS400:
326 case CHIP_RS480:
327 rdev->asic = &rs400_asic;
328 break;
329 case CHIP_RS600:
330 rdev->asic = &rs600_asic;
331 break;
332 case CHIP_RS690:
333 case CHIP_RS740:
334 rdev->asic = &rs690_asic;
335 break;
336 case CHIP_RV515:
337 rdev->asic = &rv515_asic;
338 break;
339 case CHIP_R520:
340 case CHIP_RV530:
341 case CHIP_RV560:
342 case CHIP_RV570:
343 case CHIP_R580:
344 rdev->asic = &r520_asic;
345 break;
346 case CHIP_R600:
347 case CHIP_RV610:
348 case CHIP_RV630:
349 case CHIP_RV620:
350 case CHIP_RV635:
351 case CHIP_RV670:
352 case CHIP_RS780:
3ce0a23d
JG		 353 case CHIP_RS880:
354 rdev->asic = &r600_asic;
355 break;
771fe6b9
JG		 356 case CHIP_RV770:
357 case CHIP_RV730:
358 case CHIP_RV710:
3ce0a23d
JG		 359 case CHIP_RV740:
360 rdev->asic = &rv770_asic;
361 break;
771fe6b9
JG		 362 default:
363 /* FIXME: not supported yet */
364 return -EINVAL;
365 }
366 return 0;
367}
368
369
370/*
371 * Wrapper around modesetting bits.
372 */
373int radeon_clocks_init(struct radeon_device *rdev)
374{
375 int r;
376
377 radeon_get_clock_info(rdev->ddev);
378 r = radeon_static_clocks_init(rdev->ddev);
379 if (r) {
380 return r;
381 }
382 DRM_INFO("Clocks initialized !\n");
383 return 0;
384}
385
386void radeon_clocks_fini(struct radeon_device *rdev)
387{
388}
389
390/* ATOM accessor methods */
391static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
392{
393 struct radeon_device *rdev = info->dev->dev_private;
394 uint32_t r;
395
396 r = rdev->pll_rreg(rdev, reg);
397 return r;
398}
399
400static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
401{
402 struct radeon_device *rdev = info->dev->dev_private;
403
404 rdev->pll_wreg(rdev, reg, val);
405}
406
407static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
408{
409 struct radeon_device *rdev = info->dev->dev_private;
410 uint32_t r;
411
412 r = rdev->mc_rreg(rdev, reg);
413 return r;
414}
415
416static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
417{
418 struct radeon_device *rdev = info->dev->dev_private;
419
420 rdev->mc_wreg(rdev, reg, val);
421}
422
423static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
424{
425 struct radeon_device *rdev = info->dev->dev_private;
426
427 WREG32(reg*4, val);
428}
429
430static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
431{
432 struct radeon_device *rdev = info->dev->dev_private;
433 uint32_t r;
434
435 r = RREG32(reg*4);
436 return r;
437}
438
439static struct card_info atom_card_info = {
440 .dev = NULL,
441 .reg_read = cail_reg_read,
442 .reg_write = cail_reg_write,
443 .mc_read = cail_mc_read,
444 .mc_write = cail_mc_write,
445 .pll_read = cail_pll_read,
446 .pll_write = cail_pll_write,
447};
448
449int radeon_atombios_init(struct radeon_device *rdev)
450{
451 atom_card_info.dev = rdev->ddev;
452 rdev->mode_info.atom_context = atom_parse(&atom_card_info, rdev->bios);
453 radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
454 return 0;
455}
456
457void radeon_atombios_fini(struct radeon_device *rdev)
458{
459 kfree(rdev->mode_info.atom_context);
460}
461
462int radeon_combios_init(struct radeon_device *rdev)
463{
464 radeon_combios_initialize_bios_scratch_regs(rdev->ddev);
465 return 0;
466}
467
468void radeon_combios_fini(struct radeon_device *rdev)
469{
470}
471
771fe6b9
JG		 472
473/*
474 * Radeon device.
475 */
476int radeon_device_init(struct radeon_device *rdev,
477 struct drm_device *ddev,
478 struct pci_dev *pdev,
479 uint32_t flags)
480{
6cf8a3f5 481 int r;
ad49f501 482 int dma_bits;
771fe6b9
JG		 483
484 DRM_INFO("radeon: Initializing kernel modesetting.\n");
485 rdev->shutdown = false;
486 rdev->ddev = ddev;
487 rdev->pdev = pdev;
488 rdev->flags = flags;
489 rdev->family = flags & RADEON_FAMILY_MASK;
490 rdev->is_atom_bios = false;
491 rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
492 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
493 rdev->gpu_lockup = false;
494 /* mutex initialization are all done here so we
495 * can recall function without having locking issues */
496 mutex_init(&rdev->cs_mutex);
497 mutex_init(&rdev->ib_pool.mutex);
498 mutex_init(&rdev->cp.mutex);
499 rwlock_init(&rdev->fence_drv.lock);
500
501 if (radeon_agpmode == -1) {
502 rdev->flags &= ~RADEON_IS_AGP;
c000273e 503 if (rdev->family >= CHIP_RV515 ||
771fe6b9
JG		 504 rdev->family == CHIP_RV380 ||
505 rdev->family == CHIP_RV410 ||
506 rdev->family == CHIP_R423) {
507 DRM_INFO("Forcing AGP to PCIE mode\n");
508 rdev->flags |= RADEON_IS_PCIE;
509 } else {
510 DRM_INFO("Forcing AGP to PCI mode\n");
511 rdev->flags |= RADEON_IS_PCI;
512 }
513 }
514
515 /* Set asic functions */
516 r = radeon_asic_init(rdev);
517 if (r) {
518 return r;
519 }
520
ad49f501
DA		 521 /* set DMA mask + need_dma32 flags.
522 * PCIE - can handle 40-bits.
523 * IGP - can handle 40-bits (in theory)
524 * AGP - generally dma32 is safest
525 * PCI - only dma32
526 */
527 rdev->need_dma32 = false;
528 if (rdev->flags & RADEON_IS_AGP)
529 rdev->need_dma32 = true;
530 if (rdev->flags & RADEON_IS_PCI)
531 rdev->need_dma32 = true;
532
533 dma_bits = rdev->need_dma32 ? 32 : 40;
534 r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
771fe6b9
JG		 535 if (r) {
536 printk(KERN_WARNING "radeon: No suitable DMA available.\n");
537 }
538
539 /* Registers mapping */
540 /* TODO: block userspace mapping of io register */
541 rdev->rmmio_base = drm_get_resource_start(rdev->ddev, 2);
542 rdev->rmmio_size = drm_get_resource_len(rdev->ddev, 2);
543 rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size);
544 if (rdev->rmmio == NULL) {
545 return -ENOMEM;
546 }
547 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
548 DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
549
3ce0a23d
JG		 550 rdev->new_init_path = false;
551 r = radeon_init(rdev);
552 if (r) {
553 return r;
554 }
555 if (!rdev->new_init_path) {
556 /* Setup errata flags */
557 radeon_errata(rdev);
558 /* Initialize scratch registers */
559 radeon_scratch_init(rdev);
560 /* Initialize surface registers */
561 radeon_surface_init(rdev);
562
563 /* TODO: disable VGA need to use VGA request */
564 /* BIOS*/
565 if (!radeon_get_bios(rdev)) {
566 if (ASIC_IS_AVIVO(rdev))
567 return -EINVAL;
568 }
569 if (rdev->is_atom_bios) {
570 r = radeon_atombios_init(rdev);
571 if (r) {
572 return r;
573 }
574 } else {
575 r = radeon_combios_init(rdev);
576 if (r) {
577 return r;
578 }
579 }
580 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
581 if (radeon_gpu_reset(rdev)) {
582 /* FIXME: what do we want to do here ? */
583 }
584 /* check if cards are posted or not */
585 if (!radeon_card_posted(rdev) && rdev->bios) {
586 DRM_INFO("GPU not posted. posting now...\n");
587 if (rdev->is_atom_bios) {
588 atom_asic_init(rdev->mode_info.atom_context);
589 } else {
590 radeon_combios_asic_init(rdev->ddev);
591 }
592 }
593 /* Initialize clocks */
594 r = radeon_clocks_init(rdev);
771fe6b9
JG		 595 if (r) {
596 return r;
597 }
3ce0a23d
JG		 598 /* Get vram informations */
599 radeon_vram_info(rdev);
600
601 /* Add an MTRR for the VRAM */
602 rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size,
603 MTRR_TYPE_WRCOMB, 1);
604 DRM_INFO("Detected VRAM RAM=%uM, BAR=%uM\n",
605 (unsigned)(rdev->mc.mc_vram_size >> 20),
606 (unsigned)(rdev->mc.aper_size >> 20));
607 DRM_INFO("RAM width %dbits %cDR\n",
608 rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
609 /* Initialize memory controller (also test AGP) */
610 r = radeon_mc_init(rdev);
771fe6b9
JG		 611 if (r) {
612 return r;
613 }
3ce0a23d
JG		 614 /* Fence driver */
615 r = radeon_fence_driver_init(rdev);
771fe6b9 616 if (r) {
771fe6b9
JG		 617 return r;
618 }
3ce0a23d 619 r = radeon_irq_kms_init(rdev);
771fe6b9 620 if (r) {
771fe6b9
JG		 621 return r;
622 }
3ce0a23d
JG		 623 /* Memory manager */
624 r = radeon_object_init(rdev);
771fe6b9 625 if (r) {
771fe6b9
JG		 626 return r;
627 }
3ce0a23d
JG		 628 /* Initialize GART (initialize after TTM so we can allocate
629 * memory through TTM but finalize after TTM) */
630 r = radeon_gart_enable(rdev);
631 if (!r) {
632 r = radeon_gem_init(rdev);
633 }
634
635 /* 1M ring buffer */
636 if (!r) {
637 r = radeon_cp_init(rdev, 1024 * 1024);
638 }
639 if (!r) {
640 r = radeon_wb_init(rdev);
641 if (r) {
642 DRM_ERROR("radeon: failled initializing WB (%d).\n", r);
643 return r;
644 }
645 }
646 if (!r) {
647 r = radeon_ib_pool_init(rdev);
648 if (r) {
649 DRM_ERROR("radeon: failled initializing IB pool (%d).\n", r);
650 return r;
651 }
652 }
653 if (!r) {
654 r = radeon_ib_test(rdev);
655 if (r) {
656 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
657 return r;
658 }
659 }
771fe6b9 660 }
6cf8a3f5 661 DRM_INFO("radeon: kernel modesetting successfully initialized.\n");
ecc0b326
MD		 662 if (radeon_testing) {
663 radeon_test_moves(rdev);
664 }
771fe6b9
JG		 665 if (radeon_benchmarking) {
666 radeon_benchmark(rdev);
667 }
6cf8a3f5 668 return 0;
771fe6b9
JG		 669}
670
671void radeon_device_fini(struct radeon_device *rdev)
672{
771fe6b9
JG		 673 DRM_INFO("radeon: finishing device.\n");
674 rdev->shutdown = true;
675 /* Order matter so becarefull if you rearrange anythings */
3ce0a23d
JG		 676 if (!rdev->new_init_path) {
677 radeon_ib_pool_fini(rdev);
678 radeon_cp_fini(rdev);
679 radeon_wb_fini(rdev);
680 radeon_gem_fini(rdev);
681 radeon_mc_fini(rdev);
771fe6b9 682#if __OS_HAS_AGP
3ce0a23d 683 radeon_agp_fini(rdev);
771fe6b9 684#endif
3ce0a23d
JG		 685 radeon_irq_kms_fini(rdev);
686 radeon_fence_driver_fini(rdev);
687 radeon_clocks_fini(rdev);
688 radeon_object_fini(rdev);
689 if (rdev->is_atom_bios) {
690 radeon_atombios_fini(rdev);
691 } else {
692 radeon_combios_fini(rdev);
693 }
694 kfree(rdev->bios);
695 rdev->bios = NULL;
771fe6b9 696 } else {
3ce0a23d 697 radeon_fini(rdev);
771fe6b9 698 }
771fe6b9
JG		 699 iounmap(rdev->rmmio);
700 rdev->rmmio = NULL;
701}
702
703
704/*
705 * Suspend & resume.
706 */
707int radeon_suspend_kms(struct drm_device *dev, pm_message_t state)
708{
709 struct radeon_device *rdev = dev->dev_private;
710 struct drm_crtc *crtc;
711
712 if (dev == NULL || rdev == NULL) {
713 return -ENODEV;
714 }
715 if (state.event == PM_EVENT_PRETHAW) {
716 return 0;
717 }
718 /* unpin the front buffers */
719 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
720 struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->fb);
721 struct radeon_object *robj;
722
723 if (rfb == NULL || rfb->obj == NULL) {
724 continue;
725 }
726 robj = rfb->obj->driver_private;
727 if (robj != rdev->fbdev_robj) {
728 radeon_object_unpin(robj);
729 }
730 }
731 /* evict vram memory */
732 radeon_object_evict_vram(rdev);
733 /* wait for gpu to finish processing current batch */
734 radeon_fence_wait_last(rdev);
735
3ce0a23d
JG		 736 if (!rdev->new_init_path) {
737 radeon_cp_disable(rdev);
738 radeon_gart_disable(rdev);
739 } else {
740 radeon_suspend(rdev);
741 }
771fe6b9
JG		 742 /* evict remaining vram memory */
743 radeon_object_evict_vram(rdev);
744
745 rdev->irq.sw_int = false;
746 radeon_irq_set(rdev);
747
748 pci_save_state(dev->pdev);
749 if (state.event == PM_EVENT_SUSPEND) {
750 /* Shut down the device */
751 pci_disable_device(dev->pdev);
752 pci_set_power_state(dev->pdev, PCI_D3hot);
753 }
754 acquire_console_sem();
755 fb_set_suspend(rdev->fbdev_info, 1);
756 release_console_sem();
757 return 0;
758}
759
760int radeon_resume_kms(struct drm_device *dev)
761{
762 struct radeon_device *rdev = dev->dev_private;
763 int r;
764
765 acquire_console_sem();
766 pci_set_power_state(dev->pdev, PCI_D0);
767 pci_restore_state(dev->pdev);
768 if (pci_enable_device(dev->pdev)) {
769 release_console_sem();
770 return -1;
771 }
772 pci_set_master(dev->pdev);
773 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
774 if (radeon_gpu_reset(rdev)) {
775 /* FIXME: what do we want to do here ? */
776 }
3ce0a23d
JG		 777 if (!rdev->new_init_path) {
778 /* post card */
779 if (rdev->is_atom_bios) {
780 atom_asic_init(rdev->mode_info.atom_context);
781 } else {
782 radeon_combios_asic_init(rdev->ddev);
783 }
784 /* Initialize clocks */
785 r = radeon_clocks_init(rdev);
786 if (r) {
787 release_console_sem();
788 return r;
789 }
790 /* Enable IRQ */
791 rdev->irq.sw_int = true;
792 radeon_irq_set(rdev);
793 /* Initialize GPU Memory Controller */
794 r = radeon_mc_init(rdev);
795 if (r) {
796 goto out;
797 }
798 r = radeon_gart_enable(rdev);
799 if (r) {
800 goto out;
801 }
802 r = radeon_cp_init(rdev, rdev->cp.ring_size);
803 if (r) {
804 goto out;
805 }
771fe6b9 806 } else {
3ce0a23d 807 radeon_resume(rdev);
771fe6b9
JG		 808 }
809out:
810 fb_set_suspend(rdev->fbdev_info, 0);
811 release_console_sem();
812
813 /* blat the mode back in */
814 drm_helper_resume_force_mode(dev);
815 return 0;
816}
817
818
819/*
820 * Debugfs
821 */
822struct radeon_debugfs {
823 struct drm_info_list *files;
824 unsigned num_files;
825};
826static struct radeon_debugfs _radeon_debugfs[RADEON_DEBUGFS_MAX_NUM_FILES];
827static unsigned _radeon_debugfs_count = 0;
828
829int radeon_debugfs_add_files(struct radeon_device *rdev,
830 struct drm_info_list *files,
831 unsigned nfiles)
832{
833 unsigned i;
834
835 for (i = 0; i < _radeon_debugfs_count; i++) {
836 if (_radeon_debugfs[i].files == files) {
837 /* Already registered */
838 return 0;
839 }
840 }
841 if ((_radeon_debugfs_count + nfiles) > RADEON_DEBUGFS_MAX_NUM_FILES) {
842 DRM_ERROR("Reached maximum number of debugfs files.\n");
843 DRM_ERROR("Report so we increase RADEON_DEBUGFS_MAX_NUM_FILES.\n");
844 return -EINVAL;
845 }
846 _radeon_debugfs[_radeon_debugfs_count].files = files;
847 _radeon_debugfs[_radeon_debugfs_count].num_files = nfiles;
848 _radeon_debugfs_count++;
849#if defined(CONFIG_DEBUG_FS)
850 drm_debugfs_create_files(files, nfiles,
851 rdev->ddev->control->debugfs_root,
852 rdev->ddev->control);
853 drm_debugfs_create_files(files, nfiles,
854 rdev->ddev->primary->debugfs_root,
855 rdev->ddev->primary);
856#endif
857 return 0;
858}
859
860#if defined(CONFIG_DEBUG_FS)
861int radeon_debugfs_init(struct drm_minor *minor)
862{
863 return 0;
864}
865
866void radeon_debugfs_cleanup(struct drm_minor *minor)
867{
868 unsigned i;
869
870 for (i = 0; i < _radeon_debugfs_count; i++) {
871 drm_debugfs_remove_files(_radeon_debugfs[i].files,
872 _radeon_debugfs[i].num_files, minor);
873 }
874}
875#endif
Clone of davem's net-next-2.6 tree