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drm/radeon/kms: remove unused r600_gart_clear_page
[net-next-2.6.git] / drivers / gpu / drm / radeon / radeon_device.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include <linux/console.h>
29#include <drm/drmP.h>
30#include <drm/drm_crtc_helper.h>
31#include <drm/radeon_drm.h>
28d52043 32#include <linux/vgaarb.h>
771fe6b9
JG		 33#include "radeon_reg.h"
34#include "radeon.h"
35#include "radeon_asic.h"
36#include "atom.h"
37
b1e3a6d1
MD		 38/*
39 * Clear GPU surface registers.
40 */
3ce0a23d 41void radeon_surface_init(struct radeon_device *rdev)
b1e3a6d1
MD		 42{
43 /* FIXME: check this out */
44 if (rdev->family < CHIP_R600) {
45 int i;
46
550e2d92
DA		 47 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
48 if (rdev->surface_regs[i].bo)
49 radeon_bo_get_surface_reg(rdev->surface_regs[i].bo);
50 else
51 radeon_clear_surface_reg(rdev, i);
b1e3a6d1 52 }
e024e110
DA		 53 /* enable surfaces */
54 WREG32(RADEON_SURFACE_CNTL, 0);
b1e3a6d1
MD		 55 }
56}
57
771fe6b9
JG		 58/*
59 * GPU scratch registers helpers function.
60 */
3ce0a23d 61void radeon_scratch_init(struct radeon_device *rdev)
771fe6b9
JG		 62{
63 int i;
64
65 /* FIXME: check this out */
66 if (rdev->family < CHIP_R300) {
67 rdev->scratch.num_reg = 5;
68 } else {
69 rdev->scratch.num_reg = 7;
70 }
71 for (i = 0; i < rdev->scratch.num_reg; i++) {
72 rdev->scratch.free[i] = true;
73 rdev->scratch.reg[i] = RADEON_SCRATCH_REG0 + (i * 4);
74 }
75}
76
77int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg)
78{
79 int i;
80
81 for (i = 0; i < rdev->scratch.num_reg; i++) {
82 if (rdev->scratch.free[i]) {
83 rdev->scratch.free[i] = false;
84 *reg = rdev->scratch.reg[i];
85 return 0;
86 }
87 }
88 return -EINVAL;
89}
90
91void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
92{
93 int i;
94
95 for (i = 0; i < rdev->scratch.num_reg; i++) {
96 if (rdev->scratch.reg[i] == reg) {
97 rdev->scratch.free[i] = true;
98 return;
99 }
100 }
101}
102
103/*
104 * MC common functions
105 */
106int radeon_mc_setup(struct radeon_device *rdev)
107{
108 uint32_t tmp;
109
110 /* Some chips have an "issue" with the memory controller, the
111 * location must be aligned to the size. We just align it down,
112 * too bad if we walk over the top of system memory, we don't
113 * use DMA without a remapped anyway.
114 * Affected chips are rv280, all r3xx, and all r4xx, but not IGP
115 */
116 /* FGLRX seems to setup like this, VRAM a 0, then GART.
117 */
118 /*
119 * Note: from R6xx the address space is 40bits but here we only
120 * use 32bits (still have to see a card which would exhaust 4G
121 * address space).
122 */
123 if (rdev->mc.vram_location != 0xFFFFFFFFUL) {
124 /* vram location was already setup try to put gtt after
125 * if it fits */
7a50f01a 126 tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size;
771fe6b9
JG		 127 tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1);
128 if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) {
129 rdev->mc.gtt_location = tmp;
130 } else {
131 if (rdev->mc.gtt_size >= rdev->mc.vram_location) {
132 printk(KERN_ERR "[drm] GTT too big to fit "
133 "before or after vram location.\n");
134 return -EINVAL;
135 }
136 rdev->mc.gtt_location = 0;
137 }
138 } else if (rdev->mc.gtt_location != 0xFFFFFFFFUL) {
139 /* gtt location was already setup try to put vram before
140 * if it fits */
7a50f01a 141 if (rdev->mc.mc_vram_size < rdev->mc.gtt_location) {
771fe6b9
JG		 142 rdev->mc.vram_location = 0;
143 } else {
144 tmp = rdev->mc.gtt_location + rdev->mc.gtt_size;
7a50f01a
DA		 145 tmp += (rdev->mc.mc_vram_size - 1);
146 tmp &= ~(rdev->mc.mc_vram_size - 1);
147 if ((0xFFFFFFFFUL - tmp) >= rdev->mc.mc_vram_size) {
771fe6b9
JG		 148 rdev->mc.vram_location = tmp;
149 } else {
150 printk(KERN_ERR "[drm] vram too big to fit "
151 "before or after GTT location.\n");
152 return -EINVAL;
153 }
154 }
155 } else {
156 rdev->mc.vram_location = 0;
17332925
DA		 157 tmp = rdev->mc.mc_vram_size;
158 tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1);
159 rdev->mc.gtt_location = tmp;
771fe6b9 160 }
9f022ddf
JG		 161 rdev->mc.vram_start = rdev->mc.vram_location;
162 rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
163 rdev->mc.gtt_start = rdev->mc.gtt_location;
164 rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
3ce0a23d 165 DRM_INFO("radeon: VRAM %uM\n", (unsigned)(rdev->mc.mc_vram_size >> 20));
771fe6b9 166 DRM_INFO("radeon: VRAM from 0x%08X to 0x%08X\n",
3ce0a23d
JG		 167 (unsigned)rdev->mc.vram_location,
168 (unsigned)(rdev->mc.vram_location + rdev->mc.mc_vram_size - 1));
169 DRM_INFO("radeon: GTT %uM\n", (unsigned)(rdev->mc.gtt_size >> 20));
771fe6b9 170 DRM_INFO("radeon: GTT from 0x%08X to 0x%08X\n",
3ce0a23d
JG		 171 (unsigned)rdev->mc.gtt_location,
172 (unsigned)(rdev->mc.gtt_location + rdev->mc.gtt_size - 1));
771fe6b9
JG		 173 return 0;
174}
175
176
177/*
178 * GPU helpers function.
179 */
9f022ddf 180bool radeon_card_posted(struct radeon_device *rdev)
771fe6b9
JG		 181{
182 uint32_t reg;
183
184 /* first check CRTCs */
bcc1c2a1
AD		 185 if (ASIC_IS_DCE4(rdev)) {
186 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
187 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) |
188 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
189 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) |
190 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
191 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
192 if (reg & EVERGREEN_CRTC_MASTER_EN)
193 return true;
194 } else if (ASIC_IS_AVIVO(rdev)) {
771fe6b9
JG		 195 reg = RREG32(AVIVO_D1CRTC_CONTROL) |
196 RREG32(AVIVO_D2CRTC_CONTROL);
197 if (reg & AVIVO_CRTC_EN) {
198 return true;
199 }
200 } else {
201 reg = RREG32(RADEON_CRTC_GEN_CNTL) |
202 RREG32(RADEON_CRTC2_GEN_CNTL);
203 if (reg & RADEON_CRTC_EN) {
204 return true;
205 }
206 }
207
208 /* then check MEM_SIZE, in case the crtcs are off */
209 if (rdev->family >= CHIP_R600)
210 reg = RREG32(R600_CONFIG_MEMSIZE);
211 else
212 reg = RREG32(RADEON_CONFIG_MEMSIZE);
213
214 if (reg)
215 return true;
216
217 return false;
218
219}
220
72542d77
DA		 221bool radeon_boot_test_post_card(struct radeon_device *rdev)
222{
223 if (radeon_card_posted(rdev))
224 return true;
225
226 if (rdev->bios) {
227 DRM_INFO("GPU not posted. posting now...\n");
228 if (rdev->is_atom_bios)
229 atom_asic_init(rdev->mode_info.atom_context);
230 else
231 radeon_combios_asic_init(rdev->ddev);
232 return true;
233 } else {
234 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
235 return false;
236 }
237}
238
3ce0a23d
JG		 239int radeon_dummy_page_init(struct radeon_device *rdev)
240{
82568565
DA		 241 if (rdev->dummy_page.page)
242 return 0;
3ce0a23d
JG		 243 rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
244 if (rdev->dummy_page.page == NULL)
245 return -ENOMEM;
246 rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page,
247 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
248 if (!rdev->dummy_page.addr) {
249 __free_page(rdev->dummy_page.page);
250 rdev->dummy_page.page = NULL;
251 return -ENOMEM;
252 }
253 return 0;
254}
255
256void radeon_dummy_page_fini(struct radeon_device *rdev)
257{
258 if (rdev->dummy_page.page == NULL)
259 return;
260 pci_unmap_page(rdev->pdev, rdev->dummy_page.addr,
261 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
262 __free_page(rdev->dummy_page.page);
263 rdev->dummy_page.page = NULL;
264}
265
771fe6b9
JG		 266
267/*
268 * Registers accessors functions.
269 */
270uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
271{
272 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
273 BUG_ON(1);
274 return 0;
275}
276
277void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
278{
279 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
280 reg, v);
281 BUG_ON(1);
282}
283
284void radeon_register_accessor_init(struct radeon_device *rdev)
285{
771fe6b9
JG		 286 rdev->mc_rreg = &radeon_invalid_rreg;
287 rdev->mc_wreg = &radeon_invalid_wreg;
288 rdev->pll_rreg = &radeon_invalid_rreg;
289 rdev->pll_wreg = &radeon_invalid_wreg;
771fe6b9
JG		 290 rdev->pciep_rreg = &radeon_invalid_rreg;
291 rdev->pciep_wreg = &radeon_invalid_wreg;
292
293 /* Don't change order as we are overridding accessor. */
294 if (rdev->family < CHIP_RV515) {
de1b2898
DA		 295 rdev->pcie_reg_mask = 0xff;
296 } else {
297 rdev->pcie_reg_mask = 0x7ff;
771fe6b9
JG		 298 }
299 /* FIXME: not sure here */
300 if (rdev->family <= CHIP_R580) {
301 rdev->pll_rreg = &r100_pll_rreg;
302 rdev->pll_wreg = &r100_pll_wreg;
303 }
905b6822
JG		 304 if (rdev->family >= CHIP_R420) {
305 rdev->mc_rreg = &r420_mc_rreg;
306 rdev->mc_wreg = &r420_mc_wreg;
307 }
771fe6b9
JG		 308 if (rdev->family >= CHIP_RV515) {
309 rdev->mc_rreg = &rv515_mc_rreg;
310 rdev->mc_wreg = &rv515_mc_wreg;
311 }
312 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
313 rdev->mc_rreg = &rs400_mc_rreg;
314 rdev->mc_wreg = &rs400_mc_wreg;
315 }
316 if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
317 rdev->mc_rreg = &rs690_mc_rreg;
318 rdev->mc_wreg = &rs690_mc_wreg;
319 }
320 if (rdev->family == CHIP_RS600) {
321 rdev->mc_rreg = &rs600_mc_rreg;
322 rdev->mc_wreg = &rs600_mc_wreg;
323 }
bcc1c2a1 324 if ((rdev->family >= CHIP_R600) && (rdev->family <= CHIP_RV740)) {
771fe6b9
JG		 325 rdev->pciep_rreg = &r600_pciep_rreg;
326 rdev->pciep_wreg = &r600_pciep_wreg;
327 }
328}
329
330
331/*
332 * ASIC
333 */
334int radeon_asic_init(struct radeon_device *rdev)
335{
336 radeon_register_accessor_init(rdev);
337 switch (rdev->family) {
338 case CHIP_R100:
339 case CHIP_RV100:
340 case CHIP_RS100:
341 case CHIP_RV200:
342 case CHIP_RS200:
343 case CHIP_R200:
344 case CHIP_RV250:
345 case CHIP_RS300:
346 case CHIP_RV280:
347 rdev->asic = &r100_asic;
348 break;
349 case CHIP_R300:
350 case CHIP_R350:
351 case CHIP_RV350:
352 case CHIP_RV380:
353 rdev->asic = &r300_asic;
4aac0473 354 if (rdev->flags & RADEON_IS_PCIE) {
4aac0473
JG		 355 rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
356 rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
357 }
771fe6b9
JG		 358 break;
359 case CHIP_R420:
360 case CHIP_R423:
361 case CHIP_RV410:
362 rdev->asic = &r420_asic;
363 break;
364 case CHIP_RS400:
365 case CHIP_RS480:
366 rdev->asic = &rs400_asic;
367 break;
368 case CHIP_RS600:
369 rdev->asic = &rs600_asic;
370 break;
371 case CHIP_RS690:
372 case CHIP_RS740:
373 rdev->asic = &rs690_asic;
374 break;
375 case CHIP_RV515:
376 rdev->asic = &rv515_asic;
377 break;
378 case CHIP_R520:
379 case CHIP_RV530:
380 case CHIP_RV560:
381 case CHIP_RV570:
382 case CHIP_R580:
383 rdev->asic = &r520_asic;
384 break;
385 case CHIP_R600:
386 case CHIP_RV610:
387 case CHIP_RV630:
388 case CHIP_RV620:
389 case CHIP_RV635:
390 case CHIP_RV670:
391 case CHIP_RS780:
3ce0a23d
JG		 392 case CHIP_RS880:
393 rdev->asic = &r600_asic;
394 break;
771fe6b9
JG		 395 case CHIP_RV770:
396 case CHIP_RV730:
397 case CHIP_RV710:
3ce0a23d
JG		 398 case CHIP_RV740:
399 rdev->asic = &rv770_asic;
400 break;
bcc1c2a1
AD		 401 case CHIP_CEDAR:
402 case CHIP_REDWOOD:
403 case CHIP_JUNIPER:
404 case CHIP_CYPRESS:
405 case CHIP_HEMLOCK:
406 rdev->asic = &evergreen_asic;
407 break;
771fe6b9
JG		 408 default:
409 /* FIXME: not supported yet */
410 return -EINVAL;
411 }
5ea597f3
RM		 412
413 if (rdev->flags & RADEON_IS_IGP) {
414 rdev->asic->get_memory_clock = NULL;
415 rdev->asic->set_memory_clock = NULL;
416 }
417
771fe6b9
JG		 418 return 0;
419}
420
421
422/*
423 * Wrapper around modesetting bits.
424 */
425int radeon_clocks_init(struct radeon_device *rdev)
426{
427 int r;
428
771fe6b9
JG		 429 r = radeon_static_clocks_init(rdev->ddev);
430 if (r) {
431 return r;
432 }
433 DRM_INFO("Clocks initialized !\n");
434 return 0;
435}
436
437void radeon_clocks_fini(struct radeon_device *rdev)
438{
439}
440
441/* ATOM accessor methods */
442static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
443{
444 struct radeon_device *rdev = info->dev->dev_private;
445 uint32_t r;
446
447 r = rdev->pll_rreg(rdev, reg);
448 return r;
449}
450
451static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
452{
453 struct radeon_device *rdev = info->dev->dev_private;
454
455 rdev->pll_wreg(rdev, reg, val);
456}
457
458static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
459{
460 struct radeon_device *rdev = info->dev->dev_private;
461 uint32_t r;
462
463 r = rdev->mc_rreg(rdev, reg);
464 return r;
465}
466
467static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
468{
469 struct radeon_device *rdev = info->dev->dev_private;
470
471 rdev->mc_wreg(rdev, reg, val);
472}
473
474static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
475{
476 struct radeon_device *rdev = info->dev->dev_private;
477
478 WREG32(reg*4, val);
479}
480
481static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
482{
483 struct radeon_device *rdev = info->dev->dev_private;
484 uint32_t r;
485
486 r = RREG32(reg*4);
487 return r;
488}
489
771fe6b9
JG		 490int radeon_atombios_init(struct radeon_device *rdev)
491{
61c4b24b
MF		 492 struct card_info *atom_card_info =
493 kzalloc(sizeof(struct card_info), GFP_KERNEL);
494
495 if (!atom_card_info)
496 return -ENOMEM;
497
498 rdev->mode_info.atom_card_info = atom_card_info;
499 atom_card_info->dev = rdev->ddev;
500 atom_card_info->reg_read = cail_reg_read;
501 atom_card_info->reg_write = cail_reg_write;
502 atom_card_info->mc_read = cail_mc_read;
503 atom_card_info->mc_write = cail_mc_write;
504 atom_card_info->pll_read = cail_pll_read;
505 atom_card_info->pll_write = cail_pll_write;
506
507 rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios);
c31ad97f 508 mutex_init(&rdev->mode_info.atom_context->mutex);
771fe6b9 509 radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
d904ef9b 510 atom_allocate_fb_scratch(rdev->mode_info.atom_context);
771fe6b9
JG		 511 return 0;
512}
513
514void radeon_atombios_fini(struct radeon_device *rdev)
515{
4a04a844
JG		 516 if (rdev->mode_info.atom_context) {
517 kfree(rdev->mode_info.atom_context->scratch);
518 kfree(rdev->mode_info.atom_context);
519 }
61c4b24b 520 kfree(rdev->mode_info.atom_card_info);
771fe6b9
JG		 521}
522
523int radeon_combios_init(struct radeon_device *rdev)
524{
525 radeon_combios_initialize_bios_scratch_regs(rdev->ddev);
526 return 0;
527}
528
529void radeon_combios_fini(struct radeon_device *rdev)
530{
531}
532
28d52043
DA		 533/* if we get transitioned to only one device, tak VGA back */
534static unsigned int radeon_vga_set_decode(void *cookie, bool state)
535{
536 struct radeon_device *rdev = cookie;
28d52043
DA		 537 radeon_vga_set_state(rdev, state);
538 if (state)
539 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
540 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
541 else
542 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
543}
c1176d6f 544
b574f251
JG		 545void radeon_agp_disable(struct radeon_device *rdev)
546{
547 rdev->flags &= ~RADEON_IS_AGP;
548 if (rdev->family >= CHIP_R600) {
549 DRM_INFO("Forcing AGP to PCIE mode\n");
550 rdev->flags |= RADEON_IS_PCIE;
551 } else if (rdev->family >= CHIP_RV515 ||
552 rdev->family == CHIP_RV380 ||
553 rdev->family == CHIP_RV410 ||
554 rdev->family == CHIP_R423) {
555 DRM_INFO("Forcing AGP to PCIE mode\n");
556 rdev->flags |= RADEON_IS_PCIE;
557 rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
558 rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
559 } else {
560 DRM_INFO("Forcing AGP to PCI mode\n");
561 rdev->flags |= RADEON_IS_PCI;
562 rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
563 rdev->asic->gart_set_page = &r100_pci_gart_set_page;
564 }
700a0cc0 565 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
b574f251 566}
771fe6b9 567
36421338
JG		 568void radeon_check_arguments(struct radeon_device *rdev)
569{
570 /* vramlimit must be a power of two */
571 switch (radeon_vram_limit) {
572 case 0:
573 case 4:
574 case 8:
575 case 16:
576 case 32:
577 case 64:
578 case 128:
579 case 256:
580 case 512:
581 case 1024:
582 case 2048:
583 case 4096:
584 break;
585 default:
586 dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n",
587 radeon_vram_limit);
588 radeon_vram_limit = 0;
589 break;
590 }
591 radeon_vram_limit = radeon_vram_limit << 20;
592 /* gtt size must be power of two and greater or equal to 32M */
593 switch (radeon_gart_size) {
594 case 4:
595 case 8:
596 case 16:
597 dev_warn(rdev->dev, "gart size (%d) too small forcing to 512M\n",
598 radeon_gart_size);
599 radeon_gart_size = 512;
600 break;
601 case 32:
602 case 64:
603 case 128:
604 case 256:
605 case 512:
606 case 1024:
607 case 2048:
608 case 4096:
609 break;
610 default:
611 dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n",
612 radeon_gart_size);
613 radeon_gart_size = 512;
614 break;
615 }
616 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
617 /* AGP mode can only be -1, 1, 2, 4, 8 */
618 switch (radeon_agpmode) {
619 case -1:
620 case 0:
621 case 1:
622 case 2:
623 case 4:
624 case 8:
625 break;
626 default:
627 dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: "
628 "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode);
629 radeon_agpmode = 0;
630 break;
631 }
632}
633
771fe6b9
JG		 634int radeon_device_init(struct radeon_device *rdev,
635 struct drm_device *ddev,
636 struct pci_dev *pdev,
637 uint32_t flags)
638{
6cf8a3f5 639 int r;
ad49f501 640 int dma_bits;
771fe6b9
JG		 641
642 DRM_INFO("radeon: Initializing kernel modesetting.\n");
643 rdev->shutdown = false;
9f022ddf 644 rdev->dev = &pdev->dev;
771fe6b9
JG		 645 rdev->ddev = ddev;
646 rdev->pdev = pdev;
647 rdev->flags = flags;
648 rdev->family = flags & RADEON_FAMILY_MASK;
649 rdev->is_atom_bios = false;
650 rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
651 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
652 rdev->gpu_lockup = false;
733289c2 653 rdev->accel_working = false;
771fe6b9
JG		 654 /* mutex initialization are all done here so we
655 * can recall function without having locking issues */
656 mutex_init(&rdev->cs_mutex);
657 mutex_init(&rdev->ib_pool.mutex);
658 mutex_init(&rdev->cp.mutex);
40bacf16 659 mutex_init(&rdev->dc_hw_i2c_mutex);
d8f60cfc
AD		 660 if (rdev->family >= CHIP_R600)
661 spin_lock_init(&rdev->ih.lock);
4c788679 662 mutex_init(&rdev->gem.mutex);
c913e23a 663 mutex_init(&rdev->pm.mutex);
771fe6b9 664 rwlock_init(&rdev->fence_drv.lock);
9f022ddf 665 INIT_LIST_HEAD(&rdev->gem.objects);
73a6d3fc 666 init_waitqueue_head(&rdev->irq.vblank_queue);
771fe6b9 667
d4877cf2
AD		 668 /* setup workqueue */
669 rdev->wq = create_workqueue("radeon");
670 if (rdev->wq == NULL)
671 return -ENOMEM;
672
4aac0473
JG		 673 /* Set asic functions */
674 r = radeon_asic_init(rdev);
36421338 675 if (r)
4aac0473 676 return r;
36421338 677 radeon_check_arguments(rdev);
4aac0473 678
30256a3f 679 if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) {
b574f251 680 radeon_agp_disable(rdev);
771fe6b9
JG		 681 }
682
ad49f501
DA		 683 /* set DMA mask + need_dma32 flags.
684 * PCIE - can handle 40-bits.
685 * IGP - can handle 40-bits (in theory)
686 * AGP - generally dma32 is safest
687 * PCI - only dma32
688 */
689 rdev->need_dma32 = false;
690 if (rdev->flags & RADEON_IS_AGP)
691 rdev->need_dma32 = true;
692 if (rdev->flags & RADEON_IS_PCI)
693 rdev->need_dma32 = true;
694
695 dma_bits = rdev->need_dma32 ? 32 : 40;
696 r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
771fe6b9
JG		 697 if (r) {
698 printk(KERN_WARNING "radeon: No suitable DMA available.\n");
699 }
700
701 /* Registers mapping */
702 /* TODO: block userspace mapping of io register */
703 rdev->rmmio_base = drm_get_resource_start(rdev->ddev, 2);
704 rdev->rmmio_size = drm_get_resource_len(rdev->ddev, 2);
705 rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size);
706 if (rdev->rmmio == NULL) {
707 return -ENOMEM;
708 }
709 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
710 DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
711
28d52043 712 /* if we have > 1 VGA cards, then disable the radeon VGA resources */
93239ea1
DA		 713 /* this will fail for cards that aren't VGA class devices, just
714 * ignore it */
715 vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode);
28d52043 716
3ce0a23d 717 r = radeon_init(rdev);
b574f251 718 if (r)
3ce0a23d 719 return r;
3ce0a23d 720
b574f251
JG		 721 if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) {
722 /* Acceleration not working on AGP card try again
723 * with fallback to PCI or PCIE GART
724 */
1a029b76 725 radeon_gpu_reset(rdev);
b574f251
JG		 726 radeon_fini(rdev);
727 radeon_agp_disable(rdev);
728 r = radeon_init(rdev);
4aac0473
JG		 729 if (r)
730 return r;
771fe6b9 731 }
ecc0b326
MD		 732 if (radeon_testing) {
733 radeon_test_moves(rdev);
734 }
771fe6b9
JG		 735 if (radeon_benchmarking) {
736 radeon_benchmark(rdev);
737 }
6cf8a3f5 738 return 0;
771fe6b9
JG		 739}
740
741void radeon_device_fini(struct radeon_device *rdev)
742{
771fe6b9
JG		 743 DRM_INFO("radeon: finishing device.\n");
744 rdev->shutdown = true;
62a8ea3f 745 radeon_fini(rdev);
d4877cf2 746 destroy_workqueue(rdev->wq);
c1176d6f 747 vga_client_register(rdev->pdev, NULL, NULL, NULL);
771fe6b9
JG		 748 iounmap(rdev->rmmio);
749 rdev->rmmio = NULL;
750}
751
752
753/*
754 * Suspend & resume.
755 */
756int radeon_suspend_kms(struct drm_device *dev, pm_message_t state)
757{
875c1866 758 struct radeon_device *rdev;
771fe6b9 759 struct drm_crtc *crtc;
4c788679 760 int r;
771fe6b9 761
875c1866 762 if (dev == NULL || dev->dev_private == NULL) {
771fe6b9
JG		 763 return -ENODEV;
764 }
765 if (state.event == PM_EVENT_PRETHAW) {
766 return 0;
767 }
875c1866
DJ		 768 rdev = dev->dev_private;
769
771fe6b9
JG		 770 /* unpin the front buffers */
771 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
772 struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->fb);
4c788679 773 struct radeon_bo *robj;
771fe6b9
JG		 774
775 if (rfb == NULL || rfb->obj == NULL) {
776 continue;
777 }
778 robj = rfb->obj->driver_private;
4c788679
JG		 779 if (robj != rdev->fbdev_rbo) {
780 r = radeon_bo_reserve(robj, false);
781 if (unlikely(r == 0)) {
782 radeon_bo_unpin(robj);
783 radeon_bo_unreserve(robj);
784 }
771fe6b9
JG		 785 }
786 }
787 /* evict vram memory */
4c788679 788 radeon_bo_evict_vram(rdev);
771fe6b9
JG		 789 /* wait for gpu to finish processing current batch */
790 radeon_fence_wait_last(rdev);
791
f657c2a7
YZ		 792 radeon_save_bios_scratch_regs(rdev);
793
62a8ea3f 794 radeon_suspend(rdev);
d4877cf2 795 radeon_hpd_fini(rdev);
771fe6b9 796 /* evict remaining vram memory */
4c788679 797 radeon_bo_evict_vram(rdev);
771fe6b9 798
771fe6b9
JG		 799 pci_save_state(dev->pdev);
800 if (state.event == PM_EVENT_SUSPEND) {
801 /* Shut down the device */
802 pci_disable_device(dev->pdev);
803 pci_set_power_state(dev->pdev, PCI_D3hot);
804 }
805 acquire_console_sem();
806 fb_set_suspend(rdev->fbdev_info, 1);
807 release_console_sem();
808 return 0;
809}
810
811int radeon_resume_kms(struct drm_device *dev)
812{
813 struct radeon_device *rdev = dev->dev_private;
771fe6b9
JG		 814
815 acquire_console_sem();
816 pci_set_power_state(dev->pdev, PCI_D0);
817 pci_restore_state(dev->pdev);
818 if (pci_enable_device(dev->pdev)) {
819 release_console_sem();
820 return -1;
821 }
822 pci_set_master(dev->pdev);
0ebf1717
DA		 823 /* resume AGP if in use */
824 radeon_agp_resume(rdev);
62a8ea3f 825 radeon_resume(rdev);
f657c2a7 826 radeon_restore_bios_scratch_regs(rdev);
771fe6b9
JG		 827 fb_set_suspend(rdev->fbdev_info, 0);
828 release_console_sem();
829
d4877cf2
AD		 830 /* reset hpd state */
831 radeon_hpd_init(rdev);
771fe6b9
JG		 832 /* blat the mode back in */
833 drm_helper_resume_force_mode(dev);
834 return 0;
835}
836
837
838/*
839 * Debugfs
840 */
841struct radeon_debugfs {
842 struct drm_info_list *files;
843 unsigned num_files;
844};
845static struct radeon_debugfs _radeon_debugfs[RADEON_DEBUGFS_MAX_NUM_FILES];
846static unsigned _radeon_debugfs_count = 0;
847
848int radeon_debugfs_add_files(struct radeon_device *rdev,
849 struct drm_info_list *files,
850 unsigned nfiles)
851{
852 unsigned i;
853
854 for (i = 0; i < _radeon_debugfs_count; i++) {
855 if (_radeon_debugfs[i].files == files) {
856 /* Already registered */
857 return 0;
858 }
859 }
860 if ((_radeon_debugfs_count + nfiles) > RADEON_DEBUGFS_MAX_NUM_FILES) {
861 DRM_ERROR("Reached maximum number of debugfs files.\n");
862 DRM_ERROR("Report so we increase RADEON_DEBUGFS_MAX_NUM_FILES.\n");
863 return -EINVAL;
864 }
865 _radeon_debugfs[_radeon_debugfs_count].files = files;
866 _radeon_debugfs[_radeon_debugfs_count].num_files = nfiles;
867 _radeon_debugfs_count++;
868#if defined(CONFIG_DEBUG_FS)
869 drm_debugfs_create_files(files, nfiles,
870 rdev->ddev->control->debugfs_root,
871 rdev->ddev->control);
872 drm_debugfs_create_files(files, nfiles,
873 rdev->ddev->primary->debugfs_root,
874 rdev->ddev->primary);
875#endif
876 return 0;
877}
878
879#if defined(CONFIG_DEBUG_FS)
880int radeon_debugfs_init(struct drm_minor *minor)
881{
882 return 0;
883}
884
885void radeon_debugfs_cleanup(struct drm_minor *minor)
886{
887 unsigned i;
888
889 for (i = 0; i < _radeon_debugfs_count; i++) {
890 drm_debugfs_remove_files(_radeon_debugfs[i].files,
891 _radeon_debugfs[i].num_files, minor);
892 }
893}
894#endif
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