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drm/radeon/kms: don't fail if we fail to init GPU acceleration
[net-next-2.6.git] / drivers / gpu / drm / radeon / radeon_device.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include <linux/console.h>
29#include <drm/drmP.h>
30#include <drm/drm_crtc_helper.h>
31#include <drm/radeon_drm.h>
32#include "radeon_reg.h"
33#include "radeon.h"
34#include "radeon_asic.h"
35#include "atom.h"
36
b1e3a6d1
MD		 37/*
38 * Clear GPU surface registers.
39 */
3ce0a23d 40void radeon_surface_init(struct radeon_device *rdev)
b1e3a6d1
MD		 41{
42 /* FIXME: check this out */
43 if (rdev->family < CHIP_R600) {
44 int i;
45
46 for (i = 0; i < 8; i++) {
47 WREG32(RADEON_SURFACE0_INFO +
48 i * (RADEON_SURFACE1_INFO - RADEON_SURFACE0_INFO),
49 0);
50 }
e024e110
DA		 51 /* enable surfaces */
52 WREG32(RADEON_SURFACE_CNTL, 0);
b1e3a6d1
MD		 53 }
54}
55
771fe6b9
JG		 56/*
57 * GPU scratch registers helpers function.
58 */
3ce0a23d 59void radeon_scratch_init(struct radeon_device *rdev)
771fe6b9
JG		 60{
61 int i;
62
63 /* FIXME: check this out */
64 if (rdev->family < CHIP_R300) {
65 rdev->scratch.num_reg = 5;
66 } else {
67 rdev->scratch.num_reg = 7;
68 }
69 for (i = 0; i < rdev->scratch.num_reg; i++) {
70 rdev->scratch.free[i] = true;
71 rdev->scratch.reg[i] = RADEON_SCRATCH_REG0 + (i * 4);
72 }
73}
74
75int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg)
76{
77 int i;
78
79 for (i = 0; i < rdev->scratch.num_reg; i++) {
80 if (rdev->scratch.free[i]) {
81 rdev->scratch.free[i] = false;
82 *reg = rdev->scratch.reg[i];
83 return 0;
84 }
85 }
86 return -EINVAL;
87}
88
89void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
90{
91 int i;
92
93 for (i = 0; i < rdev->scratch.num_reg; i++) {
94 if (rdev->scratch.reg[i] == reg) {
95 rdev->scratch.free[i] = true;
96 return;
97 }
98 }
99}
100
101/*
102 * MC common functions
103 */
104int radeon_mc_setup(struct radeon_device *rdev)
105{
106 uint32_t tmp;
107
108 /* Some chips have an "issue" with the memory controller, the
109 * location must be aligned to the size. We just align it down,
110 * too bad if we walk over the top of system memory, we don't
111 * use DMA without a remapped anyway.
112 * Affected chips are rv280, all r3xx, and all r4xx, but not IGP
113 */
114 /* FGLRX seems to setup like this, VRAM a 0, then GART.
115 */
116 /*
117 * Note: from R6xx the address space is 40bits but here we only
118 * use 32bits (still have to see a card which would exhaust 4G
119 * address space).
120 */
121 if (rdev->mc.vram_location != 0xFFFFFFFFUL) {
122 /* vram location was already setup try to put gtt after
123 * if it fits */
7a50f01a 124 tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size;
771fe6b9
JG		 125 tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1);
126 if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) {
127 rdev->mc.gtt_location = tmp;
128 } else {
129 if (rdev->mc.gtt_size >= rdev->mc.vram_location) {
130 printk(KERN_ERR "[drm] GTT too big to fit "
131 "before or after vram location.\n");
132 return -EINVAL;
133 }
134 rdev->mc.gtt_location = 0;
135 }
136 } else if (rdev->mc.gtt_location != 0xFFFFFFFFUL) {
137 /* gtt location was already setup try to put vram before
138 * if it fits */
7a50f01a 139 if (rdev->mc.mc_vram_size < rdev->mc.gtt_location) {
771fe6b9
JG		 140 rdev->mc.vram_location = 0;
141 } else {
142 tmp = rdev->mc.gtt_location + rdev->mc.gtt_size;
7a50f01a
DA		 143 tmp += (rdev->mc.mc_vram_size - 1);
144 tmp &= ~(rdev->mc.mc_vram_size - 1);
145 if ((0xFFFFFFFFUL - tmp) >= rdev->mc.mc_vram_size) {
771fe6b9
JG		 146 rdev->mc.vram_location = tmp;
147 } else {
148 printk(KERN_ERR "[drm] vram too big to fit "
149 "before or after GTT location.\n");
150 return -EINVAL;
151 }
152 }
153 } else {
154 rdev->mc.vram_location = 0;
17332925
DA		 155 tmp = rdev->mc.mc_vram_size;
156 tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1);
157 rdev->mc.gtt_location = tmp;
771fe6b9 158 }
9f022ddf
JG		 159 rdev->mc.vram_start = rdev->mc.vram_location;
160 rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
161 rdev->mc.gtt_start = rdev->mc.gtt_location;
162 rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
3ce0a23d 163 DRM_INFO("radeon: VRAM %uM\n", (unsigned)(rdev->mc.mc_vram_size >> 20));
771fe6b9 164 DRM_INFO("radeon: VRAM from 0x%08X to 0x%08X\n",
3ce0a23d
JG		 165 (unsigned)rdev->mc.vram_location,
166 (unsigned)(rdev->mc.vram_location + rdev->mc.mc_vram_size - 1));
167 DRM_INFO("radeon: GTT %uM\n", (unsigned)(rdev->mc.gtt_size >> 20));
771fe6b9 168 DRM_INFO("radeon: GTT from 0x%08X to 0x%08X\n",
3ce0a23d
JG		 169 (unsigned)rdev->mc.gtt_location,
170 (unsigned)(rdev->mc.gtt_location + rdev->mc.gtt_size - 1));
771fe6b9
JG		 171 return 0;
172}
173
174
175/*
176 * GPU helpers function.
177 */
9f022ddf 178bool radeon_card_posted(struct radeon_device *rdev)
771fe6b9
JG		 179{
180 uint32_t reg;
181
182 /* first check CRTCs */
183 if (ASIC_IS_AVIVO(rdev)) {
184 reg = RREG32(AVIVO_D1CRTC_CONTROL) |
185 RREG32(AVIVO_D2CRTC_CONTROL);
186 if (reg & AVIVO_CRTC_EN) {
187 return true;
188 }
189 } else {
190 reg = RREG32(RADEON_CRTC_GEN_CNTL) |
191 RREG32(RADEON_CRTC2_GEN_CNTL);
192 if (reg & RADEON_CRTC_EN) {
193 return true;
194 }
195 }
196
197 /* then check MEM_SIZE, in case the crtcs are off */
198 if (rdev->family >= CHIP_R600)
199 reg = RREG32(R600_CONFIG_MEMSIZE);
200 else
201 reg = RREG32(RADEON_CONFIG_MEMSIZE);
202
203 if (reg)
204 return true;
205
206 return false;
207
208}
209
3ce0a23d
JG		 210int radeon_dummy_page_init(struct radeon_device *rdev)
211{
212 rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
213 if (rdev->dummy_page.page == NULL)
214 return -ENOMEM;
215 rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page,
216 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
217 if (!rdev->dummy_page.addr) {
218 __free_page(rdev->dummy_page.page);
219 rdev->dummy_page.page = NULL;
220 return -ENOMEM;
221 }
222 return 0;
223}
224
225void radeon_dummy_page_fini(struct radeon_device *rdev)
226{
227 if (rdev->dummy_page.page == NULL)
228 return;
229 pci_unmap_page(rdev->pdev, rdev->dummy_page.addr,
230 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
231 __free_page(rdev->dummy_page.page);
232 rdev->dummy_page.page = NULL;
233}
234
771fe6b9
JG		 235
236/*
237 * Registers accessors functions.
238 */
239uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
240{
241 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
242 BUG_ON(1);
243 return 0;
244}
245
246void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
247{
248 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
249 reg, v);
250 BUG_ON(1);
251}
252
253void radeon_register_accessor_init(struct radeon_device *rdev)
254{
771fe6b9
JG		 255 rdev->mc_rreg = &radeon_invalid_rreg;
256 rdev->mc_wreg = &radeon_invalid_wreg;
257 rdev->pll_rreg = &radeon_invalid_rreg;
258 rdev->pll_wreg = &radeon_invalid_wreg;
771fe6b9
JG		 259 rdev->pciep_rreg = &radeon_invalid_rreg;
260 rdev->pciep_wreg = &radeon_invalid_wreg;
261
262 /* Don't change order as we are overridding accessor. */
263 if (rdev->family < CHIP_RV515) {
de1b2898
DA		 264 rdev->pcie_reg_mask = 0xff;
265 } else {
266 rdev->pcie_reg_mask = 0x7ff;
771fe6b9
JG		 267 }
268 /* FIXME: not sure here */
269 if (rdev->family <= CHIP_R580) {
270 rdev->pll_rreg = &r100_pll_rreg;
271 rdev->pll_wreg = &r100_pll_wreg;
272 }
905b6822
JG		 273 if (rdev->family >= CHIP_R420) {
274 rdev->mc_rreg = &r420_mc_rreg;
275 rdev->mc_wreg = &r420_mc_wreg;
276 }
771fe6b9
JG		 277 if (rdev->family >= CHIP_RV515) {
278 rdev->mc_rreg = &rv515_mc_rreg;
279 rdev->mc_wreg = &rv515_mc_wreg;
280 }
281 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
282 rdev->mc_rreg = &rs400_mc_rreg;
283 rdev->mc_wreg = &rs400_mc_wreg;
284 }
285 if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
286 rdev->mc_rreg = &rs690_mc_rreg;
287 rdev->mc_wreg = &rs690_mc_wreg;
288 }
289 if (rdev->family == CHIP_RS600) {
290 rdev->mc_rreg = &rs600_mc_rreg;
291 rdev->mc_wreg = &rs600_mc_wreg;
292 }
293 if (rdev->family >= CHIP_R600) {
294 rdev->pciep_rreg = &r600_pciep_rreg;
295 rdev->pciep_wreg = &r600_pciep_wreg;
296 }
297}
298
299
300/*
301 * ASIC
302 */
303int radeon_asic_init(struct radeon_device *rdev)
304{
305 radeon_register_accessor_init(rdev);
306 switch (rdev->family) {
307 case CHIP_R100:
308 case CHIP_RV100:
309 case CHIP_RS100:
310 case CHIP_RV200:
311 case CHIP_RS200:
312 case CHIP_R200:
313 case CHIP_RV250:
314 case CHIP_RS300:
315 case CHIP_RV280:
316 rdev->asic = &r100_asic;
317 break;
318 case CHIP_R300:
319 case CHIP_R350:
320 case CHIP_RV350:
321 case CHIP_RV380:
322 rdev->asic = &r300_asic;
4aac0473
JG		 323 if (rdev->flags & RADEON_IS_PCIE) {
324 rdev->asic->gart_init = &rv370_pcie_gart_init;
325 rdev->asic->gart_fini = &rv370_pcie_gart_fini;
326 rdev->asic->gart_enable = &rv370_pcie_gart_enable;
327 rdev->asic->gart_disable = &rv370_pcie_gart_disable;
328 rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
329 rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
330 }
771fe6b9
JG		 331 break;
332 case CHIP_R420:
333 case CHIP_R423:
334 case CHIP_RV410:
335 rdev->asic = &r420_asic;
336 break;
337 case CHIP_RS400:
338 case CHIP_RS480:
339 rdev->asic = &rs400_asic;
340 break;
341 case CHIP_RS600:
342 rdev->asic = &rs600_asic;
343 break;
344 case CHIP_RS690:
345 case CHIP_RS740:
346 rdev->asic = &rs690_asic;
347 break;
348 case CHIP_RV515:
349 rdev->asic = &rv515_asic;
350 break;
351 case CHIP_R520:
352 case CHIP_RV530:
353 case CHIP_RV560:
354 case CHIP_RV570:
355 case CHIP_R580:
356 rdev->asic = &r520_asic;
357 break;
358 case CHIP_R600:
359 case CHIP_RV610:
360 case CHIP_RV630:
361 case CHIP_RV620:
362 case CHIP_RV635:
363 case CHIP_RV670:
364 case CHIP_RS780:
3ce0a23d
JG		 365 case CHIP_RS880:
366 rdev->asic = &r600_asic;
367 break;
771fe6b9
JG		 368 case CHIP_RV770:
369 case CHIP_RV730:
370 case CHIP_RV710:
3ce0a23d
JG		 371 case CHIP_RV740:
372 rdev->asic = &rv770_asic;
373 break;
771fe6b9
JG		 374 default:
375 /* FIXME: not supported yet */
376 return -EINVAL;
377 }
378 return 0;
379}
380
381
382/*
383 * Wrapper around modesetting bits.
384 */
385int radeon_clocks_init(struct radeon_device *rdev)
386{
387 int r;
388
389 radeon_get_clock_info(rdev->ddev);
390 r = radeon_static_clocks_init(rdev->ddev);
391 if (r) {
392 return r;
393 }
394 DRM_INFO("Clocks initialized !\n");
395 return 0;
396}
397
398void radeon_clocks_fini(struct radeon_device *rdev)
399{
400}
401
402/* ATOM accessor methods */
403static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
404{
405 struct radeon_device *rdev = info->dev->dev_private;
406 uint32_t r;
407
408 r = rdev->pll_rreg(rdev, reg);
409 return r;
410}
411
412static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
413{
414 struct radeon_device *rdev = info->dev->dev_private;
415
416 rdev->pll_wreg(rdev, reg, val);
417}
418
419static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
420{
421 struct radeon_device *rdev = info->dev->dev_private;
422 uint32_t r;
423
424 r = rdev->mc_rreg(rdev, reg);
425 return r;
426}
427
428static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
429{
430 struct radeon_device *rdev = info->dev->dev_private;
431
432 rdev->mc_wreg(rdev, reg, val);
433}
434
435static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
436{
437 struct radeon_device *rdev = info->dev->dev_private;
438
439 WREG32(reg*4, val);
440}
441
442static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
443{
444 struct radeon_device *rdev = info->dev->dev_private;
445 uint32_t r;
446
447 r = RREG32(reg*4);
448 return r;
449}
450
451static struct card_info atom_card_info = {
452 .dev = NULL,
453 .reg_read = cail_reg_read,
454 .reg_write = cail_reg_write,
455 .mc_read = cail_mc_read,
456 .mc_write = cail_mc_write,
457 .pll_read = cail_pll_read,
458 .pll_write = cail_pll_write,
459};
460
461int radeon_atombios_init(struct radeon_device *rdev)
462{
463 atom_card_info.dev = rdev->ddev;
464 rdev->mode_info.atom_context = atom_parse(&atom_card_info, rdev->bios);
465 radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
466 return 0;
467}
468
469void radeon_atombios_fini(struct radeon_device *rdev)
470{
471 kfree(rdev->mode_info.atom_context);
472}
473
474int radeon_combios_init(struct radeon_device *rdev)
475{
476 radeon_combios_initialize_bios_scratch_regs(rdev->ddev);
477 return 0;
478}
479
480void radeon_combios_fini(struct radeon_device *rdev)
481{
482}
483
771fe6b9
JG		 484
485/*
486 * Radeon device.
487 */
488int radeon_device_init(struct radeon_device *rdev,
489 struct drm_device *ddev,
490 struct pci_dev *pdev,
491 uint32_t flags)
492{
6cf8a3f5 493 int r;
ad49f501 494 int dma_bits;
771fe6b9
JG		 495
496 DRM_INFO("radeon: Initializing kernel modesetting.\n");
497 rdev->shutdown = false;
9f022ddf 498 rdev->dev = &pdev->dev;
771fe6b9
JG		 499 rdev->ddev = ddev;
500 rdev->pdev = pdev;
501 rdev->flags = flags;
502 rdev->family = flags & RADEON_FAMILY_MASK;
503 rdev->is_atom_bios = false;
504 rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
505 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
506 rdev->gpu_lockup = false;
733289c2 507 rdev->accel_working = false;
771fe6b9
JG		 508 /* mutex initialization are all done here so we
509 * can recall function without having locking issues */
510 mutex_init(&rdev->cs_mutex);
511 mutex_init(&rdev->ib_pool.mutex);
512 mutex_init(&rdev->cp.mutex);
513 rwlock_init(&rdev->fence_drv.lock);
9f022ddf 514 INIT_LIST_HEAD(&rdev->gem.objects);
771fe6b9 515
4aac0473
JG		 516 /* Set asic functions */
517 r = radeon_asic_init(rdev);
518 if (r) {
519 return r;
520 }
521
771fe6b9
JG		 522 if (radeon_agpmode == -1) {
523 rdev->flags &= ~RADEON_IS_AGP;
c000273e 524 if (rdev->family >= CHIP_RV515 ||
771fe6b9
JG		 525 rdev->family == CHIP_RV380 ||
526 rdev->family == CHIP_RV410 ||
527 rdev->family == CHIP_R423) {
528 DRM_INFO("Forcing AGP to PCIE mode\n");
529 rdev->flags |= RADEON_IS_PCIE;
4aac0473
JG		 530 rdev->asic->gart_init = &rv370_pcie_gart_init;
531 rdev->asic->gart_fini = &rv370_pcie_gart_fini;
532 rdev->asic->gart_enable = &rv370_pcie_gart_enable;
533 rdev->asic->gart_disable = &rv370_pcie_gart_disable;
534 rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
535 rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
771fe6b9
JG		 536 } else {
537 DRM_INFO("Forcing AGP to PCI mode\n");
538 rdev->flags |= RADEON_IS_PCI;
4aac0473
JG		 539 rdev->asic->gart_init = &r100_pci_gart_init;
540 rdev->asic->gart_fini = &r100_pci_gart_fini;
541 rdev->asic->gart_enable = &r100_pci_gart_enable;
542 rdev->asic->gart_disable = &r100_pci_gart_disable;
543 rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
544 rdev->asic->gart_set_page = &r100_pci_gart_set_page;
771fe6b9
JG		 545 }
546 }
547
ad49f501
DA		 548 /* set DMA mask + need_dma32 flags.
549 * PCIE - can handle 40-bits.
550 * IGP - can handle 40-bits (in theory)
551 * AGP - generally dma32 is safest
552 * PCI - only dma32
553 */
554 rdev->need_dma32 = false;
555 if (rdev->flags & RADEON_IS_AGP)
556 rdev->need_dma32 = true;
557 if (rdev->flags & RADEON_IS_PCI)
558 rdev->need_dma32 = true;
559
560 dma_bits = rdev->need_dma32 ? 32 : 40;
561 r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
771fe6b9
JG		 562 if (r) {
563 printk(KERN_WARNING "radeon: No suitable DMA available.\n");
564 }
565
566 /* Registers mapping */
567 /* TODO: block userspace mapping of io register */
568 rdev->rmmio_base = drm_get_resource_start(rdev->ddev, 2);
569 rdev->rmmio_size = drm_get_resource_len(rdev->ddev, 2);
570 rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size);
571 if (rdev->rmmio == NULL) {
572 return -ENOMEM;
573 }
574 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
575 DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
576
3ce0a23d
JG		 577 rdev->new_init_path = false;
578 r = radeon_init(rdev);
579 if (r) {
580 return r;
581 }
582 if (!rdev->new_init_path) {
583 /* Setup errata flags */
584 radeon_errata(rdev);
585 /* Initialize scratch registers */
586 radeon_scratch_init(rdev);
587 /* Initialize surface registers */
588 radeon_surface_init(rdev);
589
590 /* TODO: disable VGA need to use VGA request */
591 /* BIOS*/
592 if (!radeon_get_bios(rdev)) {
593 if (ASIC_IS_AVIVO(rdev))
594 return -EINVAL;
595 }
596 if (rdev->is_atom_bios) {
597 r = radeon_atombios_init(rdev);
598 if (r) {
599 return r;
600 }
601 } else {
602 r = radeon_combios_init(rdev);
603 if (r) {
604 return r;
605 }
606 }
607 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
608 if (radeon_gpu_reset(rdev)) {
609 /* FIXME: what do we want to do here ? */
610 }
611 /* check if cards are posted or not */
612 if (!radeon_card_posted(rdev) && rdev->bios) {
613 DRM_INFO("GPU not posted. posting now...\n");
614 if (rdev->is_atom_bios) {
615 atom_asic_init(rdev->mode_info.atom_context);
616 } else {
617 radeon_combios_asic_init(rdev->ddev);
618 }
619 }
95a8f1bf
MD		 620 /* Get vram informations */
621 radeon_vram_info(rdev);
3ce0a23d
JG		 622 /* Initialize clocks */
623 r = radeon_clocks_init(rdev);
771fe6b9
JG		 624 if (r) {
625 return r;
626 }
3ce0a23d 627
3ce0a23d
JG		 628 /* Initialize memory controller (also test AGP) */
629 r = radeon_mc_init(rdev);
771fe6b9
JG		 630 if (r) {
631 return r;
632 }
3ce0a23d
JG		 633 /* Fence driver */
634 r = radeon_fence_driver_init(rdev);
771fe6b9 635 if (r) {
771fe6b9
JG		 636 return r;
637 }
3ce0a23d 638 r = radeon_irq_kms_init(rdev);
771fe6b9 639 if (r) {
771fe6b9
JG		 640 return r;
641 }
3ce0a23d
JG		 642 /* Memory manager */
643 r = radeon_object_init(rdev);
771fe6b9 644 if (r) {
771fe6b9
JG		 645 return r;
646 }
4aac0473
JG		 647 r = radeon_gpu_gart_init(rdev);
648 if (r)
649 return r;
3ce0a23d
JG		 650 /* Initialize GART (initialize after TTM so we can allocate
651 * memory through TTM but finalize after TTM) */
652 r = radeon_gart_enable(rdev);
733289c2
JG		 653 if (r)
654 return 0;
3ce0a23d 655 r = radeon_gem_init(rdev);
733289c2
JG		 656 if (r)
657 return 0;
3ce0a23d
JG		 658
659 /* 1M ring buffer */
733289c2
JG		 660 r = radeon_cp_init(rdev, 1024 * 1024);
661 if (r)
662 return 0;
663 r = radeon_wb_init(rdev);
664 if (r)
665 DRM_ERROR("radeon: failled initializing WB (%d).\n", r);
666 r = radeon_ib_pool_init(rdev);
667 if (r)
668 return 0;
669 r = radeon_ib_test(rdev);
670 if (r)
671 return 0;
672 rdev->accel_working = true;
771fe6b9 673 }
6cf8a3f5 674 DRM_INFO("radeon: kernel modesetting successfully initialized.\n");
ecc0b326
MD		 675 if (radeon_testing) {
676 radeon_test_moves(rdev);
677 }
771fe6b9
JG		 678 if (radeon_benchmarking) {
679 radeon_benchmark(rdev);
680 }
6cf8a3f5 681 return 0;
771fe6b9
JG		 682}
683
684void radeon_device_fini(struct radeon_device *rdev)
685{
771fe6b9
JG		 686 DRM_INFO("radeon: finishing device.\n");
687 rdev->shutdown = true;
688 /* Order matter so becarefull if you rearrange anythings */
3ce0a23d
JG		 689 if (!rdev->new_init_path) {
690 radeon_ib_pool_fini(rdev);
691 radeon_cp_fini(rdev);
692 radeon_wb_fini(rdev);
4aac0473 693 radeon_gpu_gart_fini(rdev);
3ce0a23d
JG		 694 radeon_gem_fini(rdev);
695 radeon_mc_fini(rdev);
771fe6b9 696#if __OS_HAS_AGP
3ce0a23d 697 radeon_agp_fini(rdev);
771fe6b9 698#endif
3ce0a23d
JG		 699 radeon_irq_kms_fini(rdev);
700 radeon_fence_driver_fini(rdev);
701 radeon_clocks_fini(rdev);
702 radeon_object_fini(rdev);
703 if (rdev->is_atom_bios) {
704 radeon_atombios_fini(rdev);
705 } else {
706 radeon_combios_fini(rdev);
707 }
708 kfree(rdev->bios);
709 rdev->bios = NULL;
771fe6b9 710 } else {
3ce0a23d 711 radeon_fini(rdev);
771fe6b9 712 }
771fe6b9
JG		 713 iounmap(rdev->rmmio);
714 rdev->rmmio = NULL;
715}
716
717
718/*
719 * Suspend & resume.
720 */
721int radeon_suspend_kms(struct drm_device *dev, pm_message_t state)
722{
723 struct radeon_device *rdev = dev->dev_private;
724 struct drm_crtc *crtc;
725
726 if (dev == NULL || rdev == NULL) {
727 return -ENODEV;
728 }
729 if (state.event == PM_EVENT_PRETHAW) {
730 return 0;
731 }
732 /* unpin the front buffers */
733 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
734 struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->fb);
735 struct radeon_object *robj;
736
737 if (rfb == NULL || rfb->obj == NULL) {
738 continue;
739 }
740 robj = rfb->obj->driver_private;
741 if (robj != rdev->fbdev_robj) {
742 radeon_object_unpin(robj);
743 }
744 }
745 /* evict vram memory */
746 radeon_object_evict_vram(rdev);
747 /* wait for gpu to finish processing current batch */
748 radeon_fence_wait_last(rdev);
749
f657c2a7
YZ		 750 radeon_save_bios_scratch_regs(rdev);
751
3ce0a23d
JG		 752 if (!rdev->new_init_path) {
753 radeon_cp_disable(rdev);
754 radeon_gart_disable(rdev);
9f022ddf
JG		 755 rdev->irq.sw_int = false;
756 radeon_irq_set(rdev);
3ce0a23d
JG		 757 } else {
758 radeon_suspend(rdev);
759 }
771fe6b9
JG		 760 /* evict remaining vram memory */
761 radeon_object_evict_vram(rdev);
762
771fe6b9
JG		 763 pci_save_state(dev->pdev);
764 if (state.event == PM_EVENT_SUSPEND) {
765 /* Shut down the device */
766 pci_disable_device(dev->pdev);
767 pci_set_power_state(dev->pdev, PCI_D3hot);
768 }
769 acquire_console_sem();
770 fb_set_suspend(rdev->fbdev_info, 1);
771 release_console_sem();
772 return 0;
773}
774
775int radeon_resume_kms(struct drm_device *dev)
776{
777 struct radeon_device *rdev = dev->dev_private;
778 int r;
779
780 acquire_console_sem();
781 pci_set_power_state(dev->pdev, PCI_D0);
782 pci_restore_state(dev->pdev);
783 if (pci_enable_device(dev->pdev)) {
784 release_console_sem();
785 return -1;
786 }
787 pci_set_master(dev->pdev);
788 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3ce0a23d 789 if (!rdev->new_init_path) {
9f022ddf
JG		 790 if (radeon_gpu_reset(rdev)) {
791 /* FIXME: what do we want to do here ? */
792 }
3ce0a23d
JG		 793 /* post card */
794 if (rdev->is_atom_bios) {
795 atom_asic_init(rdev->mode_info.atom_context);
796 } else {
797 radeon_combios_asic_init(rdev->ddev);
798 }
799 /* Initialize clocks */
800 r = radeon_clocks_init(rdev);
801 if (r) {
802 release_console_sem();
803 return r;
804 }
805 /* Enable IRQ */
806 rdev->irq.sw_int = true;
807 radeon_irq_set(rdev);
808 /* Initialize GPU Memory Controller */
809 r = radeon_mc_init(rdev);
810 if (r) {
811 goto out;
812 }
813 r = radeon_gart_enable(rdev);
814 if (r) {
815 goto out;
816 }
817 r = radeon_cp_init(rdev, rdev->cp.ring_size);
818 if (r) {
819 goto out;
820 }
771fe6b9 821 } else {
3ce0a23d 822 radeon_resume(rdev);
771fe6b9
JG		 823 }
824out:
f657c2a7 825 radeon_restore_bios_scratch_regs(rdev);
771fe6b9
JG		 826 fb_set_suspend(rdev->fbdev_info, 0);
827 release_console_sem();
828
829 /* blat the mode back in */
830 drm_helper_resume_force_mode(dev);
831 return 0;
832}
833
834
835/*
836 * Debugfs
837 */
838struct radeon_debugfs {
839 struct drm_info_list *files;
840 unsigned num_files;
841};
842static struct radeon_debugfs _radeon_debugfs[RADEON_DEBUGFS_MAX_NUM_FILES];
843static unsigned _radeon_debugfs_count = 0;
844
845int radeon_debugfs_add_files(struct radeon_device *rdev,
846 struct drm_info_list *files,
847 unsigned nfiles)
848{
849 unsigned i;
850
851 for (i = 0; i < _radeon_debugfs_count; i++) {
852 if (_radeon_debugfs[i].files == files) {
853 /* Already registered */
854 return 0;
855 }
856 }
857 if ((_radeon_debugfs_count + nfiles) > RADEON_DEBUGFS_MAX_NUM_FILES) {
858 DRM_ERROR("Reached maximum number of debugfs files.\n");
859 DRM_ERROR("Report so we increase RADEON_DEBUGFS_MAX_NUM_FILES.\n");
860 return -EINVAL;
861 }
862 _radeon_debugfs[_radeon_debugfs_count].files = files;
863 _radeon_debugfs[_radeon_debugfs_count].num_files = nfiles;
864 _radeon_debugfs_count++;
865#if defined(CONFIG_DEBUG_FS)
866 drm_debugfs_create_files(files, nfiles,
867 rdev->ddev->control->debugfs_root,
868 rdev->ddev->control);
869 drm_debugfs_create_files(files, nfiles,
870 rdev->ddev->primary->debugfs_root,
871 rdev->ddev->primary);
872#endif
873 return 0;
874}
875
876#if defined(CONFIG_DEBUG_FS)
877int radeon_debugfs_init(struct drm_minor *minor)
878{
879 return 0;
880}
881
882void radeon_debugfs_cleanup(struct drm_minor *minor)
883{
884 unsigned i;
885
886 for (i = 0; i < _radeon_debugfs_count; i++) {
887 drm_debugfs_remove_files(_radeon_debugfs[i].files,
888 _radeon_debugfs[i].num_files, minor);
889 }
890}
891#endif
Clone of davem's net-next-2.6 tree