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drm/radeon/kms: use udelay for short delays
[net-next-2.6.git] / drivers / gpu / drm / radeon / radeon_device.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include <linux/console.h>
29#include <drm/drmP.h>
30#include <drm/drm_crtc_helper.h>
31#include <drm/radeon_drm.h>
28d52043 32#include <linux/vgaarb.h>
771fe6b9
JG		 33#include "radeon_reg.h"
34#include "radeon.h"
35#include "radeon_asic.h"
36#include "atom.h"
37
b1e3a6d1
MD		 38/*
39 * Clear GPU surface registers.
40 */
3ce0a23d 41void radeon_surface_init(struct radeon_device *rdev)
b1e3a6d1
MD		 42{
43 /* FIXME: check this out */
44 if (rdev->family < CHIP_R600) {
45 int i;
46
550e2d92
DA		 47 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
48 if (rdev->surface_regs[i].bo)
49 radeon_bo_get_surface_reg(rdev->surface_regs[i].bo);
50 else
51 radeon_clear_surface_reg(rdev, i);
b1e3a6d1 52 }
e024e110
DA		 53 /* enable surfaces */
54 WREG32(RADEON_SURFACE_CNTL, 0);
b1e3a6d1
MD		 55 }
56}
57
771fe6b9
JG		 58/*
59 * GPU scratch registers helpers function.
60 */
3ce0a23d 61void radeon_scratch_init(struct radeon_device *rdev)
771fe6b9
JG		 62{
63 int i;
64
65 /* FIXME: check this out */
66 if (rdev->family < CHIP_R300) {
67 rdev->scratch.num_reg = 5;
68 } else {
69 rdev->scratch.num_reg = 7;
70 }
71 for (i = 0; i < rdev->scratch.num_reg; i++) {
72 rdev->scratch.free[i] = true;
73 rdev->scratch.reg[i] = RADEON_SCRATCH_REG0 + (i * 4);
74 }
75}
76
77int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg)
78{
79 int i;
80
81 for (i = 0; i < rdev->scratch.num_reg; i++) {
82 if (rdev->scratch.free[i]) {
83 rdev->scratch.free[i] = false;
84 *reg = rdev->scratch.reg[i];
85 return 0;
86 }
87 }
88 return -EINVAL;
89}
90
91void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
92{
93 int i;
94
95 for (i = 0; i < rdev->scratch.num_reg; i++) {
96 if (rdev->scratch.reg[i] == reg) {
97 rdev->scratch.free[i] = true;
98 return;
99 }
100 }
101}
102
103/*
104 * MC common functions
105 */
106int radeon_mc_setup(struct radeon_device *rdev)
107{
108 uint32_t tmp;
109
110 /* Some chips have an "issue" with the memory controller, the
111 * location must be aligned to the size. We just align it down,
112 * too bad if we walk over the top of system memory, we don't
113 * use DMA without a remapped anyway.
114 * Affected chips are rv280, all r3xx, and all r4xx, but not IGP
115 */
116 /* FGLRX seems to setup like this, VRAM a 0, then GART.
117 */
118 /*
119 * Note: from R6xx the address space is 40bits but here we only
120 * use 32bits (still have to see a card which would exhaust 4G
121 * address space).
122 */
123 if (rdev->mc.vram_location != 0xFFFFFFFFUL) {
124 /* vram location was already setup try to put gtt after
125 * if it fits */
7a50f01a 126 tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size;
771fe6b9
JG		 127 tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1);
128 if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) {
129 rdev->mc.gtt_location = tmp;
130 } else {
131 if (rdev->mc.gtt_size >= rdev->mc.vram_location) {
132 printk(KERN_ERR "[drm] GTT too big to fit "
133 "before or after vram location.\n");
134 return -EINVAL;
135 }
136 rdev->mc.gtt_location = 0;
137 }
138 } else if (rdev->mc.gtt_location != 0xFFFFFFFFUL) {
139 /* gtt location was already setup try to put vram before
140 * if it fits */
7a50f01a 141 if (rdev->mc.mc_vram_size < rdev->mc.gtt_location) {
771fe6b9
JG		 142 rdev->mc.vram_location = 0;
143 } else {
144 tmp = rdev->mc.gtt_location + rdev->mc.gtt_size;
7a50f01a
DA		 145 tmp += (rdev->mc.mc_vram_size - 1);
146 tmp &= ~(rdev->mc.mc_vram_size - 1);
147 if ((0xFFFFFFFFUL - tmp) >= rdev->mc.mc_vram_size) {
771fe6b9
JG		 148 rdev->mc.vram_location = tmp;
149 } else {
150 printk(KERN_ERR "[drm] vram too big to fit "
151 "before or after GTT location.\n");
152 return -EINVAL;
153 }
154 }
155 } else {
156 rdev->mc.vram_location = 0;
17332925
DA		 157 tmp = rdev->mc.mc_vram_size;
158 tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1);
159 rdev->mc.gtt_location = tmp;
771fe6b9 160 }
9f022ddf
JG		 161 rdev->mc.vram_start = rdev->mc.vram_location;
162 rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
163 rdev->mc.gtt_start = rdev->mc.gtt_location;
164 rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
3ce0a23d 165 DRM_INFO("radeon: VRAM %uM\n", (unsigned)(rdev->mc.mc_vram_size >> 20));
771fe6b9 166 DRM_INFO("radeon: VRAM from 0x%08X to 0x%08X\n",
3ce0a23d
JG		 167 (unsigned)rdev->mc.vram_location,
168 (unsigned)(rdev->mc.vram_location + rdev->mc.mc_vram_size - 1));
169 DRM_INFO("radeon: GTT %uM\n", (unsigned)(rdev->mc.gtt_size >> 20));
771fe6b9 170 DRM_INFO("radeon: GTT from 0x%08X to 0x%08X\n",
3ce0a23d
JG		 171 (unsigned)rdev->mc.gtt_location,
172 (unsigned)(rdev->mc.gtt_location + rdev->mc.gtt_size - 1));
771fe6b9
JG		 173 return 0;
174}
175
176
177/*
178 * GPU helpers function.
179 */
9f022ddf 180bool radeon_card_posted(struct radeon_device *rdev)
771fe6b9
JG		 181{
182 uint32_t reg;
183
184 /* first check CRTCs */
185 if (ASIC_IS_AVIVO(rdev)) {
186 reg = RREG32(AVIVO_D1CRTC_CONTROL) |
187 RREG32(AVIVO_D2CRTC_CONTROL);
188 if (reg & AVIVO_CRTC_EN) {
189 return true;
190 }
191 } else {
192 reg = RREG32(RADEON_CRTC_GEN_CNTL) |
193 RREG32(RADEON_CRTC2_GEN_CNTL);
194 if (reg & RADEON_CRTC_EN) {
195 return true;
196 }
197 }
198
199 /* then check MEM_SIZE, in case the crtcs are off */
200 if (rdev->family >= CHIP_R600)
201 reg = RREG32(R600_CONFIG_MEMSIZE);
202 else
203 reg = RREG32(RADEON_CONFIG_MEMSIZE);
204
205 if (reg)
206 return true;
207
208 return false;
209
210}
211
72542d77
DA		 212bool radeon_boot_test_post_card(struct radeon_device *rdev)
213{
214 if (radeon_card_posted(rdev))
215 return true;
216
217 if (rdev->bios) {
218 DRM_INFO("GPU not posted. posting now...\n");
219 if (rdev->is_atom_bios)
220 atom_asic_init(rdev->mode_info.atom_context);
221 else
222 radeon_combios_asic_init(rdev->ddev);
223 return true;
224 } else {
225 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
226 return false;
227 }
228}
229
3ce0a23d
JG		 230int radeon_dummy_page_init(struct radeon_device *rdev)
231{
232 rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
233 if (rdev->dummy_page.page == NULL)
234 return -ENOMEM;
235 rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page,
236 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
237 if (!rdev->dummy_page.addr) {
238 __free_page(rdev->dummy_page.page);
239 rdev->dummy_page.page = NULL;
240 return -ENOMEM;
241 }
242 return 0;
243}
244
245void radeon_dummy_page_fini(struct radeon_device *rdev)
246{
247 if (rdev->dummy_page.page == NULL)
248 return;
249 pci_unmap_page(rdev->pdev, rdev->dummy_page.addr,
250 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
251 __free_page(rdev->dummy_page.page);
252 rdev->dummy_page.page = NULL;
253}
254
771fe6b9
JG		 255
256/*
257 * Registers accessors functions.
258 */
259uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
260{
261 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
262 BUG_ON(1);
263 return 0;
264}
265
266void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
267{
268 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
269 reg, v);
270 BUG_ON(1);
271}
272
273void radeon_register_accessor_init(struct radeon_device *rdev)
274{
771fe6b9
JG		 275 rdev->mc_rreg = &radeon_invalid_rreg;
276 rdev->mc_wreg = &radeon_invalid_wreg;
277 rdev->pll_rreg = &radeon_invalid_rreg;
278 rdev->pll_wreg = &radeon_invalid_wreg;
771fe6b9
JG		 279 rdev->pciep_rreg = &radeon_invalid_rreg;
280 rdev->pciep_wreg = &radeon_invalid_wreg;
281
282 /* Don't change order as we are overridding accessor. */
283 if (rdev->family < CHIP_RV515) {
de1b2898
DA		 284 rdev->pcie_reg_mask = 0xff;
285 } else {
286 rdev->pcie_reg_mask = 0x7ff;
771fe6b9
JG		 287 }
288 /* FIXME: not sure here */
289 if (rdev->family <= CHIP_R580) {
290 rdev->pll_rreg = &r100_pll_rreg;
291 rdev->pll_wreg = &r100_pll_wreg;
292 }
905b6822
JG		 293 if (rdev->family >= CHIP_R420) {
294 rdev->mc_rreg = &r420_mc_rreg;
295 rdev->mc_wreg = &r420_mc_wreg;
296 }
771fe6b9
JG		 297 if (rdev->family >= CHIP_RV515) {
298 rdev->mc_rreg = &rv515_mc_rreg;
299 rdev->mc_wreg = &rv515_mc_wreg;
300 }
301 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
302 rdev->mc_rreg = &rs400_mc_rreg;
303 rdev->mc_wreg = &rs400_mc_wreg;
304 }
305 if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
306 rdev->mc_rreg = &rs690_mc_rreg;
307 rdev->mc_wreg = &rs690_mc_wreg;
308 }
309 if (rdev->family == CHIP_RS600) {
310 rdev->mc_rreg = &rs600_mc_rreg;
311 rdev->mc_wreg = &rs600_mc_wreg;
312 }
313 if (rdev->family >= CHIP_R600) {
314 rdev->pciep_rreg = &r600_pciep_rreg;
315 rdev->pciep_wreg = &r600_pciep_wreg;
316 }
317}
318
319
320/*
321 * ASIC
322 */
323int radeon_asic_init(struct radeon_device *rdev)
324{
325 radeon_register_accessor_init(rdev);
326 switch (rdev->family) {
327 case CHIP_R100:
328 case CHIP_RV100:
329 case CHIP_RS100:
330 case CHIP_RV200:
331 case CHIP_RS200:
332 case CHIP_R200:
333 case CHIP_RV250:
334 case CHIP_RS300:
335 case CHIP_RV280:
336 rdev->asic = &r100_asic;
337 break;
338 case CHIP_R300:
339 case CHIP_R350:
340 case CHIP_RV350:
341 case CHIP_RV380:
342 rdev->asic = &r300_asic;
4aac0473 343 if (rdev->flags & RADEON_IS_PCIE) {
4aac0473
JG		 344 rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
345 rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
346 }
771fe6b9
JG		 347 break;
348 case CHIP_R420:
349 case CHIP_R423:
350 case CHIP_RV410:
351 rdev->asic = &r420_asic;
352 break;
353 case CHIP_RS400:
354 case CHIP_RS480:
355 rdev->asic = &rs400_asic;
356 break;
357 case CHIP_RS600:
358 rdev->asic = &rs600_asic;
359 break;
360 case CHIP_RS690:
361 case CHIP_RS740:
362 rdev->asic = &rs690_asic;
363 break;
364 case CHIP_RV515:
365 rdev->asic = &rv515_asic;
366 break;
367 case CHIP_R520:
368 case CHIP_RV530:
369 case CHIP_RV560:
370 case CHIP_RV570:
371 case CHIP_R580:
372 rdev->asic = &r520_asic;
373 break;
374 case CHIP_R600:
375 case CHIP_RV610:
376 case CHIP_RV630:
377 case CHIP_RV620:
378 case CHIP_RV635:
379 case CHIP_RV670:
380 case CHIP_RS780:
3ce0a23d
JG		 381 case CHIP_RS880:
382 rdev->asic = &r600_asic;
383 break;
771fe6b9
JG		 384 case CHIP_RV770:
385 case CHIP_RV730:
386 case CHIP_RV710:
3ce0a23d
JG		 387 case CHIP_RV740:
388 rdev->asic = &rv770_asic;
389 break;
771fe6b9
JG		 390 default:
391 /* FIXME: not supported yet */
392 return -EINVAL;
393 }
5ea597f3
RM		 394
395 if (rdev->flags & RADEON_IS_IGP) {
396 rdev->asic->get_memory_clock = NULL;
397 rdev->asic->set_memory_clock = NULL;
398 }
399
771fe6b9
JG		 400 return 0;
401}
402
403
404/*
405 * Wrapper around modesetting bits.
406 */
407int radeon_clocks_init(struct radeon_device *rdev)
408{
409 int r;
410
771fe6b9
JG		 411 r = radeon_static_clocks_init(rdev->ddev);
412 if (r) {
413 return r;
414 }
415 DRM_INFO("Clocks initialized !\n");
416 return 0;
417}
418
419void radeon_clocks_fini(struct radeon_device *rdev)
420{
421}
422
423/* ATOM accessor methods */
424static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
425{
426 struct radeon_device *rdev = info->dev->dev_private;
427 uint32_t r;
428
429 r = rdev->pll_rreg(rdev, reg);
430 return r;
431}
432
433static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
434{
435 struct radeon_device *rdev = info->dev->dev_private;
436
437 rdev->pll_wreg(rdev, reg, val);
438}
439
440static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
441{
442 struct radeon_device *rdev = info->dev->dev_private;
443 uint32_t r;
444
445 r = rdev->mc_rreg(rdev, reg);
446 return r;
447}
448
449static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
450{
451 struct radeon_device *rdev = info->dev->dev_private;
452
453 rdev->mc_wreg(rdev, reg, val);
454}
455
456static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
457{
458 struct radeon_device *rdev = info->dev->dev_private;
459
460 WREG32(reg*4, val);
461}
462
463static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
464{
465 struct radeon_device *rdev = info->dev->dev_private;
466 uint32_t r;
467
468 r = RREG32(reg*4);
469 return r;
470}
471
771fe6b9
JG		 472int radeon_atombios_init(struct radeon_device *rdev)
473{
61c4b24b
MF		 474 struct card_info *atom_card_info =
475 kzalloc(sizeof(struct card_info), GFP_KERNEL);
476
477 if (!atom_card_info)
478 return -ENOMEM;
479
480 rdev->mode_info.atom_card_info = atom_card_info;
481 atom_card_info->dev = rdev->ddev;
482 atom_card_info->reg_read = cail_reg_read;
483 atom_card_info->reg_write = cail_reg_write;
484 atom_card_info->mc_read = cail_mc_read;
485 atom_card_info->mc_write = cail_mc_write;
486 atom_card_info->pll_read = cail_pll_read;
487 atom_card_info->pll_write = cail_pll_write;
488
489 rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios);
c31ad97f 490 mutex_init(&rdev->mode_info.atom_context->mutex);
771fe6b9 491 radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
d904ef9b 492 atom_allocate_fb_scratch(rdev->mode_info.atom_context);
771fe6b9
JG		 493 return 0;
494}
495
496void radeon_atombios_fini(struct radeon_device *rdev)
497{
4a04a844
JG		 498 if (rdev->mode_info.atom_context) {
499 kfree(rdev->mode_info.atom_context->scratch);
500 kfree(rdev->mode_info.atom_context);
501 }
61c4b24b 502 kfree(rdev->mode_info.atom_card_info);
771fe6b9
JG		 503}
504
505int radeon_combios_init(struct radeon_device *rdev)
506{
507 radeon_combios_initialize_bios_scratch_regs(rdev->ddev);
508 return 0;
509}
510
511void radeon_combios_fini(struct radeon_device *rdev)
512{
513}
514
28d52043
DA		 515/* if we get transitioned to only one device, tak VGA back */
516static unsigned int radeon_vga_set_decode(void *cookie, bool state)
517{
518 struct radeon_device *rdev = cookie;
28d52043
DA		 519 radeon_vga_set_state(rdev, state);
520 if (state)
521 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
522 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
523 else
524 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
525}
c1176d6f 526
b574f251
JG		 527void radeon_agp_disable(struct radeon_device *rdev)
528{
529 rdev->flags &= ~RADEON_IS_AGP;
530 if (rdev->family >= CHIP_R600) {
531 DRM_INFO("Forcing AGP to PCIE mode\n");
532 rdev->flags |= RADEON_IS_PCIE;
533 } else if (rdev->family >= CHIP_RV515 ||
534 rdev->family == CHIP_RV380 ||
535 rdev->family == CHIP_RV410 ||
536 rdev->family == CHIP_R423) {
537 DRM_INFO("Forcing AGP to PCIE mode\n");
538 rdev->flags |= RADEON_IS_PCIE;
539 rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
540 rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
541 } else {
542 DRM_INFO("Forcing AGP to PCI mode\n");
543 rdev->flags |= RADEON_IS_PCI;
544 rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
545 rdev->asic->gart_set_page = &r100_pci_gart_set_page;
546 }
700a0cc0 547 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
b574f251 548}
771fe6b9 549
36421338
JG		 550void radeon_check_arguments(struct radeon_device *rdev)
551{
552 /* vramlimit must be a power of two */
553 switch (radeon_vram_limit) {
554 case 0:
555 case 4:
556 case 8:
557 case 16:
558 case 32:
559 case 64:
560 case 128:
561 case 256:
562 case 512:
563 case 1024:
564 case 2048:
565 case 4096:
566 break;
567 default:
568 dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n",
569 radeon_vram_limit);
570 radeon_vram_limit = 0;
571 break;
572 }
573 radeon_vram_limit = radeon_vram_limit << 20;
574 /* gtt size must be power of two and greater or equal to 32M */
575 switch (radeon_gart_size) {
576 case 4:
577 case 8:
578 case 16:
579 dev_warn(rdev->dev, "gart size (%d) too small forcing to 512M\n",
580 radeon_gart_size);
581 radeon_gart_size = 512;
582 break;
583 case 32:
584 case 64:
585 case 128:
586 case 256:
587 case 512:
588 case 1024:
589 case 2048:
590 case 4096:
591 break;
592 default:
593 dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n",
594 radeon_gart_size);
595 radeon_gart_size = 512;
596 break;
597 }
598 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
599 /* AGP mode can only be -1, 1, 2, 4, 8 */
600 switch (radeon_agpmode) {
601 case -1:
602 case 0:
603 case 1:
604 case 2:
605 case 4:
606 case 8:
607 break;
608 default:
609 dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: "
610 "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode);
611 radeon_agpmode = 0;
612 break;
613 }
614}
615
771fe6b9
JG		 616int radeon_device_init(struct radeon_device *rdev,
617 struct drm_device *ddev,
618 struct pci_dev *pdev,
619 uint32_t flags)
620{
6cf8a3f5 621 int r;
ad49f501 622 int dma_bits;
771fe6b9
JG		 623
624 DRM_INFO("radeon: Initializing kernel modesetting.\n");
625 rdev->shutdown = false;
9f022ddf 626 rdev->dev = &pdev->dev;
771fe6b9
JG		 627 rdev->ddev = ddev;
628 rdev->pdev = pdev;
629 rdev->flags = flags;
630 rdev->family = flags & RADEON_FAMILY_MASK;
631 rdev->is_atom_bios = false;
632 rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
633 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
634 rdev->gpu_lockup = false;
733289c2 635 rdev->accel_working = false;
771fe6b9
JG		 636 /* mutex initialization are all done here so we
637 * can recall function without having locking issues */
638 mutex_init(&rdev->cs_mutex);
639 mutex_init(&rdev->ib_pool.mutex);
640 mutex_init(&rdev->cp.mutex);
40bacf16 641 mutex_init(&rdev->dc_hw_i2c_mutex);
d8f60cfc
AD		 642 if (rdev->family >= CHIP_R600)
643 spin_lock_init(&rdev->ih.lock);
4c788679 644 mutex_init(&rdev->gem.mutex);
c913e23a 645 mutex_init(&rdev->pm.mutex);
771fe6b9 646 rwlock_init(&rdev->fence_drv.lock);
9f022ddf 647 INIT_LIST_HEAD(&rdev->gem.objects);
771fe6b9 648
d4877cf2
AD		 649 /* setup workqueue */
650 rdev->wq = create_workqueue("radeon");
651 if (rdev->wq == NULL)
652 return -ENOMEM;
653
4aac0473
JG		 654 /* Set asic functions */
655 r = radeon_asic_init(rdev);
36421338 656 if (r)
4aac0473 657 return r;
36421338 658 radeon_check_arguments(rdev);
4aac0473 659
30256a3f 660 if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) {
b574f251 661 radeon_agp_disable(rdev);
771fe6b9
JG		 662 }
663
ad49f501
DA		 664 /* set DMA mask + need_dma32 flags.
665 * PCIE - can handle 40-bits.
666 * IGP - can handle 40-bits (in theory)
667 * AGP - generally dma32 is safest
668 * PCI - only dma32
669 */
670 rdev->need_dma32 = false;
671 if (rdev->flags & RADEON_IS_AGP)
672 rdev->need_dma32 = true;
673 if (rdev->flags & RADEON_IS_PCI)
674 rdev->need_dma32 = true;
675
676 dma_bits = rdev->need_dma32 ? 32 : 40;
677 r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
771fe6b9
JG		 678 if (r) {
679 printk(KERN_WARNING "radeon: No suitable DMA available.\n");
680 }
681
682 /* Registers mapping */
683 /* TODO: block userspace mapping of io register */
684 rdev->rmmio_base = drm_get_resource_start(rdev->ddev, 2);
685 rdev->rmmio_size = drm_get_resource_len(rdev->ddev, 2);
686 rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size);
687 if (rdev->rmmio == NULL) {
688 return -ENOMEM;
689 }
690 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
691 DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
692
28d52043 693 /* if we have > 1 VGA cards, then disable the radeon VGA resources */
93239ea1
DA		 694 /* this will fail for cards that aren't VGA class devices, just
695 * ignore it */
696 vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode);
28d52043 697
3ce0a23d 698 r = radeon_init(rdev);
b574f251 699 if (r)
3ce0a23d 700 return r;
3ce0a23d 701
b574f251
JG		 702 if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) {
703 /* Acceleration not working on AGP card try again
704 * with fallback to PCI or PCIE GART
705 */
1a029b76 706 radeon_gpu_reset(rdev);
b574f251
JG		 707 radeon_fini(rdev);
708 radeon_agp_disable(rdev);
709 r = radeon_init(rdev);
4aac0473
JG		 710 if (r)
711 return r;
771fe6b9 712 }
ecc0b326
MD		 713 if (radeon_testing) {
714 radeon_test_moves(rdev);
715 }
771fe6b9
JG		 716 if (radeon_benchmarking) {
717 radeon_benchmark(rdev);
718 }
6cf8a3f5 719 return 0;
771fe6b9
JG		 720}
721
722void radeon_device_fini(struct radeon_device *rdev)
723{
771fe6b9
JG		 724 DRM_INFO("radeon: finishing device.\n");
725 rdev->shutdown = true;
62a8ea3f 726 radeon_fini(rdev);
d4877cf2 727 destroy_workqueue(rdev->wq);
c1176d6f 728 vga_client_register(rdev->pdev, NULL, NULL, NULL);
771fe6b9
JG		 729 iounmap(rdev->rmmio);
730 rdev->rmmio = NULL;
731}
732
733
734/*
735 * Suspend & resume.
736 */
737int radeon_suspend_kms(struct drm_device *dev, pm_message_t state)
738{
875c1866 739 struct radeon_device *rdev;
771fe6b9 740 struct drm_crtc *crtc;
4c788679 741 int r;
771fe6b9 742
875c1866 743 if (dev == NULL || dev->dev_private == NULL) {
771fe6b9
JG		 744 return -ENODEV;
745 }
746 if (state.event == PM_EVENT_PRETHAW) {
747 return 0;
748 }
875c1866
DJ		 749 rdev = dev->dev_private;
750
771fe6b9
JG		 751 /* unpin the front buffers */
752 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
753 struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->fb);
4c788679 754 struct radeon_bo *robj;
771fe6b9
JG		 755
756 if (rfb == NULL || rfb->obj == NULL) {
757 continue;
758 }
759 robj = rfb->obj->driver_private;
4c788679
JG		 760 if (robj != rdev->fbdev_rbo) {
761 r = radeon_bo_reserve(robj, false);
762 if (unlikely(r == 0)) {
763 radeon_bo_unpin(robj);
764 radeon_bo_unreserve(robj);
765 }
771fe6b9
JG		 766 }
767 }
768 /* evict vram memory */
4c788679 769 radeon_bo_evict_vram(rdev);
771fe6b9
JG		 770 /* wait for gpu to finish processing current batch */
771 radeon_fence_wait_last(rdev);
772
f657c2a7
YZ		 773 radeon_save_bios_scratch_regs(rdev);
774
62a8ea3f 775 radeon_suspend(rdev);
d4877cf2 776 radeon_hpd_fini(rdev);
771fe6b9 777 /* evict remaining vram memory */
4c788679 778 radeon_bo_evict_vram(rdev);
771fe6b9 779
771fe6b9
JG		 780 pci_save_state(dev->pdev);
781 if (state.event == PM_EVENT_SUSPEND) {
782 /* Shut down the device */
783 pci_disable_device(dev->pdev);
784 pci_set_power_state(dev->pdev, PCI_D3hot);
785 }
786 acquire_console_sem();
787 fb_set_suspend(rdev->fbdev_info, 1);
788 release_console_sem();
789 return 0;
790}
791
792int radeon_resume_kms(struct drm_device *dev)
793{
794 struct radeon_device *rdev = dev->dev_private;
771fe6b9
JG		 795
796 acquire_console_sem();
797 pci_set_power_state(dev->pdev, PCI_D0);
798 pci_restore_state(dev->pdev);
799 if (pci_enable_device(dev->pdev)) {
800 release_console_sem();
801 return -1;
802 }
803 pci_set_master(dev->pdev);
0ebf1717
DA		 804 /* resume AGP if in use */
805 radeon_agp_resume(rdev);
62a8ea3f 806 radeon_resume(rdev);
f657c2a7 807 radeon_restore_bios_scratch_regs(rdev);
771fe6b9
JG		 808 fb_set_suspend(rdev->fbdev_info, 0);
809 release_console_sem();
810
d4877cf2
AD		 811 /* reset hpd state */
812 radeon_hpd_init(rdev);
771fe6b9
JG		 813 /* blat the mode back in */
814 drm_helper_resume_force_mode(dev);
815 return 0;
816}
817
818
819/*
820 * Debugfs
821 */
822struct radeon_debugfs {
823 struct drm_info_list *files;
824 unsigned num_files;
825};
826static struct radeon_debugfs _radeon_debugfs[RADEON_DEBUGFS_MAX_NUM_FILES];
827static unsigned _radeon_debugfs_count = 0;
828
829int radeon_debugfs_add_files(struct radeon_device *rdev,
830 struct drm_info_list *files,
831 unsigned nfiles)
832{
833 unsigned i;
834
835 for (i = 0; i < _radeon_debugfs_count; i++) {
836 if (_radeon_debugfs[i].files == files) {
837 /* Already registered */
838 return 0;
839 }
840 }
841 if ((_radeon_debugfs_count + nfiles) > RADEON_DEBUGFS_MAX_NUM_FILES) {
842 DRM_ERROR("Reached maximum number of debugfs files.\n");
843 DRM_ERROR("Report so we increase RADEON_DEBUGFS_MAX_NUM_FILES.\n");
844 return -EINVAL;
845 }
846 _radeon_debugfs[_radeon_debugfs_count].files = files;
847 _radeon_debugfs[_radeon_debugfs_count].num_files = nfiles;
848 _radeon_debugfs_count++;
849#if defined(CONFIG_DEBUG_FS)
850 drm_debugfs_create_files(files, nfiles,
851 rdev->ddev->control->debugfs_root,
852 rdev->ddev->control);
853 drm_debugfs_create_files(files, nfiles,
854 rdev->ddev->primary->debugfs_root,
855 rdev->ddev->primary);
856#endif
857 return 0;
858}
859
860#if defined(CONFIG_DEBUG_FS)
861int radeon_debugfs_init(struct drm_minor *minor)
862{
863 return 0;
864}
865
866void radeon_debugfs_cleanup(struct drm_minor *minor)
867{
868 unsigned i;
869
870 for (i = 0; i < _radeon_debugfs_count; i++) {
871 drm_debugfs_remove_files(_radeon_debugfs[i].files,
872 _radeon_debugfs[i].num_files, minor);
873 }
874}
875#endif
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