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drm/edid: Add modes for Established Timings III section
[net-next-2.6.git] / drivers / gpu / drm / radeon / radeon_combios.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2004 ATI Technologies Inc., Markham, Ontario
3 * Copyright 2007-8 Advanced Micro Devices, Inc.
4 * Copyright 2008 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 */
27#include "drmP.h"
28#include "radeon_drm.h"
29#include "radeon.h"
30#include "atom.h"
31
32#ifdef CONFIG_PPC_PMAC
33/* not sure which of these are needed */
34#include <asm/machdep.h>
35#include <asm/pmac_feature.h>
36#include <asm/prom.h>
37#include <asm/pci-bridge.h>
38#endif /* CONFIG_PPC_PMAC */
39
40/* from radeon_encoder.c */
41extern uint32_t
42radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device,
43 uint8_t dac);
44extern void radeon_link_encoder_connector(struct drm_device *dev);
45
46/* from radeon_connector.c */
47extern void
48radeon_add_legacy_connector(struct drm_device *dev,
49 uint32_t connector_id,
50 uint32_t supported_device,
51 int connector_type,
b75fad06 52 struct radeon_i2c_bus_rec *i2c_bus,
eed45b30
AD		 53 uint16_t connector_object_id,
54 struct radeon_hpd *hpd);
771fe6b9
JG		 55
56/* from radeon_legacy_encoder.c */
57extern void
58radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id,
59 uint32_t supported_device);
60
61/* old legacy ATI BIOS routines */
62
63/* COMBIOS table offsets */
64enum radeon_combios_table_offset {
65 /* absolute offset tables */
66 COMBIOS_ASIC_INIT_1_TABLE,
67 COMBIOS_BIOS_SUPPORT_TABLE,
68 COMBIOS_DAC_PROGRAMMING_TABLE,
69 COMBIOS_MAX_COLOR_DEPTH_TABLE,
70 COMBIOS_CRTC_INFO_TABLE,
71 COMBIOS_PLL_INFO_TABLE,
72 COMBIOS_TV_INFO_TABLE,
73 COMBIOS_DFP_INFO_TABLE,
74 COMBIOS_HW_CONFIG_INFO_TABLE,
75 COMBIOS_MULTIMEDIA_INFO_TABLE,
76 COMBIOS_TV_STD_PATCH_TABLE,
77 COMBIOS_LCD_INFO_TABLE,
78 COMBIOS_MOBILE_INFO_TABLE,
79 COMBIOS_PLL_INIT_TABLE,
80 COMBIOS_MEM_CONFIG_TABLE,
81 COMBIOS_SAVE_MASK_TABLE,
82 COMBIOS_HARDCODED_EDID_TABLE,
83 COMBIOS_ASIC_INIT_2_TABLE,
84 COMBIOS_CONNECTOR_INFO_TABLE,
85 COMBIOS_DYN_CLK_1_TABLE,
86 COMBIOS_RESERVED_MEM_TABLE,
87 COMBIOS_EXT_TMDS_INFO_TABLE,
88 COMBIOS_MEM_CLK_INFO_TABLE,
89 COMBIOS_EXT_DAC_INFO_TABLE,
90 COMBIOS_MISC_INFO_TABLE,
91 COMBIOS_CRT_INFO_TABLE,
92 COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE,
93 COMBIOS_COMPONENT_VIDEO_INFO_TABLE,
94 COMBIOS_FAN_SPEED_INFO_TABLE,
95 COMBIOS_OVERDRIVE_INFO_TABLE,
96 COMBIOS_OEM_INFO_TABLE,
97 COMBIOS_DYN_CLK_2_TABLE,
98 COMBIOS_POWER_CONNECTOR_INFO_TABLE,
99 COMBIOS_I2C_INFO_TABLE,
100 /* relative offset tables */
101 COMBIOS_ASIC_INIT_3_TABLE, /* offset from misc info */
102 COMBIOS_ASIC_INIT_4_TABLE, /* offset from misc info */
103 COMBIOS_DETECTED_MEM_TABLE, /* offset from misc info */
104 COMBIOS_ASIC_INIT_5_TABLE, /* offset from misc info */
105 COMBIOS_RAM_RESET_TABLE, /* offset from mem config */
106 COMBIOS_POWERPLAY_INFO_TABLE, /* offset from mobile info */
107 COMBIOS_GPIO_INFO_TABLE, /* offset from mobile info */
108 COMBIOS_LCD_DDC_INFO_TABLE, /* offset from mobile info */
109 COMBIOS_TMDS_POWER_TABLE, /* offset from mobile info */
110 COMBIOS_TMDS_POWER_ON_TABLE, /* offset from tmds power */
111 COMBIOS_TMDS_POWER_OFF_TABLE, /* offset from tmds power */
112};
113
114enum radeon_combios_ddc {
115 DDC_NONE_DETECTED,
116 DDC_MONID,
117 DDC_DVI,
118 DDC_VGA,
119 DDC_CRT2,
120 DDC_LCD,
121 DDC_GPIO,
122};
123
124enum radeon_combios_connector {
125 CONNECTOR_NONE_LEGACY,
126 CONNECTOR_PROPRIETARY_LEGACY,
127 CONNECTOR_CRT_LEGACY,
128 CONNECTOR_DVI_I_LEGACY,
129 CONNECTOR_DVI_D_LEGACY,
130 CONNECTOR_CTV_LEGACY,
131 CONNECTOR_STV_LEGACY,
132 CONNECTOR_UNSUPPORTED_LEGACY
133};
134
135const int legacy_connector_convert[] = {
136 DRM_MODE_CONNECTOR_Unknown,
137 DRM_MODE_CONNECTOR_DVID,
138 DRM_MODE_CONNECTOR_VGA,
139 DRM_MODE_CONNECTOR_DVII,
140 DRM_MODE_CONNECTOR_DVID,
141 DRM_MODE_CONNECTOR_Composite,
142 DRM_MODE_CONNECTOR_SVIDEO,
143 DRM_MODE_CONNECTOR_Unknown,
144};
145
146static uint16_t combios_get_table_offset(struct drm_device *dev,
147 enum radeon_combios_table_offset table)
148{
149 struct radeon_device *rdev = dev->dev_private;
150 int rev;
151 uint16_t offset = 0, check_offset;
152
03047cdf
MD		 153 if (!rdev->bios)
154 return 0;
155
771fe6b9
JG		 156 switch (table) {
157 /* absolute offset tables */
158 case COMBIOS_ASIC_INIT_1_TABLE:
159 check_offset = RBIOS16(rdev->bios_header_start + 0xc);
160 if (check_offset)
161 offset = check_offset;
162 break;
163 case COMBIOS_BIOS_SUPPORT_TABLE:
164 check_offset = RBIOS16(rdev->bios_header_start + 0x14);
165 if (check_offset)
166 offset = check_offset;
167 break;
168 case COMBIOS_DAC_PROGRAMMING_TABLE:
169 check_offset = RBIOS16(rdev->bios_header_start + 0x2a);
170 if (check_offset)
171 offset = check_offset;
172 break;
173 case COMBIOS_MAX_COLOR_DEPTH_TABLE:
174 check_offset = RBIOS16(rdev->bios_header_start + 0x2c);
175 if (check_offset)
176 offset = check_offset;
177 break;
178 case COMBIOS_CRTC_INFO_TABLE:
179 check_offset = RBIOS16(rdev->bios_header_start + 0x2e);
180 if (check_offset)
181 offset = check_offset;
182 break;
183 case COMBIOS_PLL_INFO_TABLE:
184 check_offset = RBIOS16(rdev->bios_header_start + 0x30);
185 if (check_offset)
186 offset = check_offset;
187 break;
188 case COMBIOS_TV_INFO_TABLE:
189 check_offset = RBIOS16(rdev->bios_header_start + 0x32);
190 if (check_offset)
191 offset = check_offset;
192 break;
193 case COMBIOS_DFP_INFO_TABLE:
194 check_offset = RBIOS16(rdev->bios_header_start + 0x34);
195 if (check_offset)
196 offset = check_offset;
197 break;
198 case COMBIOS_HW_CONFIG_INFO_TABLE:
199 check_offset = RBIOS16(rdev->bios_header_start + 0x36);
200 if (check_offset)
201 offset = check_offset;
202 break;
203 case COMBIOS_MULTIMEDIA_INFO_TABLE:
204 check_offset = RBIOS16(rdev->bios_header_start + 0x38);
205 if (check_offset)
206 offset = check_offset;
207 break;
208 case COMBIOS_TV_STD_PATCH_TABLE:
209 check_offset = RBIOS16(rdev->bios_header_start + 0x3e);
210 if (check_offset)
211 offset = check_offset;
212 break;
213 case COMBIOS_LCD_INFO_TABLE:
214 check_offset = RBIOS16(rdev->bios_header_start + 0x40);
215 if (check_offset)
216 offset = check_offset;
217 break;
218 case COMBIOS_MOBILE_INFO_TABLE:
219 check_offset = RBIOS16(rdev->bios_header_start + 0x42);
220 if (check_offset)
221 offset = check_offset;
222 break;
223 case COMBIOS_PLL_INIT_TABLE:
224 check_offset = RBIOS16(rdev->bios_header_start + 0x46);
225 if (check_offset)
226 offset = check_offset;
227 break;
228 case COMBIOS_MEM_CONFIG_TABLE:
229 check_offset = RBIOS16(rdev->bios_header_start + 0x48);
230 if (check_offset)
231 offset = check_offset;
232 break;
233 case COMBIOS_SAVE_MASK_TABLE:
234 check_offset = RBIOS16(rdev->bios_header_start + 0x4a);
235 if (check_offset)
236 offset = check_offset;
237 break;
238 case COMBIOS_HARDCODED_EDID_TABLE:
239 check_offset = RBIOS16(rdev->bios_header_start + 0x4c);
240 if (check_offset)
241 offset = check_offset;
242 break;
243 case COMBIOS_ASIC_INIT_2_TABLE:
244 check_offset = RBIOS16(rdev->bios_header_start + 0x4e);
245 if (check_offset)
246 offset = check_offset;
247 break;
248 case COMBIOS_CONNECTOR_INFO_TABLE:
249 check_offset = RBIOS16(rdev->bios_header_start + 0x50);
250 if (check_offset)
251 offset = check_offset;
252 break;
253 case COMBIOS_DYN_CLK_1_TABLE:
254 check_offset = RBIOS16(rdev->bios_header_start + 0x52);
255 if (check_offset)
256 offset = check_offset;
257 break;
258 case COMBIOS_RESERVED_MEM_TABLE:
259 check_offset = RBIOS16(rdev->bios_header_start + 0x54);
260 if (check_offset)
261 offset = check_offset;
262 break;
263 case COMBIOS_EXT_TMDS_INFO_TABLE:
264 check_offset = RBIOS16(rdev->bios_header_start + 0x58);
265 if (check_offset)
266 offset = check_offset;
267 break;
268 case COMBIOS_MEM_CLK_INFO_TABLE:
269 check_offset = RBIOS16(rdev->bios_header_start + 0x5a);
270 if (check_offset)
271 offset = check_offset;
272 break;
273 case COMBIOS_EXT_DAC_INFO_TABLE:
274 check_offset = RBIOS16(rdev->bios_header_start + 0x5c);
275 if (check_offset)
276 offset = check_offset;
277 break;
278 case COMBIOS_MISC_INFO_TABLE:
279 check_offset = RBIOS16(rdev->bios_header_start + 0x5e);
280 if (check_offset)
281 offset = check_offset;
282 break;
283 case COMBIOS_CRT_INFO_TABLE:
284 check_offset = RBIOS16(rdev->bios_header_start + 0x60);
285 if (check_offset)
286 offset = check_offset;
287 break;
288 case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE:
289 check_offset = RBIOS16(rdev->bios_header_start + 0x62);
290 if (check_offset)
291 offset = check_offset;
292 break;
293 case COMBIOS_COMPONENT_VIDEO_INFO_TABLE:
294 check_offset = RBIOS16(rdev->bios_header_start + 0x64);
295 if (check_offset)
296 offset = check_offset;
297 break;
298 case COMBIOS_FAN_SPEED_INFO_TABLE:
299 check_offset = RBIOS16(rdev->bios_header_start + 0x66);
300 if (check_offset)
301 offset = check_offset;
302 break;
303 case COMBIOS_OVERDRIVE_INFO_TABLE:
304 check_offset = RBIOS16(rdev->bios_header_start + 0x68);
305 if (check_offset)
306 offset = check_offset;
307 break;
308 case COMBIOS_OEM_INFO_TABLE:
309 check_offset = RBIOS16(rdev->bios_header_start + 0x6a);
310 if (check_offset)
311 offset = check_offset;
312 break;
313 case COMBIOS_DYN_CLK_2_TABLE:
314 check_offset = RBIOS16(rdev->bios_header_start + 0x6c);
315 if (check_offset)
316 offset = check_offset;
317 break;
318 case COMBIOS_POWER_CONNECTOR_INFO_TABLE:
319 check_offset = RBIOS16(rdev->bios_header_start + 0x6e);
320 if (check_offset)
321 offset = check_offset;
322 break;
323 case COMBIOS_I2C_INFO_TABLE:
324 check_offset = RBIOS16(rdev->bios_header_start + 0x70);
325 if (check_offset)
326 offset = check_offset;
327 break;
328 /* relative offset tables */
329 case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */
330 check_offset =
331 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
332 if (check_offset) {
333 rev = RBIOS8(check_offset);
334 if (rev > 0) {
335 check_offset = RBIOS16(check_offset + 0x3);
336 if (check_offset)
337 offset = check_offset;
338 }
339 }
340 break;
341 case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */
342 check_offset =
343 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
344 if (check_offset) {
345 rev = RBIOS8(check_offset);
346 if (rev > 0) {
347 check_offset = RBIOS16(check_offset + 0x5);
348 if (check_offset)
349 offset = check_offset;
350 }
351 }
352 break;
353 case COMBIOS_DETECTED_MEM_TABLE: /* offset from misc info */
354 check_offset =
355 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
356 if (check_offset) {
357 rev = RBIOS8(check_offset);
358 if (rev > 0) {
359 check_offset = RBIOS16(check_offset + 0x7);
360 if (check_offset)
361 offset = check_offset;
362 }
363 }
364 break;
365 case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */
366 check_offset =
367 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
368 if (check_offset) {
369 rev = RBIOS8(check_offset);
370 if (rev == 2) {
371 check_offset = RBIOS16(check_offset + 0x9);
372 if (check_offset)
373 offset = check_offset;
374 }
375 }
376 break;
377 case COMBIOS_RAM_RESET_TABLE: /* offset from mem config */
378 check_offset =
379 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
380 if (check_offset) {
381 while (RBIOS8(check_offset++));
382 check_offset += 2;
383 if (check_offset)
384 offset = check_offset;
385 }
386 break;
387 case COMBIOS_POWERPLAY_INFO_TABLE: /* offset from mobile info */
388 check_offset =
389 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
390 if (check_offset) {
391 check_offset = RBIOS16(check_offset + 0x11);
392 if (check_offset)
393 offset = check_offset;
394 }
395 break;
396 case COMBIOS_GPIO_INFO_TABLE: /* offset from mobile info */
397 check_offset =
398 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
399 if (check_offset) {
400 check_offset = RBIOS16(check_offset + 0x13);
401 if (check_offset)
402 offset = check_offset;
403 }
404 break;
405 case COMBIOS_LCD_DDC_INFO_TABLE: /* offset from mobile info */
406 check_offset =
407 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
408 if (check_offset) {
409 check_offset = RBIOS16(check_offset + 0x15);
410 if (check_offset)
411 offset = check_offset;
412 }
413 break;
414 case COMBIOS_TMDS_POWER_TABLE: /* offset from mobile info */
415 check_offset =
416 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
417 if (check_offset) {
418 check_offset = RBIOS16(check_offset + 0x17);
419 if (check_offset)
420 offset = check_offset;
421 }
422 break;
423 case COMBIOS_TMDS_POWER_ON_TABLE: /* offset from tmds power */
424 check_offset =
425 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
426 if (check_offset) {
427 check_offset = RBIOS16(check_offset + 0x2);
428 if (check_offset)
429 offset = check_offset;
430 }
431 break;
432 case COMBIOS_TMDS_POWER_OFF_TABLE: /* offset from tmds power */
433 check_offset =
434 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
435 if (check_offset) {
436 check_offset = RBIOS16(check_offset + 0x4);
437 if (check_offset)
438 offset = check_offset;
439 }
440 break;
441 default:
442 break;
443 }
444
445 return offset;
446
447}
448
3c537889
AD		 449bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev)
450{
451 int edid_info;
452 struct edid *edid;
453 edid_info = combios_get_table_offset(rdev->ddev, COMBIOS_HARDCODED_EDID_TABLE);
454 if (!edid_info)
455 return false;
456
457 edid = kmalloc(EDID_LENGTH * (DRM_MAX_EDID_EXT_NUM + 1),
458 GFP_KERNEL);
459 if (edid == NULL)
460 return false;
461
462 memcpy((unsigned char *)edid,
463 (unsigned char *)(rdev->bios + edid_info), EDID_LENGTH);
464
465 if (!drm_edid_is_valid(edid)) {
466 kfree(edid);
467 return false;
468 }
469
470 rdev->mode_info.bios_hardcoded_edid = edid;
471 return true;
472}
473
474struct edid *
475radeon_combios_get_hardcoded_edid(struct radeon_device *rdev)
476{
477 if (rdev->mode_info.bios_hardcoded_edid)
478 return rdev->mode_info.bios_hardcoded_edid;
479 return NULL;
480}
481
6a93cb25
AD		 482static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev,
483 int ddc_line)
771fe6b9
JG		 484{
485 struct radeon_i2c_bus_rec i2c;
486
6a93cb25
AD		 487 if (ddc_line == RADEON_GPIOPAD_MASK) {
488 i2c.mask_clk_reg = RADEON_GPIOPAD_MASK;
489 i2c.mask_data_reg = RADEON_GPIOPAD_MASK;
490 i2c.a_clk_reg = RADEON_GPIOPAD_A;
491 i2c.a_data_reg = RADEON_GPIOPAD_A;
492 i2c.en_clk_reg = RADEON_GPIOPAD_EN;
493 i2c.en_data_reg = RADEON_GPIOPAD_EN;
494 i2c.y_clk_reg = RADEON_GPIOPAD_Y;
495 i2c.y_data_reg = RADEON_GPIOPAD_Y;
496 } else if (ddc_line == RADEON_MDGPIO_MASK) {
497 i2c.mask_clk_reg = RADEON_MDGPIO_MASK;
498 i2c.mask_data_reg = RADEON_MDGPIO_MASK;
499 i2c.a_clk_reg = RADEON_MDGPIO_A;
500 i2c.a_data_reg = RADEON_MDGPIO_A;
501 i2c.en_clk_reg = RADEON_MDGPIO_EN;
502 i2c.en_data_reg = RADEON_MDGPIO_EN;
503 i2c.y_clk_reg = RADEON_MDGPIO_Y;
504 i2c.y_data_reg = RADEON_MDGPIO_Y;
771fe6b9 505 } else {
6a93cb25
AD		 506 i2c.mask_clk_mask = RADEON_GPIO_EN_1;
507 i2c.mask_data_mask = RADEON_GPIO_EN_0;
508 i2c.a_clk_mask = RADEON_GPIO_A_1;
509 i2c.a_data_mask = RADEON_GPIO_A_0;
510 i2c.en_clk_mask = RADEON_GPIO_EN_1;
511 i2c.en_data_mask = RADEON_GPIO_EN_0;
512 i2c.y_clk_mask = RADEON_GPIO_Y_1;
513 i2c.y_data_mask = RADEON_GPIO_Y_0;
514
771fe6b9
JG		 515 i2c.mask_clk_reg = ddc_line;
516 i2c.mask_data_reg = ddc_line;
517 i2c.a_clk_reg = ddc_line;
518 i2c.a_data_reg = ddc_line;
9b9fe724
AD		 519 i2c.en_clk_reg = ddc_line;
520 i2c.en_data_reg = ddc_line;
521 i2c.y_clk_reg = ddc_line;
522 i2c.y_data_reg = ddc_line;
771fe6b9
JG		 523 }
524
40bacf16
AD		 525 switch (rdev->family) {
526 case CHIP_R100:
527 case CHIP_RV100:
528 case CHIP_RS100:
529 case CHIP_RV200:
530 case CHIP_RS200:
531 case CHIP_RS300:
532 switch (ddc_line) {
533 case RADEON_GPIO_DVI_DDC:
b28ea411 534 i2c.hw_capable = true;
40bacf16
AD		 535 break;
536 default:
537 i2c.hw_capable = false;
538 break;
539 }
540 break;
541 case CHIP_R200:
542 switch (ddc_line) {
543 case RADEON_GPIO_DVI_DDC:
544 case RADEON_GPIO_MONID:
545 i2c.hw_capable = true;
546 break;
547 default:
548 i2c.hw_capable = false;
549 break;
550 }
551 break;
552 case CHIP_RV250:
553 case CHIP_RV280:
554 switch (ddc_line) {
555 case RADEON_GPIO_VGA_DDC:
556 case RADEON_GPIO_DVI_DDC:
557 case RADEON_GPIO_CRT2_DDC:
558 i2c.hw_capable = true;
559 break;
560 default:
561 i2c.hw_capable = false;
562 break;
563 }
564 break;
565 case CHIP_R300:
566 case CHIP_R350:
567 switch (ddc_line) {
568 case RADEON_GPIO_VGA_DDC:
569 case RADEON_GPIO_DVI_DDC:
570 i2c.hw_capable = true;
571 break;
572 default:
573 i2c.hw_capable = false;
574 break;
575 }
576 break;
577 case CHIP_RV350:
578 case CHIP_RV380:
579 case CHIP_RS400:
580 case CHIP_RS480:
6a93cb25
AD		 581 switch (ddc_line) {
582 case RADEON_GPIO_VGA_DDC:
583 case RADEON_GPIO_DVI_DDC:
584 i2c.hw_capable = true;
585 break;
586 case RADEON_GPIO_MONID:
587 /* hw i2c on RADEON_GPIO_MONID doesn't seem to work
588 * reliably on some pre-r4xx hardware; not sure why.
589 */
590 i2c.hw_capable = false;
591 break;
592 default:
593 i2c.hw_capable = false;
594 break;
595 }
40bacf16
AD		 596 break;
597 default:
598 i2c.hw_capable = false;
599 break;
6a93cb25
AD		 600 }
601 i2c.mm_i2c = false;
602 i2c.i2c_id = 0;
bcc1c2a1 603 i2c.hpd_id = 0;
6a93cb25 604
771fe6b9
JG		 605 if (ddc_line)
606 i2c.valid = true;
607 else
608 i2c.valid = false;
609
610 return i2c;
611}
612
613bool radeon_combios_get_clock_info(struct drm_device *dev)
614{
615 struct radeon_device *rdev = dev->dev_private;
616 uint16_t pll_info;
617 struct radeon_pll *p1pll = &rdev->clock.p1pll;
618 struct radeon_pll *p2pll = &rdev->clock.p2pll;
619 struct radeon_pll *spll = &rdev->clock.spll;
620 struct radeon_pll *mpll = &rdev->clock.mpll;
621 int8_t rev;
622 uint16_t sclk, mclk;
623
771fe6b9
JG		 624 pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE);
625 if (pll_info) {
626 rev = RBIOS8(pll_info);
627
628 /* pixel clocks */
629 p1pll->reference_freq = RBIOS16(pll_info + 0xe);
630 p1pll->reference_div = RBIOS16(pll_info + 0x10);
631 p1pll->pll_out_min = RBIOS32(pll_info + 0x12);
632 p1pll->pll_out_max = RBIOS32(pll_info + 0x16);
86cb2bbf
AD		 633 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
634 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
771fe6b9
JG		 635
636 if (rev > 9) {
637 p1pll->pll_in_min = RBIOS32(pll_info + 0x36);
638 p1pll->pll_in_max = RBIOS32(pll_info + 0x3a);
639 } else {
640 p1pll->pll_in_min = 40;
641 p1pll->pll_in_max = 500;
642 }
643 *p2pll = *p1pll;
644
645 /* system clock */
646 spll->reference_freq = RBIOS16(pll_info + 0x1a);
647 spll->reference_div = RBIOS16(pll_info + 0x1c);
648 spll->pll_out_min = RBIOS32(pll_info + 0x1e);
649 spll->pll_out_max = RBIOS32(pll_info + 0x22);
650
651 if (rev > 10) {
652 spll->pll_in_min = RBIOS32(pll_info + 0x48);
653 spll->pll_in_max = RBIOS32(pll_info + 0x4c);
654 } else {
655 /* ??? */
656 spll->pll_in_min = 40;
657 spll->pll_in_max = 500;
658 }
659
660 /* memory clock */
661 mpll->reference_freq = RBIOS16(pll_info + 0x26);
662 mpll->reference_div = RBIOS16(pll_info + 0x28);
663 mpll->pll_out_min = RBIOS32(pll_info + 0x2a);
664 mpll->pll_out_max = RBIOS32(pll_info + 0x2e);
665
666 if (rev > 10) {
667 mpll->pll_in_min = RBIOS32(pll_info + 0x5a);
668 mpll->pll_in_max = RBIOS32(pll_info + 0x5e);
669 } else {
670 /* ??? */
671 mpll->pll_in_min = 40;
672 mpll->pll_in_max = 500;
673 }
674
675 /* default sclk/mclk */
676 sclk = RBIOS16(pll_info + 0xa);
677 mclk = RBIOS16(pll_info + 0x8);
678 if (sclk == 0)
679 sclk = 200 * 100;
680 if (mclk == 0)
681 mclk = 200 * 100;
682
683 rdev->clock.default_sclk = sclk;
684 rdev->clock.default_mclk = mclk;
685
686 return true;
687 }
688 return false;
689}
690
06b6476d
AD		 691bool radeon_combios_sideport_present(struct radeon_device *rdev)
692{
693 struct drm_device *dev = rdev->ddev;
694 u16 igp_info;
695
696 igp_info = combios_get_table_offset(dev, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE);
697
698 if (igp_info) {
699 if (RBIOS16(igp_info + 0x4))
700 return true;
701 }
702 return false;
703}
704
246263cc
AD		 705static const uint32_t default_primarydac_adj[CHIP_LAST] = {
706 0x00000808, /* r100 */
707 0x00000808, /* rv100 */
708 0x00000808, /* rs100 */
709 0x00000808, /* rv200 */
710 0x00000808, /* rs200 */
711 0x00000808, /* r200 */
712 0x00000808, /* rv250 */
713 0x00000000, /* rs300 */
714 0x00000808, /* rv280 */
715 0x00000808, /* r300 */
716 0x00000808, /* r350 */
717 0x00000808, /* rv350 */
718 0x00000808, /* rv380 */
719 0x00000808, /* r420 */
720 0x00000808, /* r423 */
721 0x00000808, /* rv410 */
722 0x00000000, /* rs400 */
723 0x00000000, /* rs480 */
724};
725
726static void radeon_legacy_get_primary_dac_info_from_table(struct radeon_device *rdev,
727 struct radeon_encoder_primary_dac *p_dac)
728{
729 p_dac->ps2_pdac_adj = default_primarydac_adj[rdev->family];
730 return;
731}
732
771fe6b9
JG		 733struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct
734 radeon_encoder
735 *encoder)
736{
737 struct drm_device *dev = encoder->base.dev;
738 struct radeon_device *rdev = dev->dev_private;
739 uint16_t dac_info;
740 uint8_t rev, bg, dac;
741 struct radeon_encoder_primary_dac *p_dac = NULL;
246263cc 742 int found = 0;
771fe6b9 743
246263cc
AD		 744 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac),
745 GFP_KERNEL);
746
747 if (!p_dac)
771fe6b9
JG		 748 return NULL;
749
750 /* check CRT table */
751 dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
752 if (dac_info) {
771fe6b9
JG		 753 rev = RBIOS8(dac_info) & 0x3;
754 if (rev < 2) {
755 bg = RBIOS8(dac_info + 0x2) & 0xf;
756 dac = (RBIOS8(dac_info + 0x2) >> 4) & 0xf;
757 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
758 } else {
759 bg = RBIOS8(dac_info + 0x2) & 0xf;
760 dac = RBIOS8(dac_info + 0x3) & 0xf;
761 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
762 }
246263cc 763 found = 1;
771fe6b9
JG		 764 }
765
246263cc
AD		 766 if (!found) /* fallback to defaults */
767 radeon_legacy_get_primary_dac_info_from_table(rdev, p_dac);
768
771fe6b9
JG		 769 return p_dac;
770}
771
d79766fa
AD		 772enum radeon_tv_std
773radeon_combios_get_tv_info(struct radeon_device *rdev)
771fe6b9 774{
d79766fa 775 struct drm_device *dev = rdev->ddev;
771fe6b9
JG		 776 uint16_t tv_info;
777 enum radeon_tv_std tv_std = TV_STD_NTSC;
778
779 tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
780 if (tv_info) {
781 if (RBIOS8(tv_info + 6) == 'T') {
782 switch (RBIOS8(tv_info + 7) & 0xf) {
783 case 1:
784 tv_std = TV_STD_NTSC;
785 DRM_INFO("Default TV standard: NTSC\n");
786 break;
787 case 2:
788 tv_std = TV_STD_PAL;
789 DRM_INFO("Default TV standard: PAL\n");
790 break;
791 case 3:
792 tv_std = TV_STD_PAL_M;
793 DRM_INFO("Default TV standard: PAL-M\n");
794 break;
795 case 4:
796 tv_std = TV_STD_PAL_60;
797 DRM_INFO("Default TV standard: PAL-60\n");
798 break;
799 case 5:
800 tv_std = TV_STD_NTSC_J;
801 DRM_INFO("Default TV standard: NTSC-J\n");
802 break;
803 case 6:
804 tv_std = TV_STD_SCART_PAL;
805 DRM_INFO("Default TV standard: SCART-PAL\n");
806 break;
807 default:
808 tv_std = TV_STD_NTSC;
809 DRM_INFO
810 ("Unknown TV standard; defaulting to NTSC\n");
811 break;
812 }
813
814 switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) {
815 case 0:
816 DRM_INFO("29.498928713 MHz TV ref clk\n");
817 break;
818 case 1:
819 DRM_INFO("28.636360000 MHz TV ref clk\n");
820 break;
821 case 2:
822 DRM_INFO("14.318180000 MHz TV ref clk\n");
823 break;
824 case 3:
825 DRM_INFO("27.000000000 MHz TV ref clk\n");
826 break;
827 default:
828 break;
829 }
830 }
831 }
832 return tv_std;
833}
834
835static const uint32_t default_tvdac_adj[CHIP_LAST] = {
836 0x00000000, /* r100 */
837 0x00280000, /* rv100 */
838 0x00000000, /* rs100 */
839 0x00880000, /* rv200 */
840 0x00000000, /* rs200 */
841 0x00000000, /* r200 */
842 0x00770000, /* rv250 */
843 0x00290000, /* rs300 */
844 0x00560000, /* rv280 */
845 0x00780000, /* r300 */
846 0x00770000, /* r350 */
847 0x00780000, /* rv350 */
848 0x00780000, /* rv380 */
849 0x01080000, /* r420 */
850 0x01080000, /* r423 */
851 0x01080000, /* rv410 */
852 0x00780000, /* rs400 */
853 0x00780000, /* rs480 */
854};
855
6a719e05
DA		 856static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev,
857 struct radeon_encoder_tv_dac *tv_dac)
771fe6b9 858{
771fe6b9
JG		 859 tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family];
860 if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250))
861 tv_dac->ps2_tvdac_adj = 0x00880000;
862 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
863 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
6a719e05 864 return;
771fe6b9
JG		 865}
866
867struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
868 radeon_encoder
869 *encoder)
870{
871 struct drm_device *dev = encoder->base.dev;
872 struct radeon_device *rdev = dev->dev_private;
873 uint16_t dac_info;
874 uint8_t rev, bg, dac;
875 struct radeon_encoder_tv_dac *tv_dac = NULL;
6a719e05
DA		 876 int found = 0;
877
878 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
879 if (!tv_dac)
880 return NULL;
771fe6b9 881
771fe6b9
JG		 882 /* first check TV table */
883 dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
884 if (dac_info) {
771fe6b9
JG		 885 rev = RBIOS8(dac_info + 0x3);
886 if (rev > 4) {
887 bg = RBIOS8(dac_info + 0xc) & 0xf;
888 dac = RBIOS8(dac_info + 0xd) & 0xf;
889 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
890
891 bg = RBIOS8(dac_info + 0xe) & 0xf;
892 dac = RBIOS8(dac_info + 0xf) & 0xf;
893 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
894
895 bg = RBIOS8(dac_info + 0x10) & 0xf;
896 dac = RBIOS8(dac_info + 0x11) & 0xf;
897 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
6a719e05 898 found = 1;
771fe6b9
JG		 899 } else if (rev > 1) {
900 bg = RBIOS8(dac_info + 0xc) & 0xf;
901 dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf;
902 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
903
904 bg = RBIOS8(dac_info + 0xd) & 0xf;
905 dac = (RBIOS8(dac_info + 0xd) >> 4) & 0xf;
906 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
907
908 bg = RBIOS8(dac_info + 0xe) & 0xf;
909 dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf;
910 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
6a719e05 911 found = 1;
771fe6b9 912 }
d79766fa 913 tv_dac->tv_std = radeon_combios_get_tv_info(rdev);
6a719e05
DA		 914 }
915 if (!found) {
771fe6b9
JG		 916 /* then check CRT table */
917 dac_info =
918 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
919 if (dac_info) {
771fe6b9
JG		 920 rev = RBIOS8(dac_info) & 0x3;
921 if (rev < 2) {
922 bg = RBIOS8(dac_info + 0x3) & 0xf;
923 dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf;
924 tv_dac->ps2_tvdac_adj =
925 (bg << 16) | (dac << 20);
926 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
927 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
6a719e05 928 found = 1;
771fe6b9
JG		 929 } else {
930 bg = RBIOS8(dac_info + 0x4) & 0xf;
931 dac = RBIOS8(dac_info + 0x5) & 0xf;
932 tv_dac->ps2_tvdac_adj =
933 (bg << 16) | (dac << 20);
934 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
935 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
6a719e05 936 found = 1;
771fe6b9 937 }
6fe7ac3f
AD		 938 } else {
939 DRM_INFO("No TV DAC info found in BIOS\n");
771fe6b9
JG		 940 }
941 }
942
6a719e05
DA		 943 if (!found) /* fallback to defaults */
944 radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac);
945
771fe6b9
JG		 946 return tv_dac;
947}
948
949static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct
950 radeon_device
951 *rdev)
952{
953 struct radeon_encoder_lvds *lvds = NULL;
954 uint32_t fp_vert_stretch, fp_horz_stretch;
955 uint32_t ppll_div_sel, ppll_val;
8b5c7444 956 uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
771fe6b9
JG		 957
958 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
959
960 if (!lvds)
961 return NULL;
962
963 fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH);
964 fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH);
965
8b5c7444
MD		 966 /* These should be fail-safe defaults, fingers crossed */
967 lvds->panel_pwr_delay = 200;
968 lvds->panel_vcc_delay = 2000;
969
970 lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
971 lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf;
972 lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf;
973
771fe6b9 974 if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE)
de2103e4 975 lvds->native_mode.vdisplay =
771fe6b9
JG		 976 ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >>
977 RADEON_VERT_PANEL_SHIFT) + 1;
978 else
de2103e4 979 lvds->native_mode.vdisplay =
771fe6b9
JG		 980 (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1;
981
982 if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE)
de2103e4 983 lvds->native_mode.hdisplay =
771fe6b9
JG		 984 (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >>
985 RADEON_HORZ_PANEL_SHIFT) + 1) * 8;
986 else
de2103e4 987 lvds->native_mode.hdisplay =
771fe6b9
JG		 988 ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8;
989
de2103e4
AD		 990 if ((lvds->native_mode.hdisplay < 640) ||
991 (lvds->native_mode.vdisplay < 480)) {
992 lvds->native_mode.hdisplay = 640;
993 lvds->native_mode.vdisplay = 480;
771fe6b9
JG		 994 }
995
996 ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3;
997 ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel);
998 if ((ppll_val & 0x000707ff) == 0x1bb)
999 lvds->use_bios_dividers = false;
1000 else {
1001 lvds->panel_ref_divider =
1002 RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
1003 lvds->panel_post_divider = (ppll_val >> 16) & 0x7;
1004 lvds->panel_fb_divider = ppll_val & 0x7ff;
1005
1006 if ((lvds->panel_ref_divider != 0) &&
1007 (lvds->panel_fb_divider > 3))
1008 lvds->use_bios_dividers = true;
1009 }
1010 lvds->panel_vcc_delay = 200;
1011
1012 DRM_INFO("Panel info derived from registers\n");
de2103e4
AD		 1013 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1014 lvds->native_mode.vdisplay);
771fe6b9
JG		 1015
1016 return lvds;
1017}
1018
1019struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
1020 *encoder)
1021{
1022 struct drm_device *dev = encoder->base.dev;
1023 struct radeon_device *rdev = dev->dev_private;
1024 uint16_t lcd_info;
1025 uint32_t panel_setup;
1026 char stmp[30];
1027 int tmp, i;
1028 struct radeon_encoder_lvds *lvds = NULL;
1029
771fe6b9
JG		 1030 lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
1031
1032 if (lcd_info) {
1033 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
1034
1035 if (!lvds)
1036 return NULL;
1037
1038 for (i = 0; i < 24; i++)
1039 stmp[i] = RBIOS8(lcd_info + i + 1);
1040 stmp[24] = 0;
1041
1042 DRM_INFO("Panel ID String: %s\n", stmp);
1043
de2103e4
AD		 1044 lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19);
1045 lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b);
771fe6b9 1046
de2103e4
AD		 1047 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1048 lvds->native_mode.vdisplay);
771fe6b9
JG		 1049
1050 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c);
94cf6434 1051 lvds->panel_vcc_delay = min_t(u16, lvds->panel_vcc_delay, 2000);
771fe6b9
JG		 1052
1053 lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24);
1054 lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf;
1055 lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf;
1056
1057 lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e);
1058 lvds->panel_post_divider = RBIOS8(lcd_info + 0x30);
1059 lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31);
1060 if ((lvds->panel_ref_divider != 0) &&
1061 (lvds->panel_fb_divider > 3))
1062 lvds->use_bios_dividers = true;
1063
1064 panel_setup = RBIOS32(lcd_info + 0x39);
1065 lvds->lvds_gen_cntl = 0xff00;
1066 if (panel_setup & 0x1)
1067 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT;
1068
1069 if ((panel_setup >> 4) & 0x1)
1070 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE;
1071
1072 switch ((panel_setup >> 8) & 0x7) {
1073 case 0:
1074 lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM;
1075 break;
1076 case 1:
1077 lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY;
1078 break;
1079 case 2:
1080 lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY;
1081 break;
1082 default:
1083 break;
1084 }
1085
1086 if ((panel_setup >> 16) & 0x1)
1087 lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW;
1088
1089 if ((panel_setup >> 17) & 0x1)
1090 lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW;
1091
1092 if ((panel_setup >> 18) & 0x1)
1093 lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW;
1094
1095 if ((panel_setup >> 23) & 0x1)
1096 lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL;
1097
1098 lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000);
1099
1100 for (i = 0; i < 32; i++) {
1101 tmp = RBIOS16(lcd_info + 64 + i * 2);
1102 if (tmp == 0)
1103 break;
1104
de2103e4 1105 if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) &&
771fe6b9 1106 (RBIOS16(tmp + 2) ==
de2103e4
AD		 1107 lvds->native_mode.vdisplay)) {
1108 lvds->native_mode.htotal = RBIOS16(tmp + 17) * 8;
1109 lvds->native_mode.hsync_start = RBIOS16(tmp + 21) * 8;
1110 lvds->native_mode.hsync_end = (RBIOS8(tmp + 23) +
1111 RBIOS16(tmp + 21)) * 8;
1112
1113 lvds->native_mode.vtotal = RBIOS16(tmp + 24);
1114 lvds->native_mode.vsync_start = RBIOS16(tmp + 28) & 0x7ff;
1115 lvds->native_mode.vsync_end =
1116 ((RBIOS16(tmp + 28) & 0xf800) >> 11) +
1117 (RBIOS16(tmp + 28) & 0x7ff);
1118
1119 lvds->native_mode.clock = RBIOS16(tmp + 9) * 10;
771fe6b9 1120 lvds->native_mode.flags = 0;
de2103e4
AD		 1121 /* set crtc values */
1122 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1123
771fe6b9
JG		 1124 }
1125 }
6fe7ac3f 1126 } else {
771fe6b9 1127 DRM_INFO("No panel info found in BIOS\n");
8dfaa8a7 1128 lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
6fe7ac3f 1129 }
03047cdf 1130
8dfaa8a7
MD		 1131 if (lvds)
1132 encoder->native_mode = lvds->native_mode;
771fe6b9
JG		 1133 return lvds;
1134}
1135
1136static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = {
1137 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R100 */
1138 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV100 */
1139 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS100 */
1140 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV200 */
1141 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RS200 */
1142 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R200 */
1143 {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}}, /* CHIP_RV250 */
1144 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS300 */
1145 {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}}, /* CHIP_RV280 */
1146 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R300 */
1147 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R350 */
1148 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV350 */
1149 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV380 */
1150 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R420 */
1151 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R423 */
1152 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RV410 */
fcec570b
AD		 1153 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS400 */
1154 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS480 */
771fe6b9
JG		 1155};
1156
445282db
DA		 1157bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
1158 struct radeon_encoder_int_tmds *tmds)
771fe6b9 1159{
445282db
DA		 1160 struct drm_device *dev = encoder->base.dev;
1161 struct radeon_device *rdev = dev->dev_private;
771fe6b9 1162 int i;
771fe6b9
JG		 1163
1164 for (i = 0; i < 4; i++) {
1165 tmds->tmds_pll[i].value =
445282db 1166 default_tmds_pll[rdev->family][i].value;
771fe6b9
JG		 1167 tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq;
1168 }
1169
445282db 1170 return true;
771fe6b9
JG		 1171}
1172
445282db
DA		 1173bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
1174 struct radeon_encoder_int_tmds *tmds)
771fe6b9
JG		 1175{
1176 struct drm_device *dev = encoder->base.dev;
1177 struct radeon_device *rdev = dev->dev_private;
1178 uint16_t tmds_info;
1179 int i, n;
1180 uint8_t ver;
771fe6b9 1181
771fe6b9
JG		 1182 tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
1183
1184 if (tmds_info) {
771fe6b9
JG		 1185 ver = RBIOS8(tmds_info);
1186 DRM_INFO("DFP table revision: %d\n", ver);
1187 if (ver == 3) {
1188 n = RBIOS8(tmds_info + 5) + 1;
1189 if (n > 4)
1190 n = 4;
1191 for (i = 0; i < n; i++) {
1192 tmds->tmds_pll[i].value =
1193 RBIOS32(tmds_info + i * 10 + 0x08);
1194 tmds->tmds_pll[i].freq =
1195 RBIOS16(tmds_info + i * 10 + 0x10);
1196 DRM_DEBUG("TMDS PLL From COMBIOS %u %x\n",
1197 tmds->tmds_pll[i].freq,
1198 tmds->tmds_pll[i].value);
1199 }
1200 } else if (ver == 4) {
1201 int stride = 0;
1202 n = RBIOS8(tmds_info + 5) + 1;
1203 if (n > 4)
1204 n = 4;
1205 for (i = 0; i < n; i++) {
1206 tmds->tmds_pll[i].value =
1207 RBIOS32(tmds_info + stride + 0x08);
1208 tmds->tmds_pll[i].freq =
1209 RBIOS16(tmds_info + stride + 0x10);
1210 if (i == 0)
1211 stride += 10;
1212 else
1213 stride += 6;
1214 DRM_DEBUG("TMDS PLL From COMBIOS %u %x\n",
1215 tmds->tmds_pll[i].freq,
1216 tmds->tmds_pll[i].value);
1217 }
1218 }
fcec570b 1219 } else {
771fe6b9 1220 DRM_INFO("No TMDS info found in BIOS\n");
fcec570b
AD		 1221 return false;
1222 }
445282db
DA		 1223 return true;
1224}
1225
fcec570b
AD		 1226bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
1227 struct radeon_encoder_ext_tmds *tmds)
445282db 1228{
fcec570b
AD		 1229 struct drm_device *dev = encoder->base.dev;
1230 struct radeon_device *rdev = dev->dev_private;
1231 struct radeon_i2c_bus_rec i2c_bus;
445282db 1232
fcec570b 1233 /* default for macs */
6a93cb25 1234 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
fcec570b 1235 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
445282db 1236
fcec570b
AD		 1237 /* XXX some macs have duallink chips */
1238 switch (rdev->mode_info.connector_table) {
1239 case CT_POWERBOOK_EXTERNAL:
1240 case CT_MINI_EXTERNAL:
1241 default:
1242 tmds->dvo_chip = DVO_SIL164;
1243 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1244 break;
1245 }
445282db 1246
fcec570b 1247 return true;
771fe6b9
JG		 1248}
1249
fcec570b
AD		 1250bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
1251 struct radeon_encoder_ext_tmds *tmds)
771fe6b9
JG		 1252{
1253 struct drm_device *dev = encoder->base.dev;
1254 struct radeon_device *rdev = dev->dev_private;
fcec570b
AD		 1255 uint16_t offset;
1256 uint8_t ver, id, blocks, clk, data;
1257 int i;
1258 enum radeon_combios_ddc gpio;
1259 struct radeon_i2c_bus_rec i2c_bus;
771fe6b9 1260
fcec570b
AD		 1261 tmds->i2c_bus = NULL;
1262 if (rdev->flags & RADEON_IS_IGP) {
1263 offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE);
1264 if (offset) {
1265 ver = RBIOS8(offset);
1266 DRM_INFO("GPIO Table revision: %d\n", ver);
1267 blocks = RBIOS8(offset + 2);
1268 for (i = 0; i < blocks; i++) {
1269 id = RBIOS8(offset + 3 + (i * 5) + 0);
1270 if (id == 136) {
1271 clk = RBIOS8(offset + 3 + (i * 5) + 3);
1272 data = RBIOS8(offset + 3 + (i * 5) + 4);
1273 i2c_bus.valid = true;
1274 i2c_bus.mask_clk_mask = (1 << clk);
1275 i2c_bus.mask_data_mask = (1 << data);
1276 i2c_bus.a_clk_mask = (1 << clk);
1277 i2c_bus.a_data_mask = (1 << data);
1278 i2c_bus.en_clk_mask = (1 << clk);
1279 i2c_bus.en_data_mask = (1 << data);
1280 i2c_bus.y_clk_mask = (1 << clk);
1281 i2c_bus.y_data_mask = (1 << data);
1282 i2c_bus.mask_clk_reg = RADEON_GPIOPAD_MASK;
1283 i2c_bus.mask_data_reg = RADEON_GPIOPAD_MASK;
1284 i2c_bus.a_clk_reg = RADEON_GPIOPAD_A;
1285 i2c_bus.a_data_reg = RADEON_GPIOPAD_A;
1286 i2c_bus.en_clk_reg = RADEON_GPIOPAD_EN;
1287 i2c_bus.en_data_reg = RADEON_GPIOPAD_EN;
1288 i2c_bus.y_clk_reg = RADEON_GPIOPAD_Y;
1289 i2c_bus.y_data_reg = RADEON_GPIOPAD_Y;
1290 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1291 tmds->dvo_chip = DVO_SIL164;
1292 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1293 break;
1294 }
1295 }
1296 }
1297 } else {
1298 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1299 if (offset) {
1300 ver = RBIOS8(offset);
1301 DRM_INFO("External TMDS Table revision: %d\n", ver);
1302 tmds->slave_addr = RBIOS8(offset + 4 + 2);
1303 tmds->slave_addr >>= 1; /* 7 bit addressing */
1304 gpio = RBIOS8(offset + 4 + 3);
1305 switch (gpio) {
1306 case DDC_MONID:
6a93cb25 1307 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
fcec570b
AD		 1308 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1309 break;
1310 case DDC_DVI:
6a93cb25 1311 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
fcec570b
AD		 1312 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1313 break;
1314 case DDC_VGA:
6a93cb25 1315 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
fcec570b
AD		 1316 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1317 break;
1318 case DDC_CRT2:
1319 /* R3xx+ chips don't have GPIO_CRT2_DDC gpio pad */
1320 if (rdev->family >= CHIP_R300)
6a93cb25 1321 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
fcec570b 1322 else
6a93cb25 1323 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
fcec570b
AD		 1324 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1325 break;
1326 case DDC_LCD: /* MM i2c */
40bacf16
AD		 1327 i2c_bus.valid = true;
1328 i2c_bus.hw_capable = true;
1329 i2c_bus.mm_i2c = true;
1330 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
fcec570b
AD		 1331 break;
1332 default:
1333 DRM_ERROR("Unsupported gpio %d\n", gpio);
1334 break;
1335 }
1336 }
771fe6b9 1337 }
fcec570b
AD		 1338
1339 if (!tmds->i2c_bus) {
1340 DRM_INFO("No valid Ext TMDS info found in BIOS\n");
1341 return false;
1342 }
1343
1344 return true;
771fe6b9
JG		 1345}
1346
1347bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1348{
1349 struct radeon_device *rdev = dev->dev_private;
1350 struct radeon_i2c_bus_rec ddc_i2c;
eed45b30 1351 struct radeon_hpd hpd;
771fe6b9
JG		 1352
1353 rdev->mode_info.connector_table = radeon_connector_table;
1354 if (rdev->mode_info.connector_table == CT_NONE) {
1355#ifdef CONFIG_PPC_PMAC
71a157e8 1356 if (of_machine_is_compatible("PowerBook3,3")) {
771fe6b9
JG		 1357 /* powerbook with VGA */
1358 rdev->mode_info.connector_table = CT_POWERBOOK_VGA;
71a157e8
GL		 1359 } else if (of_machine_is_compatible("PowerBook3,4") ||
1360 of_machine_is_compatible("PowerBook3,5")) {
771fe6b9
JG		 1361 /* powerbook with internal tmds */
1362 rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL;
71a157e8
GL		 1363 } else if (of_machine_is_compatible("PowerBook5,1") ||
1364 of_machine_is_compatible("PowerBook5,2") ||
1365 of_machine_is_compatible("PowerBook5,3") ||
1366 of_machine_is_compatible("PowerBook5,4") ||
1367 of_machine_is_compatible("PowerBook5,5")) {
771fe6b9
JG		 1368 /* powerbook with external single link tmds (sil164) */
1369 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
71a157e8 1370 } else if (of_machine_is_compatible("PowerBook5,6")) {
771fe6b9
JG		 1371 /* powerbook with external dual or single link tmds */
1372 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
71a157e8
GL		 1373 } else if (of_machine_is_compatible("PowerBook5,7") ||
1374 of_machine_is_compatible("PowerBook5,8") ||
1375 of_machine_is_compatible("PowerBook5,9")) {
771fe6b9
JG		 1376 /* PowerBook6,2 ? */
1377 /* powerbook with external dual link tmds (sil1178?) */
1378 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
71a157e8
GL		 1379 } else if (of_machine_is_compatible("PowerBook4,1") ||
1380 of_machine_is_compatible("PowerBook4,2") ||
1381 of_machine_is_compatible("PowerBook4,3") ||
1382 of_machine_is_compatible("PowerBook6,3") ||
1383 of_machine_is_compatible("PowerBook6,5") ||
1384 of_machine_is_compatible("PowerBook6,7")) {
771fe6b9
JG		 1385 /* ibook */
1386 rdev->mode_info.connector_table = CT_IBOOK;
71a157e8 1387 } else if (of_machine_is_compatible("PowerMac4,4")) {
771fe6b9
JG		 1388 /* emac */
1389 rdev->mode_info.connector_table = CT_EMAC;
71a157e8 1390 } else if (of_machine_is_compatible("PowerMac10,1")) {
771fe6b9
JG		 1391 /* mini with internal tmds */
1392 rdev->mode_info.connector_table = CT_MINI_INTERNAL;
71a157e8 1393 } else if (of_machine_is_compatible("PowerMac10,2")) {
771fe6b9
JG		 1394 /* mini with external tmds */
1395 rdev->mode_info.connector_table = CT_MINI_EXTERNAL;
71a157e8 1396 } else if (of_machine_is_compatible("PowerMac12,1")) {
771fe6b9
JG		 1397 /* PowerMac8,1 ? */
1398 /* imac g5 isight */
1399 rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT;
1400 } else
1401#endif /* CONFIG_PPC_PMAC */
1402 rdev->mode_info.connector_table = CT_GENERIC;
1403 }
1404
1405 switch (rdev->mode_info.connector_table) {
1406 case CT_GENERIC:
1407 DRM_INFO("Connector Table: %d (generic)\n",
1408 rdev->mode_info.connector_table);
1409 /* these are the most common settings */
1410 if (rdev->flags & RADEON_SINGLE_CRTC) {
1411 /* VGA - primary dac */
6a93cb25 1412 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
eed45b30 1413 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1414 radeon_add_legacy_encoder(dev,
1415 radeon_get_encoder_id(dev,
1416 ATOM_DEVICE_CRT1_SUPPORT,
1417 1),
1418 ATOM_DEVICE_CRT1_SUPPORT);
1419 radeon_add_legacy_connector(dev, 0,
1420 ATOM_DEVICE_CRT1_SUPPORT,
1421 DRM_MODE_CONNECTOR_VGA,
b75fad06 1422 &ddc_i2c,
eed45b30
AD		 1423 CONNECTOR_OBJECT_ID_VGA,
1424 &hpd);
771fe6b9
JG		 1425 } else if (rdev->flags & RADEON_IS_MOBILITY) {
1426 /* LVDS */
6a93cb25 1427 ddc_i2c = combios_setup_i2c_bus(rdev, 0);
eed45b30 1428 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1429 radeon_add_legacy_encoder(dev,
1430 radeon_get_encoder_id(dev,
1431 ATOM_DEVICE_LCD1_SUPPORT,
1432 0),
1433 ATOM_DEVICE_LCD1_SUPPORT);
1434 radeon_add_legacy_connector(dev, 0,
1435 ATOM_DEVICE_LCD1_SUPPORT,
1436 DRM_MODE_CONNECTOR_LVDS,
b75fad06 1437 &ddc_i2c,
eed45b30
AD		 1438 CONNECTOR_OBJECT_ID_LVDS,
1439 &hpd);
771fe6b9
JG		 1440
1441 /* VGA - primary dac */
6a93cb25 1442 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
eed45b30 1443 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1444 radeon_add_legacy_encoder(dev,
1445 radeon_get_encoder_id(dev,
1446 ATOM_DEVICE_CRT1_SUPPORT,
1447 1),
1448 ATOM_DEVICE_CRT1_SUPPORT);
1449 radeon_add_legacy_connector(dev, 1,
1450 ATOM_DEVICE_CRT1_SUPPORT,
1451 DRM_MODE_CONNECTOR_VGA,
b75fad06 1452 &ddc_i2c,
eed45b30
AD		 1453 CONNECTOR_OBJECT_ID_VGA,
1454 &hpd);
771fe6b9
JG		 1455 } else {
1456 /* DVI-I - tv dac, int tmds */
6a93cb25 1457 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
eed45b30 1458 hpd.hpd = RADEON_HPD_1;
771fe6b9
JG		 1459 radeon_add_legacy_encoder(dev,
1460 radeon_get_encoder_id(dev,
1461 ATOM_DEVICE_DFP1_SUPPORT,
1462 0),
1463 ATOM_DEVICE_DFP1_SUPPORT);
1464 radeon_add_legacy_encoder(dev,
1465 radeon_get_encoder_id(dev,
1466 ATOM_DEVICE_CRT2_SUPPORT,
1467 2),
1468 ATOM_DEVICE_CRT2_SUPPORT);
1469 radeon_add_legacy_connector(dev, 0,
1470 ATOM_DEVICE_DFP1_SUPPORT |
1471 ATOM_DEVICE_CRT2_SUPPORT,
1472 DRM_MODE_CONNECTOR_DVII,
b75fad06 1473 &ddc_i2c,
eed45b30
AD		 1474 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1475 &hpd);
771fe6b9
JG		 1476
1477 /* VGA - primary dac */
6a93cb25 1478 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
eed45b30 1479 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1480 radeon_add_legacy_encoder(dev,
1481 radeon_get_encoder_id(dev,
1482 ATOM_DEVICE_CRT1_SUPPORT,
1483 1),
1484 ATOM_DEVICE_CRT1_SUPPORT);
1485 radeon_add_legacy_connector(dev, 1,
1486 ATOM_DEVICE_CRT1_SUPPORT,
1487 DRM_MODE_CONNECTOR_VGA,
b75fad06 1488 &ddc_i2c,
eed45b30
AD		 1489 CONNECTOR_OBJECT_ID_VGA,
1490 &hpd);
771fe6b9
JG		 1491 }
1492
1493 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
1494 /* TV - tv dac */
eed45b30
AD		 1495 ddc_i2c.valid = false;
1496 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1497 radeon_add_legacy_encoder(dev,
1498 radeon_get_encoder_id(dev,
1499 ATOM_DEVICE_TV1_SUPPORT,
1500 2),
1501 ATOM_DEVICE_TV1_SUPPORT);
1502 radeon_add_legacy_connector(dev, 2,
1503 ATOM_DEVICE_TV1_SUPPORT,
1504 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1505 &ddc_i2c,
eed45b30
AD		 1506 CONNECTOR_OBJECT_ID_SVIDEO,
1507 &hpd);
771fe6b9
JG		 1508 }
1509 break;
1510 case CT_IBOOK:
1511 DRM_INFO("Connector Table: %d (ibook)\n",
1512 rdev->mode_info.connector_table);
1513 /* LVDS */
6a93cb25 1514 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
eed45b30 1515 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1516 radeon_add_legacy_encoder(dev,
1517 radeon_get_encoder_id(dev,
1518 ATOM_DEVICE_LCD1_SUPPORT,
1519 0),
1520 ATOM_DEVICE_LCD1_SUPPORT);
1521 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
b75fad06 1522 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
eed45b30
AD		 1523 CONNECTOR_OBJECT_ID_LVDS,
1524 &hpd);
771fe6b9 1525 /* VGA - TV DAC */
6a93cb25 1526 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
eed45b30 1527 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1528 radeon_add_legacy_encoder(dev,
1529 radeon_get_encoder_id(dev,
1530 ATOM_DEVICE_CRT2_SUPPORT,
1531 2),
1532 ATOM_DEVICE_CRT2_SUPPORT);
1533 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
b75fad06 1534 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
eed45b30
AD		 1535 CONNECTOR_OBJECT_ID_VGA,
1536 &hpd);
771fe6b9 1537 /* TV - TV DAC */
eed45b30
AD		 1538 ddc_i2c.valid = false;
1539 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1540 radeon_add_legacy_encoder(dev,
1541 radeon_get_encoder_id(dev,
1542 ATOM_DEVICE_TV1_SUPPORT,
1543 2),
1544 ATOM_DEVICE_TV1_SUPPORT);
1545 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1546 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1547 &ddc_i2c,
eed45b30
AD		 1548 CONNECTOR_OBJECT_ID_SVIDEO,
1549 &hpd);
771fe6b9
JG		 1550 break;
1551 case CT_POWERBOOK_EXTERNAL:
1552 DRM_INFO("Connector Table: %d (powerbook external tmds)\n",
1553 rdev->mode_info.connector_table);
1554 /* LVDS */
6a93cb25 1555 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
eed45b30 1556 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1557 radeon_add_legacy_encoder(dev,
1558 radeon_get_encoder_id(dev,
1559 ATOM_DEVICE_LCD1_SUPPORT,
1560 0),
1561 ATOM_DEVICE_LCD1_SUPPORT);
1562 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
b75fad06 1563 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
eed45b30
AD		 1564 CONNECTOR_OBJECT_ID_LVDS,
1565 &hpd);
771fe6b9 1566 /* DVI-I - primary dac, ext tmds */
6a93cb25 1567 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
eed45b30 1568 hpd.hpd = RADEON_HPD_2; /* ??? */
771fe6b9
JG		 1569 radeon_add_legacy_encoder(dev,
1570 radeon_get_encoder_id(dev,
1571 ATOM_DEVICE_DFP2_SUPPORT,
1572 0),
1573 ATOM_DEVICE_DFP2_SUPPORT);
1574 radeon_add_legacy_encoder(dev,
1575 radeon_get_encoder_id(dev,
1576 ATOM_DEVICE_CRT1_SUPPORT,
1577 1),
1578 ATOM_DEVICE_CRT1_SUPPORT);
b75fad06 1579 /* XXX some are SL */
771fe6b9
JG		 1580 radeon_add_legacy_connector(dev, 1,
1581 ATOM_DEVICE_DFP2_SUPPORT |
1582 ATOM_DEVICE_CRT1_SUPPORT,
b75fad06 1583 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
eed45b30
AD		 1584 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
1585 &hpd);
771fe6b9 1586 /* TV - TV DAC */
eed45b30
AD		 1587 ddc_i2c.valid = false;
1588 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1589 radeon_add_legacy_encoder(dev,
1590 radeon_get_encoder_id(dev,
1591 ATOM_DEVICE_TV1_SUPPORT,
1592 2),
1593 ATOM_DEVICE_TV1_SUPPORT);
1594 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1595 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1596 &ddc_i2c,
eed45b30
AD		 1597 CONNECTOR_OBJECT_ID_SVIDEO,
1598 &hpd);
771fe6b9
JG		 1599 break;
1600 case CT_POWERBOOK_INTERNAL:
1601 DRM_INFO("Connector Table: %d (powerbook internal tmds)\n",
1602 rdev->mode_info.connector_table);
1603 /* LVDS */
6a93cb25 1604 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
eed45b30 1605 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1606 radeon_add_legacy_encoder(dev,
1607 radeon_get_encoder_id(dev,
1608 ATOM_DEVICE_LCD1_SUPPORT,
1609 0),
1610 ATOM_DEVICE_LCD1_SUPPORT);
1611 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
b75fad06 1612 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
eed45b30
AD		 1613 CONNECTOR_OBJECT_ID_LVDS,
1614 &hpd);
771fe6b9 1615 /* DVI-I - primary dac, int tmds */
6a93cb25 1616 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
eed45b30 1617 hpd.hpd = RADEON_HPD_1; /* ??? */
771fe6b9
JG		 1618 radeon_add_legacy_encoder(dev,
1619 radeon_get_encoder_id(dev,
1620 ATOM_DEVICE_DFP1_SUPPORT,
1621 0),
1622 ATOM_DEVICE_DFP1_SUPPORT);
1623 radeon_add_legacy_encoder(dev,
1624 radeon_get_encoder_id(dev,
1625 ATOM_DEVICE_CRT1_SUPPORT,
1626 1),
1627 ATOM_DEVICE_CRT1_SUPPORT);
1628 radeon_add_legacy_connector(dev, 1,
1629 ATOM_DEVICE_DFP1_SUPPORT |
1630 ATOM_DEVICE_CRT1_SUPPORT,
b75fad06 1631 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
eed45b30
AD		 1632 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1633 &hpd);
771fe6b9 1634 /* TV - TV DAC */
eed45b30
AD		 1635 ddc_i2c.valid = false;
1636 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1637 radeon_add_legacy_encoder(dev,
1638 radeon_get_encoder_id(dev,
1639 ATOM_DEVICE_TV1_SUPPORT,
1640 2),
1641 ATOM_DEVICE_TV1_SUPPORT);
1642 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1643 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1644 &ddc_i2c,
eed45b30
AD		 1645 CONNECTOR_OBJECT_ID_SVIDEO,
1646 &hpd);
771fe6b9
JG		 1647 break;
1648 case CT_POWERBOOK_VGA:
1649 DRM_INFO("Connector Table: %d (powerbook vga)\n",
1650 rdev->mode_info.connector_table);
1651 /* LVDS */
6a93cb25 1652 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
eed45b30 1653 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1654 radeon_add_legacy_encoder(dev,
1655 radeon_get_encoder_id(dev,
1656 ATOM_DEVICE_LCD1_SUPPORT,
1657 0),
1658 ATOM_DEVICE_LCD1_SUPPORT);
1659 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
b75fad06 1660 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
eed45b30
AD		 1661 CONNECTOR_OBJECT_ID_LVDS,
1662 &hpd);
771fe6b9 1663 /* VGA - primary dac */
6a93cb25 1664 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
eed45b30 1665 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1666 radeon_add_legacy_encoder(dev,
1667 radeon_get_encoder_id(dev,
1668 ATOM_DEVICE_CRT1_SUPPORT,
1669 1),
1670 ATOM_DEVICE_CRT1_SUPPORT);
1671 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
b75fad06 1672 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
eed45b30
AD		 1673 CONNECTOR_OBJECT_ID_VGA,
1674 &hpd);
771fe6b9 1675 /* TV - TV DAC */
eed45b30
AD		 1676 ddc_i2c.valid = false;
1677 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1678 radeon_add_legacy_encoder(dev,
1679 radeon_get_encoder_id(dev,
1680 ATOM_DEVICE_TV1_SUPPORT,
1681 2),
1682 ATOM_DEVICE_TV1_SUPPORT);
1683 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1684 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1685 &ddc_i2c,
eed45b30
AD		 1686 CONNECTOR_OBJECT_ID_SVIDEO,
1687 &hpd);
771fe6b9
JG		 1688 break;
1689 case CT_MINI_EXTERNAL:
1690 DRM_INFO("Connector Table: %d (mini external tmds)\n",
1691 rdev->mode_info.connector_table);
1692 /* DVI-I - tv dac, ext tmds */
6a93cb25 1693 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
eed45b30 1694 hpd.hpd = RADEON_HPD_2; /* ??? */
771fe6b9
JG		 1695 radeon_add_legacy_encoder(dev,
1696 radeon_get_encoder_id(dev,
1697 ATOM_DEVICE_DFP2_SUPPORT,
1698 0),
1699 ATOM_DEVICE_DFP2_SUPPORT);
1700 radeon_add_legacy_encoder(dev,
1701 radeon_get_encoder_id(dev,
1702 ATOM_DEVICE_CRT2_SUPPORT,
1703 2),
1704 ATOM_DEVICE_CRT2_SUPPORT);
b75fad06 1705 /* XXX are any DL? */
771fe6b9
JG		 1706 radeon_add_legacy_connector(dev, 0,
1707 ATOM_DEVICE_DFP2_SUPPORT |
1708 ATOM_DEVICE_CRT2_SUPPORT,
b75fad06 1709 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
eed45b30
AD		 1710 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1711 &hpd);
771fe6b9 1712 /* TV - TV DAC */
eed45b30
AD		 1713 ddc_i2c.valid = false;
1714 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1715 radeon_add_legacy_encoder(dev,
1716 radeon_get_encoder_id(dev,
1717 ATOM_DEVICE_TV1_SUPPORT,
1718 2),
1719 ATOM_DEVICE_TV1_SUPPORT);
1720 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1721 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1722 &ddc_i2c,
eed45b30
AD		 1723 CONNECTOR_OBJECT_ID_SVIDEO,
1724 &hpd);
771fe6b9
JG		 1725 break;
1726 case CT_MINI_INTERNAL:
1727 DRM_INFO("Connector Table: %d (mini internal tmds)\n",
1728 rdev->mode_info.connector_table);
1729 /* DVI-I - tv dac, int tmds */
6a93cb25 1730 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
eed45b30 1731 hpd.hpd = RADEON_HPD_1; /* ??? */
771fe6b9
JG		 1732 radeon_add_legacy_encoder(dev,
1733 radeon_get_encoder_id(dev,
1734 ATOM_DEVICE_DFP1_SUPPORT,
1735 0),
1736 ATOM_DEVICE_DFP1_SUPPORT);
1737 radeon_add_legacy_encoder(dev,
1738 radeon_get_encoder_id(dev,
1739 ATOM_DEVICE_CRT2_SUPPORT,
1740 2),
1741 ATOM_DEVICE_CRT2_SUPPORT);
1742 radeon_add_legacy_connector(dev, 0,
1743 ATOM_DEVICE_DFP1_SUPPORT |
1744 ATOM_DEVICE_CRT2_SUPPORT,
b75fad06 1745 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
eed45b30
AD		 1746 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1747 &hpd);
771fe6b9 1748 /* TV - TV DAC */
eed45b30
AD		 1749 ddc_i2c.valid = false;
1750 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1751 radeon_add_legacy_encoder(dev,
1752 radeon_get_encoder_id(dev,
1753 ATOM_DEVICE_TV1_SUPPORT,
1754 2),
1755 ATOM_DEVICE_TV1_SUPPORT);
1756 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1757 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1758 &ddc_i2c,
eed45b30
AD		 1759 CONNECTOR_OBJECT_ID_SVIDEO,
1760 &hpd);
771fe6b9
JG		 1761 break;
1762 case CT_IMAC_G5_ISIGHT:
1763 DRM_INFO("Connector Table: %d (imac g5 isight)\n",
1764 rdev->mode_info.connector_table);
1765 /* DVI-D - int tmds */
6a93cb25 1766 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
eed45b30 1767 hpd.hpd = RADEON_HPD_1; /* ??? */
771fe6b9
JG		 1768 radeon_add_legacy_encoder(dev,
1769 radeon_get_encoder_id(dev,
1770 ATOM_DEVICE_DFP1_SUPPORT,
1771 0),
1772 ATOM_DEVICE_DFP1_SUPPORT);
1773 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT,
b75fad06 1774 DRM_MODE_CONNECTOR_DVID, &ddc_i2c,
eed45b30
AD		 1775 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
1776 &hpd);
771fe6b9 1777 /* VGA - tv dac */
6a93cb25 1778 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
eed45b30 1779 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1780 radeon_add_legacy_encoder(dev,
1781 radeon_get_encoder_id(dev,
1782 ATOM_DEVICE_CRT2_SUPPORT,
1783 2),
1784 ATOM_DEVICE_CRT2_SUPPORT);
1785 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
b75fad06 1786 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
eed45b30
AD		 1787 CONNECTOR_OBJECT_ID_VGA,
1788 &hpd);
771fe6b9 1789 /* TV - TV DAC */
eed45b30
AD		 1790 ddc_i2c.valid = false;
1791 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1792 radeon_add_legacy_encoder(dev,
1793 radeon_get_encoder_id(dev,
1794 ATOM_DEVICE_TV1_SUPPORT,
1795 2),
1796 ATOM_DEVICE_TV1_SUPPORT);
1797 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1798 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1799 &ddc_i2c,
eed45b30
AD		 1800 CONNECTOR_OBJECT_ID_SVIDEO,
1801 &hpd);
771fe6b9
JG		 1802 break;
1803 case CT_EMAC:
1804 DRM_INFO("Connector Table: %d (emac)\n",
1805 rdev->mode_info.connector_table);
1806 /* VGA - primary dac */
6a93cb25 1807 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
eed45b30 1808 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1809 radeon_add_legacy_encoder(dev,
1810 radeon_get_encoder_id(dev,
1811 ATOM_DEVICE_CRT1_SUPPORT,
1812 1),
1813 ATOM_DEVICE_CRT1_SUPPORT);
1814 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
b75fad06 1815 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
eed45b30
AD		 1816 CONNECTOR_OBJECT_ID_VGA,
1817 &hpd);
771fe6b9 1818 /* VGA - tv dac */
6a93cb25 1819 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
eed45b30 1820 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1821 radeon_add_legacy_encoder(dev,
1822 radeon_get_encoder_id(dev,
1823 ATOM_DEVICE_CRT2_SUPPORT,
1824 2),
1825 ATOM_DEVICE_CRT2_SUPPORT);
1826 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
b75fad06 1827 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
eed45b30
AD		 1828 CONNECTOR_OBJECT_ID_VGA,
1829 &hpd);
771fe6b9 1830 /* TV - TV DAC */
eed45b30
AD		 1831 ddc_i2c.valid = false;
1832 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1833 radeon_add_legacy_encoder(dev,
1834 radeon_get_encoder_id(dev,
1835 ATOM_DEVICE_TV1_SUPPORT,
1836 2),
1837 ATOM_DEVICE_TV1_SUPPORT);
1838 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1839 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1840 &ddc_i2c,
eed45b30
AD		 1841 CONNECTOR_OBJECT_ID_SVIDEO,
1842 &hpd);
771fe6b9
JG		 1843 break;
1844 default:
1845 DRM_INFO("Connector table: %d (invalid)\n",
1846 rdev->mode_info.connector_table);
1847 return false;
1848 }
1849
1850 radeon_link_encoder_connector(dev);
1851
1852 return true;
1853}
1854
1855static bool radeon_apply_legacy_quirks(struct drm_device *dev,
1856 int bios_index,
1857 enum radeon_combios_connector
1858 *legacy_connector,
eed45b30
AD		 1859 struct radeon_i2c_bus_rec *ddc_i2c,
1860 struct radeon_hpd *hpd)
771fe6b9
JG		 1861{
1862 struct radeon_device *rdev = dev->dev_private;
1863
1864 /* XPRESS DDC quirks */
1865 if ((rdev->family == CHIP_RS400 ||
1866 rdev->family == CHIP_RS480) &&
1867 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
6a93cb25 1868 *ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
771fe6b9
JG		 1869 else if ((rdev->family == CHIP_RS400 ||
1870 rdev->family == CHIP_RS480) &&
1871 ddc_i2c->mask_clk_reg == RADEON_GPIO_MONID) {
6a93cb25 1872 *ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIOPAD_MASK);
771fe6b9
JG		 1873 ddc_i2c->mask_clk_mask = (0x20 << 8);
1874 ddc_i2c->mask_data_mask = 0x80;
1875 ddc_i2c->a_clk_mask = (0x20 << 8);
1876 ddc_i2c->a_data_mask = 0x80;
9b9fe724
AD		 1877 ddc_i2c->en_clk_mask = (0x20 << 8);
1878 ddc_i2c->en_data_mask = 0x80;
1879 ddc_i2c->y_clk_mask = (0x20 << 8);
1880 ddc_i2c->y_data_mask = 0x80;
771fe6b9
JG		 1881 }
1882
fcec570b
AD		 1883 /* R3xx+ chips don't have GPIO_CRT2_DDC gpio pad */
1884 if ((rdev->family >= CHIP_R300) &&
1885 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
6a93cb25 1886 *ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
fcec570b 1887
771fe6b9
JG		 1888 /* Certain IBM chipset RN50s have a BIOS reporting two VGAs,
1889 one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */
1890 if (dev->pdev->device == 0x515e &&
1891 dev->pdev->subsystem_vendor == 0x1014) {
1892 if (*legacy_connector == CONNECTOR_CRT_LEGACY &&
1893 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
1894 return false;
1895 }
1896
1897 /* Some RV100 cards with 2 VGA ports show up with DVI+VGA */
1898 if (dev->pdev->device == 0x5159 &&
1899 dev->pdev->subsystem_vendor == 0x1002 &&
1900 dev->pdev->subsystem_device == 0x013a) {
1901 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
1902 *legacy_connector = CONNECTOR_CRT_LEGACY;
1903
1904 }
1905
1906 /* X300 card with extra non-existent DVI port */
1907 if (dev->pdev->device == 0x5B60 &&
1908 dev->pdev->subsystem_vendor == 0x17af &&
1909 dev->pdev->subsystem_device == 0x201e && bios_index == 2) {
1910 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
1911 return false;
1912 }
1913
1914 return true;
1915}
1916
790cfb34
AD		 1917static bool radeon_apply_legacy_tv_quirks(struct drm_device *dev)
1918{
1919 /* Acer 5102 has non-existent TV port */
1920 if (dev->pdev->device == 0x5975 &&
1921 dev->pdev->subsystem_vendor == 0x1025 &&
1922 dev->pdev->subsystem_device == 0x009f)
1923 return false;
1924
fc7f7119
AD		 1925 /* HP dc5750 has non-existent TV port */
1926 if (dev->pdev->device == 0x5974 &&
1927 dev->pdev->subsystem_vendor == 0x103c &&
1928 dev->pdev->subsystem_device == 0x280a)
1929 return false;
1930
fd874ad0
AD		 1931 /* MSI S270 has non-existent TV port */
1932 if (dev->pdev->device == 0x5955 &&
1933 dev->pdev->subsystem_vendor == 0x1462 &&
1934 dev->pdev->subsystem_device == 0x0131)
1935 return false;
1936
790cfb34
AD		 1937 return true;
1938}
1939
b75fad06
AD		 1940static uint16_t combios_check_dl_dvi(struct drm_device *dev, int is_dvi_d)
1941{
1942 struct radeon_device *rdev = dev->dev_private;
1943 uint32_t ext_tmds_info;
1944
1945 if (rdev->flags & RADEON_IS_IGP) {
1946 if (is_dvi_d)
1947 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
1948 else
1949 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
1950 }
1951 ext_tmds_info = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1952 if (ext_tmds_info) {
1953 uint8_t rev = RBIOS8(ext_tmds_info);
1954 uint8_t flags = RBIOS8(ext_tmds_info + 4 + 5);
1955 if (rev >= 3) {
1956 if (is_dvi_d)
1957 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
1958 else
1959 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
1960 } else {
1961 if (flags & 1) {
1962 if (is_dvi_d)
1963 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
1964 else
1965 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
1966 }
1967 }
1968 }
1969 if (is_dvi_d)
1970 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
1971 else
1972 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
1973}
1974
771fe6b9
JG		 1975bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
1976{
1977 struct radeon_device *rdev = dev->dev_private;
1978 uint32_t conn_info, entry, devices;
b75fad06 1979 uint16_t tmp, connector_object_id;
771fe6b9
JG		 1980 enum radeon_combios_ddc ddc_type;
1981 enum radeon_combios_connector connector;
1982 int i = 0;
1983 struct radeon_i2c_bus_rec ddc_i2c;
eed45b30 1984 struct radeon_hpd hpd;
771fe6b9 1985
771fe6b9
JG		 1986 conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE);
1987 if (conn_info) {
1988 for (i = 0; i < 4; i++) {
1989 entry = conn_info + 2 + i * 2;
1990
1991 if (!RBIOS16(entry))
1992 break;
1993
1994 tmp = RBIOS16(entry);
1995
1996 connector = (tmp >> 12) & 0xf;
1997
1998 ddc_type = (tmp >> 8) & 0xf;
1999 switch (ddc_type) {
2000 case DDC_MONID:
2001 ddc_i2c =
6a93cb25 2002 combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
771fe6b9
JG		 2003 break;
2004 case DDC_DVI:
2005 ddc_i2c =
6a93cb25 2006 combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
771fe6b9
JG		 2007 break;
2008 case DDC_VGA:
2009 ddc_i2c =
6a93cb25 2010 combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
771fe6b9
JG		 2011 break;
2012 case DDC_CRT2:
2013 ddc_i2c =
6a93cb25 2014 combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
771fe6b9
JG		 2015 break;
2016 default:
2017 break;
2018 }
2019
eed45b30
AD		 2020 switch (connector) {
2021 case CONNECTOR_PROPRIETARY_LEGACY:
2022 case CONNECTOR_DVI_I_LEGACY:
2023 case CONNECTOR_DVI_D_LEGACY:
2024 if ((tmp >> 4) & 0x1)
2025 hpd.hpd = RADEON_HPD_2;
2026 else
2027 hpd.hpd = RADEON_HPD_1;
2028 break;
2029 default:
2030 hpd.hpd = RADEON_HPD_NONE;
2031 break;
2032 }
2033
2d152c6b 2034 if (!radeon_apply_legacy_quirks(dev, i, &connector,
eed45b30 2035 &ddc_i2c, &hpd))
2d152c6b 2036 continue;
771fe6b9
JG		 2037
2038 switch (connector) {
2039 case CONNECTOR_PROPRIETARY_LEGACY:
2040 if ((tmp >> 4) & 0x1)
2041 devices = ATOM_DEVICE_DFP2_SUPPORT;
2042 else
2043 devices = ATOM_DEVICE_DFP1_SUPPORT;
2044 radeon_add_legacy_encoder(dev,
2045 radeon_get_encoder_id
2046 (dev, devices, 0),
2047 devices);
2048 radeon_add_legacy_connector(dev, i, devices,
2049 legacy_connector_convert
2050 [connector],
b75fad06 2051 &ddc_i2c,
eed45b30
AD		 2052 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
2053 &hpd);
771fe6b9
JG		 2054 break;
2055 case CONNECTOR_CRT_LEGACY:
2056 if (tmp & 0x1) {
2057 devices = ATOM_DEVICE_CRT2_SUPPORT;
2058 radeon_add_legacy_encoder(dev,
2059 radeon_get_encoder_id
2060 (dev,
2061 ATOM_DEVICE_CRT2_SUPPORT,
2062 2),
2063 ATOM_DEVICE_CRT2_SUPPORT);
2064 } else {
2065 devices = ATOM_DEVICE_CRT1_SUPPORT;
2066 radeon_add_legacy_encoder(dev,
2067 radeon_get_encoder_id
2068 (dev,
2069 ATOM_DEVICE_CRT1_SUPPORT,
2070 1),
2071 ATOM_DEVICE_CRT1_SUPPORT);
2072 }
2073 radeon_add_legacy_connector(dev,
2074 i,
2075 devices,
2076 legacy_connector_convert
2077 [connector],
b75fad06 2078 &ddc_i2c,
eed45b30
AD		 2079 CONNECTOR_OBJECT_ID_VGA,
2080 &hpd);
771fe6b9
JG		 2081 break;
2082 case CONNECTOR_DVI_I_LEGACY:
2083 devices = 0;
2084 if (tmp & 0x1) {
2085 devices |= ATOM_DEVICE_CRT2_SUPPORT;
2086 radeon_add_legacy_encoder(dev,
2087 radeon_get_encoder_id
2088 (dev,
2089 ATOM_DEVICE_CRT2_SUPPORT,
2090 2),
2091 ATOM_DEVICE_CRT2_SUPPORT);
2092 } else {
2093 devices |= ATOM_DEVICE_CRT1_SUPPORT;
2094 radeon_add_legacy_encoder(dev,
2095 radeon_get_encoder_id
2096 (dev,
2097 ATOM_DEVICE_CRT1_SUPPORT,
2098 1),
2099 ATOM_DEVICE_CRT1_SUPPORT);
2100 }
2101 if ((tmp >> 4) & 0x1) {
2102 devices |= ATOM_DEVICE_DFP2_SUPPORT;
2103 radeon_add_legacy_encoder(dev,
2104 radeon_get_encoder_id
2105 (dev,
2106 ATOM_DEVICE_DFP2_SUPPORT,
2107 0),
2108 ATOM_DEVICE_DFP2_SUPPORT);
b75fad06 2109 connector_object_id = combios_check_dl_dvi(dev, 0);
771fe6b9
JG		 2110 } else {
2111 devices |= ATOM_DEVICE_DFP1_SUPPORT;
2112 radeon_add_legacy_encoder(dev,
2113 radeon_get_encoder_id
2114 (dev,
2115 ATOM_DEVICE_DFP1_SUPPORT,
2116 0),
2117 ATOM_DEVICE_DFP1_SUPPORT);
b75fad06 2118 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
771fe6b9
JG		 2119 }
2120 radeon_add_legacy_connector(dev,
2121 i,
2122 devices,
2123 legacy_connector_convert
2124 [connector],
b75fad06 2125 &ddc_i2c,
eed45b30
AD		 2126 connector_object_id,
2127 &hpd);
771fe6b9
JG		 2128 break;
2129 case CONNECTOR_DVI_D_LEGACY:
b75fad06 2130 if ((tmp >> 4) & 0x1) {
771fe6b9 2131 devices = ATOM_DEVICE_DFP2_SUPPORT;
b75fad06
AD		 2132 connector_object_id = combios_check_dl_dvi(dev, 1);
2133 } else {
771fe6b9 2134 devices = ATOM_DEVICE_DFP1_SUPPORT;
b75fad06
AD		 2135 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2136 }
771fe6b9
JG		 2137 radeon_add_legacy_encoder(dev,
2138 radeon_get_encoder_id
2139 (dev, devices, 0),
2140 devices);
2141 radeon_add_legacy_connector(dev, i, devices,
2142 legacy_connector_convert
2143 [connector],
b75fad06 2144 &ddc_i2c,
eed45b30
AD		 2145 connector_object_id,
2146 &hpd);
771fe6b9
JG		 2147 break;
2148 case CONNECTOR_CTV_LEGACY:
2149 case CONNECTOR_STV_LEGACY:
2150 radeon_add_legacy_encoder(dev,
2151 radeon_get_encoder_id
2152 (dev,
2153 ATOM_DEVICE_TV1_SUPPORT,
2154 2),
2155 ATOM_DEVICE_TV1_SUPPORT);
2156 radeon_add_legacy_connector(dev, i,
2157 ATOM_DEVICE_TV1_SUPPORT,
2158 legacy_connector_convert
2159 [connector],
b75fad06 2160 &ddc_i2c,
eed45b30
AD		 2161 CONNECTOR_OBJECT_ID_SVIDEO,
2162 &hpd);
771fe6b9
JG		 2163 break;
2164 default:
2165 DRM_ERROR("Unknown connector type: %d\n",
2166 connector);
2167 continue;
2168 }
2169
2170 }
2171 } else {
2172 uint16_t tmds_info =
2173 combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
2174 if (tmds_info) {
2175 DRM_DEBUG("Found DFP table, assuming DVI connector\n");
2176
2177 radeon_add_legacy_encoder(dev,
2178 radeon_get_encoder_id(dev,
2179 ATOM_DEVICE_CRT1_SUPPORT,
2180 1),
2181 ATOM_DEVICE_CRT1_SUPPORT);
2182 radeon_add_legacy_encoder(dev,
2183 radeon_get_encoder_id(dev,
2184 ATOM_DEVICE_DFP1_SUPPORT,
2185 0),
2186 ATOM_DEVICE_DFP1_SUPPORT);
2187
6a93cb25 2188 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
eed45b30 2189 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 2190 radeon_add_legacy_connector(dev,
2191 0,
2192 ATOM_DEVICE_CRT1_SUPPORT |
2193 ATOM_DEVICE_DFP1_SUPPORT,
2194 DRM_MODE_CONNECTOR_DVII,
b75fad06 2195 &ddc_i2c,
eed45b30
AD		 2196 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2197 &hpd);
771fe6b9 2198 } else {
d0c403e9
AD		 2199 uint16_t crt_info =
2200 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
2201 DRM_DEBUG("Found CRT table, assuming VGA connector\n");
2202 if (crt_info) {
2203 radeon_add_legacy_encoder(dev,
2204 radeon_get_encoder_id(dev,
2205 ATOM_DEVICE_CRT1_SUPPORT,
2206 1),
2207 ATOM_DEVICE_CRT1_SUPPORT);
6a93cb25 2208 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
eed45b30 2209 hpd.hpd = RADEON_HPD_NONE;
d0c403e9
AD		 2210 radeon_add_legacy_connector(dev,
2211 0,
2212 ATOM_DEVICE_CRT1_SUPPORT,
2213 DRM_MODE_CONNECTOR_VGA,
b75fad06 2214 &ddc_i2c,
eed45b30
AD		 2215 CONNECTOR_OBJECT_ID_VGA,
2216 &hpd);
d0c403e9
AD		 2217 } else {
2218 DRM_DEBUG("No connector info found\n");
2219 return false;
2220 }
771fe6b9
JG		 2221 }
2222 }
2223
2224 if (rdev->flags & RADEON_IS_MOBILITY || rdev->flags & RADEON_IS_IGP) {
2225 uint16_t lcd_info =
2226 combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
2227 if (lcd_info) {
2228 uint16_t lcd_ddc_info =
2229 combios_get_table_offset(dev,
2230 COMBIOS_LCD_DDC_INFO_TABLE);
2231
2232 radeon_add_legacy_encoder(dev,
2233 radeon_get_encoder_id(dev,
2234 ATOM_DEVICE_LCD1_SUPPORT,
2235 0),
2236 ATOM_DEVICE_LCD1_SUPPORT);
2237
2238 if (lcd_ddc_info) {
2239 ddc_type = RBIOS8(lcd_ddc_info + 2);
2240 switch (ddc_type) {
2241 case DDC_MONID:
2242 ddc_i2c =
2243 combios_setup_i2c_bus
6a93cb25 2244 (rdev, RADEON_GPIO_MONID);
771fe6b9
JG		 2245 break;
2246 case DDC_DVI:
2247 ddc_i2c =
2248 combios_setup_i2c_bus
6a93cb25 2249 (rdev, RADEON_GPIO_DVI_DDC);
771fe6b9
JG		 2250 break;
2251 case DDC_VGA:
2252 ddc_i2c =
2253 combios_setup_i2c_bus
6a93cb25 2254 (rdev, RADEON_GPIO_VGA_DDC);
771fe6b9
JG		 2255 break;
2256 case DDC_CRT2:
2257 ddc_i2c =
2258 combios_setup_i2c_bus
6a93cb25 2259 (rdev, RADEON_GPIO_CRT2_DDC);
771fe6b9
JG		 2260 break;
2261 case DDC_LCD:
2262 ddc_i2c =
2263 combios_setup_i2c_bus
6a93cb25 2264 (rdev, RADEON_GPIOPAD_MASK);
771fe6b9
JG		 2265 ddc_i2c.mask_clk_mask =
2266 RBIOS32(lcd_ddc_info + 3);
2267 ddc_i2c.mask_data_mask =
2268 RBIOS32(lcd_ddc_info + 7);
2269 ddc_i2c.a_clk_mask =
2270 RBIOS32(lcd_ddc_info + 3);
2271 ddc_i2c.a_data_mask =
2272 RBIOS32(lcd_ddc_info + 7);
9b9fe724 2273 ddc_i2c.en_clk_mask =
771fe6b9 2274 RBIOS32(lcd_ddc_info + 3);
9b9fe724 2275 ddc_i2c.en_data_mask =
771fe6b9 2276 RBIOS32(lcd_ddc_info + 7);
9b9fe724 2277 ddc_i2c.y_clk_mask =
771fe6b9 2278 RBIOS32(lcd_ddc_info + 3);
9b9fe724 2279 ddc_i2c.y_data_mask =
771fe6b9
JG		 2280 RBIOS32(lcd_ddc_info + 7);
2281 break;
2282 case DDC_GPIO:
2283 ddc_i2c =
2284 combios_setup_i2c_bus
6a93cb25 2285 (rdev, RADEON_MDGPIO_MASK);
771fe6b9
JG		 2286 ddc_i2c.mask_clk_mask =
2287 RBIOS32(lcd_ddc_info + 3);
2288 ddc_i2c.mask_data_mask =
2289 RBIOS32(lcd_ddc_info + 7);
2290 ddc_i2c.a_clk_mask =
2291 RBIOS32(lcd_ddc_info + 3);
2292 ddc_i2c.a_data_mask =
2293 RBIOS32(lcd_ddc_info + 7);
9b9fe724 2294 ddc_i2c.en_clk_mask =
771fe6b9 2295 RBIOS32(lcd_ddc_info + 3);
9b9fe724 2296 ddc_i2c.en_data_mask =
771fe6b9 2297 RBIOS32(lcd_ddc_info + 7);
9b9fe724 2298 ddc_i2c.y_clk_mask =
771fe6b9 2299 RBIOS32(lcd_ddc_info + 3);
9b9fe724 2300 ddc_i2c.y_data_mask =
771fe6b9
JG		 2301 RBIOS32(lcd_ddc_info + 7);
2302 break;
2303 default:
2304 ddc_i2c.valid = false;
2305 break;
2306 }
2307 DRM_DEBUG("LCD DDC Info Table found!\n");
2308 } else
2309 ddc_i2c.valid = false;
2310
eed45b30 2311 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 2312 radeon_add_legacy_connector(dev,
2313 5,
2314 ATOM_DEVICE_LCD1_SUPPORT,
2315 DRM_MODE_CONNECTOR_LVDS,
b75fad06 2316 &ddc_i2c,
eed45b30
AD		 2317 CONNECTOR_OBJECT_ID_LVDS,
2318 &hpd);
771fe6b9
JG		 2319 }
2320 }
2321
2322 /* check TV table */
2323 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
2324 uint32_t tv_info =
2325 combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
2326 if (tv_info) {
2327 if (RBIOS8(tv_info + 6) == 'T') {
790cfb34 2328 if (radeon_apply_legacy_tv_quirks(dev)) {
eed45b30 2329 hpd.hpd = RADEON_HPD_NONE;
790cfb34
AD		 2330 radeon_add_legacy_encoder(dev,
2331 radeon_get_encoder_id
2332 (dev,
2333 ATOM_DEVICE_TV1_SUPPORT,
2334 2),
2335 ATOM_DEVICE_TV1_SUPPORT);
2336 radeon_add_legacy_connector(dev, 6,
2337 ATOM_DEVICE_TV1_SUPPORT,
2338 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 2339 &ddc_i2c,
eed45b30
AD		 2340 CONNECTOR_OBJECT_ID_SVIDEO,
2341 &hpd);
790cfb34 2342 }
771fe6b9
JG		 2343 }
2344 }
2345 }
2346
2347 radeon_link_encoder_connector(dev);
2348
2349 return true;
2350}
2351
56278a8e
AD		 2352void radeon_combios_get_power_modes(struct radeon_device *rdev)
2353{
2354 struct drm_device *dev = rdev->ddev;
2355 u16 offset, misc, misc2 = 0;
2356 u8 rev, blocks, tmp;
2357 int state_index = 0;
2358
2359 rdev->pm.default_power_state = NULL;
56278a8e 2360
56278a8e
AD		 2361 if (rdev->flags & RADEON_IS_MOBILITY) {
2362 offset = combios_get_table_offset(dev, COMBIOS_POWERPLAY_INFO_TABLE);
2363 if (offset) {
2364 rev = RBIOS8(offset);
2365 blocks = RBIOS8(offset + 0x2);
2366 /* power mode 0 tends to be the only valid one */
2367 rdev->pm.power_state[state_index].num_clock_modes = 1;
2368 rdev->pm.power_state[state_index].clock_info[0].mclk = RBIOS32(offset + 0x5 + 0x2);
2369 rdev->pm.power_state[state_index].clock_info[0].sclk = RBIOS32(offset + 0x5 + 0x6);
2370 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2371 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2372 goto default_mode;
2373 /* skip overclock modes for now */
2374 if ((rdev->pm.power_state[state_index].clock_info[0].mclk >
27459324 2375 rdev->clock.default_mclk + RADEON_MODE_OVERCLOCK_MARGIN) ||
56278a8e 2376 (rdev->pm.power_state[state_index].clock_info[0].sclk >
27459324 2377 rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN))
56278a8e 2378 goto default_mode;
0ec0e74f
AD		 2379 rdev->pm.power_state[state_index].type =
2380 POWER_STATE_TYPE_BATTERY;
56278a8e
AD		 2381 misc = RBIOS16(offset + 0x5 + 0x0);
2382 if (rev > 4)
2383 misc2 = RBIOS16(offset + 0x5 + 0xe);
2384 if (misc & 0x4) {
2385 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_GPIO;
2386 if (misc & 0x8)
2387 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2388 true;
2389 else
2390 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2391 false;
2392 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = true;
2393 if (rev < 6) {
2394 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2395 RBIOS16(offset + 0x5 + 0xb) * 4;
2396 tmp = RBIOS8(offset + 0x5 + 0xd);
2397 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2398 } else {
2399 u8 entries = RBIOS8(offset + 0x5 + 0xb);
2400 u16 voltage_table_offset = RBIOS16(offset + 0x5 + 0xc);
2401 if (entries && voltage_table_offset) {
2402 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2403 RBIOS16(voltage_table_offset) * 4;
2404 tmp = RBIOS8(voltage_table_offset + 0x2);
2405 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2406 } else
2407 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = false;
2408 }
2409 switch ((misc2 & 0x700) >> 8) {
2410 case 0:
2411 default:
2412 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 0;
2413 break;
2414 case 1:
2415 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 33;
2416 break;
2417 case 2:
2418 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 66;
2419 break;
2420 case 3:
2421 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 99;
2422 break;
2423 case 4:
2424 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 132;
2425 break;
2426 }
2427 } else
2428 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2429 if (rev > 6)
2430 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =
2431 RBIOS8(offset + 0x5 + 0x10);
2432 state_index++;
2433 } else {
2434 /* XXX figure out some good default low power mode for mobility cards w/out power tables */
2435 }
2436 } else {
2437 /* XXX figure out some good default low power mode for desktop cards */
2438 }
2439
2440default_mode:
2441 /* add the default mode */
0ec0e74f
AD		 2442 rdev->pm.power_state[state_index].type =
2443 POWER_STATE_TYPE_DEFAULT;
56278a8e
AD		 2444 rdev->pm.power_state[state_index].num_clock_modes = 1;
2445 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2446 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2447 rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0];
56278a8e
AD		 2448 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2449 if (rdev->asic->get_pcie_lanes)
2450 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = radeon_get_pcie_lanes(rdev);
2451 else
2452 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = 16;
2453 rdev->pm.default_power_state = &rdev->pm.power_state[state_index];
56278a8e 2454 rdev->pm.num_power_states = state_index + 1;
9038dfdf
RM		 2455
2456 rdev->pm.current_power_state = rdev->pm.default_power_state;
2457 rdev->pm.current_clock_mode =
2458 rdev->pm.default_power_state->default_clock_mode;
56278a8e
AD		 2459}
2460
fcec570b
AD		 2461void radeon_external_tmds_setup(struct drm_encoder *encoder)
2462{
2463 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2464 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2465
2466 if (!tmds)
2467 return;
2468
2469 switch (tmds->dvo_chip) {
2470 case DVO_SIL164:
2471 /* sil 164 */
5a6f98f5
AD		 2472 radeon_i2c_put_byte(tmds->i2c_bus,
2473 tmds->slave_addr,
2474 0x08, 0x30);
2475 radeon_i2c_put_byte(tmds->i2c_bus,
fcec570b
AD		 2476 tmds->slave_addr,
2477 0x09, 0x00);
5a6f98f5
AD		 2478 radeon_i2c_put_byte(tmds->i2c_bus,
2479 tmds->slave_addr,
2480 0x0a, 0x90);
2481 radeon_i2c_put_byte(tmds->i2c_bus,
2482 tmds->slave_addr,
2483 0x0c, 0x89);
2484 radeon_i2c_put_byte(tmds->i2c_bus,
fcec570b
AD		 2485 tmds->slave_addr,
2486 0x08, 0x3b);
fcec570b
AD		 2487 break;
2488 case DVO_SIL1178:
2489 /* sil 1178 - untested */
2490 /*
2491 * 0x0f, 0x44
2492 * 0x0f, 0x4c
2493 * 0x0e, 0x01
2494 * 0x0a, 0x80
2495 * 0x09, 0x30
2496 * 0x0c, 0xc9
2497 * 0x0d, 0x70
2498 * 0x08, 0x32
2499 * 0x08, 0x33
2500 */
2501 break;
2502 default:
2503 break;
2504 }
2505
2506}
2507
2508bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder)
2509{
2510 struct drm_device *dev = encoder->dev;
2511 struct radeon_device *rdev = dev->dev_private;
2512 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2513 uint16_t offset;
2514 uint8_t blocks, slave_addr, rev;
2515 uint32_t index, id;
2516 uint32_t reg, val, and_mask, or_mask;
2517 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2518
fcec570b
AD		 2519 if (!tmds)
2520 return false;
2521
2522 if (rdev->flags & RADEON_IS_IGP) {
2523 offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_ON_TABLE);
2524 rev = RBIOS8(offset);
2525 if (offset) {
2526 rev = RBIOS8(offset);
2527 if (rev > 1) {
2528 blocks = RBIOS8(offset + 3);
2529 index = offset + 4;
2530 while (blocks > 0) {
2531 id = RBIOS16(index);
2532 index += 2;
2533 switch (id >> 13) {
2534 case 0:
2535 reg = (id & 0x1fff) * 4;
2536 val = RBIOS32(index);
2537 index += 4;
2538 WREG32(reg, val);
2539 break;
2540 case 2:
2541 reg = (id & 0x1fff) * 4;
2542 and_mask = RBIOS32(index);
2543 index += 4;
2544 or_mask = RBIOS32(index);
2545 index += 4;
2546 val = RREG32(reg);
2547 val = (val & and_mask) | or_mask;
2548 WREG32(reg, val);
2549 break;
2550 case 3:
2551 val = RBIOS16(index);
2552 index += 2;
2553 udelay(val);
2554 break;
2555 case 4:
2556 val = RBIOS16(index);
2557 index += 2;
2558 udelay(val * 1000);
2559 break;
2560 case 6:
2561 slave_addr = id & 0xff;
2562 slave_addr >>= 1; /* 7 bit addressing */
2563 index++;
2564 reg = RBIOS8(index);
2565 index++;
2566 val = RBIOS8(index);
2567 index++;
5a6f98f5
AD		 2568 radeon_i2c_put_byte(tmds->i2c_bus,
2569 slave_addr,
2570 reg, val);
fcec570b
AD		 2571 break;
2572 default:
2573 DRM_ERROR("Unknown id %d\n", id >> 13);
2574 break;
2575 }
2576 blocks--;
2577 }
2578 return true;
2579 }
2580 }
2581 } else {
2582 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2583 if (offset) {
2584 index = offset + 10;
2585 id = RBIOS16(index);
2586 while (id != 0xffff) {
2587 index += 2;
2588 switch (id >> 13) {
2589 case 0:
2590 reg = (id & 0x1fff) * 4;
2591 val = RBIOS32(index);
2592 WREG32(reg, val);
2593 break;
2594 case 2:
2595 reg = (id & 0x1fff) * 4;
2596 and_mask = RBIOS32(index);
2597 index += 4;
2598 or_mask = RBIOS32(index);
2599 index += 4;
2600 val = RREG32(reg);
2601 val = (val & and_mask) | or_mask;
2602 WREG32(reg, val);
2603 break;
2604 case 4:
2605 val = RBIOS16(index);
2606 index += 2;
2607 udelay(val);
2608 break;
2609 case 5:
2610 reg = id & 0x1fff;
2611 and_mask = RBIOS32(index);
2612 index += 4;
2613 or_mask = RBIOS32(index);
2614 index += 4;
2615 val = RREG32_PLL(reg);
2616 val = (val & and_mask) | or_mask;
2617 WREG32_PLL(reg, val);
2618 break;
2619 case 6:
2620 reg = id & 0x1fff;
2621 val = RBIOS8(index);
2622 index += 1;
5a6f98f5
AD		 2623 radeon_i2c_put_byte(tmds->i2c_bus,
2624 tmds->slave_addr,
2625 reg, val);
fcec570b
AD		 2626 break;
2627 default:
2628 DRM_ERROR("Unknown id %d\n", id >> 13);
2629 break;
2630 }
2631 id = RBIOS16(index);
2632 }
2633 return true;
2634 }
2635 }
2636 return false;
2637}
2638
771fe6b9
JG		 2639static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset)
2640{
2641 struct radeon_device *rdev = dev->dev_private;
2642
2643 if (offset) {
2644 while (RBIOS16(offset)) {
2645 uint16_t cmd = ((RBIOS16(offset) & 0xe000) >> 13);
2646 uint32_t addr = (RBIOS16(offset) & 0x1fff);
2647 uint32_t val, and_mask, or_mask;
2648 uint32_t tmp;
2649
2650 offset += 2;
2651 switch (cmd) {
2652 case 0:
2653 val = RBIOS32(offset);
2654 offset += 4;
2655 WREG32(addr, val);
2656 break;
2657 case 1:
2658 val = RBIOS32(offset);
2659 offset += 4;
2660 WREG32(addr, val);
2661 break;
2662 case 2:
2663 and_mask = RBIOS32(offset);
2664 offset += 4;
2665 or_mask = RBIOS32(offset);
2666 offset += 4;
2667 tmp = RREG32(addr);
2668 tmp &= and_mask;
2669 tmp |= or_mask;
2670 WREG32(addr, tmp);
2671 break;
2672 case 3:
2673 and_mask = RBIOS32(offset);
2674 offset += 4;
2675 or_mask = RBIOS32(offset);
2676 offset += 4;
2677 tmp = RREG32(addr);
2678 tmp &= and_mask;
2679 tmp |= or_mask;
2680 WREG32(addr, tmp);
2681 break;
2682 case 4:
2683 val = RBIOS16(offset);
2684 offset += 2;
2685 udelay(val);
2686 break;
2687 case 5:
2688 val = RBIOS16(offset);
2689 offset += 2;
2690 switch (addr) {
2691 case 8:
2692 while (val--) {
2693 if (!
2694 (RREG32_PLL
2695 (RADEON_CLK_PWRMGT_CNTL) &
2696 RADEON_MC_BUSY))
2697 break;
2698 }
2699 break;
2700 case 9:
2701 while (val--) {
2702 if ((RREG32(RADEON_MC_STATUS) &
2703 RADEON_MC_IDLE))
2704 break;
2705 }
2706 break;
2707 default:
2708 break;
2709 }
2710 break;
2711 default:
2712 break;
2713 }
2714 }
2715 }
2716}
2717
2718static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset)
2719{
2720 struct radeon_device *rdev = dev->dev_private;
2721
2722 if (offset) {
2723 while (RBIOS8(offset)) {
2724 uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6);
2725 uint8_t addr = (RBIOS8(offset) & 0x3f);
2726 uint32_t val, shift, tmp;
2727 uint32_t and_mask, or_mask;
2728
2729 offset++;
2730 switch (cmd) {
2731 case 0:
2732 val = RBIOS32(offset);
2733 offset += 4;
2734 WREG32_PLL(addr, val);
2735 break;
2736 case 1:
2737 shift = RBIOS8(offset) * 8;
2738 offset++;
2739 and_mask = RBIOS8(offset) << shift;
2740 and_mask |= ~(0xff << shift);
2741 offset++;
2742 or_mask = RBIOS8(offset) << shift;
2743 offset++;
2744 tmp = RREG32_PLL(addr);
2745 tmp &= and_mask;
2746 tmp |= or_mask;
2747 WREG32_PLL(addr, tmp);
2748 break;
2749 case 2:
2750 case 3:
2751 tmp = 1000;
2752 switch (addr) {
2753 case 1:
2754 udelay(150);
2755 break;
2756 case 2:
2757 udelay(1000);
2758 break;
2759 case 3:
2760 while (tmp--) {
2761 if (!
2762 (RREG32_PLL
2763 (RADEON_CLK_PWRMGT_CNTL) &
2764 RADEON_MC_BUSY))
2765 break;
2766 }
2767 break;
2768 case 4:
2769 while (tmp--) {
2770 if (RREG32_PLL
2771 (RADEON_CLK_PWRMGT_CNTL) &
2772 RADEON_DLL_READY)
2773 break;
2774 }
2775 break;
2776 case 5:
2777 tmp =
2778 RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);
2779 if (tmp & RADEON_CG_NO1_DEBUG_0) {
2780#if 0
2781 uint32_t mclk_cntl =
2782 RREG32_PLL
2783 (RADEON_MCLK_CNTL);
2784 mclk_cntl &= 0xffff0000;
2785 /*mclk_cntl |= 0x00001111;*//* ??? */
2786 WREG32_PLL(RADEON_MCLK_CNTL,
2787 mclk_cntl);
2788 udelay(10000);
2789#endif
2790 WREG32_PLL
2791 (RADEON_CLK_PWRMGT_CNTL,
2792 tmp &
2793 ~RADEON_CG_NO1_DEBUG_0);
2794 udelay(10000);
2795 }
2796 break;
2797 default:
2798 break;
2799 }
2800 break;
2801 default:
2802 break;
2803 }
2804 }
2805 }
2806}
2807
2808static void combios_parse_ram_reset_table(struct drm_device *dev,
2809 uint16_t offset)
2810{
2811 struct radeon_device *rdev = dev->dev_private;
2812 uint32_t tmp;
2813
2814 if (offset) {
2815 uint8_t val = RBIOS8(offset);
2816 while (val != 0xff) {
2817 offset++;
2818
2819 if (val == 0x0f) {
2820 uint32_t channel_complete_mask;
2821
2822 if (ASIC_IS_R300(rdev))
2823 channel_complete_mask =
2824 R300_MEM_PWRUP_COMPLETE;
2825 else
2826 channel_complete_mask =
2827 RADEON_MEM_PWRUP_COMPLETE;
2828 tmp = 20000;
2829 while (tmp--) {
2830 if ((RREG32(RADEON_MEM_STR_CNTL) &
2831 channel_complete_mask) ==
2832 channel_complete_mask)
2833 break;
2834 }
2835 } else {
2836 uint32_t or_mask = RBIOS16(offset);
2837 offset += 2;
2838
2839 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2840 tmp &= RADEON_SDRAM_MODE_MASK;
2841 tmp |= or_mask;
2842 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
2843
2844 or_mask = val << 24;
2845 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2846 tmp &= RADEON_B3MEM_RESET_MASK;
2847 tmp |= or_mask;
2848 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
2849 }
2850 val = RBIOS8(offset);
2851 }
2852 }
2853}
2854
2855static uint32_t combios_detect_ram(struct drm_device *dev, int ram,
2856 int mem_addr_mapping)
2857{
2858 struct radeon_device *rdev = dev->dev_private;
2859 uint32_t mem_cntl;
2860 uint32_t mem_size;
2861 uint32_t addr = 0;
2862
2863 mem_cntl = RREG32(RADEON_MEM_CNTL);
2864 if (mem_cntl & RV100_HALF_MODE)
2865 ram /= 2;
2866 mem_size = ram;
2867 mem_cntl &= ~(0xff << 8);
2868 mem_cntl |= (mem_addr_mapping & 0xff) << 8;
2869 WREG32(RADEON_MEM_CNTL, mem_cntl);
2870 RREG32(RADEON_MEM_CNTL);
2871
2872 /* sdram reset ? */
2873
2874 /* something like this???? */
2875 while (ram--) {
2876 addr = ram * 1024 * 1024;
2877 /* write to each page */
2878 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
2879 WREG32(RADEON_MM_DATA, 0xdeadbeef);
2880 /* read back and verify */
2881 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
2882 if (RREG32(RADEON_MM_DATA) != 0xdeadbeef)
2883 return 0;
2884 }
2885
2886 return mem_size;
2887}
2888
2889static void combios_write_ram_size(struct drm_device *dev)
2890{
2891 struct radeon_device *rdev = dev->dev_private;
2892 uint8_t rev;
2893 uint16_t offset;
2894 uint32_t mem_size = 0;
2895 uint32_t mem_cntl = 0;
2896
2897 /* should do something smarter here I guess... */
2898 if (rdev->flags & RADEON_IS_IGP)
2899 return;
2900
2901 /* first check detected mem table */
2902 offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE);
2903 if (offset) {
2904 rev = RBIOS8(offset);
2905 if (rev < 3) {
2906 mem_cntl = RBIOS32(offset + 1);
2907 mem_size = RBIOS16(offset + 5);
2908 if (((rdev->flags & RADEON_FAMILY_MASK) < CHIP_R200) &&
2909 ((dev->pdev->device != 0x515e)
2910 && (dev->pdev->device != 0x5969)))
2911 WREG32(RADEON_MEM_CNTL, mem_cntl);
2912 }
2913 }
2914
2915 if (!mem_size) {
2916 offset =
2917 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
2918 if (offset) {
2919 rev = RBIOS8(offset - 1);
2920 if (rev < 1) {
2921 if (((rdev->flags & RADEON_FAMILY_MASK) <
2922 CHIP_R200)
2923 && ((dev->pdev->device != 0x515e)
2924 && (dev->pdev->device != 0x5969))) {
2925 int ram = 0;
2926 int mem_addr_mapping = 0;
2927
2928 while (RBIOS8(offset)) {
2929 ram = RBIOS8(offset);
2930 mem_addr_mapping =
2931 RBIOS8(offset + 1);
2932 if (mem_addr_mapping != 0x25)
2933 ram *= 2;
2934 mem_size =
2935 combios_detect_ram(dev, ram,
2936 mem_addr_mapping);
2937 if (mem_size)
2938 break;
2939 offset += 2;
2940 }
2941 } else
2942 mem_size = RBIOS8(offset);
2943 } else {
2944 mem_size = RBIOS8(offset);
2945 mem_size *= 2; /* convert to MB */
2946 }
2947 }
2948 }
2949
2950 mem_size *= (1024 * 1024); /* convert to bytes */
2951 WREG32(RADEON_CONFIG_MEMSIZE, mem_size);
2952}
2953
2954void radeon_combios_dyn_clk_setup(struct drm_device *dev, int enable)
2955{
2956 uint16_t dyn_clk_info =
2957 combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
2958
2959 if (dyn_clk_info)
2960 combios_parse_pll_table(dev, dyn_clk_info);
2961}
2962
2963void radeon_combios_asic_init(struct drm_device *dev)
2964{
2965 struct radeon_device *rdev = dev->dev_private;
2966 uint16_t table;
2967
2968 /* port hardcoded mac stuff from radeonfb */
2969 if (rdev->bios == NULL)
2970 return;
2971
2972 /* ASIC INIT 1 */
2973 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE);
2974 if (table)
2975 combios_parse_mmio_table(dev, table);
2976
2977 /* PLL INIT */
2978 table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE);
2979 if (table)
2980 combios_parse_pll_table(dev, table);
2981
2982 /* ASIC INIT 2 */
2983 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE);
2984 if (table)
2985 combios_parse_mmio_table(dev, table);
2986
2987 if (!(rdev->flags & RADEON_IS_IGP)) {
2988 /* ASIC INIT 4 */
2989 table =
2990 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE);
2991 if (table)
2992 combios_parse_mmio_table(dev, table);
2993
2994 /* RAM RESET */
2995 table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE);
2996 if (table)
2997 combios_parse_ram_reset_table(dev, table);
2998
2999 /* ASIC INIT 3 */
3000 table =
3001 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE);
3002 if (table)
3003 combios_parse_mmio_table(dev, table);
3004
3005 /* write CONFIG_MEMSIZE */
3006 combios_write_ram_size(dev);
3007 }
3008
3009 /* DYN CLK 1 */
3010 table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
3011 if (table)
3012 combios_parse_pll_table(dev, table);
3013
3014}
3015
3016void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev)
3017{
3018 struct radeon_device *rdev = dev->dev_private;
3019 uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch;
3020
3021 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
3022 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3023 bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH);
3024
3025 /* let the bios control the backlight */
3026 bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN;
3027
3028 /* tell the bios not to handle mode switching */
3029 bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS |
3030 RADEON_ACC_MODE_CHANGE);
3031
3032 /* tell the bios a driver is loaded */
3033 bios_7_scratch |= RADEON_DRV_LOADED;
3034
3035 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
3036 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3037 WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch);
3038}
3039
3040void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock)
3041{
3042 struct drm_device *dev = encoder->dev;
3043 struct radeon_device *rdev = dev->dev_private;
3044 uint32_t bios_6_scratch;
3045
3046 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3047
3048 if (lock)
3049 bios_6_scratch |= RADEON_DRIVER_CRITICAL;
3050 else
3051 bios_6_scratch &= ~RADEON_DRIVER_CRITICAL;
3052
3053 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3054}
3055
3056void
3057radeon_combios_connected_scratch_regs(struct drm_connector *connector,
3058 struct drm_encoder *encoder,
3059 bool connected)
3060{
3061 struct drm_device *dev = connector->dev;
3062 struct radeon_device *rdev = dev->dev_private;
3063 struct radeon_connector *radeon_connector =
3064 to_radeon_connector(connector);
3065 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3066 uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH);
3067 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3068
3069 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
3070 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
3071 if (connected) {
3072 DRM_DEBUG("TV1 connected\n");
3073 /* fix me */
3074 bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO;
3075 /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */
3076 bios_5_scratch |= RADEON_TV1_ON;
3077 bios_5_scratch |= RADEON_ACC_REQ_TV1;
3078 } else {
3079 DRM_DEBUG("TV1 disconnected\n");
3080 bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK;
3081 bios_5_scratch &= ~RADEON_TV1_ON;
3082 bios_5_scratch &= ~RADEON_ACC_REQ_TV1;
3083 }
3084 }
3085 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
3086 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
3087 if (connected) {
3088 DRM_DEBUG("LCD1 connected\n");
3089 bios_4_scratch |= RADEON_LCD1_ATTACHED;
3090 bios_5_scratch |= RADEON_LCD1_ON;
3091 bios_5_scratch |= RADEON_ACC_REQ_LCD1;
3092 } else {
3093 DRM_DEBUG("LCD1 disconnected\n");
3094 bios_4_scratch &= ~RADEON_LCD1_ATTACHED;
3095 bios_5_scratch &= ~RADEON_LCD1_ON;
3096 bios_5_scratch &= ~RADEON_ACC_REQ_LCD1;
3097 }
3098 }
3099 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
3100 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
3101 if (connected) {
3102 DRM_DEBUG("CRT1 connected\n");
3103 bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR;
3104 bios_5_scratch |= RADEON_CRT1_ON;
3105 bios_5_scratch |= RADEON_ACC_REQ_CRT1;
3106 } else {
3107 DRM_DEBUG("CRT1 disconnected\n");
3108 bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK;
3109 bios_5_scratch &= ~RADEON_CRT1_ON;
3110 bios_5_scratch &= ~RADEON_ACC_REQ_CRT1;
3111 }
3112 }
3113 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
3114 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
3115 if (connected) {
3116 DRM_DEBUG("CRT2 connected\n");
3117 bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR;
3118 bios_5_scratch |= RADEON_CRT2_ON;
3119 bios_5_scratch |= RADEON_ACC_REQ_CRT2;
3120 } else {
3121 DRM_DEBUG("CRT2 disconnected\n");
3122 bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK;
3123 bios_5_scratch &= ~RADEON_CRT2_ON;
3124 bios_5_scratch &= ~RADEON_ACC_REQ_CRT2;
3125 }
3126 }
3127 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
3128 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
3129 if (connected) {
3130 DRM_DEBUG("DFP1 connected\n");
3131 bios_4_scratch |= RADEON_DFP1_ATTACHED;
3132 bios_5_scratch |= RADEON_DFP1_ON;
3133 bios_5_scratch |= RADEON_ACC_REQ_DFP1;
3134 } else {
3135 DRM_DEBUG("DFP1 disconnected\n");
3136 bios_4_scratch &= ~RADEON_DFP1_ATTACHED;
3137 bios_5_scratch &= ~RADEON_DFP1_ON;
3138 bios_5_scratch &= ~RADEON_ACC_REQ_DFP1;
3139 }
3140 }
3141 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
3142 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
3143 if (connected) {
3144 DRM_DEBUG("DFP2 connected\n");
3145 bios_4_scratch |= RADEON_DFP2_ATTACHED;
3146 bios_5_scratch |= RADEON_DFP2_ON;
3147 bios_5_scratch |= RADEON_ACC_REQ_DFP2;
3148 } else {
3149 DRM_DEBUG("DFP2 disconnected\n");
3150 bios_4_scratch &= ~RADEON_DFP2_ATTACHED;
3151 bios_5_scratch &= ~RADEON_DFP2_ON;
3152 bios_5_scratch &= ~RADEON_ACC_REQ_DFP2;
3153 }
3154 }
3155 WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch);
3156 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3157}
3158
3159void
3160radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
3161{
3162 struct drm_device *dev = encoder->dev;
3163 struct radeon_device *rdev = dev->dev_private;
3164 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3165 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3166
3167 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
3168 bios_5_scratch &= ~RADEON_TV1_CRTC_MASK;
3169 bios_5_scratch |= (crtc << RADEON_TV1_CRTC_SHIFT);
3170 }
3171 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
3172 bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK;
3173 bios_5_scratch |= (crtc << RADEON_CRT1_CRTC_SHIFT);
3174 }
3175 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
3176 bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK;
3177 bios_5_scratch |= (crtc << RADEON_CRT2_CRTC_SHIFT);
3178 }
3179 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
3180 bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK;
3181 bios_5_scratch |= (crtc << RADEON_LCD1_CRTC_SHIFT);
3182 }
3183 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
3184 bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK;
3185 bios_5_scratch |= (crtc << RADEON_DFP1_CRTC_SHIFT);
3186 }
3187 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3188 bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK;
3189 bios_5_scratch |= (crtc << RADEON_DFP2_CRTC_SHIFT);
3190 }
3191 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3192}
3193
3194void
3195radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
3196{
3197 struct drm_device *dev = encoder->dev;
3198 struct radeon_device *rdev = dev->dev_private;
3199 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3200 uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3201
3202 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
3203 if (on)
3204 bios_6_scratch |= RADEON_TV_DPMS_ON;
3205 else
3206 bios_6_scratch &= ~RADEON_TV_DPMS_ON;
3207 }
3208 if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3209 if (on)
3210 bios_6_scratch |= RADEON_CRT_DPMS_ON;
3211 else
3212 bios_6_scratch &= ~RADEON_CRT_DPMS_ON;
3213 }
3214 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3215 if (on)
3216 bios_6_scratch |= RADEON_LCD_DPMS_ON;
3217 else
3218 bios_6_scratch &= ~RADEON_LCD_DPMS_ON;
3219 }
3220 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
3221 if (on)
3222 bios_6_scratch |= RADEON_DFP_DPMS_ON;
3223 else
3224 bios_6_scratch &= ~RADEON_DFP_DPMS_ON;
3225 }
3226 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3227}
Clone of davem's net-next-2.6 tree