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Merge branch 'drm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied...
[net-next-2.6.git] / drivers / gpu / drm / radeon / radeon_atombios.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26#include "drmP.h"
27#include "radeon_drm.h"
28#include "radeon.h"
29
30#include "atom.h"
31#include "atom-bits.h"
32
33/* from radeon_encoder.c */
34extern uint32_t
5137ee94
AD		 35radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
36 uint8_t dac);
771fe6b9
JG		 37extern void radeon_link_encoder_connector(struct drm_device *dev);
38extern void
5137ee94 39radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum,
771fe6b9
JG		 40 uint32_t supported_device);
41
42/* from radeon_connector.c */
43extern void
44radeon_add_atom_connector(struct drm_device *dev,
45 uint32_t connector_id,
46 uint32_t supported_device,
47 int connector_type,
48 struct radeon_i2c_bus_rec *i2c_bus,
5137ee94 49 uint32_t igp_lane_info,
eed45b30 50 uint16_t connector_object_id,
26b5bc98
AD		 51 struct radeon_hpd *hpd,
52 struct radeon_router *router);
771fe6b9
JG		 53
54/* from radeon_legacy_encoder.c */
55extern void
5137ee94 56radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
771fe6b9
JG		 57 uint32_t supported_device);
58
59union atom_supported_devices {
60 struct _ATOM_SUPPORTED_DEVICES_INFO info;
61 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
62 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
63};
64
eed45b30
AD		 65static inline struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
66 uint8_t id)
771fe6b9 67{
771fe6b9 68 struct atom_context *ctx = rdev->mode_info.atom_context;
6a93cb25 69 ATOM_GPIO_I2C_ASSIGMENT *gpio;
771fe6b9
JG		 70 struct radeon_i2c_bus_rec i2c;
71 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
72 struct _ATOM_GPIO_I2C_INFO *i2c_info;
95beb690
AD		 73 uint16_t data_offset, size;
74 int i, num_indices;
771fe6b9
JG		 75
76 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
77 i2c.valid = false;
78
95beb690 79 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
a084e6ee
AD		 80 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
81
95beb690
AD		 82 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
83 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
84
85 for (i = 0; i < num_indices; i++) {
a084e6ee
AD		 86 gpio = &i2c_info->asGPIO_Info[i];
87
ea39302b
AD		 88 /* some evergreen boards have bad data for this entry */
89 if (ASIC_IS_DCE4(rdev)) {
90 if ((i == 7) &&
91 (gpio->usClkMaskRegisterIndex == 0x1936) &&
92 (gpio->sucI2cId.ucAccess == 0)) {
93 gpio->sucI2cId.ucAccess = 0x97;
94 gpio->ucDataMaskShift = 8;
95 gpio->ucDataEnShift = 8;
96 gpio->ucDataY_Shift = 8;
97 gpio->ucDataA_Shift = 8;
98 }
99 }
100
a084e6ee
AD		 101 if (gpio->sucI2cId.ucAccess == id) {
102 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
103 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
104 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
105 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
106 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
107 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
108 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
109 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
110 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
111 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
112 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
113 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
114 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
115 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
116 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
117 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
118
119 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
120 i2c.hw_capable = true;
121 else
122 i2c.hw_capable = false;
123
124 if (gpio->sucI2cId.ucAccess == 0xa0)
125 i2c.mm_i2c = true;
126 else
127 i2c.mm_i2c = false;
128
129 i2c.i2c_id = gpio->sucI2cId.ucAccess;
130
f376b94f
AD		 131 if (i2c.mask_clk_reg)
132 i2c.valid = true;
a084e6ee
AD		 133 break;
134 }
d3f420d1
AD		 135 }
136 }
771fe6b9
JG		 137
138 return i2c;
139}
140
f376b94f
AD		 141void radeon_atombios_i2c_init(struct radeon_device *rdev)
142{
143 struct atom_context *ctx = rdev->mode_info.atom_context;
144 ATOM_GPIO_I2C_ASSIGMENT *gpio;
145 struct radeon_i2c_bus_rec i2c;
146 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
147 struct _ATOM_GPIO_I2C_INFO *i2c_info;
148 uint16_t data_offset, size;
149 int i, num_indices;
150 char stmp[32];
151
152 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
153
154 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
155 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
156
157 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
158 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
159
160 for (i = 0; i < num_indices; i++) {
161 gpio = &i2c_info->asGPIO_Info[i];
162 i2c.valid = false;
ea39302b
AD		 163
164 /* some evergreen boards have bad data for this entry */
165 if (ASIC_IS_DCE4(rdev)) {
166 if ((i == 7) &&
167 (gpio->usClkMaskRegisterIndex == 0x1936) &&
168 (gpio->sucI2cId.ucAccess == 0)) {
169 gpio->sucI2cId.ucAccess = 0x97;
170 gpio->ucDataMaskShift = 8;
171 gpio->ucDataEnShift = 8;
172 gpio->ucDataY_Shift = 8;
173 gpio->ucDataA_Shift = 8;
174 }
175 }
176
f376b94f
AD		 177 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
178 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
179 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
180 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
181 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
182 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
183 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
184 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
185 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
186 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
187 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
188 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
189 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
190 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
191 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
192 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
193
194 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
195 i2c.hw_capable = true;
196 else
197 i2c.hw_capable = false;
198
199 if (gpio->sucI2cId.ucAccess == 0xa0)
200 i2c.mm_i2c = true;
201 else
202 i2c.mm_i2c = false;
203
204 i2c.i2c_id = gpio->sucI2cId.ucAccess;
205
206 if (i2c.mask_clk_reg) {
207 i2c.valid = true;
208 sprintf(stmp, "0x%x", i2c.i2c_id);
209 rdev->i2c_bus[i] = radeon_i2c_create(rdev->ddev, &i2c, stmp);
210 }
211 }
212 }
213}
214
eed45b30
AD		 215static inline struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev,
216 u8 id)
217{
218 struct atom_context *ctx = rdev->mode_info.atom_context;
219 struct radeon_gpio_rec gpio;
220 int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
221 struct _ATOM_GPIO_PIN_LUT *gpio_info;
222 ATOM_GPIO_PIN_ASSIGNMENT *pin;
223 u16 data_offset, size;
224 int i, num_indices;
225
226 memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
227 gpio.valid = false;
228
a084e6ee
AD		 229 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
230 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
eed45b30 231
a084e6ee
AD		 232 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
233 sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
eed45b30 234
a084e6ee
AD		 235 for (i = 0; i < num_indices; i++) {
236 pin = &gpio_info->asGPIO_Pin[i];
237 if (id == pin->ucGPIO_ID) {
238 gpio.id = pin->ucGPIO_ID;
239 gpio.reg = pin->usGpioPin_AIndex * 4;
240 gpio.mask = (1 << pin->ucGpioPinBitShift);
241 gpio.valid = true;
242 break;
243 }
eed45b30
AD		 244 }
245 }
246
247 return gpio;
248}
249
250static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
251 struct radeon_gpio_rec *gpio)
252{
253 struct radeon_hpd hpd;
bcc1c2a1
AD		 254 u32 reg;
255
1d978dac
JD		 256 memset(&hpd, 0, sizeof(struct radeon_hpd));
257
bcc1c2a1
AD		 258 if (ASIC_IS_DCE4(rdev))
259 reg = EVERGREEN_DC_GPIO_HPD_A;
260 else
261 reg = AVIVO_DC_GPIO_HPD_A;
262
eed45b30 263 hpd.gpio = *gpio;
bcc1c2a1 264 if (gpio->reg == reg) {
eed45b30
AD		 265 switch(gpio->mask) {
266 case (1 << 0):
267 hpd.hpd = RADEON_HPD_1;
268 break;
269 case (1 << 8):
270 hpd.hpd = RADEON_HPD_2;
271 break;
272 case (1 << 16):
273 hpd.hpd = RADEON_HPD_3;
274 break;
275 case (1 << 24):
276 hpd.hpd = RADEON_HPD_4;
277 break;
278 case (1 << 26):
279 hpd.hpd = RADEON_HPD_5;
280 break;
281 case (1 << 28):
282 hpd.hpd = RADEON_HPD_6;
283 break;
284 default:
285 hpd.hpd = RADEON_HPD_NONE;
286 break;
287 }
288 } else
289 hpd.hpd = RADEON_HPD_NONE;
290 return hpd;
291}
292
771fe6b9
JG		 293static bool radeon_atom_apply_quirks(struct drm_device *dev,
294 uint32_t supported_device,
295 int *connector_type,
848577ee 296 struct radeon_i2c_bus_rec *i2c_bus,
eed45b30
AD		 297 uint16_t *line_mux,
298 struct radeon_hpd *hpd)
771fe6b9 299{
9ea2c4be 300 struct radeon_device *rdev = dev->dev_private;
771fe6b9
JG		 301
302 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
303 if ((dev->pdev->device == 0x791e) &&
304 (dev->pdev->subsystem_vendor == 0x1043) &&
305 (dev->pdev->subsystem_device == 0x826d)) {
306 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
307 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
308 *connector_type = DRM_MODE_CONNECTOR_DVID;
309 }
310
c86a9038
AD		 311 /* Asrock RS600 board lists the DVI port as HDMI */
312 if ((dev->pdev->device == 0x7941) &&
313 (dev->pdev->subsystem_vendor == 0x1849) &&
314 (dev->pdev->subsystem_device == 0x7941)) {
315 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
316 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
317 *connector_type = DRM_MODE_CONNECTOR_DVID;
318 }
319
f36fce0f
AD		 320 /* MSI K9A2GM V2/V3 board has no HDMI or DVI */
321 if ((dev->pdev->device == 0x796e) &&
322 (dev->pdev->subsystem_vendor == 0x1462) &&
323 (dev->pdev->subsystem_device == 0x7302)) {
324 if ((supported_device == ATOM_DEVICE_DFP2_SUPPORT) ||
325 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
326 return false;
327 }
328
771fe6b9
JG		 329 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
330 if ((dev->pdev->device == 0x7941) &&
331 (dev->pdev->subsystem_vendor == 0x147b) &&
332 (dev->pdev->subsystem_device == 0x2412)) {
333 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
334 return false;
335 }
336
337 /* Falcon NW laptop lists vga ddc line for LVDS */
338 if ((dev->pdev->device == 0x5653) &&
339 (dev->pdev->subsystem_vendor == 0x1462) &&
340 (dev->pdev->subsystem_device == 0x0291)) {
848577ee 341 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
771fe6b9 342 i2c_bus->valid = false;
848577ee
AD		 343 *line_mux = 53;
344 }
771fe6b9
JG		 345 }
346
4e3f9b78
AD		 347 /* HIS X1300 is DVI+VGA, not DVI+DVI */
348 if ((dev->pdev->device == 0x7146) &&
349 (dev->pdev->subsystem_vendor == 0x17af) &&
350 (dev->pdev->subsystem_device == 0x2058)) {
351 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
352 return false;
353 }
354
aa1a750e
DA		 355 /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
356 if ((dev->pdev->device == 0x7142) &&
357 (dev->pdev->subsystem_vendor == 0x1458) &&
358 (dev->pdev->subsystem_device == 0x2134)) {
359 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
360 return false;
361 }
362
363
771fe6b9
JG		 364 /* Funky macbooks */
365 if ((dev->pdev->device == 0x71C5) &&
366 (dev->pdev->subsystem_vendor == 0x106b) &&
367 (dev->pdev->subsystem_device == 0x0080)) {
368 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
369 (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
370 return false;
e1e8a5dd
AD		 371 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT)
372 *line_mux = 0x90;
771fe6b9
JG		 373 }
374
771fe6b9
JG		 375 /* ASUS HD 3600 XT board lists the DVI port as HDMI */
376 if ((dev->pdev->device == 0x9598) &&
377 (dev->pdev->subsystem_vendor == 0x1043) &&
378 (dev->pdev->subsystem_device == 0x01da)) {
705af9c7 379 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
d42571ef 380 *connector_type = DRM_MODE_CONNECTOR_DVII;
705af9c7
AD		 381 }
382 }
383
e153b70b
AD		 384 /* ASUS HD 3600 board lists the DVI port as HDMI */
385 if ((dev->pdev->device == 0x9598) &&
386 (dev->pdev->subsystem_vendor == 0x1043) &&
387 (dev->pdev->subsystem_device == 0x01e4)) {
388 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
389 *connector_type = DRM_MODE_CONNECTOR_DVII;
390 }
391 }
392
705af9c7
AD		 393 /* ASUS HD 3450 board lists the DVI port as HDMI */
394 if ((dev->pdev->device == 0x95C5) &&
395 (dev->pdev->subsystem_vendor == 0x1043) &&
396 (dev->pdev->subsystem_device == 0x01e2)) {
397 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
d42571ef 398 *connector_type = DRM_MODE_CONNECTOR_DVII;
771fe6b9
JG		 399 }
400 }
401
705af9c7
AD		 402 /* some BIOSes seem to report DAC on HDMI - usually this is a board with
403 * HDMI + VGA reporting as HDMI
404 */
405 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
406 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
407 *connector_type = DRM_MODE_CONNECTOR_VGA;
408 *line_mux = 0;
409 }
410 }
411
9ea2c4be 412 /* Acer laptop reports DVI-D as DVI-I and hpd pins reversed */
3e5f8ff3
AD		 413 if ((dev->pdev->device == 0x95c4) &&
414 (dev->pdev->subsystem_vendor == 0x1025) &&
415 (dev->pdev->subsystem_device == 0x013c)) {
9ea2c4be
AD		 416 struct radeon_gpio_rec gpio;
417
3e5f8ff3 418 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
9ea2c4be
AD		 419 (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
420 gpio = radeon_lookup_gpio(rdev, 6);
421 *hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
3e5f8ff3 422 *connector_type = DRM_MODE_CONNECTOR_DVID;
9ea2c4be
AD		 423 } else if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
424 (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
425 gpio = radeon_lookup_gpio(rdev, 7);
426 *hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
427 }
3e5f8ff3
AD		 428 }
429
efa8450f
DA		 430 /* XFX Pine Group device rv730 reports no VGA DDC lines
431 * even though they are wired up to record 0x93
432 */
433 if ((dev->pdev->device == 0x9498) &&
434 (dev->pdev->subsystem_vendor == 0x1682) &&
435 (dev->pdev->subsystem_device == 0x2452)) {
436 struct radeon_device *rdev = dev->dev_private;
437 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
438 }
771fe6b9
JG		 439 return true;
440}
441
442const int supported_devices_connector_convert[] = {
443 DRM_MODE_CONNECTOR_Unknown,
444 DRM_MODE_CONNECTOR_VGA,
445 DRM_MODE_CONNECTOR_DVII,
446 DRM_MODE_CONNECTOR_DVID,
447 DRM_MODE_CONNECTOR_DVIA,
448 DRM_MODE_CONNECTOR_SVIDEO,
449 DRM_MODE_CONNECTOR_Composite,
450 DRM_MODE_CONNECTOR_LVDS,
451 DRM_MODE_CONNECTOR_Unknown,
452 DRM_MODE_CONNECTOR_Unknown,
453 DRM_MODE_CONNECTOR_HDMIA,
454 DRM_MODE_CONNECTOR_HDMIB,
455 DRM_MODE_CONNECTOR_Unknown,
456 DRM_MODE_CONNECTOR_Unknown,
457 DRM_MODE_CONNECTOR_9PinDIN,
458 DRM_MODE_CONNECTOR_DisplayPort
459};
460
b75fad06
AD		 461const uint16_t supported_devices_connector_object_id_convert[] = {
462 CONNECTOR_OBJECT_ID_NONE,
463 CONNECTOR_OBJECT_ID_VGA,
464 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
465 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
466 CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
467 CONNECTOR_OBJECT_ID_COMPOSITE,
468 CONNECTOR_OBJECT_ID_SVIDEO,
469 CONNECTOR_OBJECT_ID_LVDS,
470 CONNECTOR_OBJECT_ID_9PIN_DIN,
471 CONNECTOR_OBJECT_ID_9PIN_DIN,
472 CONNECTOR_OBJECT_ID_DISPLAYPORT,
473 CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
474 CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
475 CONNECTOR_OBJECT_ID_SVIDEO
476};
477
771fe6b9
JG		 478const int object_connector_convert[] = {
479 DRM_MODE_CONNECTOR_Unknown,
480 DRM_MODE_CONNECTOR_DVII,
481 DRM_MODE_CONNECTOR_DVII,
482 DRM_MODE_CONNECTOR_DVID,
483 DRM_MODE_CONNECTOR_DVID,
484 DRM_MODE_CONNECTOR_VGA,
485 DRM_MODE_CONNECTOR_Composite,
486 DRM_MODE_CONNECTOR_SVIDEO,
487 DRM_MODE_CONNECTOR_Unknown,
705af9c7 488 DRM_MODE_CONNECTOR_Unknown,
771fe6b9
JG		 489 DRM_MODE_CONNECTOR_9PinDIN,
490 DRM_MODE_CONNECTOR_Unknown,
491 DRM_MODE_CONNECTOR_HDMIA,
492 DRM_MODE_CONNECTOR_HDMIB,
771fe6b9
JG		 493 DRM_MODE_CONNECTOR_LVDS,
494 DRM_MODE_CONNECTOR_9PinDIN,
495 DRM_MODE_CONNECTOR_Unknown,
496 DRM_MODE_CONNECTOR_Unknown,
497 DRM_MODE_CONNECTOR_Unknown,
196c58d2
AD		 498 DRM_MODE_CONNECTOR_DisplayPort,
499 DRM_MODE_CONNECTOR_eDP,
500 DRM_MODE_CONNECTOR_Unknown
771fe6b9
JG		 501};
502
503bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
504{
505 struct radeon_device *rdev = dev->dev_private;
506 struct radeon_mode_info *mode_info = &rdev->mode_info;
507 struct atom_context *ctx = mode_info->atom_context;
508 int index = GetIndexIntoMasterTable(DATA, Object_Header);
eed45b30
AD		 509 u16 size, data_offset;
510 u8 frev, crev;
771fe6b9 511 ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
26b5bc98 512 ATOM_OBJECT_TABLE *router_obj;
771fe6b9
JG		 513 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
514 ATOM_OBJECT_HEADER *obj_header;
26b5bc98 515 int i, j, k, path_size, device_support;
771fe6b9 516 int connector_type;
eed45b30 517 u16 igp_lane_info, conn_id, connector_object_id;
771fe6b9 518 struct radeon_i2c_bus_rec ddc_bus;
26b5bc98 519 struct radeon_router router;
eed45b30
AD		 520 struct radeon_gpio_rec gpio;
521 struct radeon_hpd hpd;
522
a084e6ee 523 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
771fe6b9
JG		 524 return false;
525
526 if (crev < 2)
527 return false;
528
529 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
530 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
531 (ctx->bios + data_offset +
532 le16_to_cpu(obj_header->usDisplayPathTableOffset));
533 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
534 (ctx->bios + data_offset +
535 le16_to_cpu(obj_header->usConnectorObjectTableOffset));
26b5bc98
AD		 536 router_obj = (ATOM_OBJECT_TABLE *)
537 (ctx->bios + data_offset +
538 le16_to_cpu(obj_header->usRouterObjectTableOffset));
771fe6b9
JG		 539 device_support = le16_to_cpu(obj_header->usDeviceSupport);
540
541 path_size = 0;
542 for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
543 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
544 ATOM_DISPLAY_OBJECT_PATH *path;
545 addr += path_size;
546 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
547 path_size += le16_to_cpu(path->usSize);
5137ee94 548
771fe6b9
JG		 549 if (device_support & le16_to_cpu(path->usDeviceTag)) {
550 uint8_t con_obj_id, con_obj_num, con_obj_type;
551
552 con_obj_id =
553 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
554 >> OBJECT_ID_SHIFT;
555 con_obj_num =
556 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
557 >> ENUM_ID_SHIFT;
558 con_obj_type =
559 (le16_to_cpu(path->usConnObjectId) &
560 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
561
4bbd4973
DA		 562 /* TODO CV support */
563 if (le16_to_cpu(path->usDeviceTag) ==
564 ATOM_DEVICE_CV_SUPPORT)
771fe6b9
JG		 565 continue;
566
ee59f2b4
AD		 567 /* IGP chips */
568 if ((rdev->flags & RADEON_IS_IGP) &&
771fe6b9
JG		 569 (con_obj_id ==
570 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
571 uint16_t igp_offset = 0;
572 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
573
574 index =
575 GetIndexIntoMasterTable(DATA,
576 IntegratedSystemInfo);
577
a084e6ee
AD		 578 if (atom_parse_data_header(ctx, index, &size, &frev,
579 &crev, &igp_offset)) {
580
581 if (crev >= 2) {
582 igp_obj =
583 (ATOM_INTEGRATED_SYSTEM_INFO_V2
584 *) (ctx->bios + igp_offset);
585
586 if (igp_obj) {
587 uint32_t slot_config, ct;
588
589 if (con_obj_num == 1)
590 slot_config =
591 igp_obj->
592 ulDDISlot1Config;
593 else
594 slot_config =
595 igp_obj->
596 ulDDISlot2Config;
597
598 ct = (slot_config >> 16) & 0xff;
599 connector_type =
600 object_connector_convert
601 [ct];
602 connector_object_id = ct;
603 igp_lane_info =
604 slot_config & 0xffff;
605 } else
606 continue;
771fe6b9
JG		 607 } else
608 continue;
a084e6ee
AD		 609 } else {
610 igp_lane_info = 0;
611 connector_type =
612 object_connector_convert[con_obj_id];
613 connector_object_id = con_obj_id;
614 }
771fe6b9
JG		 615 } else {
616 igp_lane_info = 0;
617 connector_type =
618 object_connector_convert[con_obj_id];
b75fad06 619 connector_object_id = con_obj_id;
771fe6b9
JG		 620 }
621
622 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
623 continue;
624
bdd91b2b
TW		 625 router.ddc_valid = false;
626 router.cd_valid = false;
26b5bc98
AD		 627 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
628 uint8_t grph_obj_id, grph_obj_num, grph_obj_type;
771fe6b9 629
26b5bc98 630 grph_obj_id =
771fe6b9
JG		 631 (le16_to_cpu(path->usGraphicObjIds[j]) &
632 OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
26b5bc98 633 grph_obj_num =
771fe6b9
JG		 634 (le16_to_cpu(path->usGraphicObjIds[j]) &
635 ENUM_ID_MASK) >> ENUM_ID_SHIFT;
26b5bc98 636 grph_obj_type =
771fe6b9
JG		 637 (le16_to_cpu(path->usGraphicObjIds[j]) &
638 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
639
26b5bc98 640 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
5137ee94 641 u16 encoder_obj = le16_to_cpu(path->usGraphicObjIds[j]);
771fe6b9
JG		 642
643 radeon_add_atom_encoder(dev,
5137ee94 644 encoder_obj,
771fe6b9
JG		 645 le16_to_cpu
646 (path->
647 usDeviceTag));
648
26b5bc98 649 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
26b5bc98 650 for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
bdd91b2b 651 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID);
26b5bc98
AD		 652 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
653 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
654 (ctx->bios + data_offset +
655 le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
656 ATOM_I2C_RECORD *i2c_record;
657 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
658 ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
fb939dfc 659 ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path;
26b5bc98
AD		 660 ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
661 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
662 (ctx->bios + data_offset +
663 le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
664 int enum_id;
665
666 router.router_id = router_obj_id;
667 for (enum_id = 0; enum_id < router_src_dst_table->ucNumberOfDst;
668 enum_id++) {
669 if (le16_to_cpu(path->usConnObjectId) ==
670 le16_to_cpu(router_src_dst_table->usDstObjectID[enum_id]))
671 break;
672 }
673
674 while (record->ucRecordType > 0 &&
675 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
676 switch (record->ucRecordType) {
677 case ATOM_I2C_RECORD_TYPE:
678 i2c_record =
679 (ATOM_I2C_RECORD *)
680 record;
681 i2c_config =
682 (ATOM_I2C_ID_CONFIG_ACCESS *)
683 &i2c_record->sucI2cId;
684 router.i2c_info =
685 radeon_lookup_i2c_gpio(rdev,
686 i2c_config->
687 ucAccess);
688 router.i2c_addr = i2c_record->ucI2CAddr >> 1;
689 break;
690 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
691 ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
692 record;
fb939dfc
AD		 693 router.ddc_valid = true;
694 router.ddc_mux_type = ddc_path->ucMuxType;
695 router.ddc_mux_control_pin = ddc_path->ucMuxControlPin;
696 router.ddc_mux_state = ddc_path->ucMuxState[enum_id];
697 break;
698 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE:
699 cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *)
700 record;
701 router.cd_valid = true;
702 router.cd_mux_type = cd_path->ucMuxType;
703 router.cd_mux_control_pin = cd_path->ucMuxControlPin;
704 router.cd_mux_state = cd_path->ucMuxState[enum_id];
26b5bc98
AD		 705 break;
706 }
707 record = (ATOM_COMMON_RECORD_HEADER *)
708 ((char *)record + record->ucRecordSize);
709 }
710 }
711 }
771fe6b9
JG		 712 }
713 }
714
eed45b30 715 /* look up gpio for ddc, hpd */
2bfcc0fc
AD		 716 ddc_bus.valid = false;
717 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 718 if ((le16_to_cpu(path->usDeviceTag) &
eed45b30 719 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
771fe6b9
JG		 720 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
721 if (le16_to_cpu(path->usConnObjectId) ==
722 le16_to_cpu(con_obj->asObjects[j].
723 usObjectID)) {
724 ATOM_COMMON_RECORD_HEADER
725 *record =
726 (ATOM_COMMON_RECORD_HEADER
727 *)
728 (ctx->bios + data_offset +
729 le16_to_cpu(con_obj->
730 asObjects[j].
731 usRecordOffset));
732 ATOM_I2C_RECORD *i2c_record;
eed45b30 733 ATOM_HPD_INT_RECORD *hpd_record;
d3f420d1 734 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
6a93cb25 735
771fe6b9
JG		 736 while (record->ucRecordType > 0
737 && record->
738 ucRecordType <=
739 ATOM_MAX_OBJECT_RECORD_NUMBER) {
eed45b30 740 switch (record->ucRecordType) {
771fe6b9
JG		 741 case ATOM_I2C_RECORD_TYPE:
742 i2c_record =
eed45b30
AD		 743 (ATOM_I2C_RECORD *)
744 record;
d3f420d1
AD		 745 i2c_config =
746 (ATOM_I2C_ID_CONFIG_ACCESS *)
747 &i2c_record->sucI2cId;
eed45b30 748 ddc_bus = radeon_lookup_i2c_gpio(rdev,
d3f420d1
AD		 749 i2c_config->
750 ucAccess);
eed45b30
AD		 751 break;
752 case ATOM_HPD_INT_RECORD_TYPE:
753 hpd_record =
754 (ATOM_HPD_INT_RECORD *)
755 record;
756 gpio = radeon_lookup_gpio(rdev,
757 hpd_record->ucHPDIntGPIOID);
758 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
759 hpd.plugged_state = hpd_record->ucPlugged_PinState;
771fe6b9
JG		 760 break;
761 }
762 record =
763 (ATOM_COMMON_RECORD_HEADER
764 *) ((char *)record
765 +
766 record->
767 ucRecordSize);
768 }
769 break;
770 }
771 }
eed45b30 772 }
771fe6b9 773
bcc1c2a1 774 /* needed for aux chan transactions */
8e36ed00 775 ddc_bus.hpd = hpd.hpd;
bcc1c2a1 776
705af9c7
AD		 777 conn_id = le16_to_cpu(path->usConnObjectId);
778
779 if (!radeon_atom_apply_quirks
780 (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
eed45b30 781 &ddc_bus, &conn_id, &hpd))
705af9c7
AD		 782 continue;
783
771fe6b9 784 radeon_add_atom_connector(dev,
705af9c7 785 conn_id,
771fe6b9
JG		 786 le16_to_cpu(path->
787 usDeviceTag),
788 connector_type, &ddc_bus,
5137ee94 789 igp_lane_info,
eed45b30 790 connector_object_id,
26b5bc98
AD		 791 &hpd,
792 &router);
771fe6b9
JG		 793
794 }
795 }
796
797 radeon_link_encoder_connector(dev);
798
799 return true;
800}
801
b75fad06
AD		 802static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
803 int connector_type,
804 uint16_t devices)
805{
806 struct radeon_device *rdev = dev->dev_private;
807
808 if (rdev->flags & RADEON_IS_IGP) {
809 return supported_devices_connector_object_id_convert
810 [connector_type];
811 } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
812 (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
813 (devices & ATOM_DEVICE_DFP2_SUPPORT)) {
814 struct radeon_mode_info *mode_info = &rdev->mode_info;
815 struct atom_context *ctx = mode_info->atom_context;
816 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
817 uint16_t size, data_offset;
818 uint8_t frev, crev;
819 ATOM_XTMDS_INFO *xtmds;
820
a084e6ee
AD		 821 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) {
822 xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
b75fad06 823
a084e6ee
AD		 824 if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
825 if (connector_type == DRM_MODE_CONNECTOR_DVII)
826 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
827 else
828 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
829 } else {
830 if (connector_type == DRM_MODE_CONNECTOR_DVII)
831 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
832 else
833 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
834 }
835 } else
836 return supported_devices_connector_object_id_convert
837 [connector_type];
b75fad06
AD		 838 } else {
839 return supported_devices_connector_object_id_convert
840 [connector_type];
841 }
842}
843
771fe6b9
JG		 844struct bios_connector {
845 bool valid;
705af9c7 846 uint16_t line_mux;
771fe6b9
JG		 847 uint16_t devices;
848 int connector_type;
849 struct radeon_i2c_bus_rec ddc_bus;
eed45b30 850 struct radeon_hpd hpd;
771fe6b9
JG		 851};
852
853bool radeon_get_atom_connector_info_from_supported_devices_table(struct
854 drm_device
855 *dev)
856{
857 struct radeon_device *rdev = dev->dev_private;
858 struct radeon_mode_info *mode_info = &rdev->mode_info;
859 struct atom_context *ctx = mode_info->atom_context;
860 int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
861 uint16_t size, data_offset;
862 uint8_t frev, crev;
863 uint16_t device_support;
864 uint8_t dac;
865 union atom_supported_devices *supported_devices;
eed45b30 866 int i, j, max_device;
f49d273d
PB		 867 struct bios_connector *bios_connectors;
868 size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE;
26b5bc98
AD		 869 struct radeon_router router;
870
fb939dfc
AD		 871 router.ddc_valid = false;
872 router.cd_valid = false;
771fe6b9 873
f49d273d
PB		 874 bios_connectors = kzalloc(bc_size, GFP_KERNEL);
875 if (!bios_connectors)
876 return false;
877
878 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev,
879 &data_offset)) {
880 kfree(bios_connectors);
a084e6ee 881 return false;
f49d273d 882 }
771fe6b9
JG		 883
884 supported_devices =
885 (union atom_supported_devices *)(ctx->bios + data_offset);
886
887 device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
888
eed45b30
AD		 889 if (frev > 1)
890 max_device = ATOM_MAX_SUPPORTED_DEVICE;
891 else
892 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
893
894 for (i = 0; i < max_device; i++) {
771fe6b9
JG		 895 ATOM_CONNECTOR_INFO_I2C ci =
896 supported_devices->info.asConnInfo[i];
897
898 bios_connectors[i].valid = false;
899
900 if (!(device_support & (1 << i))) {
901 continue;
902 }
903
904 if (i == ATOM_DEVICE_CV_INDEX) {
d9fdaafb 905 DRM_DEBUG_KMS("Skipping Component Video\n");
771fe6b9
JG		 906 continue;
907 }
908
771fe6b9
JG		 909 bios_connectors[i].connector_type =
910 supported_devices_connector_convert[ci.sucConnectorInfo.
911 sbfAccess.
912 bfConnectorType];
913
914 if (bios_connectors[i].connector_type ==
915 DRM_MODE_CONNECTOR_Unknown)
916 continue;
917
918 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
919
d3f420d1
AD		 920 bios_connectors[i].line_mux =
921 ci.sucI2cId.ucAccess;
771fe6b9
JG		 922
923 /* give tv unique connector ids */
924 if (i == ATOM_DEVICE_TV1_INDEX) {
925 bios_connectors[i].ddc_bus.valid = false;
926 bios_connectors[i].line_mux = 50;
927 } else if (i == ATOM_DEVICE_TV2_INDEX) {
928 bios_connectors[i].ddc_bus.valid = false;
929 bios_connectors[i].line_mux = 51;
930 } else if (i == ATOM_DEVICE_CV_INDEX) {
931 bios_connectors[i].ddc_bus.valid = false;
932 bios_connectors[i].line_mux = 52;
933 } else
934 bios_connectors[i].ddc_bus =
eed45b30
AD		 935 radeon_lookup_i2c_gpio(rdev,
936 bios_connectors[i].line_mux);
937
938 if ((crev > 1) && (frev > 1)) {
939 u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
940 switch (isb) {
941 case 0x4:
942 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
943 break;
944 case 0xa:
945 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
946 break;
947 default:
948 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
949 break;
950 }
951 } else {
952 if (i == ATOM_DEVICE_DFP1_INDEX)
953 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
954 else if (i == ATOM_DEVICE_DFP2_INDEX)
955 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
956 else
957 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
958 }
771fe6b9
JG		 959
960 /* Always set the connector type to VGA for CRT1/CRT2. if they are
961 * shared with a DVI port, we'll pick up the DVI connector when we
962 * merge the outputs. Some bioses incorrectly list VGA ports as DVI.
963 */
964 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
965 bios_connectors[i].connector_type =
966 DRM_MODE_CONNECTOR_VGA;
967
968 if (!radeon_atom_apply_quirks
969 (dev, (1 << i), &bios_connectors[i].connector_type,
eed45b30
AD		 970 &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
971 &bios_connectors[i].hpd))
771fe6b9
JG		 972 continue;
973
974 bios_connectors[i].valid = true;
975 bios_connectors[i].devices = (1 << i);
976
977 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
978 radeon_add_atom_encoder(dev,
5137ee94 979 radeon_get_encoder_enum(dev,
771fe6b9
JG		 980 (1 << i),
981 dac),
982 (1 << i));
983 else
984 radeon_add_legacy_encoder(dev,
5137ee94 985 radeon_get_encoder_enum(dev,
f56cd64f 986 (1 << i),
771fe6b9
JG		 987 dac),
988 (1 << i));
989 }
990
991 /* combine shared connectors */
eed45b30 992 for (i = 0; i < max_device; i++) {
771fe6b9 993 if (bios_connectors[i].valid) {
eed45b30 994 for (j = 0; j < max_device; j++) {
771fe6b9
JG		 995 if (bios_connectors[j].valid && (i != j)) {
996 if (bios_connectors[i].line_mux ==
997 bios_connectors[j].line_mux) {
f56cd64f
AD		 998 /* make sure not to combine LVDS */
999 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1000 bios_connectors[i].line_mux = 53;
1001 bios_connectors[i].ddc_bus.valid = false;
1002 continue;
1003 }
1004 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1005 bios_connectors[j].line_mux = 53;
1006 bios_connectors[j].ddc_bus.valid = false;
1007 continue;
1008 }
1009 /* combine analog and digital for DVI-I */
1010 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1011 (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
1012 ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1013 (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
1014 bios_connectors[i].devices |=
1015 bios_connectors[j].devices;
1016 bios_connectors[i].connector_type =
1017 DRM_MODE_CONNECTOR_DVII;
1018 if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
eed45b30
AD		 1019 bios_connectors[i].hpd =
1020 bios_connectors[j].hpd;
f56cd64f 1021 bios_connectors[j].valid = false;
771fe6b9
JG		 1022 }
1023 }
1024 }
1025 }
1026 }
1027 }
1028
1029 /* add the connectors */
eed45b30 1030 for (i = 0; i < max_device; i++) {
b75fad06
AD		 1031 if (bios_connectors[i].valid) {
1032 uint16_t connector_object_id =
1033 atombios_get_connector_object_id(dev,
1034 bios_connectors[i].connector_type,
1035 bios_connectors[i].devices);
771fe6b9
JG		 1036 radeon_add_atom_connector(dev,
1037 bios_connectors[i].line_mux,
1038 bios_connectors[i].devices,
1039 bios_connectors[i].
1040 connector_type,
1041 &bios_connectors[i].ddc_bus,
5137ee94 1042 0,
eed45b30 1043 connector_object_id,
26b5bc98
AD		 1044 &bios_connectors[i].hpd,
1045 &router);
b75fad06 1046 }
771fe6b9
JG		 1047 }
1048
1049 radeon_link_encoder_connector(dev);
1050
f49d273d 1051 kfree(bios_connectors);
771fe6b9
JG		 1052 return true;
1053}
1054
1055union firmware_info {
1056 ATOM_FIRMWARE_INFO info;
1057 ATOM_FIRMWARE_INFO_V1_2 info_12;
1058 ATOM_FIRMWARE_INFO_V1_3 info_13;
1059 ATOM_FIRMWARE_INFO_V1_4 info_14;
bcc1c2a1 1060 ATOM_FIRMWARE_INFO_V2_1 info_21;
771fe6b9
JG		 1061};
1062
1063bool radeon_atom_get_clock_info(struct drm_device *dev)
1064{
1065 struct radeon_device *rdev = dev->dev_private;
1066 struct radeon_mode_info *mode_info = &rdev->mode_info;
1067 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
1068 union firmware_info *firmware_info;
1069 uint8_t frev, crev;
1070 struct radeon_pll *p1pll = &rdev->clock.p1pll;
1071 struct radeon_pll *p2pll = &rdev->clock.p2pll;
bcc1c2a1 1072 struct radeon_pll *dcpll = &rdev->clock.dcpll;
771fe6b9
JG		 1073 struct radeon_pll *spll = &rdev->clock.spll;
1074 struct radeon_pll *mpll = &rdev->clock.mpll;
1075 uint16_t data_offset;
1076
a084e6ee
AD		 1077 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1078 &frev, &crev, &data_offset)) {
1079 firmware_info =
1080 (union firmware_info *)(mode_info->atom_context->bios +
1081 data_offset);
771fe6b9
JG		 1082 /* pixel clocks */
1083 p1pll->reference_freq =
1084 le16_to_cpu(firmware_info->info.usReferenceClock);
1085 p1pll->reference_div = 0;
1086
bc293e58
MF		 1087 if (crev < 2)
1088 p1pll->pll_out_min =
1089 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
1090 else
1091 p1pll->pll_out_min =
1092 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
771fe6b9
JG		 1093 p1pll->pll_out_max =
1094 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
1095
86cb2bbf
AD		 1096 if (crev >= 4) {
1097 p1pll->lcd_pll_out_min =
1098 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
1099 if (p1pll->lcd_pll_out_min == 0)
1100 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1101 p1pll->lcd_pll_out_max =
1102 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
1103 if (p1pll->lcd_pll_out_max == 0)
1104 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1105 } else {
1106 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1107 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1108 }
1109
771fe6b9
JG		 1110 if (p1pll->pll_out_min == 0) {
1111 if (ASIC_IS_AVIVO(rdev))
1112 p1pll->pll_out_min = 64800;
1113 else
1114 p1pll->pll_out_min = 20000;
8f552a66
AD		 1115 } else if (p1pll->pll_out_min > 64800) {
1116 /* Limiting the pll output range is a good thing generally as
1117 * it limits the number of possible pll combinations for a given
1118 * frequency presumably to the ones that work best on each card.
1119 * However, certain duallink DVI monitors seem to like
1120 * pll combinations that would be limited by this at least on
1121 * pre-DCE 3.0 r6xx hardware. This might need to be adjusted per
1122 * family.
1123 */
48dfaaeb 1124 p1pll->pll_out_min = 64800;
771fe6b9
JG		 1125 }
1126
1127 p1pll->pll_in_min =
1128 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
1129 p1pll->pll_in_max =
1130 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
1131
1132 *p2pll = *p1pll;
1133
1134 /* system clock */
1135 spll->reference_freq =
1136 le16_to_cpu(firmware_info->info.usReferenceClock);
1137 spll->reference_div = 0;
1138
1139 spll->pll_out_min =
1140 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
1141 spll->pll_out_max =
1142 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
1143
1144 /* ??? */
1145 if (spll->pll_out_min == 0) {
1146 if (ASIC_IS_AVIVO(rdev))
1147 spll->pll_out_min = 64800;
1148 else
1149 spll->pll_out_min = 20000;
1150 }
1151
1152 spll->pll_in_min =
1153 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
1154 spll->pll_in_max =
1155 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
1156
1157 /* memory clock */
1158 mpll->reference_freq =
1159 le16_to_cpu(firmware_info->info.usReferenceClock);
1160 mpll->reference_div = 0;
1161
1162 mpll->pll_out_min =
1163 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
1164 mpll->pll_out_max =
1165 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
1166
1167 /* ??? */
1168 if (mpll->pll_out_min == 0) {
1169 if (ASIC_IS_AVIVO(rdev))
1170 mpll->pll_out_min = 64800;
1171 else
1172 mpll->pll_out_min = 20000;
1173 }
1174
1175 mpll->pll_in_min =
1176 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
1177 mpll->pll_in_max =
1178 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
1179
1180 rdev->clock.default_sclk =
1181 le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
1182 rdev->clock.default_mclk =
1183 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
1184
bcc1c2a1
AD		 1185 if (ASIC_IS_DCE4(rdev)) {
1186 rdev->clock.default_dispclk =
1187 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
1188 if (rdev->clock.default_dispclk == 0)
1189 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1190 rdev->clock.dp_extclk =
1191 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
1192 }
1193 *dcpll = *p1pll;
1194
771fe6b9
JG		 1195 return true;
1196 }
bcc1c2a1 1197
771fe6b9
JG		 1198 return false;
1199}
1200
06b6476d
AD		 1201union igp_info {
1202 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1203 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1204};
1205
1206bool radeon_atombios_sideport_present(struct radeon_device *rdev)
1207{
1208 struct radeon_mode_info *mode_info = &rdev->mode_info;
1209 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1210 union igp_info *igp_info;
1211 u8 frev, crev;
1212 u16 data_offset;
1213
4c70b2ea
AD		 1214 /* sideport is AMD only */
1215 if (rdev->family == CHIP_RS600)
1216 return false;
1217
a084e6ee
AD		 1218 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1219 &frev, &crev, &data_offset)) {
1220 igp_info = (union igp_info *)(mode_info->atom_context->bios +
06b6476d 1221 data_offset);
06b6476d
AD		 1222 switch (crev) {
1223 case 1:
4c70b2ea
AD		 1224 if (igp_info->info.ulBootUpMemoryClock)
1225 return true;
06b6476d
AD		 1226 break;
1227 case 2:
4b80d954 1228 if (igp_info->info_2.ulBootUpSidePortClock)
06b6476d
AD		 1229 return true;
1230 break;
1231 default:
1232 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1233 break;
1234 }
1235 }
1236 return false;
1237}
1238
445282db
DA		 1239bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
1240 struct radeon_encoder_int_tmds *tmds)
771fe6b9
JG		 1241{
1242 struct drm_device *dev = encoder->base.dev;
1243 struct radeon_device *rdev = dev->dev_private;
1244 struct radeon_mode_info *mode_info = &rdev->mode_info;
1245 int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
1246 uint16_t data_offset;
1247 struct _ATOM_TMDS_INFO *tmds_info;
1248 uint8_t frev, crev;
1249 uint16_t maxfreq;
1250 int i;
771fe6b9 1251
a084e6ee
AD		 1252 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1253 &frev, &crev, &data_offset)) {
1254 tmds_info =
1255 (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
1256 data_offset);
771fe6b9 1257
771fe6b9
JG		 1258 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
1259 for (i = 0; i < 4; i++) {
1260 tmds->tmds_pll[i].freq =
1261 le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
1262 tmds->tmds_pll[i].value =
1263 tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
1264 tmds->tmds_pll[i].value |=
1265 (tmds_info->asMiscInfo[i].
1266 ucPLL_VCO_Gain & 0x3f) << 6;
1267 tmds->tmds_pll[i].value |=
1268 (tmds_info->asMiscInfo[i].
1269 ucPLL_DutyCycle & 0xf) << 12;
1270 tmds->tmds_pll[i].value |=
1271 (tmds_info->asMiscInfo[i].
1272 ucPLL_VoltageSwing & 0xf) << 16;
1273
d9fdaafb 1274 DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n",
771fe6b9
JG		 1275 tmds->tmds_pll[i].freq,
1276 tmds->tmds_pll[i].value);
1277
1278 if (maxfreq == tmds->tmds_pll[i].freq) {
1279 tmds->tmds_pll[i].freq = 0xffffffff;
1280 break;
1281 }
1282 }
445282db 1283 return true;
771fe6b9 1284 }
445282db 1285 return false;
771fe6b9
JG		 1286}
1287
ba032a58
AD		 1288bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
1289 struct radeon_atom_ss *ss,
1290 int id)
ebbe1cb9 1291{
ebbe1cb9
AD		 1292 struct radeon_mode_info *mode_info = &rdev->mode_info;
1293 int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
ba032a58 1294 uint16_t data_offset, size;
ebbe1cb9
AD		 1295 struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1296 uint8_t frev, crev;
ba032a58 1297 int i, num_indices;
ebbe1cb9 1298
ba032a58
AD		 1299 memset(ss, 0, sizeof(struct radeon_atom_ss));
1300 if (atom_parse_data_header(mode_info->atom_context, index, &size,
a084e6ee
AD		 1301 &frev, &crev, &data_offset)) {
1302 ss_info =
1303 (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
ebbe1cb9 1304
ba032a58
AD		 1305 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1306 sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT);
ebbe1cb9 1307
ba032a58 1308 for (i = 0; i < num_indices; i++) {
279b215e
AD		 1309 if (ss_info->asSS_Info[i].ucSS_Id == id) {
1310 ss->percentage =
1311 le16_to_cpu(ss_info->asSS_Info[i].usSpreadSpectrumPercentage);
1312 ss->type = ss_info->asSS_Info[i].ucSpreadSpectrumType;
1313 ss->step = ss_info->asSS_Info[i].ucSS_Step;
1314 ss->delay = ss_info->asSS_Info[i].ucSS_Delay;
1315 ss->range = ss_info->asSS_Info[i].ucSS_Range;
1316 ss->refdiv = ss_info->asSS_Info[i].ucRecommendedRef_Div;
ba032a58
AD		 1317 return true;
1318 }
1319 }
1320 }
1321 return false;
1322}
1323
1324union asic_ss_info {
1325 struct _ATOM_ASIC_INTERNAL_SS_INFO info;
1326 struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2;
1327 struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3;
1328};
1329
1330bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
1331 struct radeon_atom_ss *ss,
1332 int id, u32 clock)
1333{
1334 struct radeon_mode_info *mode_info = &rdev->mode_info;
1335 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
1336 uint16_t data_offset, size;
1337 union asic_ss_info *ss_info;
1338 uint8_t frev, crev;
1339 int i, num_indices;
1340
1341 memset(ss, 0, sizeof(struct radeon_atom_ss));
1342 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1343 &frev, &crev, &data_offset)) {
1344
1345 ss_info =
1346 (union asic_ss_info *)(mode_info->atom_context->bios + data_offset);
1347
1348 switch (frev) {
1349 case 1:
1350 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1351 sizeof(ATOM_ASIC_SS_ASSIGNMENT);
1352
1353 for (i = 0; i < num_indices; i++) {
1354 if ((ss_info->info.asSpreadSpectrum[i].ucClockIndication == id) &&
1355 (clock <= ss_info->info.asSpreadSpectrum[i].ulTargetClockRange)) {
1356 ss->percentage =
1357 le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1358 ss->type = ss_info->info.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1359 ss->rate = le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadRateInKhz);
1360 return true;
1361 }
279b215e 1362 }
ba032a58
AD		 1363 break;
1364 case 2:
1365 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1366 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
1367 for (i = 0; i < num_indices; i++) {
1368 if ((ss_info->info_2.asSpreadSpectrum[i].ucClockIndication == id) &&
1369 (clock <= ss_info->info_2.asSpreadSpectrum[i].ulTargetClockRange)) {
1370 ss->percentage =
1371 le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1372 ss->type = ss_info->info_2.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1373 ss->rate = le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadRateIn10Hz);
1374 return true;
1375 }
1376 }
1377 break;
1378 case 3:
1379 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1380 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
1381 for (i = 0; i < num_indices; i++) {
1382 if ((ss_info->info_3.asSpreadSpectrum[i].ucClockIndication == id) &&
1383 (clock <= ss_info->info_3.asSpreadSpectrum[i].ulTargetClockRange)) {
1384 ss->percentage =
1385 le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1386 ss->type = ss_info->info_3.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1387 ss->rate = le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadRateIn10Hz);
1388 return true;
1389 }
1390 }
1391 break;
1392 default:
1393 DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev);
1394 break;
279b215e 1395 }
ba032a58 1396
ebbe1cb9 1397 }
ba032a58 1398 return false;
ebbe1cb9
AD		 1399}
1400
771fe6b9
JG		 1401union lvds_info {
1402 struct _ATOM_LVDS_INFO info;
1403 struct _ATOM_LVDS_INFO_V12 info_12;
1404};
1405
1406struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1407 radeon_encoder
1408 *encoder)
1409{
1410 struct drm_device *dev = encoder->base.dev;
1411 struct radeon_device *rdev = dev->dev_private;
1412 struct radeon_mode_info *mode_info = &rdev->mode_info;
1413 int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
7dde8a19 1414 uint16_t data_offset, misc;
771fe6b9
JG		 1415 union lvds_info *lvds_info;
1416 uint8_t frev, crev;
1417 struct radeon_encoder_atom_dig *lvds = NULL;
5137ee94 1418 int encoder_enum = (encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
771fe6b9 1419
a084e6ee
AD		 1420 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1421 &frev, &crev, &data_offset)) {
1422 lvds_info =
1423 (union lvds_info *)(mode_info->atom_context->bios + data_offset);
771fe6b9
JG		 1424 lvds =
1425 kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1426
1427 if (!lvds)
1428 return NULL;
1429
de2103e4 1430 lvds->native_mode.clock =
771fe6b9 1431 le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
de2103e4 1432 lvds->native_mode.hdisplay =
771fe6b9 1433 le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
de2103e4 1434 lvds->native_mode.vdisplay =
771fe6b9 1435 le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
de2103e4
AD		 1436 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1437 le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1438 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1439 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1440 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1441 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1442 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1443 le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1444 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1ff26a36 1445 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
de2103e4
AD		 1446 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1447 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
771fe6b9
JG		 1448 lvds->panel_pwr_delay =
1449 le16_to_cpu(lvds_info->info.usOffDelayInMs);
ba032a58 1450 lvds->lcd_misc = lvds_info->info.ucLVDS_Misc;
7dde8a19
AD		 1451
1452 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1453 if (misc & ATOM_VSYNC_POLARITY)
1454 lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1455 if (misc & ATOM_HSYNC_POLARITY)
1456 lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1457 if (misc & ATOM_COMPOSITESYNC)
1458 lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1459 if (misc & ATOM_INTERLACE)
1460 lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1461 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1462 lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1463
de2103e4
AD		 1464 /* set crtc values */
1465 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
771fe6b9 1466
ba032a58 1467 lvds->lcd_ss_id = lvds_info->info.ucSS_Id;
ebbe1cb9 1468
771fe6b9 1469 encoder->native_mode = lvds->native_mode;
5137ee94
AD		 1470
1471 if (encoder_enum == 2)
1472 lvds->linkb = true;
1473 else
1474 lvds->linkb = false;
1475
771fe6b9
JG		 1476 }
1477 return lvds;
1478}
1479
6fe7ac3f
AD		 1480struct radeon_encoder_primary_dac *
1481radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1482{
1483 struct drm_device *dev = encoder->base.dev;
1484 struct radeon_device *rdev = dev->dev_private;
1485 struct radeon_mode_info *mode_info = &rdev->mode_info;
1486 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1487 uint16_t data_offset;
1488 struct _COMPASSIONATE_DATA *dac_info;
1489 uint8_t frev, crev;
1490 uint8_t bg, dac;
6fe7ac3f
AD		 1491 struct radeon_encoder_primary_dac *p_dac = NULL;
1492
a084e6ee
AD		 1493 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1494 &frev, &crev, &data_offset)) {
1495 dac_info = (struct _COMPASSIONATE_DATA *)
1496 (mode_info->atom_context->bios + data_offset);
6fe7ac3f 1497
6fe7ac3f
AD		 1498 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
1499
1500 if (!p_dac)
1501 return NULL;
1502
1503 bg = dac_info->ucDAC1_BG_Adjustment;
1504 dac = dac_info->ucDAC1_DAC_Adjustment;
1505 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1506
1507 }
1508 return p_dac;
1509}
1510
4ce001ab 1511bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
5a9bcacc 1512 struct drm_display_mode *mode)
4ce001ab
DA		 1513{
1514 struct radeon_mode_info *mode_info = &rdev->mode_info;
1515 ATOM_ANALOG_TV_INFO *tv_info;
1516 ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1517 ATOM_DTD_FORMAT *dtd_timings;
1518 int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1519 u8 frev, crev;
5a9bcacc 1520 u16 data_offset, misc;
4ce001ab 1521
a084e6ee
AD		 1522 if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL,
1523 &frev, &crev, &data_offset))
1524 return false;
4ce001ab
DA		 1525
1526 switch (crev) {
1527 case 1:
1528 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
0031c41b 1529 if (index >= MAX_SUPPORTED_TV_TIMING)
4ce001ab
DA		 1530 return false;
1531
5a9bcacc
AD		 1532 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1533 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1534 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1535 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1536 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1537
1538 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1539 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1540 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1541 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1542 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1543
1544 mode->flags = 0;
1545 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1546 if (misc & ATOM_VSYNC_POLARITY)
1547 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1548 if (misc & ATOM_HSYNC_POLARITY)
1549 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1550 if (misc & ATOM_COMPOSITESYNC)
1551 mode->flags |= DRM_MODE_FLAG_CSYNC;
1552 if (misc & ATOM_INTERLACE)
1553 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1554 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1555 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1556
1557 mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
4ce001ab
DA		 1558
1559 if (index == 1) {
1560 /* PAL timings appear to have wrong values for totals */
5a9bcacc
AD		 1561 mode->crtc_htotal -= 1;
1562 mode->crtc_vtotal -= 1;
4ce001ab
DA		 1563 }
1564 break;
1565 case 2:
1566 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
0031c41b 1567 if (index >= MAX_SUPPORTED_TV_TIMING_V1_2)
4ce001ab
DA		 1568 return false;
1569
1570 dtd_timings = &tv_info_v1_2->aModeTimings[index];
5a9bcacc
AD		 1571 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1572 le16_to_cpu(dtd_timings->usHBlanking_Time);
1573 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1574 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1575 le16_to_cpu(dtd_timings->usHSyncOffset);
1576 mode->crtc_hsync_end = mode->crtc_hsync_start +
1577 le16_to_cpu(dtd_timings->usHSyncWidth);
1578
1579 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1580 le16_to_cpu(dtd_timings->usVBlanking_Time);
1581 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1582 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1583 le16_to_cpu(dtd_timings->usVSyncOffset);
1584 mode->crtc_vsync_end = mode->crtc_vsync_start +
1585 le16_to_cpu(dtd_timings->usVSyncWidth);
1586
1587 mode->flags = 0;
1588 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1589 if (misc & ATOM_VSYNC_POLARITY)
1590 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1591 if (misc & ATOM_HSYNC_POLARITY)
1592 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1593 if (misc & ATOM_COMPOSITESYNC)
1594 mode->flags |= DRM_MODE_FLAG_CSYNC;
1595 if (misc & ATOM_INTERLACE)
1596 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1597 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1598 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1599
1600 mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
4ce001ab
DA		 1601 break;
1602 }
1603 return true;
1604}
1605
d79766fa
AD		 1606enum radeon_tv_std
1607radeon_atombios_get_tv_info(struct radeon_device *rdev)
1608{
1609 struct radeon_mode_info *mode_info = &rdev->mode_info;
1610 int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1611 uint16_t data_offset;
1612 uint8_t frev, crev;
1613 struct _ATOM_ANALOG_TV_INFO *tv_info;
1614 enum radeon_tv_std tv_std = TV_STD_NTSC;
1615
a084e6ee
AD		 1616 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1617 &frev, &crev, &data_offset)) {
d79766fa 1618
a084e6ee
AD		 1619 tv_info = (struct _ATOM_ANALOG_TV_INFO *)
1620 (mode_info->atom_context->bios + data_offset);
d79766fa 1621
a084e6ee
AD		 1622 switch (tv_info->ucTV_BootUpDefaultStandard) {
1623 case ATOM_TV_NTSC:
1624 tv_std = TV_STD_NTSC;
40f76d81 1625 DRM_DEBUG_KMS("Default TV standard: NTSC\n");
a084e6ee
AD		 1626 break;
1627 case ATOM_TV_NTSCJ:
1628 tv_std = TV_STD_NTSC_J;
40f76d81 1629 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
a084e6ee
AD		 1630 break;
1631 case ATOM_TV_PAL:
1632 tv_std = TV_STD_PAL;
40f76d81 1633 DRM_DEBUG_KMS("Default TV standard: PAL\n");
a084e6ee
AD		 1634 break;
1635 case ATOM_TV_PALM:
1636 tv_std = TV_STD_PAL_M;
40f76d81 1637 DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
a084e6ee
AD		 1638 break;
1639 case ATOM_TV_PALN:
1640 tv_std = TV_STD_PAL_N;
40f76d81 1641 DRM_DEBUG_KMS("Default TV standard: PAL-N\n");
a084e6ee
AD		 1642 break;
1643 case ATOM_TV_PALCN:
1644 tv_std = TV_STD_PAL_CN;
40f76d81 1645 DRM_DEBUG_KMS("Default TV standard: PAL-CN\n");
a084e6ee
AD		 1646 break;
1647 case ATOM_TV_PAL60:
1648 tv_std = TV_STD_PAL_60;
40f76d81 1649 DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
a084e6ee
AD		 1650 break;
1651 case ATOM_TV_SECAM:
1652 tv_std = TV_STD_SECAM;
40f76d81 1653 DRM_DEBUG_KMS("Default TV standard: SECAM\n");
a084e6ee
AD		 1654 break;
1655 default:
1656 tv_std = TV_STD_NTSC;
40f76d81 1657 DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n");
a084e6ee
AD		 1658 break;
1659 }
d79766fa
AD		 1660 }
1661 return tv_std;
1662}
1663
6fe7ac3f
AD		 1664struct radeon_encoder_tv_dac *
1665radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1666{
1667 struct drm_device *dev = encoder->base.dev;
1668 struct radeon_device *rdev = dev->dev_private;
1669 struct radeon_mode_info *mode_info = &rdev->mode_info;
1670 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1671 uint16_t data_offset;
1672 struct _COMPASSIONATE_DATA *dac_info;
1673 uint8_t frev, crev;
1674 uint8_t bg, dac;
6fe7ac3f
AD		 1675 struct radeon_encoder_tv_dac *tv_dac = NULL;
1676
a084e6ee
AD		 1677 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1678 &frev, &crev, &data_offset)) {
6fe7ac3f 1679
a084e6ee
AD		 1680 dac_info = (struct _COMPASSIONATE_DATA *)
1681 (mode_info->atom_context->bios + data_offset);
6fe7ac3f 1682
6fe7ac3f
AD		 1683 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1684
1685 if (!tv_dac)
1686 return NULL;
1687
1688 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1689 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1690 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1691
1692 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1693 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1694 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1695
1696 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1697 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1698 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1699
d79766fa 1700 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
6fe7ac3f
AD		 1701 }
1702 return tv_dac;
1703}
1704
29fb52ca
AD		 1705static const char *thermal_controller_names[] = {
1706 "NONE",
678e7dfa
AD		 1707 "lm63",
1708 "adm1032",
1709 "adm1030",
1710 "max6649",
1711 "lm64",
1712 "f75375",
1713 "asc7xxx",
29fb52ca
AD		 1714};
1715
1716static const char *pp_lib_thermal_controller_names[] = {
1717 "NONE",
678e7dfa
AD		 1718 "lm63",
1719 "adm1032",
1720 "adm1030",
1721 "max6649",
1722 "lm64",
1723 "f75375",
29fb52ca
AD		 1724 "RV6xx",
1725 "RV770",
678e7dfa 1726 "adt7473",
49f65982
AD		 1727 "External GPIO",
1728 "Evergreen",
678e7dfa 1729 "adt7473 with internal",
49f65982 1730
29fb52ca
AD		 1731};
1732
56278a8e
AD		 1733union power_info {
1734 struct _ATOM_POWERPLAY_INFO info;
1735 struct _ATOM_POWERPLAY_INFO_V2 info_2;
1736 struct _ATOM_POWERPLAY_INFO_V3 info_3;
1737 struct _ATOM_PPLIB_POWERPLAYTABLE info_4;
1738};
1739
1740void radeon_atombios_get_power_modes(struct radeon_device *rdev)
771fe6b9 1741{
56278a8e
AD		 1742 struct radeon_mode_info *mode_info = &rdev->mode_info;
1743 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
1744 u16 data_offset;
1745 u8 frev, crev;
1746 u32 misc, misc2 = 0, sclk, mclk;
1747 union power_info *power_info;
1748 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
1749 struct _ATOM_PPLIB_STATE *power_state;
1750 int num_modes = 0, i, j;
1751 int state_index = 0, mode_index = 0;
29fb52ca 1752 struct radeon_i2c_bus_rec i2c_bus;
771fe6b9 1753
a48b9b4e 1754 rdev->pm.default_power_state_index = -1;
56278a8e 1755
a084e6ee
AD		 1756 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1757 &frev, &crev, &data_offset)) {
1758 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
56278a8e 1759 if (frev < 4) {
29fb52ca
AD		 1760 /* add the i2c bus for thermal/fan chip */
1761 if (power_info->info.ucOverdriveThermalController > 0) {
1762 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
1763 thermal_controller_names[power_info->info.ucOverdriveThermalController],
1764 power_info->info.ucOverdriveControllerAddress >> 1);
1765 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
f376b94f 1766 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
678e7dfa
AD		 1767 if (rdev->pm.i2c_bus) {
1768 struct i2c_board_info info = { };
1769 const char *name = thermal_controller_names[power_info->info.
1770 ucOverdriveThermalController];
1771 info.addr = power_info->info.ucOverdriveControllerAddress >> 1;
1772 strlcpy(info.type, name, sizeof(info.type));
1773 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
1774 }
29fb52ca 1775 }
56278a8e
AD		 1776 num_modes = power_info->info.ucNumOfPowerModeEntries;
1777 if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
1778 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
02b17cc0 1779 /* last mode is usually default, array is low to high */
56278a8e
AD		 1780 for (i = 0; i < num_modes; i++) {
1781 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
1782 switch (frev) {
1783 case 1:
1784 rdev->pm.power_state[state_index].num_clock_modes = 1;
1785 rdev->pm.power_state[state_index].clock_info[0].mclk =
1786 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
1787 rdev->pm.power_state[state_index].clock_info[0].sclk =
1788 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
1789 /* skip invalid modes */
1790 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1791 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1792 continue;
79daedc9 1793 rdev->pm.power_state[state_index].pcie_lanes =
56278a8e
AD		 1794 power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
1795 misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
84d88f4c
AD		 1796 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
1797 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
56278a8e
AD		 1798 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1799 VOLTAGE_GPIO;
1800 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1801 radeon_lookup_gpio(rdev,
1802 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
1803 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1804 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1805 true;
1806 else
1807 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1808 false;
1809 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1810 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1811 VOLTAGE_VDDC;
1812 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1813 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
1814 }
d7311171 1815 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
79daedc9 1816 rdev->pm.power_state[state_index].misc = misc;
0ec0e74f
AD		 1817 /* order matters! */
1818 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1819 rdev->pm.power_state[state_index].type =
1820 POWER_STATE_TYPE_POWERSAVE;
1821 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1822 rdev->pm.power_state[state_index].type =
1823 POWER_STATE_TYPE_BATTERY;
1824 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1825 rdev->pm.power_state[state_index].type =
1826 POWER_STATE_TYPE_BATTERY;
1827 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1828 rdev->pm.power_state[state_index].type =
1829 POWER_STATE_TYPE_BALANCED;
a48b9b4e 1830 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
0ec0e74f
AD		 1831 rdev->pm.power_state[state_index].type =
1832 POWER_STATE_TYPE_PERFORMANCE;
a48b9b4e 1833 rdev->pm.power_state[state_index].flags &=
d7311171 1834 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
a48b9b4e 1835 }
56278a8e 1836 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
0ec0e74f
AD		 1837 rdev->pm.power_state[state_index].type =
1838 POWER_STATE_TYPE_DEFAULT;
a48b9b4e 1839 rdev->pm.default_power_state_index = state_index;
56278a8e
AD		 1840 rdev->pm.power_state[state_index].default_clock_mode =
1841 &rdev->pm.power_state[state_index].clock_info[0];
a48b9b4e 1842 rdev->pm.power_state[state_index].flags &=
d7311171
AD		 1843 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1844 } else if (state_index == 0) {
1845 rdev->pm.power_state[state_index].clock_info[0].flags |=
1846 RADEON_PM_MODE_NO_DISPLAY;
56278a8e
AD		 1847 }
1848 state_index++;
1849 break;
1850 case 2:
1851 rdev->pm.power_state[state_index].num_clock_modes = 1;
1852 rdev->pm.power_state[state_index].clock_info[0].mclk =
1853 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
1854 rdev->pm.power_state[state_index].clock_info[0].sclk =
1855 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
1856 /* skip invalid modes */
1857 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1858 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1859 continue;
79daedc9 1860 rdev->pm.power_state[state_index].pcie_lanes =
56278a8e
AD		 1861 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
1862 misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
1863 misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
84d88f4c
AD		 1864 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
1865 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
56278a8e
AD		 1866 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1867 VOLTAGE_GPIO;
1868 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1869 radeon_lookup_gpio(rdev,
1870 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
1871 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1872 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1873 true;
1874 else
1875 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1876 false;
1877 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1878 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1879 VOLTAGE_VDDC;
1880 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1881 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
1882 }
d7311171 1883 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
79daedc9
AD		 1884 rdev->pm.power_state[state_index].misc = misc;
1885 rdev->pm.power_state[state_index].misc2 = misc2;
0ec0e74f
AD		 1886 /* order matters! */
1887 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1888 rdev->pm.power_state[state_index].type =
1889 POWER_STATE_TYPE_POWERSAVE;
1890 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1891 rdev->pm.power_state[state_index].type =
1892 POWER_STATE_TYPE_BATTERY;
1893 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1894 rdev->pm.power_state[state_index].type =
1895 POWER_STATE_TYPE_BATTERY;
1896 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1897 rdev->pm.power_state[state_index].type =
1898 POWER_STATE_TYPE_BALANCED;
a48b9b4e 1899 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
0ec0e74f
AD		 1900 rdev->pm.power_state[state_index].type =
1901 POWER_STATE_TYPE_PERFORMANCE;
a48b9b4e 1902 rdev->pm.power_state[state_index].flags &=
d7311171 1903 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
a48b9b4e 1904 }
0ec0e74f
AD		 1905 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1906 rdev->pm.power_state[state_index].type =
1907 POWER_STATE_TYPE_BALANCED;
a48b9b4e
AD		 1908 if (misc2 & ATOM_PM_MISCINFO2_MULTI_DISPLAY_SUPPORT)
1909 rdev->pm.power_state[state_index].flags &=
d7311171 1910 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
56278a8e 1911 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
0ec0e74f
AD		 1912 rdev->pm.power_state[state_index].type =
1913 POWER_STATE_TYPE_DEFAULT;
a48b9b4e 1914 rdev->pm.default_power_state_index = state_index;
56278a8e
AD		 1915 rdev->pm.power_state[state_index].default_clock_mode =
1916 &rdev->pm.power_state[state_index].clock_info[0];
a48b9b4e 1917 rdev->pm.power_state[state_index].flags &=
d7311171
AD		 1918 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1919 } else if (state_index == 0) {
1920 rdev->pm.power_state[state_index].clock_info[0].flags |=
1921 RADEON_PM_MODE_NO_DISPLAY;
56278a8e
AD		 1922 }
1923 state_index++;
1924 break;
1925 case 3:
1926 rdev->pm.power_state[state_index].num_clock_modes = 1;
1927 rdev->pm.power_state[state_index].clock_info[0].mclk =
1928 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
1929 rdev->pm.power_state[state_index].clock_info[0].sclk =
1930 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
1931 /* skip invalid modes */
1932 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1933 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1934 continue;
79daedc9 1935 rdev->pm.power_state[state_index].pcie_lanes =
56278a8e
AD		 1936 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
1937 misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
1938 misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
84d88f4c
AD		 1939 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
1940 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
56278a8e
AD		 1941 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1942 VOLTAGE_GPIO;
1943 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1944 radeon_lookup_gpio(rdev,
1945 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
1946 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1947 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1948 true;
1949 else
1950 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1951 false;
1952 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1953 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1954 VOLTAGE_VDDC;
1955 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1956 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
1957 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
1958 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
1959 true;
1960 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
1961 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
1962 }
1963 }
d7311171 1964 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
79daedc9
AD		 1965 rdev->pm.power_state[state_index].misc = misc;
1966 rdev->pm.power_state[state_index].misc2 = misc2;
0ec0e74f
AD		 1967 /* order matters! */
1968 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1969 rdev->pm.power_state[state_index].type =
1970 POWER_STATE_TYPE_POWERSAVE;
1971 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1972 rdev->pm.power_state[state_index].type =
1973 POWER_STATE_TYPE_BATTERY;
1974 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1975 rdev->pm.power_state[state_index].type =
1976 POWER_STATE_TYPE_BATTERY;
1977 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1978 rdev->pm.power_state[state_index].type =
1979 POWER_STATE_TYPE_BALANCED;
a48b9b4e 1980 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
0ec0e74f
AD		 1981 rdev->pm.power_state[state_index].type =
1982 POWER_STATE_TYPE_PERFORMANCE;
a48b9b4e 1983 rdev->pm.power_state[state_index].flags &=
d7311171 1984 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
a48b9b4e 1985 }
0ec0e74f
AD		 1986 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1987 rdev->pm.power_state[state_index].type =
1988 POWER_STATE_TYPE_BALANCED;
56278a8e 1989 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
0ec0e74f
AD		 1990 rdev->pm.power_state[state_index].type =
1991 POWER_STATE_TYPE_DEFAULT;
a48b9b4e 1992 rdev->pm.default_power_state_index = state_index;
56278a8e
AD		 1993 rdev->pm.power_state[state_index].default_clock_mode =
1994 &rdev->pm.power_state[state_index].clock_info[0];
d7311171
AD		 1995 } else if (state_index == 0) {
1996 rdev->pm.power_state[state_index].clock_info[0].flags |=
1997 RADEON_PM_MODE_NO_DISPLAY;
56278a8e
AD		 1998 }
1999 state_index++;
2000 break;
2001 }
2002 }
02b17cc0 2003 /* last mode is usually default */
a48b9b4e 2004 if (rdev->pm.default_power_state_index == -1) {
02b17cc0
AD		 2005 rdev->pm.power_state[state_index - 1].type =
2006 POWER_STATE_TYPE_DEFAULT;
a48b9b4e 2007 rdev->pm.default_power_state_index = state_index - 1;
02b17cc0
AD		 2008 rdev->pm.power_state[state_index - 1].default_clock_mode =
2009 &rdev->pm.power_state[state_index - 1].clock_info[0];
a48b9b4e 2010 rdev->pm.power_state[state_index].flags &=
d7311171 2011 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
79daedc9
AD		 2012 rdev->pm.power_state[state_index].misc = 0;
2013 rdev->pm.power_state[state_index].misc2 = 0;
02b17cc0 2014 }
49f65982 2015 } else {
c5e8ce61
AD		 2016 int fw_index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
2017 uint8_t fw_frev, fw_crev;
2018 uint16_t fw_data_offset, vddc = 0;
2019 union firmware_info *firmware_info;
2020 ATOM_PPLIB_THERMALCONTROLLER *controller = &power_info->info_4.sThermalController;
2021
2022 if (atom_parse_data_header(mode_info->atom_context, fw_index, NULL,
2023 &fw_frev, &fw_crev, &fw_data_offset)) {
2024 firmware_info =
2025 (union firmware_info *)(mode_info->atom_context->bios +
2026 fw_data_offset);
2027 vddc = firmware_info->info_14.usBootUpVDDCVoltage;
2028 }
2029
29fb52ca 2030 /* add the i2c bus for thermal/fan chip */
678e7dfa 2031 if (controller->ucType > 0) {
21a8122a 2032 if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) {
29fb52ca 2033 DRM_INFO("Internal thermal controller %s fan control\n",
678e7dfa 2034 (controller->ucFanParameters &
29fb52ca 2035 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
21a8122a
AD		 2036 rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX;
2037 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) {
2038 DRM_INFO("Internal thermal controller %s fan control\n",
2039 (controller->ucFanParameters &
2040 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2041 rdev->pm.int_thermal_type = THERMAL_TYPE_RV770;
2042 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) {
2043 DRM_INFO("Internal thermal controller %s fan control\n",
2044 (controller->ucFanParameters &
2045 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2046 rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN;
678e7dfa 2047 } else if ((controller->ucType ==
49f65982 2048 ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) ||
678e7dfa 2049 (controller->ucType ==
49f65982
AD		 2050 ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL)) {
2051 DRM_INFO("Special thermal controller config\n");
29fb52ca
AD		 2052 } else {
2053 DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
678e7dfa
AD		 2054 pp_lib_thermal_controller_names[controller->ucType],
2055 controller->ucI2cAddress >> 1,
2056 (controller->ucFanParameters &
29fb52ca 2057 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
678e7dfa 2058 i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine);
f376b94f 2059 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
678e7dfa
AD		 2060 if (rdev->pm.i2c_bus) {
2061 struct i2c_board_info info = { };
2062 const char *name = pp_lib_thermal_controller_names[controller->ucType];
2063 info.addr = controller->ucI2cAddress >> 1;
2064 strlcpy(info.type, name, sizeof(info.type));
2065 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2066 }
2067
29fb52ca
AD		 2068 }
2069 }
02b17cc0 2070 /* first mode is usually default, followed by low to high */
56278a8e
AD		 2071 for (i = 0; i < power_info->info_4.ucNumStates; i++) {
2072 mode_index = 0;
2073 power_state = (struct _ATOM_PPLIB_STATE *)
2074 (mode_info->atom_context->bios +
2075 data_offset +
2076 le16_to_cpu(power_info->info_4.usStateArrayOffset) +
2077 i * power_info->info_4.ucStateEntrySize);
2078 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2079 (mode_info->atom_context->bios +
2080 data_offset +
2081 le16_to_cpu(power_info->info_4.usNonClockInfoArrayOffset) +
2082 (power_state->ucNonClockStateIndex *
2083 power_info->info_4.ucNonClockSize));
56278a8e
AD		 2084 for (j = 0; j < (power_info->info_4.ucStateEntrySize - 1); j++) {
2085 if (rdev->flags & RADEON_IS_IGP) {
2086 struct _ATOM_PPLIB_RS780_CLOCK_INFO *clock_info =
2087 (struct _ATOM_PPLIB_RS780_CLOCK_INFO *)
2088 (mode_info->atom_context->bios +
2089 data_offset +
2090 le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) +
2091 (power_state->ucClockStateIndices[j] *
2092 power_info->info_4.ucClockInfoSize));
2093 sclk = le16_to_cpu(clock_info->usLowEngineClockLow);
2094 sclk |= clock_info->ucLowEngineClockHigh << 16;
2095 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2096 /* skip invalid modes */
2097 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
2098 continue;
aa1df0f2 2099 /* voltage works differently on IGPs */
56278a8e 2100 mode_index++;
49f65982
AD		 2101 } else if (ASIC_IS_DCE4(rdev)) {
2102 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO *clock_info =
2103 (struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO *)
2104 (mode_info->atom_context->bios +
2105 data_offset +
2106 le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) +
2107 (power_state->ucClockStateIndices[j] *
2108 power_info->info_4.ucClockInfoSize));
2109 sclk = le16_to_cpu(clock_info->usEngineClockLow);
2110 sclk |= clock_info->ucEngineClockHigh << 16;
2111 mclk = le16_to_cpu(clock_info->usMemoryClockLow);
2112 mclk |= clock_info->ucMemoryClockHigh << 16;
2113 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2114 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2115 /* skip invalid modes */
2116 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
2117 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
2118 continue;
49f65982
AD		 2119 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2120 VOLTAGE_SW;
2121 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2122 clock_info->usVDDC;
2123 /* XXX usVDDCI */
2124 mode_index++;
56278a8e
AD		 2125 } else {
2126 struct _ATOM_PPLIB_R600_CLOCK_INFO *clock_info =
2127 (struct _ATOM_PPLIB_R600_CLOCK_INFO *)
2128 (mode_info->atom_context->bios +
2129 data_offset +
2130 le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) +
2131 (power_state->ucClockStateIndices[j] *
2132 power_info->info_4.ucClockInfoSize));
2133 sclk = le16_to_cpu(clock_info->usEngineClockLow);
2134 sclk |= clock_info->ucEngineClockHigh << 16;
2135 mclk = le16_to_cpu(clock_info->usMemoryClockLow);
2136 mclk |= clock_info->ucMemoryClockHigh << 16;
2137 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2138 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2139 /* skip invalid modes */
2140 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
2141 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
2142 continue;
56278a8e
AD		 2143 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2144 VOLTAGE_SW;
2145 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2146 clock_info->usVDDC;
2147 mode_index++;
2148 }
2149 }
2150 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2151 if (mode_index) {
845db70d 2152 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
56278a8e 2153 misc2 = le16_to_cpu(non_clock_info->usClassification);
79daedc9
AD		 2154 rdev->pm.power_state[state_index].misc = misc;
2155 rdev->pm.power_state[state_index].misc2 = misc2;
2156 rdev->pm.power_state[state_index].pcie_lanes =
845db70d
RM		 2157 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
2158 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
0ec0e74f
AD		 2159 switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
2160 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
2161 rdev->pm.power_state[state_index].type =
2162 POWER_STATE_TYPE_BATTERY;
2163 break;
2164 case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
2165 rdev->pm.power_state[state_index].type =
2166 POWER_STATE_TYPE_BALANCED;
2167 break;
2168 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
2169 rdev->pm.power_state[state_index].type =
2170 POWER_STATE_TYPE_PERFORMANCE;
2171 break;
a44d2f37
AD		 2172 case ATOM_PPLIB_CLASSIFICATION_UI_NONE:
2173 if (misc2 & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
2174 rdev->pm.power_state[state_index].type =
2175 POWER_STATE_TYPE_PERFORMANCE;
2176 break;
0ec0e74f 2177 }
a48b9b4e
AD		 2178 rdev->pm.power_state[state_index].flags = 0;
2179 if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
2180 rdev->pm.power_state[state_index].flags |=
d7311171 2181 RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
56278a8e 2182 if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
0ec0e74f
AD		 2183 rdev->pm.power_state[state_index].type =
2184 POWER_STATE_TYPE_DEFAULT;
a48b9b4e 2185 rdev->pm.default_power_state_index = state_index;
56278a8e
AD		 2186 rdev->pm.power_state[state_index].default_clock_mode =
2187 &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
c5e8ce61
AD		 2188 /* patch the table values with the default slck/mclk from firmware info */
2189 for (j = 0; j < mode_index; j++) {
2190 rdev->pm.power_state[state_index].clock_info[j].mclk =
2191 rdev->clock.default_mclk;
2192 rdev->pm.power_state[state_index].clock_info[j].sclk =
2193 rdev->clock.default_sclk;
2194 if (vddc)
2195 rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
2196 vddc;
2197 }
56278a8e
AD		 2198 }
2199 state_index++;
2200 }
2201 }
d7311171
AD		 2202 /* if multiple clock modes, mark the lowest as no display */
2203 for (i = 0; i < state_index; i++) {
2204 if (rdev->pm.power_state[i].num_clock_modes > 1)
2205 rdev->pm.power_state[i].clock_info[0].flags |=
2206 RADEON_PM_MODE_NO_DISPLAY;
2207 }
02b17cc0 2208 /* first mode is usually default */
a48b9b4e 2209 if (rdev->pm.default_power_state_index == -1) {
02b17cc0
AD		 2210 rdev->pm.power_state[0].type =
2211 POWER_STATE_TYPE_DEFAULT;
a48b9b4e 2212 rdev->pm.default_power_state_index = 0;
02b17cc0
AD		 2213 rdev->pm.power_state[0].default_clock_mode =
2214 &rdev->pm.power_state[0].clock_info[0];
2215 }
56278a8e
AD		 2216 }
2217 } else {
56278a8e 2218 /* add the default mode */
0ec0e74f
AD		 2219 rdev->pm.power_state[state_index].type =
2220 POWER_STATE_TYPE_DEFAULT;
56278a8e
AD		 2221 rdev->pm.power_state[state_index].num_clock_modes = 1;
2222 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2223 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2224 rdev->pm.power_state[state_index].default_clock_mode =
2225 &rdev->pm.power_state[state_index].clock_info[0];
56278a8e 2226 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
79daedc9 2227 rdev->pm.power_state[state_index].pcie_lanes = 16;
a48b9b4e
AD		 2228 rdev->pm.default_power_state_index = state_index;
2229 rdev->pm.power_state[state_index].flags = 0;
56278a8e
AD		 2230 state_index++;
2231 }
02b17cc0 2232
56278a8e 2233 rdev->pm.num_power_states = state_index;
9038dfdf 2234
a48b9b4e
AD		 2235 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2236 rdev->pm.current_clock_mode_index = 0;
4d60173f 2237 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
771fe6b9
JG		 2238}
2239
771fe6b9 2240void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
771fe6b9 2241{
771fe6b9
JG		 2242 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
2243 int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
771fe6b9
JG		 2244
2245 args.ucEnable = enable;
2246
2247 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2248}
2249
7433874e
RM		 2250uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
2251{
2252 GET_ENGINE_CLOCK_PS_ALLOCATION args;
2253 int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
2254
2255 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2256 return args.ulReturnEngineClock;
2257}
2258
2259uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
2260{
2261 GET_MEMORY_CLOCK_PS_ALLOCATION args;
2262 int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
2263
2264 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2265 return args.ulReturnMemoryClock;
2266}
2267
771fe6b9
JG		 2268void radeon_atom_set_engine_clock(struct radeon_device *rdev,
2269 uint32_t eng_clock)
2270{
2271 SET_ENGINE_CLOCK_PS_ALLOCATION args;
2272 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
2273
2274 args.ulTargetEngineClock = eng_clock; /* 10 khz */
2275
2276 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2277}
2278
2279void radeon_atom_set_memory_clock(struct radeon_device *rdev,
2280 uint32_t mem_clock)
2281{
2282 SET_MEMORY_CLOCK_PS_ALLOCATION args;
2283 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
2284
2285 if (rdev->flags & RADEON_IS_IGP)
2286 return;
2287
2288 args.ulTargetMemoryClock = mem_clock; /* 10 khz */
2289
2290 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2291}
2292
7ac9aa5a
AD		 2293union set_voltage {
2294 struct _SET_VOLTAGE_PS_ALLOCATION alloc;
2295 struct _SET_VOLTAGE_PARAMETERS v1;
2296 struct _SET_VOLTAGE_PARAMETERS_V2 v2;
2297};
2298
2299void radeon_atom_set_voltage(struct radeon_device *rdev, u16 level)
2300{
2301 union set_voltage args;
2302 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
2303 u8 frev, crev, volt_index = level;
2304
2305 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2306 return;
2307
2308 switch (crev) {
2309 case 1:
2310 args.v1.ucVoltageType = SET_VOLTAGE_TYPE_ASIC_VDDC;
2311 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;
2312 args.v1.ucVoltageIndex = volt_index;
2313 break;
2314 case 2:
2315 args.v2.ucVoltageType = SET_VOLTAGE_TYPE_ASIC_VDDC;
2316 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
2317 args.v2.usVoltageLevel = cpu_to_le16(level);
2318 break;
2319 default:
2320 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
2321 return;
2322 }
2323
2324 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2325}
2326
2327
2328
771fe6b9
JG		 2329void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
2330{
2331 struct radeon_device *rdev = dev->dev_private;
2332 uint32_t bios_2_scratch, bios_6_scratch;
2333
2334 if (rdev->family >= CHIP_R600) {
4ce001ab 2335 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
771fe6b9
JG		 2336 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2337 } else {
4ce001ab 2338 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
771fe6b9
JG		 2339 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2340 }
2341
2342 /* let the bios control the backlight */
2343 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
2344
2345 /* tell the bios not to handle mode switching */
2346 bios_6_scratch |= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH | ATOM_S6_ACC_MODE);
2347
2348 if (rdev->family >= CHIP_R600) {
2349 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
2350 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2351 } else {
2352 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
2353 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2354 }
2355
2356}
2357
f657c2a7
YZ		 2358void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
2359{
2360 uint32_t scratch_reg;
2361 int i;
2362
2363 if (rdev->family >= CHIP_R600)
2364 scratch_reg = R600_BIOS_0_SCRATCH;
2365 else
2366 scratch_reg = RADEON_BIOS_0_SCRATCH;
2367
2368 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2369 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
2370}
2371
2372void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
2373{
2374 uint32_t scratch_reg;
2375 int i;
2376
2377 if (rdev->family >= CHIP_R600)
2378 scratch_reg = R600_BIOS_0_SCRATCH;
2379 else
2380 scratch_reg = RADEON_BIOS_0_SCRATCH;
2381
2382 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2383 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
2384}
2385
771fe6b9
JG		 2386void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
2387{
2388 struct drm_device *dev = encoder->dev;
2389 struct radeon_device *rdev = dev->dev_private;
2390 uint32_t bios_6_scratch;
2391
2392 if (rdev->family >= CHIP_R600)
2393 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2394 else
2395 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2396
2397 if (lock)
2398 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
2399 else
2400 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
2401
2402 if (rdev->family >= CHIP_R600)
2403 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2404 else
2405 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2406}
2407
2408/* at some point we may want to break this out into individual functions */
2409void
2410radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
2411 struct drm_encoder *encoder,
2412 bool connected)
2413{
2414 struct drm_device *dev = connector->dev;
2415 struct radeon_device *rdev = dev->dev_private;
2416 struct radeon_connector *radeon_connector =
2417 to_radeon_connector(connector);
2418 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2419 uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
2420
2421 if (rdev->family >= CHIP_R600) {
2422 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2423 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2424 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2425 } else {
2426 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2427 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2428 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2429 }
2430
2431 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
2432 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
2433 if (connected) {
d9fdaafb 2434 DRM_DEBUG_KMS("TV1 connected\n");
771fe6b9
JG		 2435 bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
2436 bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
2437 } else {
d9fdaafb 2438 DRM_DEBUG_KMS("TV1 disconnected\n");
771fe6b9
JG		 2439 bios_0_scratch &= ~ATOM_S0_TV1_MASK;
2440 bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
2441 bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
2442 }
2443 }
2444 if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
2445 (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
2446 if (connected) {
d9fdaafb 2447 DRM_DEBUG_KMS("CV connected\n");
771fe6b9
JG		 2448 bios_3_scratch |= ATOM_S3_CV_ACTIVE;
2449 bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
2450 } else {
d9fdaafb 2451 DRM_DEBUG_KMS("CV disconnected\n");
771fe6b9
JG		 2452 bios_0_scratch &= ~ATOM_S0_CV_MASK;
2453 bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
2454 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
2455 }
2456 }
2457 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
2458 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
2459 if (connected) {
d9fdaafb 2460 DRM_DEBUG_KMS("LCD1 connected\n");
771fe6b9
JG		 2461 bios_0_scratch |= ATOM_S0_LCD1;
2462 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
2463 bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
2464 } else {
d9fdaafb 2465 DRM_DEBUG_KMS("LCD1 disconnected\n");
771fe6b9
JG		 2466 bios_0_scratch &= ~ATOM_S0_LCD1;
2467 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
2468 bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
2469 }
2470 }
2471 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
2472 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
2473 if (connected) {
d9fdaafb 2474 DRM_DEBUG_KMS("CRT1 connected\n");
771fe6b9
JG		 2475 bios_0_scratch |= ATOM_S0_CRT1_COLOR;
2476 bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
2477 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
2478 } else {
d9fdaafb 2479 DRM_DEBUG_KMS("CRT1 disconnected\n");
771fe6b9
JG		 2480 bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
2481 bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
2482 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
2483 }
2484 }
2485 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
2486 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
2487 if (connected) {
d9fdaafb 2488 DRM_DEBUG_KMS("CRT2 connected\n");
771fe6b9
JG		 2489 bios_0_scratch |= ATOM_S0_CRT2_COLOR;
2490 bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
2491 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
2492 } else {
d9fdaafb 2493 DRM_DEBUG_KMS("CRT2 disconnected\n");
771fe6b9
JG		 2494 bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
2495 bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
2496 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
2497 }
2498 }
2499 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
2500 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
2501 if (connected) {
d9fdaafb 2502 DRM_DEBUG_KMS("DFP1 connected\n");
771fe6b9
JG		 2503 bios_0_scratch |= ATOM_S0_DFP1;
2504 bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
2505 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
2506 } else {
d9fdaafb 2507 DRM_DEBUG_KMS("DFP1 disconnected\n");
771fe6b9
JG		 2508 bios_0_scratch &= ~ATOM_S0_DFP1;
2509 bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
2510 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
2511 }
2512 }
2513 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
2514 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
2515 if (connected) {
d9fdaafb 2516 DRM_DEBUG_KMS("DFP2 connected\n");
771fe6b9
JG		 2517 bios_0_scratch |= ATOM_S0_DFP2;
2518 bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
2519 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
2520 } else {
d9fdaafb 2521 DRM_DEBUG_KMS("DFP2 disconnected\n");
771fe6b9
JG		 2522 bios_0_scratch &= ~ATOM_S0_DFP2;
2523 bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
2524 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
2525 }
2526 }
2527 if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
2528 (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
2529 if (connected) {
d9fdaafb 2530 DRM_DEBUG_KMS("DFP3 connected\n");
771fe6b9
JG		 2531 bios_0_scratch |= ATOM_S0_DFP3;
2532 bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
2533 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
2534 } else {
d9fdaafb 2535 DRM_DEBUG_KMS("DFP3 disconnected\n");
771fe6b9
JG		 2536 bios_0_scratch &= ~ATOM_S0_DFP3;
2537 bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
2538 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
2539 }
2540 }
2541 if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
2542 (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
2543 if (connected) {
d9fdaafb 2544 DRM_DEBUG_KMS("DFP4 connected\n");
771fe6b9
JG		 2545 bios_0_scratch |= ATOM_S0_DFP4;
2546 bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
2547 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
2548 } else {
d9fdaafb 2549 DRM_DEBUG_KMS("DFP4 disconnected\n");
771fe6b9
JG		 2550 bios_0_scratch &= ~ATOM_S0_DFP4;
2551 bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
2552 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
2553 }
2554 }
2555 if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
2556 (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
2557 if (connected) {
d9fdaafb 2558 DRM_DEBUG_KMS("DFP5 connected\n");
771fe6b9
JG		 2559 bios_0_scratch |= ATOM_S0_DFP5;
2560 bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
2561 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
2562 } else {
d9fdaafb 2563 DRM_DEBUG_KMS("DFP5 disconnected\n");
771fe6b9
JG		 2564 bios_0_scratch &= ~ATOM_S0_DFP5;
2565 bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
2566 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
2567 }
2568 }
2569
2570 if (rdev->family >= CHIP_R600) {
2571 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
2572 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2573 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2574 } else {
2575 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
2576 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2577 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2578 }
2579}
2580
2581void
2582radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
2583{
2584 struct drm_device *dev = encoder->dev;
2585 struct radeon_device *rdev = dev->dev_private;
2586 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2587 uint32_t bios_3_scratch;
2588
2589 if (rdev->family >= CHIP_R600)
2590 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2591 else
2592 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2593
2594 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2595 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
2596 bios_3_scratch |= (crtc << 18);
2597 }
2598 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2599 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
2600 bios_3_scratch |= (crtc << 24);
2601 }
2602 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2603 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
2604 bios_3_scratch |= (crtc << 16);
2605 }
2606 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2607 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
2608 bios_3_scratch |= (crtc << 20);
2609 }
2610 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2611 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
2612 bios_3_scratch |= (crtc << 17);
2613 }
2614 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2615 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
2616 bios_3_scratch |= (crtc << 19);
2617 }
2618 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2619 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
2620 bios_3_scratch |= (crtc << 23);
2621 }
2622 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
2623 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
2624 bios_3_scratch |= (crtc << 25);
2625 }
2626
2627 if (rdev->family >= CHIP_R600)
2628 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2629 else
2630 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2631}
2632
2633void
2634radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
2635{
2636 struct drm_device *dev = encoder->dev;
2637 struct radeon_device *rdev = dev->dev_private;
2638 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2639 uint32_t bios_2_scratch;
2640
2641 if (rdev->family >= CHIP_R600)
2642 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
2643 else
2644 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
2645
2646 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2647 if (on)
2648 bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
2649 else
2650 bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
2651 }
2652 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2653 if (on)
2654 bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
2655 else
2656 bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
2657 }
2658 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2659 if (on)
2660 bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
2661 else
2662 bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
2663 }
2664 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2665 if (on)
2666 bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
2667 else
2668 bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
2669 }
2670 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2671 if (on)
2672 bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
2673 else
2674 bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
2675 }
2676 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2677 if (on)
2678 bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
2679 else
2680 bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
2681 }
2682 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2683 if (on)
2684 bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
2685 else
2686 bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
2687 }
2688 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
2689 if (on)
2690 bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
2691 else
2692 bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
2693 }
2694 if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
2695 if (on)
2696 bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
2697 else
2698 bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
2699 }
2700 if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
2701 if (on)
2702 bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
2703 else
2704 bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
2705 }
2706
2707 if (rdev->family >= CHIP_R600)
2708 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
2709 else
2710 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
2711}
Clone of davem's net-next-2.6 tree