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[net-next-2.6.git] / drivers / gpu / drm / radeon / radeon_atombios.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26#include "drmP.h"
27#include "radeon_drm.h"
28#include "radeon.h"
29
30#include "atom.h"
31#include "atom-bits.h"
32
33/* from radeon_encoder.c */
34extern uint32_t
35radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device,
36 uint8_t dac);
37extern void radeon_link_encoder_connector(struct drm_device *dev);
38extern void
39radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id,
40 uint32_t supported_device);
41
42/* from radeon_connector.c */
43extern void
44radeon_add_atom_connector(struct drm_device *dev,
45 uint32_t connector_id,
46 uint32_t supported_device,
47 int connector_type,
48 struct radeon_i2c_bus_rec *i2c_bus,
b75fad06 49 bool linkb, uint32_t igp_lane_info,
eed45b30
AD		 50 uint16_t connector_object_id,
51 struct radeon_hpd *hpd);
771fe6b9
JG		 52
53/* from radeon_legacy_encoder.c */
54extern void
55radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id,
56 uint32_t supported_device);
57
58union atom_supported_devices {
59 struct _ATOM_SUPPORTED_DEVICES_INFO info;
60 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
61 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
62};
63
eed45b30
AD		 64static inline struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
65 uint8_t id)
771fe6b9 66{
771fe6b9 67 struct atom_context *ctx = rdev->mode_info.atom_context;
6a93cb25 68 ATOM_GPIO_I2C_ASSIGMENT *gpio;
771fe6b9
JG		 69 struct radeon_i2c_bus_rec i2c;
70 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
71 struct _ATOM_GPIO_I2C_INFO *i2c_info;
72 uint16_t data_offset;
d3f420d1 73 int i;
771fe6b9
JG		 74
75 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
76 i2c.valid = false;
77
a084e6ee
AD		 78 if (atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) {
79 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
80
81 for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
82 gpio = &i2c_info->asGPIO_Info[i];
83
84 if (gpio->sucI2cId.ucAccess == id) {
85 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
86 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
87 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
88 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
89 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
90 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
91 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
92 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
93 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
94 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
95 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
96 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
97 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
98 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
99 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
100 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
101
102 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
103 i2c.hw_capable = true;
104 else
105 i2c.hw_capable = false;
106
107 if (gpio->sucI2cId.ucAccess == 0xa0)
108 i2c.mm_i2c = true;
109 else
110 i2c.mm_i2c = false;
111
112 i2c.i2c_id = gpio->sucI2cId.ucAccess;
113
114 i2c.valid = true;
115 break;
116 }
d3f420d1
AD		 117 }
118 }
771fe6b9
JG		 119
120 return i2c;
121}
122
eed45b30
AD		 123static inline struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev,
124 u8 id)
125{
126 struct atom_context *ctx = rdev->mode_info.atom_context;
127 struct radeon_gpio_rec gpio;
128 int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
129 struct _ATOM_GPIO_PIN_LUT *gpio_info;
130 ATOM_GPIO_PIN_ASSIGNMENT *pin;
131 u16 data_offset, size;
132 int i, num_indices;
133
134 memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
135 gpio.valid = false;
136
a084e6ee
AD		 137 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
138 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
eed45b30 139
a084e6ee
AD		 140 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
141 sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
eed45b30 142
a084e6ee
AD		 143 for (i = 0; i < num_indices; i++) {
144 pin = &gpio_info->asGPIO_Pin[i];
145 if (id == pin->ucGPIO_ID) {
146 gpio.id = pin->ucGPIO_ID;
147 gpio.reg = pin->usGpioPin_AIndex * 4;
148 gpio.mask = (1 << pin->ucGpioPinBitShift);
149 gpio.valid = true;
150 break;
151 }
eed45b30
AD		 152 }
153 }
154
155 return gpio;
156}
157
158static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
159 struct radeon_gpio_rec *gpio)
160{
161 struct radeon_hpd hpd;
bcc1c2a1
AD		 162 u32 reg;
163
164 if (ASIC_IS_DCE4(rdev))
165 reg = EVERGREEN_DC_GPIO_HPD_A;
166 else
167 reg = AVIVO_DC_GPIO_HPD_A;
168
eed45b30 169 hpd.gpio = *gpio;
bcc1c2a1 170 if (gpio->reg == reg) {
eed45b30
AD		 171 switch(gpio->mask) {
172 case (1 << 0):
173 hpd.hpd = RADEON_HPD_1;
174 break;
175 case (1 << 8):
176 hpd.hpd = RADEON_HPD_2;
177 break;
178 case (1 << 16):
179 hpd.hpd = RADEON_HPD_3;
180 break;
181 case (1 << 24):
182 hpd.hpd = RADEON_HPD_4;
183 break;
184 case (1 << 26):
185 hpd.hpd = RADEON_HPD_5;
186 break;
187 case (1 << 28):
188 hpd.hpd = RADEON_HPD_6;
189 break;
190 default:
191 hpd.hpd = RADEON_HPD_NONE;
192 break;
193 }
194 } else
195 hpd.hpd = RADEON_HPD_NONE;
196 return hpd;
197}
198
771fe6b9
JG		 199static bool radeon_atom_apply_quirks(struct drm_device *dev,
200 uint32_t supported_device,
201 int *connector_type,
848577ee 202 struct radeon_i2c_bus_rec *i2c_bus,
eed45b30
AD		 203 uint16_t *line_mux,
204 struct radeon_hpd *hpd)
771fe6b9
JG		 205{
206
207 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
208 if ((dev->pdev->device == 0x791e) &&
209 (dev->pdev->subsystem_vendor == 0x1043) &&
210 (dev->pdev->subsystem_device == 0x826d)) {
211 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
212 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
213 *connector_type = DRM_MODE_CONNECTOR_DVID;
214 }
215
c86a9038
AD		 216 /* Asrock RS600 board lists the DVI port as HDMI */
217 if ((dev->pdev->device == 0x7941) &&
218 (dev->pdev->subsystem_vendor == 0x1849) &&
219 (dev->pdev->subsystem_device == 0x7941)) {
220 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
221 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
222 *connector_type = DRM_MODE_CONNECTOR_DVID;
223 }
224
771fe6b9
JG		 225 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
226 if ((dev->pdev->device == 0x7941) &&
227 (dev->pdev->subsystem_vendor == 0x147b) &&
228 (dev->pdev->subsystem_device == 0x2412)) {
229 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
230 return false;
231 }
232
233 /* Falcon NW laptop lists vga ddc line for LVDS */
234 if ((dev->pdev->device == 0x5653) &&
235 (dev->pdev->subsystem_vendor == 0x1462) &&
236 (dev->pdev->subsystem_device == 0x0291)) {
848577ee 237 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
771fe6b9 238 i2c_bus->valid = false;
848577ee
AD		 239 *line_mux = 53;
240 }
771fe6b9
JG		 241 }
242
4e3f9b78
AD		 243 /* HIS X1300 is DVI+VGA, not DVI+DVI */
244 if ((dev->pdev->device == 0x7146) &&
245 (dev->pdev->subsystem_vendor == 0x17af) &&
246 (dev->pdev->subsystem_device == 0x2058)) {
247 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
248 return false;
249 }
250
aa1a750e
DA		 251 /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
252 if ((dev->pdev->device == 0x7142) &&
253 (dev->pdev->subsystem_vendor == 0x1458) &&
254 (dev->pdev->subsystem_device == 0x2134)) {
255 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
256 return false;
257 }
258
259
771fe6b9
JG		 260 /* Funky macbooks */
261 if ((dev->pdev->device == 0x71C5) &&
262 (dev->pdev->subsystem_vendor == 0x106b) &&
263 (dev->pdev->subsystem_device == 0x0080)) {
264 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
265 (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
266 return false;
e1e8a5dd
AD		 267 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT)
268 *line_mux = 0x90;
771fe6b9
JG		 269 }
270
771fe6b9
JG		 271 /* ASUS HD 3600 XT board lists the DVI port as HDMI */
272 if ((dev->pdev->device == 0x9598) &&
273 (dev->pdev->subsystem_vendor == 0x1043) &&
274 (dev->pdev->subsystem_device == 0x01da)) {
705af9c7 275 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
d42571ef 276 *connector_type = DRM_MODE_CONNECTOR_DVII;
705af9c7
AD		 277 }
278 }
279
280 /* ASUS HD 3450 board lists the DVI port as HDMI */
281 if ((dev->pdev->device == 0x95C5) &&
282 (dev->pdev->subsystem_vendor == 0x1043) &&
283 (dev->pdev->subsystem_device == 0x01e2)) {
284 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
d42571ef 285 *connector_type = DRM_MODE_CONNECTOR_DVII;
771fe6b9
JG		 286 }
287 }
288
705af9c7
AD		 289 /* some BIOSes seem to report DAC on HDMI - usually this is a board with
290 * HDMI + VGA reporting as HDMI
291 */
292 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
293 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
294 *connector_type = DRM_MODE_CONNECTOR_VGA;
295 *line_mux = 0;
296 }
297 }
298
3e5f8ff3
AD		 299 /* Acer laptop reports DVI-D as DVI-I */
300 if ((dev->pdev->device == 0x95c4) &&
301 (dev->pdev->subsystem_vendor == 0x1025) &&
302 (dev->pdev->subsystem_device == 0x013c)) {
303 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
304 (supported_device == ATOM_DEVICE_DFP1_SUPPORT))
305 *connector_type = DRM_MODE_CONNECTOR_DVID;
306 }
307
efa8450f
DA		 308 /* XFX Pine Group device rv730 reports no VGA DDC lines
309 * even though they are wired up to record 0x93
310 */
311 if ((dev->pdev->device == 0x9498) &&
312 (dev->pdev->subsystem_vendor == 0x1682) &&
313 (dev->pdev->subsystem_device == 0x2452)) {
314 struct radeon_device *rdev = dev->dev_private;
315 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
316 }
771fe6b9
JG		 317 return true;
318}
319
320const int supported_devices_connector_convert[] = {
321 DRM_MODE_CONNECTOR_Unknown,
322 DRM_MODE_CONNECTOR_VGA,
323 DRM_MODE_CONNECTOR_DVII,
324 DRM_MODE_CONNECTOR_DVID,
325 DRM_MODE_CONNECTOR_DVIA,
326 DRM_MODE_CONNECTOR_SVIDEO,
327 DRM_MODE_CONNECTOR_Composite,
328 DRM_MODE_CONNECTOR_LVDS,
329 DRM_MODE_CONNECTOR_Unknown,
330 DRM_MODE_CONNECTOR_Unknown,
331 DRM_MODE_CONNECTOR_HDMIA,
332 DRM_MODE_CONNECTOR_HDMIB,
333 DRM_MODE_CONNECTOR_Unknown,
334 DRM_MODE_CONNECTOR_Unknown,
335 DRM_MODE_CONNECTOR_9PinDIN,
336 DRM_MODE_CONNECTOR_DisplayPort
337};
338
b75fad06
AD		 339const uint16_t supported_devices_connector_object_id_convert[] = {
340 CONNECTOR_OBJECT_ID_NONE,
341 CONNECTOR_OBJECT_ID_VGA,
342 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
343 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
344 CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
345 CONNECTOR_OBJECT_ID_COMPOSITE,
346 CONNECTOR_OBJECT_ID_SVIDEO,
347 CONNECTOR_OBJECT_ID_LVDS,
348 CONNECTOR_OBJECT_ID_9PIN_DIN,
349 CONNECTOR_OBJECT_ID_9PIN_DIN,
350 CONNECTOR_OBJECT_ID_DISPLAYPORT,
351 CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
352 CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
353 CONNECTOR_OBJECT_ID_SVIDEO
354};
355
771fe6b9
JG		 356const int object_connector_convert[] = {
357 DRM_MODE_CONNECTOR_Unknown,
358 DRM_MODE_CONNECTOR_DVII,
359 DRM_MODE_CONNECTOR_DVII,
360 DRM_MODE_CONNECTOR_DVID,
361 DRM_MODE_CONNECTOR_DVID,
362 DRM_MODE_CONNECTOR_VGA,
363 DRM_MODE_CONNECTOR_Composite,
364 DRM_MODE_CONNECTOR_SVIDEO,
365 DRM_MODE_CONNECTOR_Unknown,
705af9c7 366 DRM_MODE_CONNECTOR_Unknown,
771fe6b9
JG		 367 DRM_MODE_CONNECTOR_9PinDIN,
368 DRM_MODE_CONNECTOR_Unknown,
369 DRM_MODE_CONNECTOR_HDMIA,
370 DRM_MODE_CONNECTOR_HDMIB,
771fe6b9
JG		 371 DRM_MODE_CONNECTOR_LVDS,
372 DRM_MODE_CONNECTOR_9PinDIN,
373 DRM_MODE_CONNECTOR_Unknown,
374 DRM_MODE_CONNECTOR_Unknown,
375 DRM_MODE_CONNECTOR_Unknown,
196c58d2
AD		 376 DRM_MODE_CONNECTOR_DisplayPort,
377 DRM_MODE_CONNECTOR_eDP,
378 DRM_MODE_CONNECTOR_Unknown
771fe6b9
JG		 379};
380
381bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
382{
383 struct radeon_device *rdev = dev->dev_private;
384 struct radeon_mode_info *mode_info = &rdev->mode_info;
385 struct atom_context *ctx = mode_info->atom_context;
386 int index = GetIndexIntoMasterTable(DATA, Object_Header);
eed45b30
AD		 387 u16 size, data_offset;
388 u8 frev, crev;
771fe6b9
JG		 389 ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
390 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
391 ATOM_OBJECT_HEADER *obj_header;
392 int i, j, path_size, device_support;
393 int connector_type;
eed45b30 394 u16 igp_lane_info, conn_id, connector_object_id;
771fe6b9
JG		 395 bool linkb;
396 struct radeon_i2c_bus_rec ddc_bus;
eed45b30
AD		 397 struct radeon_gpio_rec gpio;
398 struct radeon_hpd hpd;
399
a084e6ee 400 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
771fe6b9
JG		 401 return false;
402
403 if (crev < 2)
404 return false;
405
406 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
407 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
408 (ctx->bios + data_offset +
409 le16_to_cpu(obj_header->usDisplayPathTableOffset));
410 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
411 (ctx->bios + data_offset +
412 le16_to_cpu(obj_header->usConnectorObjectTableOffset));
413 device_support = le16_to_cpu(obj_header->usDeviceSupport);
414
415 path_size = 0;
416 for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
417 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
418 ATOM_DISPLAY_OBJECT_PATH *path;
419 addr += path_size;
420 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
421 path_size += le16_to_cpu(path->usSize);
422 linkb = false;
771fe6b9
JG		 423 if (device_support & le16_to_cpu(path->usDeviceTag)) {
424 uint8_t con_obj_id, con_obj_num, con_obj_type;
425
426 con_obj_id =
427 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
428 >> OBJECT_ID_SHIFT;
429 con_obj_num =
430 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
431 >> ENUM_ID_SHIFT;
432 con_obj_type =
433 (le16_to_cpu(path->usConnObjectId) &
434 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
435
4bbd4973
DA		 436 /* TODO CV support */
437 if (le16_to_cpu(path->usDeviceTag) ==
438 ATOM_DEVICE_CV_SUPPORT)
771fe6b9
JG		 439 continue;
440
ee59f2b4
AD		 441 /* IGP chips */
442 if ((rdev->flags & RADEON_IS_IGP) &&
771fe6b9
JG		 443 (con_obj_id ==
444 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
445 uint16_t igp_offset = 0;
446 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
447
448 index =
449 GetIndexIntoMasterTable(DATA,
450 IntegratedSystemInfo);
451
a084e6ee
AD		 452 if (atom_parse_data_header(ctx, index, &size, &frev,
453 &crev, &igp_offset)) {
454
455 if (crev >= 2) {
456 igp_obj =
457 (ATOM_INTEGRATED_SYSTEM_INFO_V2
458 *) (ctx->bios + igp_offset);
459
460 if (igp_obj) {
461 uint32_t slot_config, ct;
462
463 if (con_obj_num == 1)
464 slot_config =
465 igp_obj->
466 ulDDISlot1Config;
467 else
468 slot_config =
469 igp_obj->
470 ulDDISlot2Config;
471
472 ct = (slot_config >> 16) & 0xff;
473 connector_type =
474 object_connector_convert
475 [ct];
476 connector_object_id = ct;
477 igp_lane_info =
478 slot_config & 0xffff;
479 } else
480 continue;
771fe6b9
JG		 481 } else
482 continue;
a084e6ee
AD		 483 } else {
484 igp_lane_info = 0;
485 connector_type =
486 object_connector_convert[con_obj_id];
487 connector_object_id = con_obj_id;
488 }
771fe6b9
JG		 489 } else {
490 igp_lane_info = 0;
491 connector_type =
492 object_connector_convert[con_obj_id];
b75fad06 493 connector_object_id = con_obj_id;
771fe6b9
JG		 494 }
495
496 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
497 continue;
498
499 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2);
500 j++) {
501 uint8_t enc_obj_id, enc_obj_num, enc_obj_type;
502
503 enc_obj_id =
504 (le16_to_cpu(path->usGraphicObjIds[j]) &
505 OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
506 enc_obj_num =
507 (le16_to_cpu(path->usGraphicObjIds[j]) &
508 ENUM_ID_MASK) >> ENUM_ID_SHIFT;
509 enc_obj_type =
510 (le16_to_cpu(path->usGraphicObjIds[j]) &
511 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
512
513 /* FIXME: add support for router objects */
514 if (enc_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
515 if (enc_obj_num == 2)
516 linkb = true;
517 else
518 linkb = false;
519
520 radeon_add_atom_encoder(dev,
521 enc_obj_id,
522 le16_to_cpu
523 (path->
524 usDeviceTag));
525
526 }
527 }
528
eed45b30 529 /* look up gpio for ddc, hpd */
771fe6b9 530 if ((le16_to_cpu(path->usDeviceTag) &
eed45b30 531 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
771fe6b9
JG		 532 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
533 if (le16_to_cpu(path->usConnObjectId) ==
534 le16_to_cpu(con_obj->asObjects[j].
535 usObjectID)) {
536 ATOM_COMMON_RECORD_HEADER
537 *record =
538 (ATOM_COMMON_RECORD_HEADER
539 *)
540 (ctx->bios + data_offset +
541 le16_to_cpu(con_obj->
542 asObjects[j].
543 usRecordOffset));
544 ATOM_I2C_RECORD *i2c_record;
eed45b30 545 ATOM_HPD_INT_RECORD *hpd_record;
d3f420d1 546 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
eed45b30 547 hpd.hpd = RADEON_HPD_NONE;
6a93cb25 548
771fe6b9
JG		 549 while (record->ucRecordType > 0
550 && record->
551 ucRecordType <=
552 ATOM_MAX_OBJECT_RECORD_NUMBER) {
eed45b30 553 switch (record->ucRecordType) {
771fe6b9
JG		 554 case ATOM_I2C_RECORD_TYPE:
555 i2c_record =
eed45b30
AD		 556 (ATOM_I2C_RECORD *)
557 record;
d3f420d1
AD		 558 i2c_config =
559 (ATOM_I2C_ID_CONFIG_ACCESS *)
560 &i2c_record->sucI2cId;
eed45b30 561 ddc_bus = radeon_lookup_i2c_gpio(rdev,
d3f420d1
AD		 562 i2c_config->
563 ucAccess);
eed45b30
AD		 564 break;
565 case ATOM_HPD_INT_RECORD_TYPE:
566 hpd_record =
567 (ATOM_HPD_INT_RECORD *)
568 record;
569 gpio = radeon_lookup_gpio(rdev,
570 hpd_record->ucHPDIntGPIOID);
571 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
572 hpd.plugged_state = hpd_record->ucPlugged_PinState;
771fe6b9
JG		 573 break;
574 }
575 record =
576 (ATOM_COMMON_RECORD_HEADER
577 *) ((char *)record
578 +
579 record->
580 ucRecordSize);
581 }
582 break;
583 }
584 }
eed45b30
AD		 585 } else {
586 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 587 ddc_bus.valid = false;
eed45b30 588 }
771fe6b9 589
bcc1c2a1
AD		 590 /* needed for aux chan transactions */
591 ddc_bus.hpd_id = hpd.hpd ? (hpd.hpd - 1) : 0;
592
705af9c7
AD		 593 conn_id = le16_to_cpu(path->usConnObjectId);
594
595 if (!radeon_atom_apply_quirks
596 (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
eed45b30 597 &ddc_bus, &conn_id, &hpd))
705af9c7
AD		 598 continue;
599
771fe6b9 600 radeon_add_atom_connector(dev,
705af9c7 601 conn_id,
771fe6b9
JG		 602 le16_to_cpu(path->
603 usDeviceTag),
604 connector_type, &ddc_bus,
b75fad06 605 linkb, igp_lane_info,
eed45b30
AD		 606 connector_object_id,
607 &hpd);
771fe6b9
JG		 608
609 }
610 }
611
612 radeon_link_encoder_connector(dev);
613
614 return true;
615}
616
b75fad06
AD		 617static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
618 int connector_type,
619 uint16_t devices)
620{
621 struct radeon_device *rdev = dev->dev_private;
622
623 if (rdev->flags & RADEON_IS_IGP) {
624 return supported_devices_connector_object_id_convert
625 [connector_type];
626 } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
627 (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
628 (devices & ATOM_DEVICE_DFP2_SUPPORT)) {
629 struct radeon_mode_info *mode_info = &rdev->mode_info;
630 struct atom_context *ctx = mode_info->atom_context;
631 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
632 uint16_t size, data_offset;
633 uint8_t frev, crev;
634 ATOM_XTMDS_INFO *xtmds;
635
a084e6ee
AD		 636 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) {
637 xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
b75fad06 638
a084e6ee
AD		 639 if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
640 if (connector_type == DRM_MODE_CONNECTOR_DVII)
641 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
642 else
643 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
644 } else {
645 if (connector_type == DRM_MODE_CONNECTOR_DVII)
646 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
647 else
648 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
649 }
650 } else
651 return supported_devices_connector_object_id_convert
652 [connector_type];
b75fad06
AD		 653 } else {
654 return supported_devices_connector_object_id_convert
655 [connector_type];
656 }
657}
658
771fe6b9
JG		 659struct bios_connector {
660 bool valid;
705af9c7 661 uint16_t line_mux;
771fe6b9
JG		 662 uint16_t devices;
663 int connector_type;
664 struct radeon_i2c_bus_rec ddc_bus;
eed45b30 665 struct radeon_hpd hpd;
771fe6b9
JG		 666};
667
668bool radeon_get_atom_connector_info_from_supported_devices_table(struct
669 drm_device
670 *dev)
671{
672 struct radeon_device *rdev = dev->dev_private;
673 struct radeon_mode_info *mode_info = &rdev->mode_info;
674 struct atom_context *ctx = mode_info->atom_context;
675 int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
676 uint16_t size, data_offset;
677 uint8_t frev, crev;
678 uint16_t device_support;
679 uint8_t dac;
680 union atom_supported_devices *supported_devices;
eed45b30 681 int i, j, max_device;
771fe6b9
JG		 682 struct bios_connector bios_connectors[ATOM_MAX_SUPPORTED_DEVICE];
683
a084e6ee
AD		 684 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
685 return false;
771fe6b9
JG		 686
687 supported_devices =
688 (union atom_supported_devices *)(ctx->bios + data_offset);
689
690 device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
691
eed45b30
AD		 692 if (frev > 1)
693 max_device = ATOM_MAX_SUPPORTED_DEVICE;
694 else
695 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
696
697 for (i = 0; i < max_device; i++) {
771fe6b9
JG		 698 ATOM_CONNECTOR_INFO_I2C ci =
699 supported_devices->info.asConnInfo[i];
700
701 bios_connectors[i].valid = false;
702
703 if (!(device_support & (1 << i))) {
704 continue;
705 }
706
707 if (i == ATOM_DEVICE_CV_INDEX) {
708 DRM_DEBUG("Skipping Component Video\n");
709 continue;
710 }
711
771fe6b9
JG		 712 bios_connectors[i].connector_type =
713 supported_devices_connector_convert[ci.sucConnectorInfo.
714 sbfAccess.
715 bfConnectorType];
716
717 if (bios_connectors[i].connector_type ==
718 DRM_MODE_CONNECTOR_Unknown)
719 continue;
720
721 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
722
d3f420d1
AD		 723 bios_connectors[i].line_mux =
724 ci.sucI2cId.ucAccess;
771fe6b9
JG		 725
726 /* give tv unique connector ids */
727 if (i == ATOM_DEVICE_TV1_INDEX) {
728 bios_connectors[i].ddc_bus.valid = false;
729 bios_connectors[i].line_mux = 50;
730 } else if (i == ATOM_DEVICE_TV2_INDEX) {
731 bios_connectors[i].ddc_bus.valid = false;
732 bios_connectors[i].line_mux = 51;
733 } else if (i == ATOM_DEVICE_CV_INDEX) {
734 bios_connectors[i].ddc_bus.valid = false;
735 bios_connectors[i].line_mux = 52;
736 } else
737 bios_connectors[i].ddc_bus =
eed45b30
AD		 738 radeon_lookup_i2c_gpio(rdev,
739 bios_connectors[i].line_mux);
740
741 if ((crev > 1) && (frev > 1)) {
742 u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
743 switch (isb) {
744 case 0x4:
745 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
746 break;
747 case 0xa:
748 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
749 break;
750 default:
751 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
752 break;
753 }
754 } else {
755 if (i == ATOM_DEVICE_DFP1_INDEX)
756 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
757 else if (i == ATOM_DEVICE_DFP2_INDEX)
758 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
759 else
760 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
761 }
771fe6b9
JG		 762
763 /* Always set the connector type to VGA for CRT1/CRT2. if they are
764 * shared with a DVI port, we'll pick up the DVI connector when we
765 * merge the outputs. Some bioses incorrectly list VGA ports as DVI.
766 */
767 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
768 bios_connectors[i].connector_type =
769 DRM_MODE_CONNECTOR_VGA;
770
771 if (!radeon_atom_apply_quirks
772 (dev, (1 << i), &bios_connectors[i].connector_type,
eed45b30
AD		 773 &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
774 &bios_connectors[i].hpd))
771fe6b9
JG		 775 continue;
776
777 bios_connectors[i].valid = true;
778 bios_connectors[i].devices = (1 << i);
779
780 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
781 radeon_add_atom_encoder(dev,
782 radeon_get_encoder_id(dev,
783 (1 << i),
784 dac),
785 (1 << i));
786 else
787 radeon_add_legacy_encoder(dev,
788 radeon_get_encoder_id(dev,
f56cd64f 789 (1 << i),
771fe6b9
JG		 790 dac),
791 (1 << i));
792 }
793
794 /* combine shared connectors */
eed45b30 795 for (i = 0; i < max_device; i++) {
771fe6b9 796 if (bios_connectors[i].valid) {
eed45b30 797 for (j = 0; j < max_device; j++) {
771fe6b9
JG		 798 if (bios_connectors[j].valid && (i != j)) {
799 if (bios_connectors[i].line_mux ==
800 bios_connectors[j].line_mux) {
f56cd64f
AD		 801 /* make sure not to combine LVDS */
802 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
803 bios_connectors[i].line_mux = 53;
804 bios_connectors[i].ddc_bus.valid = false;
805 continue;
806 }
807 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
808 bios_connectors[j].line_mux = 53;
809 bios_connectors[j].ddc_bus.valid = false;
810 continue;
811 }
812 /* combine analog and digital for DVI-I */
813 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
814 (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
815 ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
816 (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
817 bios_connectors[i].devices |=
818 bios_connectors[j].devices;
819 bios_connectors[i].connector_type =
820 DRM_MODE_CONNECTOR_DVII;
821 if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
eed45b30
AD		 822 bios_connectors[i].hpd =
823 bios_connectors[j].hpd;
f56cd64f 824 bios_connectors[j].valid = false;
771fe6b9
JG		 825 }
826 }
827 }
828 }
829 }
830 }
831
832 /* add the connectors */
eed45b30 833 for (i = 0; i < max_device; i++) {
b75fad06
AD		 834 if (bios_connectors[i].valid) {
835 uint16_t connector_object_id =
836 atombios_get_connector_object_id(dev,
837 bios_connectors[i].connector_type,
838 bios_connectors[i].devices);
771fe6b9
JG		 839 radeon_add_atom_connector(dev,
840 bios_connectors[i].line_mux,
841 bios_connectors[i].devices,
842 bios_connectors[i].
843 connector_type,
844 &bios_connectors[i].ddc_bus,
b75fad06 845 false, 0,
eed45b30
AD		 846 connector_object_id,
847 &bios_connectors[i].hpd);
b75fad06 848 }
771fe6b9
JG		 849 }
850
851 radeon_link_encoder_connector(dev);
852
853 return true;
854}
855
856union firmware_info {
857 ATOM_FIRMWARE_INFO info;
858 ATOM_FIRMWARE_INFO_V1_2 info_12;
859 ATOM_FIRMWARE_INFO_V1_3 info_13;
860 ATOM_FIRMWARE_INFO_V1_4 info_14;
bcc1c2a1 861 ATOM_FIRMWARE_INFO_V2_1 info_21;
771fe6b9
JG		 862};
863
864bool radeon_atom_get_clock_info(struct drm_device *dev)
865{
866 struct radeon_device *rdev = dev->dev_private;
867 struct radeon_mode_info *mode_info = &rdev->mode_info;
868 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
869 union firmware_info *firmware_info;
870 uint8_t frev, crev;
871 struct radeon_pll *p1pll = &rdev->clock.p1pll;
872 struct radeon_pll *p2pll = &rdev->clock.p2pll;
bcc1c2a1 873 struct radeon_pll *dcpll = &rdev->clock.dcpll;
771fe6b9
JG		 874 struct radeon_pll *spll = &rdev->clock.spll;
875 struct radeon_pll *mpll = &rdev->clock.mpll;
876 uint16_t data_offset;
877
a084e6ee
AD		 878 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
879 &frev, &crev, &data_offset)) {
880 firmware_info =
881 (union firmware_info *)(mode_info->atom_context->bios +
882 data_offset);
771fe6b9
JG		 883 /* pixel clocks */
884 p1pll->reference_freq =
885 le16_to_cpu(firmware_info->info.usReferenceClock);
886 p1pll->reference_div = 0;
887
bc293e58
MF		 888 if (crev < 2)
889 p1pll->pll_out_min =
890 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
891 else
892 p1pll->pll_out_min =
893 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
771fe6b9
JG		 894 p1pll->pll_out_max =
895 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
896
86cb2bbf
AD		 897 if (crev >= 4) {
898 p1pll->lcd_pll_out_min =
899 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
900 if (p1pll->lcd_pll_out_min == 0)
901 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
902 p1pll->lcd_pll_out_max =
903 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
904 if (p1pll->lcd_pll_out_max == 0)
905 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
906 } else {
907 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
908 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
909 }
910
771fe6b9
JG		 911 if (p1pll->pll_out_min == 0) {
912 if (ASIC_IS_AVIVO(rdev))
913 p1pll->pll_out_min = 64800;
914 else
915 p1pll->pll_out_min = 20000;
8f552a66
AD		 916 } else if (p1pll->pll_out_min > 64800) {
917 /* Limiting the pll output range is a good thing generally as
918 * it limits the number of possible pll combinations for a given
919 * frequency presumably to the ones that work best on each card.
920 * However, certain duallink DVI monitors seem to like
921 * pll combinations that would be limited by this at least on
922 * pre-DCE 3.0 r6xx hardware. This might need to be adjusted per
923 * family.
924 */
b27b6375
AD		 925 if (!radeon_new_pll)
926 p1pll->pll_out_min = 64800;
771fe6b9
JG		 927 }
928
929 p1pll->pll_in_min =
930 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
931 p1pll->pll_in_max =
932 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
933
934 *p2pll = *p1pll;
935
936 /* system clock */
937 spll->reference_freq =
938 le16_to_cpu(firmware_info->info.usReferenceClock);
939 spll->reference_div = 0;
940
941 spll->pll_out_min =
942 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
943 spll->pll_out_max =
944 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
945
946 /* ??? */
947 if (spll->pll_out_min == 0) {
948 if (ASIC_IS_AVIVO(rdev))
949 spll->pll_out_min = 64800;
950 else
951 spll->pll_out_min = 20000;
952 }
953
954 spll->pll_in_min =
955 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
956 spll->pll_in_max =
957 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
958
959 /* memory clock */
960 mpll->reference_freq =
961 le16_to_cpu(firmware_info->info.usReferenceClock);
962 mpll->reference_div = 0;
963
964 mpll->pll_out_min =
965 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
966 mpll->pll_out_max =
967 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
968
969 /* ??? */
970 if (mpll->pll_out_min == 0) {
971 if (ASIC_IS_AVIVO(rdev))
972 mpll->pll_out_min = 64800;
973 else
974 mpll->pll_out_min = 20000;
975 }
976
977 mpll->pll_in_min =
978 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
979 mpll->pll_in_max =
980 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
981
982 rdev->clock.default_sclk =
983 le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
984 rdev->clock.default_mclk =
985 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
986
bcc1c2a1
AD		 987 if (ASIC_IS_DCE4(rdev)) {
988 rdev->clock.default_dispclk =
989 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
990 if (rdev->clock.default_dispclk == 0)
991 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
992 rdev->clock.dp_extclk =
993 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
994 }
995 *dcpll = *p1pll;
996
771fe6b9
JG		 997 return true;
998 }
bcc1c2a1 999
771fe6b9
JG		 1000 return false;
1001}
1002
06b6476d
AD		 1003union igp_info {
1004 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1005 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1006};
1007
1008bool radeon_atombios_sideport_present(struct radeon_device *rdev)
1009{
1010 struct radeon_mode_info *mode_info = &rdev->mode_info;
1011 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1012 union igp_info *igp_info;
1013 u8 frev, crev;
1014 u16 data_offset;
1015
a084e6ee
AD		 1016 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1017 &frev, &crev, &data_offset)) {
1018 igp_info = (union igp_info *)(mode_info->atom_context->bios +
06b6476d 1019 data_offset);
06b6476d
AD		 1020 switch (crev) {
1021 case 1:
1022 if (igp_info->info.ucMemoryType & 0xf0)
1023 return true;
1024 break;
1025 case 2:
1026 if (igp_info->info_2.ucMemoryType & 0x0f)
1027 return true;
1028 break;
1029 default:
1030 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1031 break;
1032 }
1033 }
1034 return false;
1035}
1036
445282db
DA		 1037bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
1038 struct radeon_encoder_int_tmds *tmds)
771fe6b9
JG		 1039{
1040 struct drm_device *dev = encoder->base.dev;
1041 struct radeon_device *rdev = dev->dev_private;
1042 struct radeon_mode_info *mode_info = &rdev->mode_info;
1043 int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
1044 uint16_t data_offset;
1045 struct _ATOM_TMDS_INFO *tmds_info;
1046 uint8_t frev, crev;
1047 uint16_t maxfreq;
1048 int i;
771fe6b9 1049
a084e6ee
AD		 1050 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1051 &frev, &crev, &data_offset)) {
1052 tmds_info =
1053 (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
1054 data_offset);
771fe6b9 1055
771fe6b9
JG		 1056 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
1057 for (i = 0; i < 4; i++) {
1058 tmds->tmds_pll[i].freq =
1059 le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
1060 tmds->tmds_pll[i].value =
1061 tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
1062 tmds->tmds_pll[i].value |=
1063 (tmds_info->asMiscInfo[i].
1064 ucPLL_VCO_Gain & 0x3f) << 6;
1065 tmds->tmds_pll[i].value |=
1066 (tmds_info->asMiscInfo[i].
1067 ucPLL_DutyCycle & 0xf) << 12;
1068 tmds->tmds_pll[i].value |=
1069 (tmds_info->asMiscInfo[i].
1070 ucPLL_VoltageSwing & 0xf) << 16;
1071
1072 DRM_DEBUG("TMDS PLL From ATOMBIOS %u %x\n",
1073 tmds->tmds_pll[i].freq,
1074 tmds->tmds_pll[i].value);
1075
1076 if (maxfreq == tmds->tmds_pll[i].freq) {
1077 tmds->tmds_pll[i].freq = 0xffffffff;
1078 break;
1079 }
1080 }
445282db 1081 return true;
771fe6b9 1082 }
445282db 1083 return false;
771fe6b9
JG		 1084}
1085
ebbe1cb9
AD		 1086static struct radeon_atom_ss *radeon_atombios_get_ss_info(struct
1087 radeon_encoder
1088 *encoder,
1089 int id)
1090{
1091 struct drm_device *dev = encoder->base.dev;
1092 struct radeon_device *rdev = dev->dev_private;
1093 struct radeon_mode_info *mode_info = &rdev->mode_info;
1094 int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
1095 uint16_t data_offset;
1096 struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1097 uint8_t frev, crev;
1098 struct radeon_atom_ss *ss = NULL;
279b215e 1099 int i;
ebbe1cb9
AD		 1100
1101 if (id > ATOM_MAX_SS_ENTRY)
1102 return NULL;
1103
a084e6ee
AD		 1104 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1105 &frev, &crev, &data_offset)) {
1106 ss_info =
1107 (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
ebbe1cb9 1108
ebbe1cb9
AD		 1109 ss =
1110 kzalloc(sizeof(struct radeon_atom_ss), GFP_KERNEL);
1111
1112 if (!ss)
1113 return NULL;
1114
279b215e
AD		 1115 for (i = 0; i < ATOM_MAX_SS_ENTRY; i++) {
1116 if (ss_info->asSS_Info[i].ucSS_Id == id) {
1117 ss->percentage =
1118 le16_to_cpu(ss_info->asSS_Info[i].usSpreadSpectrumPercentage);
1119 ss->type = ss_info->asSS_Info[i].ucSpreadSpectrumType;
1120 ss->step = ss_info->asSS_Info[i].ucSS_Step;
1121 ss->delay = ss_info->asSS_Info[i].ucSS_Delay;
1122 ss->range = ss_info->asSS_Info[i].ucSS_Range;
1123 ss->refdiv = ss_info->asSS_Info[i].ucRecommendedRef_Div;
1d3d51b6 1124 break;
279b215e
AD		 1125 }
1126 }
ebbe1cb9
AD		 1127 }
1128 return ss;
1129}
1130
771fe6b9
JG		 1131union lvds_info {
1132 struct _ATOM_LVDS_INFO info;
1133 struct _ATOM_LVDS_INFO_V12 info_12;
1134};
1135
1136struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1137 radeon_encoder
1138 *encoder)
1139{
1140 struct drm_device *dev = encoder->base.dev;
1141 struct radeon_device *rdev = dev->dev_private;
1142 struct radeon_mode_info *mode_info = &rdev->mode_info;
1143 int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
7dde8a19 1144 uint16_t data_offset, misc;
771fe6b9
JG		 1145 union lvds_info *lvds_info;
1146 uint8_t frev, crev;
1147 struct radeon_encoder_atom_dig *lvds = NULL;
1148
a084e6ee
AD		 1149 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1150 &frev, &crev, &data_offset)) {
1151 lvds_info =
1152 (union lvds_info *)(mode_info->atom_context->bios + data_offset);
771fe6b9
JG		 1153 lvds =
1154 kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1155
1156 if (!lvds)
1157 return NULL;
1158
de2103e4 1159 lvds->native_mode.clock =
771fe6b9 1160 le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
de2103e4 1161 lvds->native_mode.hdisplay =
771fe6b9 1162 le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
de2103e4 1163 lvds->native_mode.vdisplay =
771fe6b9 1164 le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
de2103e4
AD		 1165 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1166 le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1167 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1168 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1169 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1170 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1171 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1172 le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1173 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1174 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1175 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1176 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
771fe6b9
JG		 1177 lvds->panel_pwr_delay =
1178 le16_to_cpu(lvds_info->info.usOffDelayInMs);
1179 lvds->lvds_misc = lvds_info->info.ucLVDS_Misc;
7dde8a19
AD		 1180
1181 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1182 if (misc & ATOM_VSYNC_POLARITY)
1183 lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1184 if (misc & ATOM_HSYNC_POLARITY)
1185 lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1186 if (misc & ATOM_COMPOSITESYNC)
1187 lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1188 if (misc & ATOM_INTERLACE)
1189 lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1190 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1191 lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1192
de2103e4
AD		 1193 /* set crtc values */
1194 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
771fe6b9 1195
ebbe1cb9
AD		 1196 lvds->ss = radeon_atombios_get_ss_info(encoder, lvds_info->info.ucSS_Id);
1197
7c27f87d 1198 if (ASIC_IS_AVIVO(rdev)) {
383be5d1
AD		 1199 if (radeon_new_pll == 0)
1200 lvds->pll_algo = PLL_ALGO_LEGACY;
1201 else
1202 lvds->pll_algo = PLL_ALGO_NEW;
1203 } else {
1204 if (radeon_new_pll == 1)
1205 lvds->pll_algo = PLL_ALGO_NEW;
7c27f87d
AD		 1206 else
1207 lvds->pll_algo = PLL_ALGO_LEGACY;
383be5d1 1208 }
7c27f87d 1209
771fe6b9
JG		 1210 encoder->native_mode = lvds->native_mode;
1211 }
1212 return lvds;
1213}
1214
6fe7ac3f
AD		 1215struct radeon_encoder_primary_dac *
1216radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1217{
1218 struct drm_device *dev = encoder->base.dev;
1219 struct radeon_device *rdev = dev->dev_private;
1220 struct radeon_mode_info *mode_info = &rdev->mode_info;
1221 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1222 uint16_t data_offset;
1223 struct _COMPASSIONATE_DATA *dac_info;
1224 uint8_t frev, crev;
1225 uint8_t bg, dac;
6fe7ac3f
AD		 1226 struct radeon_encoder_primary_dac *p_dac = NULL;
1227
a084e6ee
AD		 1228 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1229 &frev, &crev, &data_offset)) {
1230 dac_info = (struct _COMPASSIONATE_DATA *)
1231 (mode_info->atom_context->bios + data_offset);
6fe7ac3f 1232
6fe7ac3f
AD		 1233 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
1234
1235 if (!p_dac)
1236 return NULL;
1237
1238 bg = dac_info->ucDAC1_BG_Adjustment;
1239 dac = dac_info->ucDAC1_DAC_Adjustment;
1240 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1241
1242 }
1243 return p_dac;
1244}
1245
4ce001ab 1246bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
5a9bcacc 1247 struct drm_display_mode *mode)
4ce001ab
DA		 1248{
1249 struct radeon_mode_info *mode_info = &rdev->mode_info;
1250 ATOM_ANALOG_TV_INFO *tv_info;
1251 ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1252 ATOM_DTD_FORMAT *dtd_timings;
1253 int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1254 u8 frev, crev;
5a9bcacc 1255 u16 data_offset, misc;
4ce001ab 1256
a084e6ee
AD		 1257 if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL,
1258 &frev, &crev, &data_offset))
1259 return false;
4ce001ab
DA		 1260
1261 switch (crev) {
1262 case 1:
1263 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1264 if (index > MAX_SUPPORTED_TV_TIMING)
1265 return false;
1266
5a9bcacc
AD		 1267 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1268 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1269 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1270 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1271 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1272
1273 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1274 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1275 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1276 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1277 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1278
1279 mode->flags = 0;
1280 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1281 if (misc & ATOM_VSYNC_POLARITY)
1282 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1283 if (misc & ATOM_HSYNC_POLARITY)
1284 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1285 if (misc & ATOM_COMPOSITESYNC)
1286 mode->flags |= DRM_MODE_FLAG_CSYNC;
1287 if (misc & ATOM_INTERLACE)
1288 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1289 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1290 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1291
1292 mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
4ce001ab
DA		 1293
1294 if (index == 1) {
1295 /* PAL timings appear to have wrong values for totals */
5a9bcacc
AD		 1296 mode->crtc_htotal -= 1;
1297 mode->crtc_vtotal -= 1;
4ce001ab
DA		 1298 }
1299 break;
1300 case 2:
1301 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
1302 if (index > MAX_SUPPORTED_TV_TIMING_V1_2)
1303 return false;
1304
1305 dtd_timings = &tv_info_v1_2->aModeTimings[index];
5a9bcacc
AD		 1306 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1307 le16_to_cpu(dtd_timings->usHBlanking_Time);
1308 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1309 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1310 le16_to_cpu(dtd_timings->usHSyncOffset);
1311 mode->crtc_hsync_end = mode->crtc_hsync_start +
1312 le16_to_cpu(dtd_timings->usHSyncWidth);
1313
1314 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1315 le16_to_cpu(dtd_timings->usVBlanking_Time);
1316 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1317 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1318 le16_to_cpu(dtd_timings->usVSyncOffset);
1319 mode->crtc_vsync_end = mode->crtc_vsync_start +
1320 le16_to_cpu(dtd_timings->usVSyncWidth);
1321
1322 mode->flags = 0;
1323 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1324 if (misc & ATOM_VSYNC_POLARITY)
1325 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1326 if (misc & ATOM_HSYNC_POLARITY)
1327 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1328 if (misc & ATOM_COMPOSITESYNC)
1329 mode->flags |= DRM_MODE_FLAG_CSYNC;
1330 if (misc & ATOM_INTERLACE)
1331 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1332 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1333 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1334
1335 mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
4ce001ab
DA		 1336 break;
1337 }
1338 return true;
1339}
1340
d79766fa
AD		 1341enum radeon_tv_std
1342radeon_atombios_get_tv_info(struct radeon_device *rdev)
1343{
1344 struct radeon_mode_info *mode_info = &rdev->mode_info;
1345 int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1346 uint16_t data_offset;
1347 uint8_t frev, crev;
1348 struct _ATOM_ANALOG_TV_INFO *tv_info;
1349 enum radeon_tv_std tv_std = TV_STD_NTSC;
1350
a084e6ee
AD		 1351 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1352 &frev, &crev, &data_offset)) {
d79766fa 1353
a084e6ee
AD		 1354 tv_info = (struct _ATOM_ANALOG_TV_INFO *)
1355 (mode_info->atom_context->bios + data_offset);
d79766fa 1356
a084e6ee
AD		 1357 switch (tv_info->ucTV_BootUpDefaultStandard) {
1358 case ATOM_TV_NTSC:
1359 tv_std = TV_STD_NTSC;
1360 DRM_INFO("Default TV standard: NTSC\n");
1361 break;
1362 case ATOM_TV_NTSCJ:
1363 tv_std = TV_STD_NTSC_J;
1364 DRM_INFO("Default TV standard: NTSC-J\n");
1365 break;
1366 case ATOM_TV_PAL:
1367 tv_std = TV_STD_PAL;
1368 DRM_INFO("Default TV standard: PAL\n");
1369 break;
1370 case ATOM_TV_PALM:
1371 tv_std = TV_STD_PAL_M;
1372 DRM_INFO("Default TV standard: PAL-M\n");
1373 break;
1374 case ATOM_TV_PALN:
1375 tv_std = TV_STD_PAL_N;
1376 DRM_INFO("Default TV standard: PAL-N\n");
1377 break;
1378 case ATOM_TV_PALCN:
1379 tv_std = TV_STD_PAL_CN;
1380 DRM_INFO("Default TV standard: PAL-CN\n");
1381 break;
1382 case ATOM_TV_PAL60:
1383 tv_std = TV_STD_PAL_60;
1384 DRM_INFO("Default TV standard: PAL-60\n");
1385 break;
1386 case ATOM_TV_SECAM:
1387 tv_std = TV_STD_SECAM;
1388 DRM_INFO("Default TV standard: SECAM\n");
1389 break;
1390 default:
1391 tv_std = TV_STD_NTSC;
1392 DRM_INFO("Unknown TV standard; defaulting to NTSC\n");
1393 break;
1394 }
d79766fa
AD		 1395 }
1396 return tv_std;
1397}
1398
6fe7ac3f
AD		 1399struct radeon_encoder_tv_dac *
1400radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1401{
1402 struct drm_device *dev = encoder->base.dev;
1403 struct radeon_device *rdev = dev->dev_private;
1404 struct radeon_mode_info *mode_info = &rdev->mode_info;
1405 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1406 uint16_t data_offset;
1407 struct _COMPASSIONATE_DATA *dac_info;
1408 uint8_t frev, crev;
1409 uint8_t bg, dac;
6fe7ac3f
AD		 1410 struct radeon_encoder_tv_dac *tv_dac = NULL;
1411
a084e6ee
AD		 1412 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1413 &frev, &crev, &data_offset)) {
6fe7ac3f 1414
a084e6ee
AD		 1415 dac_info = (struct _COMPASSIONATE_DATA *)
1416 (mode_info->atom_context->bios + data_offset);
6fe7ac3f 1417
6fe7ac3f
AD		 1418 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1419
1420 if (!tv_dac)
1421 return NULL;
1422
1423 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1424 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1425 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1426
1427 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1428 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1429 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1430
1431 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1432 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1433 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1434
d79766fa 1435 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
6fe7ac3f
AD		 1436 }
1437 return tv_dac;
1438}
1439
29fb52ca
AD		 1440static const char *thermal_controller_names[] = {
1441 "NONE",
1442 "LM63",
1443 "ADM1032",
1444 "ADM1030",
1445 "MUA6649",
1446 "LM64",
1447 "F75375",
1448 "ASC7512",
1449};
1450
1451static const char *pp_lib_thermal_controller_names[] = {
1452 "NONE",
1453 "LM63",
1454 "ADM1032",
1455 "ADM1030",
1456 "MUA6649",
1457 "LM64",
1458 "F75375",
1459 "RV6xx",
1460 "RV770",
1461 "ADT7473",
1462};
1463
56278a8e
AD		 1464union power_info {
1465 struct _ATOM_POWERPLAY_INFO info;
1466 struct _ATOM_POWERPLAY_INFO_V2 info_2;
1467 struct _ATOM_POWERPLAY_INFO_V3 info_3;
1468 struct _ATOM_PPLIB_POWERPLAYTABLE info_4;
1469};
1470
1471void radeon_atombios_get_power_modes(struct radeon_device *rdev)
771fe6b9 1472{
56278a8e
AD		 1473 struct radeon_mode_info *mode_info = &rdev->mode_info;
1474 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
1475 u16 data_offset;
1476 u8 frev, crev;
1477 u32 misc, misc2 = 0, sclk, mclk;
1478 union power_info *power_info;
1479 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
1480 struct _ATOM_PPLIB_STATE *power_state;
1481 int num_modes = 0, i, j;
1482 int state_index = 0, mode_index = 0;
29fb52ca 1483 struct radeon_i2c_bus_rec i2c_bus;
771fe6b9 1484
56278a8e 1485 rdev->pm.default_power_state = NULL;
56278a8e 1486
a084e6ee
AD		 1487 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1488 &frev, &crev, &data_offset)) {
1489 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
56278a8e 1490 if (frev < 4) {
29fb52ca
AD		 1491 /* add the i2c bus for thermal/fan chip */
1492 if (power_info->info.ucOverdriveThermalController > 0) {
1493 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
1494 thermal_controller_names[power_info->info.ucOverdriveThermalController],
1495 power_info->info.ucOverdriveControllerAddress >> 1);
1496 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
1497 rdev->pm.i2c_bus = radeon_i2c_create(rdev->ddev, &i2c_bus, "Thermal");
1498 }
56278a8e
AD		 1499 num_modes = power_info->info.ucNumOfPowerModeEntries;
1500 if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
1501 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
1502 for (i = 0; i < num_modes; i++) {
1503 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
1504 switch (frev) {
1505 case 1:
1506 rdev->pm.power_state[state_index].num_clock_modes = 1;
1507 rdev->pm.power_state[state_index].clock_info[0].mclk =
1508 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
1509 rdev->pm.power_state[state_index].clock_info[0].sclk =
1510 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
1511 /* skip invalid modes */
1512 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1513 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1514 continue;
1515 /* skip overclock modes for now */
1516 if ((rdev->pm.power_state[state_index].clock_info[0].mclk >
27459324 1517 rdev->clock.default_mclk + RADEON_MODE_OVERCLOCK_MARGIN) ||
56278a8e 1518 (rdev->pm.power_state[state_index].clock_info[0].sclk >
27459324 1519 rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN))
56278a8e
AD		 1520 continue;
1521 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =
1522 power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
1523 misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
1524 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
1525 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1526 VOLTAGE_GPIO;
1527 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1528 radeon_lookup_gpio(rdev,
1529 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
1530 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1531 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1532 true;
1533 else
1534 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1535 false;
1536 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1537 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1538 VOLTAGE_VDDC;
1539 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1540 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
1541 }
0ec0e74f
AD		 1542 /* order matters! */
1543 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1544 rdev->pm.power_state[state_index].type =
1545 POWER_STATE_TYPE_POWERSAVE;
1546 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1547 rdev->pm.power_state[state_index].type =
1548 POWER_STATE_TYPE_BATTERY;
1549 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1550 rdev->pm.power_state[state_index].type =
1551 POWER_STATE_TYPE_BATTERY;
1552 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1553 rdev->pm.power_state[state_index].type =
1554 POWER_STATE_TYPE_BALANCED;
1555 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN)
1556 rdev->pm.power_state[state_index].type =
1557 POWER_STATE_TYPE_PERFORMANCE;
56278a8e 1558 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
0ec0e74f
AD		 1559 rdev->pm.power_state[state_index].type =
1560 POWER_STATE_TYPE_DEFAULT;
56278a8e 1561 rdev->pm.default_power_state = &rdev->pm.power_state[state_index];
56278a8e
AD		 1562 rdev->pm.power_state[state_index].default_clock_mode =
1563 &rdev->pm.power_state[state_index].clock_info[0];
56278a8e
AD		 1564 }
1565 state_index++;
1566 break;
1567 case 2:
1568 rdev->pm.power_state[state_index].num_clock_modes = 1;
1569 rdev->pm.power_state[state_index].clock_info[0].mclk =
1570 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
1571 rdev->pm.power_state[state_index].clock_info[0].sclk =
1572 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
1573 /* skip invalid modes */
1574 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1575 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1576 continue;
1577 /* skip overclock modes for now */
1578 if ((rdev->pm.power_state[state_index].clock_info[0].mclk >
27459324 1579 rdev->clock.default_mclk + RADEON_MODE_OVERCLOCK_MARGIN) ||
56278a8e 1580 (rdev->pm.power_state[state_index].clock_info[0].sclk >
27459324 1581 rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN))
56278a8e
AD		 1582 continue;
1583 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =
1584 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
1585 misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
1586 misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
1587 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
1588 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1589 VOLTAGE_GPIO;
1590 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1591 radeon_lookup_gpio(rdev,
1592 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
1593 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1594 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1595 true;
1596 else
1597 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1598 false;
1599 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1600 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1601 VOLTAGE_VDDC;
1602 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1603 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
1604 }
0ec0e74f
AD		 1605 /* order matters! */
1606 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1607 rdev->pm.power_state[state_index].type =
1608 POWER_STATE_TYPE_POWERSAVE;
1609 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1610 rdev->pm.power_state[state_index].type =
1611 POWER_STATE_TYPE_BATTERY;
1612 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1613 rdev->pm.power_state[state_index].type =
1614 POWER_STATE_TYPE_BATTERY;
1615 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1616 rdev->pm.power_state[state_index].type =
1617 POWER_STATE_TYPE_BALANCED;
1618 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN)
1619 rdev->pm.power_state[state_index].type =
1620 POWER_STATE_TYPE_PERFORMANCE;
1621 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1622 rdev->pm.power_state[state_index].type =
1623 POWER_STATE_TYPE_BALANCED;
56278a8e 1624 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
0ec0e74f
AD		 1625 rdev->pm.power_state[state_index].type =
1626 POWER_STATE_TYPE_DEFAULT;
56278a8e 1627 rdev->pm.default_power_state = &rdev->pm.power_state[state_index];
56278a8e
AD		 1628 rdev->pm.power_state[state_index].default_clock_mode =
1629 &rdev->pm.power_state[state_index].clock_info[0];
56278a8e
AD		 1630 }
1631 state_index++;
1632 break;
1633 case 3:
1634 rdev->pm.power_state[state_index].num_clock_modes = 1;
1635 rdev->pm.power_state[state_index].clock_info[0].mclk =
1636 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
1637 rdev->pm.power_state[state_index].clock_info[0].sclk =
1638 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
1639 /* skip invalid modes */
1640 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1641 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1642 continue;
1643 /* skip overclock modes for now */
1644 if ((rdev->pm.power_state[state_index].clock_info[0].mclk >
27459324 1645 rdev->clock.default_mclk + RADEON_MODE_OVERCLOCK_MARGIN) ||
56278a8e 1646 (rdev->pm.power_state[state_index].clock_info[0].sclk >
27459324 1647 rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN))
56278a8e
AD		 1648 continue;
1649 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =
1650 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
1651 misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
1652 misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
1653 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
1654 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1655 VOLTAGE_GPIO;
1656 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1657 radeon_lookup_gpio(rdev,
1658 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
1659 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1660 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1661 true;
1662 else
1663 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1664 false;
1665 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1666 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1667 VOLTAGE_VDDC;
1668 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1669 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
1670 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
1671 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
1672 true;
1673 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
1674 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
1675 }
1676 }
0ec0e74f
AD		 1677 /* order matters! */
1678 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1679 rdev->pm.power_state[state_index].type =
1680 POWER_STATE_TYPE_POWERSAVE;
1681 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1682 rdev->pm.power_state[state_index].type =
1683 POWER_STATE_TYPE_BATTERY;
1684 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1685 rdev->pm.power_state[state_index].type =
1686 POWER_STATE_TYPE_BATTERY;
1687 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1688 rdev->pm.power_state[state_index].type =
1689 POWER_STATE_TYPE_BALANCED;
1690 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN)
1691 rdev->pm.power_state[state_index].type =
1692 POWER_STATE_TYPE_PERFORMANCE;
1693 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1694 rdev->pm.power_state[state_index].type =
1695 POWER_STATE_TYPE_BALANCED;
56278a8e 1696 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
0ec0e74f
AD		 1697 rdev->pm.power_state[state_index].type =
1698 POWER_STATE_TYPE_DEFAULT;
56278a8e 1699 rdev->pm.default_power_state = &rdev->pm.power_state[state_index];
56278a8e
AD		 1700 rdev->pm.power_state[state_index].default_clock_mode =
1701 &rdev->pm.power_state[state_index].clock_info[0];
56278a8e
AD		 1702 }
1703 state_index++;
1704 break;
1705 }
1706 }
1707 } else if (frev == 4) {
29fb52ca
AD		 1708 /* add the i2c bus for thermal/fan chip */
1709 /* no support for internal controller yet */
1710 if (power_info->info_4.sThermalController.ucType > 0) {
06abdb0e 1711 if ((power_info->info_4.sThermalController.ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) ||
29fb52ca
AD		 1712 (power_info->info_4.sThermalController.ucType == ATOM_PP_THERMALCONTROLLER_RV770)) {
1713 DRM_INFO("Internal thermal controller %s fan control\n",
1714 (power_info->info_4.sThermalController.ucFanParameters &
1715 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
1716 } else {
1717 DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
1718 pp_lib_thermal_controller_names[power_info->info_4.sThermalController.ucType],
1719 power_info->info_4.sThermalController.ucI2cAddress >> 1,
1720 (power_info->info_4.sThermalController.ucFanParameters &
1721 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
1722 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info_4.sThermalController.ucI2cLine);
1723 rdev->pm.i2c_bus = radeon_i2c_create(rdev->ddev, &i2c_bus, "Thermal");
1724 }
1725 }
56278a8e
AD		 1726 for (i = 0; i < power_info->info_4.ucNumStates; i++) {
1727 mode_index = 0;
1728 power_state = (struct _ATOM_PPLIB_STATE *)
1729 (mode_info->atom_context->bios +
1730 data_offset +
1731 le16_to_cpu(power_info->info_4.usStateArrayOffset) +
1732 i * power_info->info_4.ucStateEntrySize);
1733 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
1734 (mode_info->atom_context->bios +
1735 data_offset +
1736 le16_to_cpu(power_info->info_4.usNonClockInfoArrayOffset) +
1737 (power_state->ucNonClockStateIndex *
1738 power_info->info_4.ucNonClockSize));
56278a8e
AD		 1739 for (j = 0; j < (power_info->info_4.ucStateEntrySize - 1); j++) {
1740 if (rdev->flags & RADEON_IS_IGP) {
1741 struct _ATOM_PPLIB_RS780_CLOCK_INFO *clock_info =
1742 (struct _ATOM_PPLIB_RS780_CLOCK_INFO *)
1743 (mode_info->atom_context->bios +
1744 data_offset +
1745 le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) +
1746 (power_state->ucClockStateIndices[j] *
1747 power_info->info_4.ucClockInfoSize));
1748 sclk = le16_to_cpu(clock_info->usLowEngineClockLow);
1749 sclk |= clock_info->ucLowEngineClockHigh << 16;
1750 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
1751 /* skip invalid modes */
1752 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
1753 continue;
1754 /* skip overclock modes for now */
1755 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk >
27459324 1756 rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN)
56278a8e
AD		 1757 continue;
1758 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
1759 VOLTAGE_SW;
1760 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
1761 clock_info->usVDDC;
1762 mode_index++;
1763 } else {
1764 struct _ATOM_PPLIB_R600_CLOCK_INFO *clock_info =
1765 (struct _ATOM_PPLIB_R600_CLOCK_INFO *)
1766 (mode_info->atom_context->bios +
1767 data_offset +
1768 le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) +
1769 (power_state->ucClockStateIndices[j] *
1770 power_info->info_4.ucClockInfoSize));
1771 sclk = le16_to_cpu(clock_info->usEngineClockLow);
1772 sclk |= clock_info->ucEngineClockHigh << 16;
1773 mclk = le16_to_cpu(clock_info->usMemoryClockLow);
1774 mclk |= clock_info->ucMemoryClockHigh << 16;
1775 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
1776 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
1777 /* skip invalid modes */
1778 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
1779 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
1780 continue;
1781 /* skip overclock modes for now */
1782 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk >
27459324 1783 rdev->clock.default_mclk + RADEON_MODE_OVERCLOCK_MARGIN) ||
56278a8e 1784 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk >
27459324 1785 rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN))
56278a8e
AD		 1786 continue;
1787 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
1788 VOLTAGE_SW;
1789 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
1790 clock_info->usVDDC;
1791 mode_index++;
1792 }
1793 }
1794 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
1795 if (mode_index) {
845db70d 1796 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
56278a8e 1797 misc2 = le16_to_cpu(non_clock_info->usClassification);
845db70d
RM		 1798 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =
1799 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
1800 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
0ec0e74f
AD		 1801 switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
1802 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
1803 rdev->pm.power_state[state_index].type =
1804 POWER_STATE_TYPE_BATTERY;
1805 break;
1806 case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
1807 rdev->pm.power_state[state_index].type =
1808 POWER_STATE_TYPE_BALANCED;
1809 break;
1810 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
1811 rdev->pm.power_state[state_index].type =
1812 POWER_STATE_TYPE_PERFORMANCE;
1813 break;
1814 }
56278a8e 1815 if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
0ec0e74f
AD		 1816 rdev->pm.power_state[state_index].type =
1817 POWER_STATE_TYPE_DEFAULT;
56278a8e 1818 rdev->pm.default_power_state = &rdev->pm.power_state[state_index];
56278a8e
AD		 1819 rdev->pm.power_state[state_index].default_clock_mode =
1820 &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
56278a8e
AD		 1821 }
1822 state_index++;
1823 }
1824 }
1825 }
1826 } else {
1827 /* XXX figure out some good default low power mode for cards w/out power tables */
1828 }
1829
1830 if (rdev->pm.default_power_state == NULL) {
1831 /* add the default mode */
0ec0e74f
AD		 1832 rdev->pm.power_state[state_index].type =
1833 POWER_STATE_TYPE_DEFAULT;
56278a8e
AD		 1834 rdev->pm.power_state[state_index].num_clock_modes = 1;
1835 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
1836 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
1837 rdev->pm.power_state[state_index].default_clock_mode =
1838 &rdev->pm.power_state[state_index].clock_info[0];
56278a8e
AD		 1839 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
1840 if (rdev->asic->get_pcie_lanes)
1841 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = radeon_get_pcie_lanes(rdev);
1842 else
1843 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = 16;
1844 rdev->pm.default_power_state = &rdev->pm.power_state[state_index];
56278a8e
AD		 1845 state_index++;
1846 }
1847 rdev->pm.num_power_states = state_index;
9038dfdf
RM		 1848
1849 rdev->pm.current_power_state = rdev->pm.default_power_state;
1850 rdev->pm.current_clock_mode =
1851 rdev->pm.default_power_state->default_clock_mode;
771fe6b9
JG		 1852}
1853
771fe6b9 1854void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
771fe6b9 1855{
771fe6b9
JG		 1856 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
1857 int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
771fe6b9
JG		 1858
1859 args.ucEnable = enable;
1860
1861 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1862}
1863
7433874e
RM		 1864uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
1865{
1866 GET_ENGINE_CLOCK_PS_ALLOCATION args;
1867 int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
1868
1869 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1870 return args.ulReturnEngineClock;
1871}
1872
1873uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
1874{
1875 GET_MEMORY_CLOCK_PS_ALLOCATION args;
1876 int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
1877
1878 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1879 return args.ulReturnMemoryClock;
1880}
1881
771fe6b9
JG		 1882void radeon_atom_set_engine_clock(struct radeon_device *rdev,
1883 uint32_t eng_clock)
1884{
1885 SET_ENGINE_CLOCK_PS_ALLOCATION args;
1886 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
1887
1888 args.ulTargetEngineClock = eng_clock; /* 10 khz */
1889
1890 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1891}
1892
1893void radeon_atom_set_memory_clock(struct radeon_device *rdev,
1894 uint32_t mem_clock)
1895{
1896 SET_MEMORY_CLOCK_PS_ALLOCATION args;
1897 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
1898
1899 if (rdev->flags & RADEON_IS_IGP)
1900 return;
1901
1902 args.ulTargetMemoryClock = mem_clock; /* 10 khz */
1903
1904 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1905}
1906
1907void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
1908{
1909 struct radeon_device *rdev = dev->dev_private;
1910 uint32_t bios_2_scratch, bios_6_scratch;
1911
1912 if (rdev->family >= CHIP_R600) {
4ce001ab 1913 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
771fe6b9
JG		 1914 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
1915 } else {
4ce001ab 1916 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
771fe6b9
JG		 1917 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
1918 }
1919
1920 /* let the bios control the backlight */
1921 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
1922
1923 /* tell the bios not to handle mode switching */
1924 bios_6_scratch |= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH | ATOM_S6_ACC_MODE);
1925
1926 if (rdev->family >= CHIP_R600) {
1927 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
1928 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
1929 } else {
1930 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
1931 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
1932 }
1933
1934}
1935
f657c2a7
YZ		 1936void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
1937{
1938 uint32_t scratch_reg;
1939 int i;
1940
1941 if (rdev->family >= CHIP_R600)
1942 scratch_reg = R600_BIOS_0_SCRATCH;
1943 else
1944 scratch_reg = RADEON_BIOS_0_SCRATCH;
1945
1946 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
1947 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
1948}
1949
1950void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
1951{
1952 uint32_t scratch_reg;
1953 int i;
1954
1955 if (rdev->family >= CHIP_R600)
1956 scratch_reg = R600_BIOS_0_SCRATCH;
1957 else
1958 scratch_reg = RADEON_BIOS_0_SCRATCH;
1959
1960 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
1961 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
1962}
1963
771fe6b9
JG		 1964void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
1965{
1966 struct drm_device *dev = encoder->dev;
1967 struct radeon_device *rdev = dev->dev_private;
1968 uint32_t bios_6_scratch;
1969
1970 if (rdev->family >= CHIP_R600)
1971 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
1972 else
1973 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
1974
1975 if (lock)
1976 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
1977 else
1978 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
1979
1980 if (rdev->family >= CHIP_R600)
1981 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
1982 else
1983 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
1984}
1985
1986/* at some point we may want to break this out into individual functions */
1987void
1988radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
1989 struct drm_encoder *encoder,
1990 bool connected)
1991{
1992 struct drm_device *dev = connector->dev;
1993 struct radeon_device *rdev = dev->dev_private;
1994 struct radeon_connector *radeon_connector =
1995 to_radeon_connector(connector);
1996 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1997 uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
1998
1999 if (rdev->family >= CHIP_R600) {
2000 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2001 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2002 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2003 } else {
2004 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2005 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2006 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2007 }
2008
2009 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
2010 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
2011 if (connected) {
2012 DRM_DEBUG("TV1 connected\n");
2013 bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
2014 bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
2015 } else {
2016 DRM_DEBUG("TV1 disconnected\n");
2017 bios_0_scratch &= ~ATOM_S0_TV1_MASK;
2018 bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
2019 bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
2020 }
2021 }
2022 if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
2023 (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
2024 if (connected) {
2025 DRM_DEBUG("CV connected\n");
2026 bios_3_scratch |= ATOM_S3_CV_ACTIVE;
2027 bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
2028 } else {
2029 DRM_DEBUG("CV disconnected\n");
2030 bios_0_scratch &= ~ATOM_S0_CV_MASK;
2031 bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
2032 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
2033 }
2034 }
2035 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
2036 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
2037 if (connected) {
2038 DRM_DEBUG("LCD1 connected\n");
2039 bios_0_scratch |= ATOM_S0_LCD1;
2040 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
2041 bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
2042 } else {
2043 DRM_DEBUG("LCD1 disconnected\n");
2044 bios_0_scratch &= ~ATOM_S0_LCD1;
2045 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
2046 bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
2047 }
2048 }
2049 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
2050 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
2051 if (connected) {
2052 DRM_DEBUG("CRT1 connected\n");
2053 bios_0_scratch |= ATOM_S0_CRT1_COLOR;
2054 bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
2055 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
2056 } else {
2057 DRM_DEBUG("CRT1 disconnected\n");
2058 bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
2059 bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
2060 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
2061 }
2062 }
2063 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
2064 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
2065 if (connected) {
2066 DRM_DEBUG("CRT2 connected\n");
2067 bios_0_scratch |= ATOM_S0_CRT2_COLOR;
2068 bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
2069 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
2070 } else {
2071 DRM_DEBUG("CRT2 disconnected\n");
2072 bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
2073 bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
2074 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
2075 }
2076 }
2077 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
2078 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
2079 if (connected) {
2080 DRM_DEBUG("DFP1 connected\n");
2081 bios_0_scratch |= ATOM_S0_DFP1;
2082 bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
2083 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
2084 } else {
2085 DRM_DEBUG("DFP1 disconnected\n");
2086 bios_0_scratch &= ~ATOM_S0_DFP1;
2087 bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
2088 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
2089 }
2090 }
2091 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
2092 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
2093 if (connected) {
2094 DRM_DEBUG("DFP2 connected\n");
2095 bios_0_scratch |= ATOM_S0_DFP2;
2096 bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
2097 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
2098 } else {
2099 DRM_DEBUG("DFP2 disconnected\n");
2100 bios_0_scratch &= ~ATOM_S0_DFP2;
2101 bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
2102 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
2103 }
2104 }
2105 if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
2106 (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
2107 if (connected) {
2108 DRM_DEBUG("DFP3 connected\n");
2109 bios_0_scratch |= ATOM_S0_DFP3;
2110 bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
2111 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
2112 } else {
2113 DRM_DEBUG("DFP3 disconnected\n");
2114 bios_0_scratch &= ~ATOM_S0_DFP3;
2115 bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
2116 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
2117 }
2118 }
2119 if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
2120 (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
2121 if (connected) {
2122 DRM_DEBUG("DFP4 connected\n");
2123 bios_0_scratch |= ATOM_S0_DFP4;
2124 bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
2125 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
2126 } else {
2127 DRM_DEBUG("DFP4 disconnected\n");
2128 bios_0_scratch &= ~ATOM_S0_DFP4;
2129 bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
2130 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
2131 }
2132 }
2133 if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
2134 (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
2135 if (connected) {
2136 DRM_DEBUG("DFP5 connected\n");
2137 bios_0_scratch |= ATOM_S0_DFP5;
2138 bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
2139 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
2140 } else {
2141 DRM_DEBUG("DFP5 disconnected\n");
2142 bios_0_scratch &= ~ATOM_S0_DFP5;
2143 bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
2144 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
2145 }
2146 }
2147
2148 if (rdev->family >= CHIP_R600) {
2149 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
2150 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2151 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2152 } else {
2153 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
2154 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2155 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2156 }
2157}
2158
2159void
2160radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
2161{
2162 struct drm_device *dev = encoder->dev;
2163 struct radeon_device *rdev = dev->dev_private;
2164 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2165 uint32_t bios_3_scratch;
2166
2167 if (rdev->family >= CHIP_R600)
2168 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2169 else
2170 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2171
2172 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2173 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
2174 bios_3_scratch |= (crtc << 18);
2175 }
2176 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2177 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
2178 bios_3_scratch |= (crtc << 24);
2179 }
2180 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2181 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
2182 bios_3_scratch |= (crtc << 16);
2183 }
2184 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2185 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
2186 bios_3_scratch |= (crtc << 20);
2187 }
2188 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2189 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
2190 bios_3_scratch |= (crtc << 17);
2191 }
2192 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2193 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
2194 bios_3_scratch |= (crtc << 19);
2195 }
2196 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2197 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
2198 bios_3_scratch |= (crtc << 23);
2199 }
2200 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
2201 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
2202 bios_3_scratch |= (crtc << 25);
2203 }
2204
2205 if (rdev->family >= CHIP_R600)
2206 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2207 else
2208 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2209}
2210
2211void
2212radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
2213{
2214 struct drm_device *dev = encoder->dev;
2215 struct radeon_device *rdev = dev->dev_private;
2216 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2217 uint32_t bios_2_scratch;
2218
2219 if (rdev->family >= CHIP_R600)
2220 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
2221 else
2222 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
2223
2224 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2225 if (on)
2226 bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
2227 else
2228 bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
2229 }
2230 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2231 if (on)
2232 bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
2233 else
2234 bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
2235 }
2236 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2237 if (on)
2238 bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
2239 else
2240 bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
2241 }
2242 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2243 if (on)
2244 bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
2245 else
2246 bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
2247 }
2248 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2249 if (on)
2250 bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
2251 else
2252 bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
2253 }
2254 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2255 if (on)
2256 bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
2257 else
2258 bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
2259 }
2260 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2261 if (on)
2262 bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
2263 else
2264 bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
2265 }
2266 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
2267 if (on)
2268 bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
2269 else
2270 bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
2271 }
2272 if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
2273 if (on)
2274 bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
2275 else
2276 bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
2277 }
2278 if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
2279 if (on)
2280 bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
2281 else
2282 bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
2283 }
2284
2285 if (rdev->family >= CHIP_R600)
2286 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
2287 else
2288 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
2289}
Clone of davem's net-next-2.6 tree