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drm/radeon/kms: Convert RS600 to new init path
[net-next-2.6.git] / drivers / gpu / drm / radeon / radeon_asic.h
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_ASIC_H__
29#define __RADEON_ASIC_H__
30
31/*
32 * common functions
33 */
34void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
35void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
36
37void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
38void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock);
39void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
40
41/*
42 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
43 */
d4550907
JG		 44extern int r100_init(struct radeon_device *rdev);
45extern void r100_fini(struct radeon_device *rdev);
46extern int r100_suspend(struct radeon_device *rdev);
47extern int r100_resume(struct radeon_device *rdev);
771fe6b9
JG		 48uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg);
49void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
771fe6b9 50int r100_gpu_reset(struct radeon_device *rdev);
7ed220d7 51u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc);
771fe6b9
JG		 52void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
53int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
3ce0a23d 54void r100_cp_commit(struct radeon_device *rdev);
771fe6b9
JG		 55void r100_ring_start(struct radeon_device *rdev);
56int r100_irq_set(struct radeon_device *rdev);
57int r100_irq_process(struct radeon_device *rdev);
58void r100_fence_ring_emit(struct radeon_device *rdev,
59 struct radeon_fence *fence);
60int r100_cs_parse(struct radeon_cs_parser *p);
61void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
62uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg);
63int r100_copy_blit(struct radeon_device *rdev,
64 uint64_t src_offset,
65 uint64_t dst_offset,
66 unsigned num_pages,
67 struct radeon_fence *fence);
e024e110
DA		 68int r100_set_surface_reg(struct radeon_device *rdev, int reg,
69 uint32_t tiling_flags, uint32_t pitch,
70 uint32_t offset, uint32_t obj_size);
71int r100_clear_surface_reg(struct radeon_device *rdev, int reg);
c93bb85b 72void r100_bandwidth_update(struct radeon_device *rdev);
3ce0a23d
JG		 73void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
74int r100_ib_test(struct radeon_device *rdev);
75int r100_ring_test(struct radeon_device *rdev);
771fe6b9
JG		 76
77static struct radeon_asic r100_asic = {
068a117c 78 .init = &r100_init,
d4550907
JG		 79 .fini = &r100_fini,
80 .suspend = &r100_suspend,
81 .resume = &r100_resume,
82 .errata = NULL,
83 .vram_info = NULL,
771fe6b9 84 .gpu_reset = &r100_gpu_reset,
d4550907
JG		 85 .mc_init = NULL,
86 .mc_fini = NULL,
87 .wb_init = NULL,
88 .wb_fini = NULL,
89 .gart_init = NULL,
90 .gart_fini = NULL,
91 .gart_enable = NULL,
92 .gart_disable = NULL,
771fe6b9
JG		 93 .gart_tlb_flush = &r100_pci_gart_tlb_flush,
94 .gart_set_page = &r100_pci_gart_set_page,
d4550907
JG		 95 .cp_init = NULL,
96 .cp_fini = NULL,
97 .cp_disable = NULL,
3ce0a23d 98 .cp_commit = &r100_cp_commit,
771fe6b9 99 .ring_start = &r100_ring_start,
3ce0a23d
JG		 100 .ring_test = &r100_ring_test,
101 .ring_ib_execute = &r100_ring_ib_execute,
d4550907 102 .ib_test = NULL,
771fe6b9
JG		 103 .irq_set = &r100_irq_set,
104 .irq_process = &r100_irq_process,
7ed220d7 105 .get_vblank_counter = &r100_get_vblank_counter,
771fe6b9
JG		 106 .fence_ring_emit = &r100_fence_ring_emit,
107 .cs_parse = &r100_cs_parse,
108 .copy_blit = &r100_copy_blit,
109 .copy_dma = NULL,
110 .copy = &r100_copy_blit,
111 .set_engine_clock = &radeon_legacy_set_engine_clock,
112 .set_memory_clock = NULL,
113 .set_pcie_lanes = NULL,
114 .set_clock_gating = &radeon_legacy_set_clock_gating,
e024e110
DA		 115 .set_surface_reg = r100_set_surface_reg,
116 .clear_surface_reg = r100_clear_surface_reg,
c93bb85b 117 .bandwidth_update = &r100_bandwidth_update,
771fe6b9
JG		 118};
119
120
121/*
122 * r300,r350,rv350,rv380
123 */
207bf9e9
JG		 124extern int r300_init(struct radeon_device *rdev);
125extern void r300_fini(struct radeon_device *rdev);
126extern int r300_suspend(struct radeon_device *rdev);
127extern int r300_resume(struct radeon_device *rdev);
128extern int r300_gpu_reset(struct radeon_device *rdev);
129extern void r300_ring_start(struct radeon_device *rdev);
130extern void r300_fence_ring_emit(struct radeon_device *rdev,
131 struct radeon_fence *fence);
132extern int r300_cs_parse(struct radeon_cs_parser *p);
133extern void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev);
134extern int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
135extern uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg);
136extern void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
137extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes);
138extern int r300_copy_dma(struct radeon_device *rdev,
139 uint64_t src_offset,
140 uint64_t dst_offset,
141 unsigned num_pages,
142 struct radeon_fence *fence);
771fe6b9 143static struct radeon_asic r300_asic = {
068a117c 144 .init = &r300_init,
207bf9e9
JG		 145 .fini = &r300_fini,
146 .suspend = &r300_suspend,
147 .resume = &r300_resume,
148 .errata = NULL,
149 .vram_info = NULL,
771fe6b9 150 .gpu_reset = &r300_gpu_reset,
207bf9e9
JG		 151 .mc_init = NULL,
152 .mc_fini = NULL,
153 .wb_init = NULL,
154 .wb_fini = NULL,
155 .gart_init = NULL,
156 .gart_fini = NULL,
157 .gart_enable = NULL,
158 .gart_disable = NULL,
771fe6b9
JG		 159 .gart_tlb_flush = &r100_pci_gart_tlb_flush,
160 .gart_set_page = &r100_pci_gart_set_page,
207bf9e9
JG		 161 .cp_init = NULL,
162 .cp_fini = NULL,
163 .cp_disable = NULL,
3ce0a23d 164 .cp_commit = &r100_cp_commit,
771fe6b9 165 .ring_start = &r300_ring_start,
3ce0a23d
JG		 166 .ring_test = &r100_ring_test,
167 .ring_ib_execute = &r100_ring_ib_execute,
207bf9e9 168 .ib_test = NULL,
771fe6b9
JG		 169 .irq_set = &r100_irq_set,
170 .irq_process = &r100_irq_process,
7ed220d7 171 .get_vblank_counter = &r100_get_vblank_counter,
771fe6b9
JG		 172 .fence_ring_emit = &r300_fence_ring_emit,
173 .cs_parse = &r300_cs_parse,
174 .copy_blit = &r100_copy_blit,
175 .copy_dma = &r300_copy_dma,
176 .copy = &r100_copy_blit,
177 .set_engine_clock = &radeon_legacy_set_engine_clock,
178 .set_memory_clock = NULL,
179 .set_pcie_lanes = &rv370_set_pcie_lanes,
180 .set_clock_gating = &radeon_legacy_set_clock_gating,
e024e110
DA		 181 .set_surface_reg = r100_set_surface_reg,
182 .clear_surface_reg = r100_clear_surface_reg,
c93bb85b 183 .bandwidth_update = &r100_bandwidth_update,
771fe6b9
JG		 184};
185
186/*
187 * r420,r423,rv410
188 */
9f022ddf
JG		 189extern int r420_init(struct radeon_device *rdev);
190extern void r420_fini(struct radeon_device *rdev);
191extern int r420_suspend(struct radeon_device *rdev);
192extern int r420_resume(struct radeon_device *rdev);
771fe6b9 193static struct radeon_asic r420_asic = {
9f022ddf
JG		 194 .init = &r420_init,
195 .fini = &r420_fini,
196 .suspend = &r420_suspend,
197 .resume = &r420_resume,
198 .errata = NULL,
199 .vram_info = NULL,
771fe6b9 200 .gpu_reset = &r300_gpu_reset,
9f022ddf
JG		 201 .mc_init = NULL,
202 .mc_fini = NULL,
203 .wb_init = NULL,
204 .wb_fini = NULL,
4aac0473
JG		 205 .gart_enable = NULL,
206 .gart_disable = NULL,
771fe6b9
JG		 207 .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
208 .gart_set_page = &rv370_pcie_gart_set_page,
9f022ddf
JG		 209 .cp_init = NULL,
210 .cp_fini = NULL,
211 .cp_disable = NULL,
3ce0a23d 212 .cp_commit = &r100_cp_commit,
771fe6b9 213 .ring_start = &r300_ring_start,
3ce0a23d
JG		 214 .ring_test = &r100_ring_test,
215 .ring_ib_execute = &r100_ring_ib_execute,
9f022ddf 216 .ib_test = NULL,
771fe6b9
JG		 217 .irq_set = &r100_irq_set,
218 .irq_process = &r100_irq_process,
7ed220d7 219 .get_vblank_counter = &r100_get_vblank_counter,
771fe6b9
JG		 220 .fence_ring_emit = &r300_fence_ring_emit,
221 .cs_parse = &r300_cs_parse,
222 .copy_blit = &r100_copy_blit,
223 .copy_dma = &r300_copy_dma,
224 .copy = &r100_copy_blit,
225 .set_engine_clock = &radeon_atom_set_engine_clock,
226 .set_memory_clock = &radeon_atom_set_memory_clock,
227 .set_pcie_lanes = &rv370_set_pcie_lanes,
228 .set_clock_gating = &radeon_atom_set_clock_gating,
e024e110
DA		 229 .set_surface_reg = r100_set_surface_reg,
230 .clear_surface_reg = r100_clear_surface_reg,
c93bb85b 231 .bandwidth_update = &r100_bandwidth_update,
771fe6b9
JG		 232};
233
234
235/*
236 * rs400,rs480
237 */
ca6ffc64
JG		 238extern int rs400_init(struct radeon_device *rdev);
239extern void rs400_fini(struct radeon_device *rdev);
240extern int rs400_suspend(struct radeon_device *rdev);
241extern int rs400_resume(struct radeon_device *rdev);
771fe6b9
JG		 242void rs400_gart_tlb_flush(struct radeon_device *rdev);
243int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
244uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg);
245void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
246static struct radeon_asic rs400_asic = {
ca6ffc64
JG		 247 .init = &rs400_init,
248 .fini = &rs400_fini,
249 .suspend = &rs400_suspend,
250 .resume = &rs400_resume,
251 .errata = NULL,
252 .vram_info = NULL,
771fe6b9 253 .gpu_reset = &r300_gpu_reset,
ca6ffc64
JG		 254 .mc_init = NULL,
255 .mc_fini = NULL,
256 .wb_init = NULL,
257 .wb_fini = NULL,
258 .gart_init = NULL,
259 .gart_fini = NULL,
260 .gart_enable = NULL,
261 .gart_disable = NULL,
771fe6b9
JG		 262 .gart_tlb_flush = &rs400_gart_tlb_flush,
263 .gart_set_page = &rs400_gart_set_page,
ca6ffc64
JG		 264 .cp_init = NULL,
265 .cp_fini = NULL,
266 .cp_disable = NULL,
3ce0a23d 267 .cp_commit = &r100_cp_commit,
771fe6b9 268 .ring_start = &r300_ring_start,
3ce0a23d
JG		 269 .ring_test = &r100_ring_test,
270 .ring_ib_execute = &r100_ring_ib_execute,
ca6ffc64 271 .ib_test = NULL,
771fe6b9
JG		 272 .irq_set = &r100_irq_set,
273 .irq_process = &r100_irq_process,
7ed220d7 274 .get_vblank_counter = &r100_get_vblank_counter,
771fe6b9
JG		 275 .fence_ring_emit = &r300_fence_ring_emit,
276 .cs_parse = &r300_cs_parse,
277 .copy_blit = &r100_copy_blit,
278 .copy_dma = &r300_copy_dma,
279 .copy = &r100_copy_blit,
280 .set_engine_clock = &radeon_legacy_set_engine_clock,
281 .set_memory_clock = NULL,
282 .set_pcie_lanes = NULL,
283 .set_clock_gating = &radeon_legacy_set_clock_gating,
e024e110
DA		 284 .set_surface_reg = r100_set_surface_reg,
285 .clear_surface_reg = r100_clear_surface_reg,
c93bb85b 286 .bandwidth_update = &r100_bandwidth_update,
771fe6b9
JG		 287};
288
289
290/*
291 * rs600.
292 */
c010f800
JG		 293extern int rs600_init(struct radeon_device *rdev);
294extern void rs600_fini(struct radeon_device *rdev);
295extern int rs600_suspend(struct radeon_device *rdev);
296extern int rs600_resume(struct radeon_device *rdev);
771fe6b9 297int rs600_irq_set(struct radeon_device *rdev);
7ed220d7
MD		 298int rs600_irq_process(struct radeon_device *rdev);
299u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc);
771fe6b9
JG		 300void rs600_gart_tlb_flush(struct radeon_device *rdev);
301int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
302uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg);
303void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
c93bb85b 304void rs600_bandwidth_update(struct radeon_device *rdev);
771fe6b9 305static struct radeon_asic rs600_asic = {
3f7dc91a 306 .init = &rs600_init,
c010f800
JG		 307 .fini = &rs600_fini,
308 .suspend = &rs600_suspend,
309 .resume = &rs600_resume,
310 .errata = NULL,
311 .vram_info = NULL,
771fe6b9 312 .gpu_reset = &r300_gpu_reset,
c010f800
JG		 313 .mc_init = NULL,
314 .mc_fini = NULL,
315 .wb_init = NULL,
316 .wb_fini = NULL,
317 .gart_init = NULL,
318 .gart_fini = NULL,
319 .gart_enable = NULL,
320 .gart_disable = NULL,
771fe6b9
JG		 321 .gart_tlb_flush = &rs600_gart_tlb_flush,
322 .gart_set_page = &rs600_gart_set_page,
c010f800
JG		 323 .cp_init = NULL,
324 .cp_fini = NULL,
325 .cp_disable = NULL,
3ce0a23d 326 .cp_commit = &r100_cp_commit,
771fe6b9 327 .ring_start = &r300_ring_start,
3ce0a23d
JG		 328 .ring_test = &r100_ring_test,
329 .ring_ib_execute = &r100_ring_ib_execute,
c010f800 330 .ib_test = NULL,
771fe6b9 331 .irq_set = &rs600_irq_set,
7ed220d7
MD		 332 .irq_process = &rs600_irq_process,
333 .get_vblank_counter = &rs600_get_vblank_counter,
771fe6b9
JG		 334 .fence_ring_emit = &r300_fence_ring_emit,
335 .cs_parse = &r300_cs_parse,
336 .copy_blit = &r100_copy_blit,
337 .copy_dma = &r300_copy_dma,
338 .copy = &r100_copy_blit,
339 .set_engine_clock = &radeon_atom_set_engine_clock,
340 .set_memory_clock = &radeon_atom_set_memory_clock,
341 .set_pcie_lanes = NULL,
342 .set_clock_gating = &radeon_atom_set_clock_gating,
c93bb85b 343 .bandwidth_update = &rs600_bandwidth_update,
771fe6b9
JG		 344};
345
346
347/*
348 * rs690,rs740
349 */
3bc68535
JG		 350int rs690_init(struct radeon_device *rdev);
351void rs690_fini(struct radeon_device *rdev);
352int rs690_resume(struct radeon_device *rdev);
353int rs690_suspend(struct radeon_device *rdev);
771fe6b9
JG		 354uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg);
355void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
c93bb85b 356void rs690_bandwidth_update(struct radeon_device *rdev);
771fe6b9 357static struct radeon_asic rs690_asic = {
3bc68535
JG		 358 .init = &rs690_init,
359 .fini = &rs690_fini,
360 .suspend = &rs690_suspend,
361 .resume = &rs690_resume,
362 .errata = NULL,
363 .vram_info = NULL,
771fe6b9 364 .gpu_reset = &r300_gpu_reset,
3bc68535
JG		 365 .mc_init = NULL,
366 .mc_fini = NULL,
367 .wb_init = NULL,
368 .wb_fini = NULL,
369 .gart_init = NULL,
370 .gart_fini = NULL,
371 .gart_enable = NULL,
372 .gart_disable = NULL,
771fe6b9
JG		 373 .gart_tlb_flush = &rs400_gart_tlb_flush,
374 .gart_set_page = &rs400_gart_set_page,
3bc68535
JG		 375 .cp_init = NULL,
376 .cp_fini = NULL,
377 .cp_disable = NULL,
3ce0a23d 378 .cp_commit = &r100_cp_commit,
771fe6b9 379 .ring_start = &r300_ring_start,
3ce0a23d
JG		 380 .ring_test = &r100_ring_test,
381 .ring_ib_execute = &r100_ring_ib_execute,
3bc68535 382 .ib_test = NULL,
771fe6b9 383 .irq_set = &rs600_irq_set,
7ed220d7
MD		 384 .irq_process = &rs600_irq_process,
385 .get_vblank_counter = &rs600_get_vblank_counter,
771fe6b9
JG		 386 .fence_ring_emit = &r300_fence_ring_emit,
387 .cs_parse = &r300_cs_parse,
388 .copy_blit = &r100_copy_blit,
389 .copy_dma = &r300_copy_dma,
390 .copy = &r300_copy_dma,
391 .set_engine_clock = &radeon_atom_set_engine_clock,
392 .set_memory_clock = &radeon_atom_set_memory_clock,
393 .set_pcie_lanes = NULL,
394 .set_clock_gating = &radeon_atom_set_clock_gating,
e024e110
DA		 395 .set_surface_reg = r100_set_surface_reg,
396 .clear_surface_reg = r100_clear_surface_reg,
c93bb85b 397 .bandwidth_update = &rs690_bandwidth_update,
771fe6b9
JG		 398};
399
400
401/*
402 * rv515
403 */
068a117c 404int rv515_init(struct radeon_device *rdev);
d39c3b89 405void rv515_fini(struct radeon_device *rdev);
771fe6b9 406int rv515_gpu_reset(struct radeon_device *rdev);
771fe6b9
JG		 407uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg);
408void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
409void rv515_ring_start(struct radeon_device *rdev);
410uint32_t rv515_pcie_rreg(struct radeon_device *rdev, uint32_t reg);
411void rv515_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
c93bb85b 412void rv515_bandwidth_update(struct radeon_device *rdev);
d39c3b89
JG		 413int rv515_resume(struct radeon_device *rdev);
414int rv515_suspend(struct radeon_device *rdev);
771fe6b9 415static struct radeon_asic rv515_asic = {
068a117c 416 .init = &rv515_init,
d39c3b89
JG		 417 .fini = &rv515_fini,
418 .suspend = &rv515_suspend,
419 .resume = &rv515_resume,
420 .errata = NULL,
421 .vram_info = NULL,
771fe6b9 422 .gpu_reset = &rv515_gpu_reset,
d39c3b89
JG		 423 .mc_init = NULL,
424 .mc_fini = NULL,
425 .wb_init = NULL,
426 .wb_fini = NULL,
4aac0473
JG		 427 .gart_init = &rv370_pcie_gart_init,
428 .gart_fini = &rv370_pcie_gart_fini,
d39c3b89
JG		 429 .gart_enable = NULL,
430 .gart_disable = NULL,
771fe6b9
JG		 431 .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
432 .gart_set_page = &rv370_pcie_gart_set_page,
d39c3b89
JG		 433 .cp_init = NULL,
434 .cp_fini = NULL,
435 .cp_disable = NULL,
3ce0a23d 436 .cp_commit = &r100_cp_commit,
771fe6b9 437 .ring_start = &rv515_ring_start,
3ce0a23d
JG		 438 .ring_test = &r100_ring_test,
439 .ring_ib_execute = &r100_ring_ib_execute,
d39c3b89 440 .ib_test = NULL,
7ed220d7
MD		 441 .irq_set = &rs600_irq_set,
442 .irq_process = &rs600_irq_process,
443 .get_vblank_counter = &rs600_get_vblank_counter,
771fe6b9 444 .fence_ring_emit = &r300_fence_ring_emit,
068a117c 445 .cs_parse = &r300_cs_parse,
771fe6b9
JG		 446 .copy_blit = &r100_copy_blit,
447 .copy_dma = &r300_copy_dma,
448 .copy = &r100_copy_blit,
449 .set_engine_clock = &radeon_atom_set_engine_clock,
450 .set_memory_clock = &radeon_atom_set_memory_clock,
451 .set_pcie_lanes = &rv370_set_pcie_lanes,
452 .set_clock_gating = &radeon_atom_set_clock_gating,
e024e110
DA		 453 .set_surface_reg = r100_set_surface_reg,
454 .clear_surface_reg = r100_clear_surface_reg,
c93bb85b 455 .bandwidth_update = &rv515_bandwidth_update,
771fe6b9
JG		 456};
457
458
459/*
460 * r520,rv530,rv560,rv570,r580
461 */
d39c3b89 462int r520_init(struct radeon_device *rdev);
f0ed1f65 463int r520_resume(struct radeon_device *rdev);
771fe6b9 464static struct radeon_asic r520_asic = {
d39c3b89 465 .init = &r520_init,
f0ed1f65
JG		 466 .fini = &rv515_fini,
467 .suspend = &rv515_suspend,
468 .resume = &r520_resume,
469 .errata = NULL,
470 .vram_info = NULL,
771fe6b9 471 .gpu_reset = &rv515_gpu_reset,
f0ed1f65
JG		 472 .mc_init = NULL,
473 .mc_fini = NULL,
474 .wb_init = NULL,
475 .wb_fini = NULL,
476 .gart_init = NULL,
477 .gart_fini = NULL,
478 .gart_enable = NULL,
479 .gart_disable = NULL,
771fe6b9
JG		 480 .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
481 .gart_set_page = &rv370_pcie_gart_set_page,
f0ed1f65
JG		 482 .cp_init = NULL,
483 .cp_fini = NULL,
484 .cp_disable = NULL,
3ce0a23d 485 .cp_commit = &r100_cp_commit,
771fe6b9 486 .ring_start = &rv515_ring_start,
3ce0a23d
JG		 487 .ring_test = &r100_ring_test,
488 .ring_ib_execute = &r100_ring_ib_execute,
f0ed1f65 489 .ib_test = NULL,
7ed220d7
MD		 490 .irq_set = &rs600_irq_set,
491 .irq_process = &rs600_irq_process,
492 .get_vblank_counter = &rs600_get_vblank_counter,
771fe6b9 493 .fence_ring_emit = &r300_fence_ring_emit,
068a117c 494 .cs_parse = &r300_cs_parse,
771fe6b9
JG		 495 .copy_blit = &r100_copy_blit,
496 .copy_dma = &r300_copy_dma,
497 .copy = &r100_copy_blit,
498 .set_engine_clock = &radeon_atom_set_engine_clock,
499 .set_memory_clock = &radeon_atom_set_memory_clock,
500 .set_pcie_lanes = &rv370_set_pcie_lanes,
501 .set_clock_gating = &radeon_atom_set_clock_gating,
e024e110
DA		 502 .set_surface_reg = r100_set_surface_reg,
503 .clear_surface_reg = r100_clear_surface_reg,
f0ed1f65 504 .bandwidth_update = &rv515_bandwidth_update,
771fe6b9
JG		 505};
506
507/*
3ce0a23d 508 * r600,rv610,rv630,rv620,rv635,rv670,rs780,rs880
771fe6b9 509 */
3ce0a23d
JG		 510int r600_init(struct radeon_device *rdev);
511void r600_fini(struct radeon_device *rdev);
512int r600_suspend(struct radeon_device *rdev);
513int r600_resume(struct radeon_device *rdev);
514int r600_wb_init(struct radeon_device *rdev);
515void r600_wb_fini(struct radeon_device *rdev);
516void r600_cp_commit(struct radeon_device *rdev);
517void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
771fe6b9
JG		 518uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg);
519void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
3ce0a23d
JG		 520int r600_cs_parse(struct radeon_cs_parser *p);
521void r600_fence_ring_emit(struct radeon_device *rdev,
522 struct radeon_fence *fence);
523int r600_copy_dma(struct radeon_device *rdev,
524 uint64_t src_offset,
525 uint64_t dst_offset,
526 unsigned num_pages,
527 struct radeon_fence *fence);
528int r600_irq_process(struct radeon_device *rdev);
529int r600_irq_set(struct radeon_device *rdev);
530int r600_gpu_reset(struct radeon_device *rdev);
531int r600_set_surface_reg(struct radeon_device *rdev, int reg,
532 uint32_t tiling_flags, uint32_t pitch,
533 uint32_t offset, uint32_t obj_size);
534int r600_clear_surface_reg(struct radeon_device *rdev, int reg);
535void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
536int r600_ib_test(struct radeon_device *rdev);
537int r600_ring_test(struct radeon_device *rdev);
538int r600_copy_blit(struct radeon_device *rdev,
539 uint64_t src_offset, uint64_t dst_offset,
540 unsigned num_pages, struct radeon_fence *fence);
541
542static struct radeon_asic r600_asic = {
543 .errata = NULL,
544 .init = &r600_init,
545 .fini = &r600_fini,
546 .suspend = &r600_suspend,
547 .resume = &r600_resume,
548 .cp_commit = &r600_cp_commit,
549 .vram_info = NULL,
550 .gpu_reset = &r600_gpu_reset,
551 .mc_init = NULL,
552 .mc_fini = NULL,
553 .wb_init = &r600_wb_init,
554 .wb_fini = &r600_wb_fini,
555 .gart_enable = NULL,
556 .gart_disable = NULL,
557 .gart_tlb_flush = &r600_pcie_gart_tlb_flush,
558 .gart_set_page = &rs600_gart_set_page,
559 .cp_init = NULL,
560 .cp_fini = NULL,
561 .cp_disable = NULL,
562 .ring_start = NULL,
563 .ring_test = &r600_ring_test,
564 .ring_ib_execute = &r600_ring_ib_execute,
565 .ib_test = &r600_ib_test,
566 .irq_set = &r600_irq_set,
567 .irq_process = &r600_irq_process,
568 .fence_ring_emit = &r600_fence_ring_emit,
569 .cs_parse = &r600_cs_parse,
570 .copy_blit = &r600_copy_blit,
571 .copy_dma = &r600_copy_blit,
a3812877 572 .copy = &r600_copy_blit,
3ce0a23d
JG		 573 .set_engine_clock = &radeon_atom_set_engine_clock,
574 .set_memory_clock = &radeon_atom_set_memory_clock,
575 .set_pcie_lanes = NULL,
576 .set_clock_gating = &radeon_atom_set_clock_gating,
577 .set_surface_reg = r600_set_surface_reg,
578 .clear_surface_reg = r600_clear_surface_reg,
f0ed1f65 579 .bandwidth_update = &rv515_bandwidth_update,
3ce0a23d
JG		 580};
581
582/*
583 * rv770,rv730,rv710,rv740
584 */
585int rv770_init(struct radeon_device *rdev);
586void rv770_fini(struct radeon_device *rdev);
587int rv770_suspend(struct radeon_device *rdev);
588int rv770_resume(struct radeon_device *rdev);
589int rv770_gpu_reset(struct radeon_device *rdev);
590
591static struct radeon_asic rv770_asic = {
592 .errata = NULL,
593 .init = &rv770_init,
594 .fini = &rv770_fini,
595 .suspend = &rv770_suspend,
596 .resume = &rv770_resume,
597 .cp_commit = &r600_cp_commit,
598 .vram_info = NULL,
599 .gpu_reset = &rv770_gpu_reset,
600 .mc_init = NULL,
601 .mc_fini = NULL,
602 .wb_init = &r600_wb_init,
603 .wb_fini = &r600_wb_fini,
604 .gart_enable = NULL,
605 .gart_disable = NULL,
606 .gart_tlb_flush = &r600_pcie_gart_tlb_flush,
607 .gart_set_page = &rs600_gart_set_page,
608 .cp_init = NULL,
609 .cp_fini = NULL,
610 .cp_disable = NULL,
611 .ring_start = NULL,
612 .ring_test = &r600_ring_test,
613 .ring_ib_execute = &r600_ring_ib_execute,
614 .ib_test = &r600_ib_test,
615 .irq_set = &r600_irq_set,
616 .irq_process = &r600_irq_process,
617 .fence_ring_emit = &r600_fence_ring_emit,
618 .cs_parse = &r600_cs_parse,
619 .copy_blit = &r600_copy_blit,
620 .copy_dma = &r600_copy_blit,
a3812877 621 .copy = &r600_copy_blit,
3ce0a23d
JG		 622 .set_engine_clock = &radeon_atom_set_engine_clock,
623 .set_memory_clock = &radeon_atom_set_memory_clock,
624 .set_pcie_lanes = NULL,
625 .set_clock_gating = &radeon_atom_set_clock_gating,
626 .set_surface_reg = r600_set_surface_reg,
627 .clear_surface_reg = r600_clear_surface_reg,
f0ed1f65 628 .bandwidth_update = &rv515_bandwidth_update,
3ce0a23d 629};
771fe6b9
JG		 630
631#endif
Clone of davem's net-next-2.6 tree