[net-next-2.6.git] / drivers / gpu / drm / radeon / radeon_asic.h

/*
 * Copyright 2008 Advanced Micro Devices, Inc.
 * Copyright 2008 Red Hat Inc.
 * Copyright 2009 Jerome Glisse.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Dave Airlie
 *          Alex Deucher
 *          Jerome Glisse
 */
#ifndef __RADEON_ASIC_H__
#define __RADEON_ASIC_H__

/*
 * common functions
 */
uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev);
void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev);
void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);

uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev);
void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev);
void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock);
void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);

/*
 * r100,rv100,rs100,rv200,rs200
 */
extern int r100_init(struct radeon_device *rdev);
extern void r100_fini(struct radeon_device *rdev);
extern int r100_suspend(struct radeon_device *rdev);
extern int r100_resume(struct radeon_device *rdev);
uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg);
void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
void r100_vga_set_state(struct radeon_device *rdev, bool state);
int r100_gpu_reset(struct radeon_device *rdev);
u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc);
void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
void r100_cp_commit(struct radeon_device *rdev);
void r100_ring_start(struct radeon_device *rdev);
int r100_irq_set(struct radeon_device *rdev);
int r100_irq_process(struct radeon_device *rdev);
void r100_fence_ring_emit(struct radeon_device *rdev,
			  struct radeon_fence *fence);
int r100_cs_parse(struct radeon_cs_parser *p);
void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg);
int r100_copy_blit(struct radeon_device *rdev,
		   uint64_t src_offset,
		   uint64_t dst_offset,
		   unsigned num_pages,
		   struct radeon_fence *fence);
int r100_set_surface_reg(struct radeon_device *rdev, int reg,
			 uint32_t tiling_flags, uint32_t pitch,
			 uint32_t offset, uint32_t obj_size);
void r100_clear_surface_reg(struct radeon_device *rdev, int reg);
void r100_bandwidth_update(struct radeon_device *rdev);
void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
int r100_ring_test(struct radeon_device *rdev);
void r100_hpd_init(struct radeon_device *rdev);
void r100_hpd_fini(struct radeon_device *rdev);
bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
void r100_hpd_set_polarity(struct radeon_device *rdev,
			   enum radeon_hpd_id hpd);

/*
 * r200,rv250,rs300,rv280
 */
extern int r200_copy_dma(struct radeon_device *rdev,
			uint64_t src_offset,
			uint64_t dst_offset,
			unsigned num_pages,
			struct radeon_fence *fence);

/*
 * r300,r350,rv350,rv380
 */
extern int r300_init(struct radeon_device *rdev);
extern void r300_fini(struct radeon_device *rdev);
extern int r300_suspend(struct radeon_device *rdev);
extern int r300_resume(struct radeon_device *rdev);
extern int r300_gpu_reset(struct radeon_device *rdev);
extern void r300_ring_start(struct radeon_device *rdev);
extern void r300_fence_ring_emit(struct radeon_device *rdev,
				struct radeon_fence *fence);
extern int r300_cs_parse(struct radeon_cs_parser *p);
extern void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev);
extern int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
extern uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg);
extern void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes);
extern int rv370_get_pcie_lanes(struct radeon_device *rdev);

/*
 * r420,r423,rv410
 */
extern int r420_init(struct radeon_device *rdev);
extern void r420_fini(struct radeon_device *rdev);
extern int r420_suspend(struct radeon_device *rdev);
extern int r420_resume(struct radeon_device *rdev);

/*
 * rs400,rs480
 */
extern int rs400_init(struct radeon_device *rdev);
extern void rs400_fini(struct radeon_device *rdev);
extern int rs400_suspend(struct radeon_device *rdev);
extern int rs400_resume(struct radeon_device *rdev);
void rs400_gart_tlb_flush(struct radeon_device *rdev);
int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg);
void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);

/*
 * rs600.
 */
extern int rs600_init(struct radeon_device *rdev);
extern void rs600_fini(struct radeon_device *rdev);
extern int rs600_suspend(struct radeon_device *rdev);
extern int rs600_resume(struct radeon_device *rdev);
int rs600_irq_set(struct radeon_device *rdev);
int rs600_irq_process(struct radeon_device *rdev);
u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc);
void rs600_gart_tlb_flush(struct radeon_device *rdev);
int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg);
void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
void rs600_bandwidth_update(struct radeon_device *rdev);
void rs600_hpd_init(struct radeon_device *rdev);
void rs600_hpd_fini(struct radeon_device *rdev);
bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
void rs600_hpd_set_polarity(struct radeon_device *rdev,
			    enum radeon_hpd_id hpd);

/*
 * rs690,rs740
 */
int rs690_init(struct radeon_device *rdev);
void rs690_fini(struct radeon_device *rdev);
int rs690_resume(struct radeon_device *rdev);
int rs690_suspend(struct radeon_device *rdev);
uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg);
void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
void rs690_bandwidth_update(struct radeon_device *rdev);

/*
 * rv515
 */
int rv515_init(struct radeon_device *rdev);
void rv515_fini(struct radeon_device *rdev);
int rv515_gpu_reset(struct radeon_device *rdev);
uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg);
void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
void rv515_ring_start(struct radeon_device *rdev);
uint32_t rv515_pcie_rreg(struct radeon_device *rdev, uint32_t reg);
void rv515_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
void rv515_bandwidth_update(struct radeon_device *rdev);
int rv515_resume(struct radeon_device *rdev);
int rv515_suspend(struct radeon_device *rdev);

/*
 * r520,rv530,rv560,rv570,r580
 */
int r520_init(struct radeon_device *rdev);
int r520_resume(struct radeon_device *rdev);

/*
 * r600,rv610,rv630,rv620,rv635,rv670,rs780,rs880
 */
int r600_init(struct radeon_device *rdev);
void r600_fini(struct radeon_device *rdev);
int r600_suspend(struct radeon_device *rdev);
int r600_resume(struct radeon_device *rdev);
void r600_vga_set_state(struct radeon_device *rdev, bool state);
int r600_wb_init(struct radeon_device *rdev);
void r600_wb_fini(struct radeon_device *rdev);
void r600_cp_commit(struct radeon_device *rdev);
void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg);
void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
int r600_cs_parse(struct radeon_cs_parser *p);
void r600_fence_ring_emit(struct radeon_device *rdev,
			  struct radeon_fence *fence);
int r600_copy_dma(struct radeon_device *rdev,
		  uint64_t src_offset,
		  uint64_t dst_offset,
		  unsigned num_pages,
		  struct radeon_fence *fence);
int r600_irq_process(struct radeon_device *rdev);
int r600_irq_set(struct radeon_device *rdev);
int r600_gpu_reset(struct radeon_device *rdev);
int r600_set_surface_reg(struct radeon_device *rdev, int reg,
			 uint32_t tiling_flags, uint32_t pitch,
			 uint32_t offset, uint32_t obj_size);
void r600_clear_surface_reg(struct radeon_device *rdev, int reg);
void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
int r600_ring_test(struct radeon_device *rdev);
int r600_copy_blit(struct radeon_device *rdev,
		   uint64_t src_offset, uint64_t dst_offset,
		   unsigned num_pages, struct radeon_fence *fence);
void r600_hpd_init(struct radeon_device *rdev);
void r600_hpd_fini(struct radeon_device *rdev);
bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
void r600_hpd_set_polarity(struct radeon_device *rdev,
			   enum radeon_hpd_id hpd);
extern void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo);

/*
 * rv770,rv730,rv710,rv740
 */
int rv770_init(struct radeon_device *rdev);
void rv770_fini(struct radeon_device *rdev);
int rv770_suspend(struct radeon_device *rdev);
int rv770_resume(struct radeon_device *rdev);
int rv770_gpu_reset(struct radeon_device *rdev);

/*
 * evergreen
 */
int evergreen_init(struct radeon_device *rdev);
void evergreen_fini(struct radeon_device *rdev);
int evergreen_suspend(struct radeon_device *rdev);
int evergreen_resume(struct radeon_device *rdev);
int evergreen_gpu_reset(struct radeon_device *rdev);
void evergreen_bandwidth_update(struct radeon_device *rdev);
void evergreen_hpd_init(struct radeon_device *rdev);
void evergreen_hpd_fini(struct radeon_device *rdev);
bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
void evergreen_hpd_set_polarity(struct radeon_device *rdev,
				enum radeon_hpd_id hpd);
#endif
Commit	Line	Data
771fe6b9 JG	1	/*
	2	* Copyright 2008 Advanced Micro Devices, Inc.
	3	* Copyright 2008 Red Hat Inc.
	4	* Copyright 2009 Jerome Glisse.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a
	7	* copy of this software and associated documentation files (the "Software"),
	8	* to deal in the Software without restriction, including without limitation
	9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	10	* and/or sell copies of the Software, and to permit persons to whom the
	11	* Software is furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	22	* OTHER DEALINGS IN THE SOFTWARE.
	23	*
	24	* Authors: Dave Airlie
	25	* Alex Deucher
	26	* Jerome Glisse
	27	*/
	28	#ifndef __RADEON_ASIC_H__
	29	#define __RADEON_ASIC_H__
	30
	31	/*
	32	* common functions
	33	*/
7433874e	34	uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev);
771fe6b9	35	void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
5ea597f3	36	uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev);
771fe6b9 JG	37	void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
771fe6b9 JG	38
7433874e	39	uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev);
771fe6b9	40	void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
7433874e	41	uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev);
771fe6b9 JG	42	void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock);
	43	void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
	44
	45	/*
44ca7478	46	* r100,rv100,rs100,rv200,rs200
771fe6b9	47	*/
d4550907 JG	48	extern int r100_init(struct radeon_device *rdev);
	49	extern void r100_fini(struct radeon_device *rdev);
	50	extern int r100_suspend(struct radeon_device *rdev);
	51	extern int r100_resume(struct radeon_device *rdev);
771fe6b9 JG	52	uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg);
771fe6b9 JG	53	void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
28d52043	54	void r100_vga_set_state(struct radeon_device *rdev, bool state);
771fe6b9	55	int r100_gpu_reset(struct radeon_device *rdev);
7ed220d7	56	u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc);
771fe6b9 JG	57	void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
771fe6b9 JG	58	int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
3ce0a23d	59	void r100_cp_commit(struct radeon_device *rdev);
771fe6b9 JG	60	void r100_ring_start(struct radeon_device *rdev);
	61	int r100_irq_set(struct radeon_device *rdev);
	62	int r100_irq_process(struct radeon_device *rdev);
	63	void r100_fence_ring_emit(struct radeon_device *rdev,
	64	struct radeon_fence *fence);
	65	int r100_cs_parse(struct radeon_cs_parser *p);
	66	void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
	67	uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg);
	68	int r100_copy_blit(struct radeon_device *rdev,
	69	uint64_t src_offset,
	70	uint64_t dst_offset,
	71	unsigned num_pages,
	72	struct radeon_fence *fence);
e024e110 DA	73	int r100_set_surface_reg(struct radeon_device *rdev, int reg,
	74	uint32_t tiling_flags, uint32_t pitch,
	75	uint32_t offset, uint32_t obj_size);
9479c54f	76	void r100_clear_surface_reg(struct radeon_device *rdev, int reg);
c93bb85b	77	void r100_bandwidth_update(struct radeon_device *rdev);
3ce0a23d	78	void r100_ring_ib_execute(struct radeon_device rdev, struct radeon_ib ib);
3ce0a23d	79	int r100_ring_test(struct radeon_device *rdev);
429770b3 AD	80	void r100_hpd_init(struct radeon_device *rdev);
	81	void r100_hpd_fini(struct radeon_device *rdev);
	82	bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
	83	void r100_hpd_set_polarity(struct radeon_device *rdev,
	84	enum radeon_hpd_id hpd);
771fe6b9	85
44ca7478 PN	86	/*
	87	* r200,rv250,rs300,rv280
	88	*/
	89	extern int r200_copy_dma(struct radeon_device *rdev,
	90	uint64_t src_offset,
	91	uint64_t dst_offset,
	92	unsigned num_pages,
	93	struct radeon_fence *fence);
771fe6b9 JG	94
	95	/*
	96	* r300,r350,rv350,rv380
	97	*/
207bf9e9 JG	98	extern int r300_init(struct radeon_device *rdev);
	99	extern void r300_fini(struct radeon_device *rdev);
	100	extern int r300_suspend(struct radeon_device *rdev);
	101	extern int r300_resume(struct radeon_device *rdev);
	102	extern int r300_gpu_reset(struct radeon_device *rdev);
	103	extern void r300_ring_start(struct radeon_device *rdev);
	104	extern void r300_fence_ring_emit(struct radeon_device *rdev,
	105	struct radeon_fence *fence);
	106	extern int r300_cs_parse(struct radeon_cs_parser *p);
	107	extern void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev);
	108	extern int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
	109	extern uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg);
	110	extern void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
	111	extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes);
c836a412	112	extern int rv370_get_pcie_lanes(struct radeon_device *rdev);
44ca7478	113
771fe6b9 JG	114	/*
	115	* r420,r423,rv410
	116	*/
9f022ddf JG	117	extern int r420_init(struct radeon_device *rdev);
	118	extern void r420_fini(struct radeon_device *rdev);
	119	extern int r420_suspend(struct radeon_device *rdev);
	120	extern int r420_resume(struct radeon_device *rdev);
771fe6b9 JG	121
	122	/*
	123	* rs400,rs480
	124	*/
ca6ffc64 JG	125	extern int rs400_init(struct radeon_device *rdev);
	126	extern void rs400_fini(struct radeon_device *rdev);
	127	extern int rs400_suspend(struct radeon_device *rdev);
	128	extern int rs400_resume(struct radeon_device *rdev);
771fe6b9 JG	129	void rs400_gart_tlb_flush(struct radeon_device *rdev);
	130	int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
	131	uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg);
	132	void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
771fe6b9 JG	133
	134	/*
	135	* rs600.
	136	*/
c010f800 JG	137	extern int rs600_init(struct radeon_device *rdev);
	138	extern void rs600_fini(struct radeon_device *rdev);
	139	extern int rs600_suspend(struct radeon_device *rdev);
	140	extern int rs600_resume(struct radeon_device *rdev);
771fe6b9	141	int rs600_irq_set(struct radeon_device *rdev);
7ed220d7 MD	142	int rs600_irq_process(struct radeon_device *rdev);
7ed220d7 MD	143	u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc);
771fe6b9 JG	144	void rs600_gart_tlb_flush(struct radeon_device *rdev);
	145	int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
	146	uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg);
	147	void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
c93bb85b	148	void rs600_bandwidth_update(struct radeon_device *rdev);
429770b3 AD	149	void rs600_hpd_init(struct radeon_device *rdev);
	150	void rs600_hpd_fini(struct radeon_device *rdev);
	151	bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
	152	void rs600_hpd_set_polarity(struct radeon_device *rdev,
	153	enum radeon_hpd_id hpd);
	154
771fe6b9 JG	155	/*
	156	* rs690,rs740
	157	*/
3bc68535 JG	158	int rs690_init(struct radeon_device *rdev);
	159	void rs690_fini(struct radeon_device *rdev);
	160	int rs690_resume(struct radeon_device *rdev);
	161	int rs690_suspend(struct radeon_device *rdev);
771fe6b9 JG	162	uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg);
771fe6b9 JG	163	void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
c93bb85b	164	void rs690_bandwidth_update(struct radeon_device *rdev);
771fe6b9 JG	165
	166	/*
	167	* rv515
	168	*/
068a117c	169	int rv515_init(struct radeon_device *rdev);
d39c3b89	170	void rv515_fini(struct radeon_device *rdev);
771fe6b9	171	int rv515_gpu_reset(struct radeon_device *rdev);
771fe6b9 JG	172	uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg);
	173	void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
	174	void rv515_ring_start(struct radeon_device *rdev);
	175	uint32_t rv515_pcie_rreg(struct radeon_device *rdev, uint32_t reg);
	176	void rv515_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
c93bb85b	177	void rv515_bandwidth_update(struct radeon_device *rdev);
d39c3b89 JG	178	int rv515_resume(struct radeon_device *rdev);
d39c3b89 JG	179	int rv515_suspend(struct radeon_device *rdev);
771fe6b9 JG	180
	181	/*
	182	* r520,rv530,rv560,rv570,r580
	183	*/
d39c3b89	184	int r520_init(struct radeon_device *rdev);
f0ed1f65	185	int r520_resume(struct radeon_device *rdev);
771fe6b9 JG	186
771fe6b9 JG	187	/*
3ce0a23d	188	* r600,rv610,rv630,rv620,rv635,rv670,rs780,rs880
771fe6b9	189	*/
3ce0a23d JG	190	int r600_init(struct radeon_device *rdev);
	191	void r600_fini(struct radeon_device *rdev);
	192	int r600_suspend(struct radeon_device *rdev);
	193	int r600_resume(struct radeon_device *rdev);
28d52043	194	void r600_vga_set_state(struct radeon_device *rdev, bool state);
3ce0a23d JG	195	int r600_wb_init(struct radeon_device *rdev);
	196	void r600_wb_fini(struct radeon_device *rdev);
	197	void r600_cp_commit(struct radeon_device *rdev);
	198	void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
771fe6b9 JG	199	uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg);
771fe6b9 JG	200	void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
3ce0a23d JG	201	int r600_cs_parse(struct radeon_cs_parser *p);
	202	void r600_fence_ring_emit(struct radeon_device *rdev,
	203	struct radeon_fence *fence);
	204	int r600_copy_dma(struct radeon_device *rdev,
	205	uint64_t src_offset,
	206	uint64_t dst_offset,
	207	unsigned num_pages,
	208	struct radeon_fence *fence);
	209	int r600_irq_process(struct radeon_device *rdev);
	210	int r600_irq_set(struct radeon_device *rdev);
	211	int r600_gpu_reset(struct radeon_device *rdev);
	212	int r600_set_surface_reg(struct radeon_device *rdev, int reg,
	213	uint32_t tiling_flags, uint32_t pitch,
	214	uint32_t offset, uint32_t obj_size);
9479c54f	215	void r600_clear_surface_reg(struct radeon_device *rdev, int reg);
3ce0a23d	216	void r600_ring_ib_execute(struct radeon_device rdev, struct radeon_ib ib);
3ce0a23d JG	217	int r600_ring_test(struct radeon_device *rdev);
	218	int r600_copy_blit(struct radeon_device *rdev,
	219	uint64_t src_offset, uint64_t dst_offset,
	220	unsigned num_pages, struct radeon_fence *fence);
429770b3 AD	221	void r600_hpd_init(struct radeon_device *rdev);
	222	void r600_hpd_fini(struct radeon_device *rdev);
	223	bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
	224	void r600_hpd_set_polarity(struct radeon_device *rdev,
	225	enum radeon_hpd_id hpd);
062b389c	226	extern void r600_ioctl_wait_idle(struct radeon_device rdev, struct radeon_bo bo);
3ce0a23d	227
3ce0a23d JG	228	/*
	229	* rv770,rv730,rv710,rv740
	230	*/
	231	int rv770_init(struct radeon_device *rdev);
	232	void rv770_fini(struct radeon_device *rdev);
	233	int rv770_suspend(struct radeon_device *rdev);
	234	int rv770_resume(struct radeon_device *rdev);
	235	int rv770_gpu_reset(struct radeon_device *rdev);
	236
bcc1c2a1 AD	237	/*
	238	* evergreen
	239	*/
	240	int evergreen_init(struct radeon_device *rdev);
	241	void evergreen_fini(struct radeon_device *rdev);
	242	int evergreen_suspend(struct radeon_device *rdev);
	243	int evergreen_resume(struct radeon_device *rdev);
	244	int evergreen_gpu_reset(struct radeon_device *rdev);
	245	void evergreen_bandwidth_update(struct radeon_device *rdev);
	246	void evergreen_hpd_init(struct radeon_device *rdev);
	247	void evergreen_hpd_fini(struct radeon_device *rdev);
	248	bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
	249	void evergreen_hpd_set_polarity(struct radeon_device *rdev,
	250	enum radeon_hpd_id hpd);
771fe6b9	251	#endif