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drm/radeon/kms: Remove old init path as no hw use it anymore
[net-next-2.6.git] / drivers / gpu / drm / radeon / radeon_asic.h
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_ASIC_H__
29#define __RADEON_ASIC_H__
30
31/*
32 * common functions
33 */
34void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
35void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
36
37void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
38void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock);
39void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
40
41/*
42 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
43 */
d4550907
JG		 44extern int r100_init(struct radeon_device *rdev);
45extern void r100_fini(struct radeon_device *rdev);
46extern int r100_suspend(struct radeon_device *rdev);
47extern int r100_resume(struct radeon_device *rdev);
771fe6b9
JG		 48uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg);
49void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
771fe6b9 50int r100_gpu_reset(struct radeon_device *rdev);
7ed220d7 51u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc);
771fe6b9
JG		 52void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
53int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
3ce0a23d 54void r100_cp_commit(struct radeon_device *rdev);
771fe6b9
JG		 55void r100_ring_start(struct radeon_device *rdev);
56int r100_irq_set(struct radeon_device *rdev);
57int r100_irq_process(struct radeon_device *rdev);
58void r100_fence_ring_emit(struct radeon_device *rdev,
59 struct radeon_fence *fence);
60int r100_cs_parse(struct radeon_cs_parser *p);
61void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
62uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg);
63int r100_copy_blit(struct radeon_device *rdev,
64 uint64_t src_offset,
65 uint64_t dst_offset,
66 unsigned num_pages,
67 struct radeon_fence *fence);
e024e110
DA		 68int r100_set_surface_reg(struct radeon_device *rdev, int reg,
69 uint32_t tiling_flags, uint32_t pitch,
70 uint32_t offset, uint32_t obj_size);
71int r100_clear_surface_reg(struct radeon_device *rdev, int reg);
c93bb85b 72void r100_bandwidth_update(struct radeon_device *rdev);
3ce0a23d 73void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
3ce0a23d 74int r100_ring_test(struct radeon_device *rdev);
771fe6b9
JG		 75
76static struct radeon_asic r100_asic = {
068a117c 77 .init = &r100_init,
d4550907
JG		 78 .fini = &r100_fini,
79 .suspend = &r100_suspend,
80 .resume = &r100_resume,
771fe6b9 81 .gpu_reset = &r100_gpu_reset,
771fe6b9
JG		 82 .gart_tlb_flush = &r100_pci_gart_tlb_flush,
83 .gart_set_page = &r100_pci_gart_set_page,
3ce0a23d 84 .cp_commit = &r100_cp_commit,
771fe6b9 85 .ring_start = &r100_ring_start,
3ce0a23d
JG		 86 .ring_test = &r100_ring_test,
87 .ring_ib_execute = &r100_ring_ib_execute,
771fe6b9
JG		 88 .irq_set = &r100_irq_set,
89 .irq_process = &r100_irq_process,
7ed220d7 90 .get_vblank_counter = &r100_get_vblank_counter,
771fe6b9
JG		 91 .fence_ring_emit = &r100_fence_ring_emit,
92 .cs_parse = &r100_cs_parse,
93 .copy_blit = &r100_copy_blit,
94 .copy_dma = NULL,
95 .copy = &r100_copy_blit,
96 .set_engine_clock = &radeon_legacy_set_engine_clock,
97 .set_memory_clock = NULL,
98 .set_pcie_lanes = NULL,
99 .set_clock_gating = &radeon_legacy_set_clock_gating,
e024e110
DA		 100 .set_surface_reg = r100_set_surface_reg,
101 .clear_surface_reg = r100_clear_surface_reg,
c93bb85b 102 .bandwidth_update = &r100_bandwidth_update,
771fe6b9
JG		 103};
104
105
106/*
107 * r300,r350,rv350,rv380
108 */
207bf9e9
JG		 109extern int r300_init(struct radeon_device *rdev);
110extern void r300_fini(struct radeon_device *rdev);
111extern int r300_suspend(struct radeon_device *rdev);
112extern int r300_resume(struct radeon_device *rdev);
113extern int r300_gpu_reset(struct radeon_device *rdev);
114extern void r300_ring_start(struct radeon_device *rdev);
115extern void r300_fence_ring_emit(struct radeon_device *rdev,
116 struct radeon_fence *fence);
117extern int r300_cs_parse(struct radeon_cs_parser *p);
118extern void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev);
119extern int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
120extern uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg);
121extern void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
122extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes);
123extern int r300_copy_dma(struct radeon_device *rdev,
124 uint64_t src_offset,
125 uint64_t dst_offset,
126 unsigned num_pages,
127 struct radeon_fence *fence);
771fe6b9 128static struct radeon_asic r300_asic = {
068a117c 129 .init = &r300_init,
207bf9e9
JG		 130 .fini = &r300_fini,
131 .suspend = &r300_suspend,
132 .resume = &r300_resume,
771fe6b9 133 .gpu_reset = &r300_gpu_reset,
771fe6b9
JG		 134 .gart_tlb_flush = &r100_pci_gart_tlb_flush,
135 .gart_set_page = &r100_pci_gart_set_page,
3ce0a23d 136 .cp_commit = &r100_cp_commit,
771fe6b9 137 .ring_start = &r300_ring_start,
3ce0a23d
JG		 138 .ring_test = &r100_ring_test,
139 .ring_ib_execute = &r100_ring_ib_execute,
771fe6b9
JG		 140 .irq_set = &r100_irq_set,
141 .irq_process = &r100_irq_process,
7ed220d7 142 .get_vblank_counter = &r100_get_vblank_counter,
771fe6b9
JG		 143 .fence_ring_emit = &r300_fence_ring_emit,
144 .cs_parse = &r300_cs_parse,
145 .copy_blit = &r100_copy_blit,
146 .copy_dma = &r300_copy_dma,
147 .copy = &r100_copy_blit,
148 .set_engine_clock = &radeon_legacy_set_engine_clock,
149 .set_memory_clock = NULL,
150 .set_pcie_lanes = &rv370_set_pcie_lanes,
151 .set_clock_gating = &radeon_legacy_set_clock_gating,
e024e110
DA		 152 .set_surface_reg = r100_set_surface_reg,
153 .clear_surface_reg = r100_clear_surface_reg,
c93bb85b 154 .bandwidth_update = &r100_bandwidth_update,
771fe6b9
JG		 155};
156
157/*
158 * r420,r423,rv410
159 */
9f022ddf
JG		 160extern int r420_init(struct radeon_device *rdev);
161extern void r420_fini(struct radeon_device *rdev);
162extern int r420_suspend(struct radeon_device *rdev);
163extern int r420_resume(struct radeon_device *rdev);
771fe6b9 164static struct radeon_asic r420_asic = {
9f022ddf
JG		 165 .init = &r420_init,
166 .fini = &r420_fini,
167 .suspend = &r420_suspend,
168 .resume = &r420_resume,
771fe6b9 169 .gpu_reset = &r300_gpu_reset,
771fe6b9
JG		 170 .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
171 .gart_set_page = &rv370_pcie_gart_set_page,
3ce0a23d 172 .cp_commit = &r100_cp_commit,
771fe6b9 173 .ring_start = &r300_ring_start,
3ce0a23d
JG		 174 .ring_test = &r100_ring_test,
175 .ring_ib_execute = &r100_ring_ib_execute,
771fe6b9
JG		 176 .irq_set = &r100_irq_set,
177 .irq_process = &r100_irq_process,
7ed220d7 178 .get_vblank_counter = &r100_get_vblank_counter,
771fe6b9
JG		 179 .fence_ring_emit = &r300_fence_ring_emit,
180 .cs_parse = &r300_cs_parse,
181 .copy_blit = &r100_copy_blit,
182 .copy_dma = &r300_copy_dma,
183 .copy = &r100_copy_blit,
184 .set_engine_clock = &radeon_atom_set_engine_clock,
185 .set_memory_clock = &radeon_atom_set_memory_clock,
186 .set_pcie_lanes = &rv370_set_pcie_lanes,
187 .set_clock_gating = &radeon_atom_set_clock_gating,
e024e110
DA		 188 .set_surface_reg = r100_set_surface_reg,
189 .clear_surface_reg = r100_clear_surface_reg,
c93bb85b 190 .bandwidth_update = &r100_bandwidth_update,
771fe6b9
JG		 191};
192
193
194/*
195 * rs400,rs480
196 */
ca6ffc64
JG		 197extern int rs400_init(struct radeon_device *rdev);
198extern void rs400_fini(struct radeon_device *rdev);
199extern int rs400_suspend(struct radeon_device *rdev);
200extern int rs400_resume(struct radeon_device *rdev);
771fe6b9
JG		 201void rs400_gart_tlb_flush(struct radeon_device *rdev);
202int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
203uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg);
204void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
205static struct radeon_asic rs400_asic = {
ca6ffc64
JG		 206 .init = &rs400_init,
207 .fini = &rs400_fini,
208 .suspend = &rs400_suspend,
209 .resume = &rs400_resume,
771fe6b9 210 .gpu_reset = &r300_gpu_reset,
771fe6b9
JG		 211 .gart_tlb_flush = &rs400_gart_tlb_flush,
212 .gart_set_page = &rs400_gart_set_page,
3ce0a23d 213 .cp_commit = &r100_cp_commit,
771fe6b9 214 .ring_start = &r300_ring_start,
3ce0a23d
JG		 215 .ring_test = &r100_ring_test,
216 .ring_ib_execute = &r100_ring_ib_execute,
771fe6b9
JG		 217 .irq_set = &r100_irq_set,
218 .irq_process = &r100_irq_process,
7ed220d7 219 .get_vblank_counter = &r100_get_vblank_counter,
771fe6b9
JG		 220 .fence_ring_emit = &r300_fence_ring_emit,
221 .cs_parse = &r300_cs_parse,
222 .copy_blit = &r100_copy_blit,
223 .copy_dma = &r300_copy_dma,
224 .copy = &r100_copy_blit,
225 .set_engine_clock = &radeon_legacy_set_engine_clock,
226 .set_memory_clock = NULL,
227 .set_pcie_lanes = NULL,
228 .set_clock_gating = &radeon_legacy_set_clock_gating,
e024e110
DA		 229 .set_surface_reg = r100_set_surface_reg,
230 .clear_surface_reg = r100_clear_surface_reg,
c93bb85b 231 .bandwidth_update = &r100_bandwidth_update,
771fe6b9
JG		 232};
233
234
235/*
236 * rs600.
237 */
c010f800
JG		 238extern int rs600_init(struct radeon_device *rdev);
239extern void rs600_fini(struct radeon_device *rdev);
240extern int rs600_suspend(struct radeon_device *rdev);
241extern int rs600_resume(struct radeon_device *rdev);
771fe6b9 242int rs600_irq_set(struct radeon_device *rdev);
7ed220d7
MD		 243int rs600_irq_process(struct radeon_device *rdev);
244u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc);
771fe6b9
JG		 245void rs600_gart_tlb_flush(struct radeon_device *rdev);
246int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
247uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg);
248void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
c93bb85b 249void rs600_bandwidth_update(struct radeon_device *rdev);
771fe6b9 250static struct radeon_asic rs600_asic = {
3f7dc91a 251 .init = &rs600_init,
c010f800
JG		 252 .fini = &rs600_fini,
253 .suspend = &rs600_suspend,
254 .resume = &rs600_resume,
771fe6b9 255 .gpu_reset = &r300_gpu_reset,
771fe6b9
JG		 256 .gart_tlb_flush = &rs600_gart_tlb_flush,
257 .gart_set_page = &rs600_gart_set_page,
3ce0a23d 258 .cp_commit = &r100_cp_commit,
771fe6b9 259 .ring_start = &r300_ring_start,
3ce0a23d
JG		 260 .ring_test = &r100_ring_test,
261 .ring_ib_execute = &r100_ring_ib_execute,
771fe6b9 262 .irq_set = &rs600_irq_set,
7ed220d7
MD		 263 .irq_process = &rs600_irq_process,
264 .get_vblank_counter = &rs600_get_vblank_counter,
771fe6b9
JG		 265 .fence_ring_emit = &r300_fence_ring_emit,
266 .cs_parse = &r300_cs_parse,
267 .copy_blit = &r100_copy_blit,
268 .copy_dma = &r300_copy_dma,
269 .copy = &r100_copy_blit,
270 .set_engine_clock = &radeon_atom_set_engine_clock,
271 .set_memory_clock = &radeon_atom_set_memory_clock,
272 .set_pcie_lanes = NULL,
273 .set_clock_gating = &radeon_atom_set_clock_gating,
c93bb85b 274 .bandwidth_update = &rs600_bandwidth_update,
771fe6b9
JG		 275};
276
277
278/*
279 * rs690,rs740
280 */
3bc68535
JG		 281int rs690_init(struct radeon_device *rdev);
282void rs690_fini(struct radeon_device *rdev);
283int rs690_resume(struct radeon_device *rdev);
284int rs690_suspend(struct radeon_device *rdev);
771fe6b9
JG		 285uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg);
286void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
c93bb85b 287void rs690_bandwidth_update(struct radeon_device *rdev);
771fe6b9 288static struct radeon_asic rs690_asic = {
3bc68535
JG		 289 .init = &rs690_init,
290 .fini = &rs690_fini,
291 .suspend = &rs690_suspend,
292 .resume = &rs690_resume,
771fe6b9 293 .gpu_reset = &r300_gpu_reset,
771fe6b9
JG		 294 .gart_tlb_flush = &rs400_gart_tlb_flush,
295 .gart_set_page = &rs400_gart_set_page,
3ce0a23d 296 .cp_commit = &r100_cp_commit,
771fe6b9 297 .ring_start = &r300_ring_start,
3ce0a23d
JG		 298 .ring_test = &r100_ring_test,
299 .ring_ib_execute = &r100_ring_ib_execute,
771fe6b9 300 .irq_set = &rs600_irq_set,
7ed220d7
MD		 301 .irq_process = &rs600_irq_process,
302 .get_vblank_counter = &rs600_get_vblank_counter,
771fe6b9
JG		 303 .fence_ring_emit = &r300_fence_ring_emit,
304 .cs_parse = &r300_cs_parse,
305 .copy_blit = &r100_copy_blit,
306 .copy_dma = &r300_copy_dma,
307 .copy = &r300_copy_dma,
308 .set_engine_clock = &radeon_atom_set_engine_clock,
309 .set_memory_clock = &radeon_atom_set_memory_clock,
310 .set_pcie_lanes = NULL,
311 .set_clock_gating = &radeon_atom_set_clock_gating,
e024e110
DA		 312 .set_surface_reg = r100_set_surface_reg,
313 .clear_surface_reg = r100_clear_surface_reg,
c93bb85b 314 .bandwidth_update = &rs690_bandwidth_update,
771fe6b9
JG		 315};
316
317
318/*
319 * rv515
320 */
068a117c 321int rv515_init(struct radeon_device *rdev);
d39c3b89 322void rv515_fini(struct radeon_device *rdev);
771fe6b9 323int rv515_gpu_reset(struct radeon_device *rdev);
771fe6b9
JG		 324uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg);
325void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
326void rv515_ring_start(struct radeon_device *rdev);
327uint32_t rv515_pcie_rreg(struct radeon_device *rdev, uint32_t reg);
328void rv515_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
c93bb85b 329void rv515_bandwidth_update(struct radeon_device *rdev);
d39c3b89
JG		 330int rv515_resume(struct radeon_device *rdev);
331int rv515_suspend(struct radeon_device *rdev);
771fe6b9 332static struct radeon_asic rv515_asic = {
068a117c 333 .init = &rv515_init,
d39c3b89
JG		 334 .fini = &rv515_fini,
335 .suspend = &rv515_suspend,
336 .resume = &rv515_resume,
771fe6b9 337 .gpu_reset = &rv515_gpu_reset,
771fe6b9
JG		 338 .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
339 .gart_set_page = &rv370_pcie_gart_set_page,
3ce0a23d 340 .cp_commit = &r100_cp_commit,
771fe6b9 341 .ring_start = &rv515_ring_start,
3ce0a23d
JG		 342 .ring_test = &r100_ring_test,
343 .ring_ib_execute = &r100_ring_ib_execute,
7ed220d7
MD		 344 .irq_set = &rs600_irq_set,
345 .irq_process = &rs600_irq_process,
346 .get_vblank_counter = &rs600_get_vblank_counter,
771fe6b9 347 .fence_ring_emit = &r300_fence_ring_emit,
068a117c 348 .cs_parse = &r300_cs_parse,
771fe6b9
JG		 349 .copy_blit = &r100_copy_blit,
350 .copy_dma = &r300_copy_dma,
351 .copy = &r100_copy_blit,
352 .set_engine_clock = &radeon_atom_set_engine_clock,
353 .set_memory_clock = &radeon_atom_set_memory_clock,
354 .set_pcie_lanes = &rv370_set_pcie_lanes,
355 .set_clock_gating = &radeon_atom_set_clock_gating,
e024e110
DA		 356 .set_surface_reg = r100_set_surface_reg,
357 .clear_surface_reg = r100_clear_surface_reg,
c93bb85b 358 .bandwidth_update = &rv515_bandwidth_update,
771fe6b9
JG		 359};
360
361
362/*
363 * r520,rv530,rv560,rv570,r580
364 */
d39c3b89 365int r520_init(struct radeon_device *rdev);
f0ed1f65 366int r520_resume(struct radeon_device *rdev);
771fe6b9 367static struct radeon_asic r520_asic = {
d39c3b89 368 .init = &r520_init,
f0ed1f65
JG		 369 .fini = &rv515_fini,
370 .suspend = &rv515_suspend,
371 .resume = &r520_resume,
771fe6b9 372 .gpu_reset = &rv515_gpu_reset,
771fe6b9
JG		 373 .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
374 .gart_set_page = &rv370_pcie_gart_set_page,
3ce0a23d 375 .cp_commit = &r100_cp_commit,
771fe6b9 376 .ring_start = &rv515_ring_start,
3ce0a23d
JG		 377 .ring_test = &r100_ring_test,
378 .ring_ib_execute = &r100_ring_ib_execute,
7ed220d7
MD		 379 .irq_set = &rs600_irq_set,
380 .irq_process = &rs600_irq_process,
381 .get_vblank_counter = &rs600_get_vblank_counter,
771fe6b9 382 .fence_ring_emit = &r300_fence_ring_emit,
068a117c 383 .cs_parse = &r300_cs_parse,
771fe6b9
JG		 384 .copy_blit = &r100_copy_blit,
385 .copy_dma = &r300_copy_dma,
386 .copy = &r100_copy_blit,
387 .set_engine_clock = &radeon_atom_set_engine_clock,
388 .set_memory_clock = &radeon_atom_set_memory_clock,
389 .set_pcie_lanes = &rv370_set_pcie_lanes,
390 .set_clock_gating = &radeon_atom_set_clock_gating,
e024e110
DA		 391 .set_surface_reg = r100_set_surface_reg,
392 .clear_surface_reg = r100_clear_surface_reg,
f0ed1f65 393 .bandwidth_update = &rv515_bandwidth_update,
771fe6b9
JG		 394};
395
396/*
3ce0a23d 397 * r600,rv610,rv630,rv620,rv635,rv670,rs780,rs880
771fe6b9 398 */
3ce0a23d
JG		 399int r600_init(struct radeon_device *rdev);
400void r600_fini(struct radeon_device *rdev);
401int r600_suspend(struct radeon_device *rdev);
402int r600_resume(struct radeon_device *rdev);
403int r600_wb_init(struct radeon_device *rdev);
404void r600_wb_fini(struct radeon_device *rdev);
405void r600_cp_commit(struct radeon_device *rdev);
406void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
771fe6b9
JG		 407uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg);
408void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
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JG		 409int r600_cs_parse(struct radeon_cs_parser *p);
410void r600_fence_ring_emit(struct radeon_device *rdev,
411 struct radeon_fence *fence);
412int r600_copy_dma(struct radeon_device *rdev,
413 uint64_t src_offset,
414 uint64_t dst_offset,
415 unsigned num_pages,
416 struct radeon_fence *fence);
417int r600_irq_process(struct radeon_device *rdev);
418int r600_irq_set(struct radeon_device *rdev);
419int r600_gpu_reset(struct radeon_device *rdev);
420int r600_set_surface_reg(struct radeon_device *rdev, int reg,
421 uint32_t tiling_flags, uint32_t pitch,
422 uint32_t offset, uint32_t obj_size);
423int r600_clear_surface_reg(struct radeon_device *rdev, int reg);
424void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
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JG		 425int r600_ring_test(struct radeon_device *rdev);
426int r600_copy_blit(struct radeon_device *rdev,
427 uint64_t src_offset, uint64_t dst_offset,
428 unsigned num_pages, struct radeon_fence *fence);
429
430static struct radeon_asic r600_asic = {
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JG		 431 .init = &r600_init,
432 .fini = &r600_fini,
433 .suspend = &r600_suspend,
434 .resume = &r600_resume,
435 .cp_commit = &r600_cp_commit,
3ce0a23d 436 .gpu_reset = &r600_gpu_reset,
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JG		 437 .gart_tlb_flush = &r600_pcie_gart_tlb_flush,
438 .gart_set_page = &rs600_gart_set_page,
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JG		 439 .ring_test = &r600_ring_test,
440 .ring_ib_execute = &r600_ring_ib_execute,
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JG		 441 .irq_set = &r600_irq_set,
442 .irq_process = &r600_irq_process,
443 .fence_ring_emit = &r600_fence_ring_emit,
444 .cs_parse = &r600_cs_parse,
445 .copy_blit = &r600_copy_blit,
446 .copy_dma = &r600_copy_blit,
a3812877 447 .copy = &r600_copy_blit,
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JG		 448 .set_engine_clock = &radeon_atom_set_engine_clock,
449 .set_memory_clock = &radeon_atom_set_memory_clock,
450 .set_pcie_lanes = NULL,
451 .set_clock_gating = &radeon_atom_set_clock_gating,
452 .set_surface_reg = r600_set_surface_reg,
453 .clear_surface_reg = r600_clear_surface_reg,
f0ed1f65 454 .bandwidth_update = &rv515_bandwidth_update,
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JG		 455};
456
457/*
458 * rv770,rv730,rv710,rv740
459 */
460int rv770_init(struct radeon_device *rdev);
461void rv770_fini(struct radeon_device *rdev);
462int rv770_suspend(struct radeon_device *rdev);
463int rv770_resume(struct radeon_device *rdev);
464int rv770_gpu_reset(struct radeon_device *rdev);
465
466static struct radeon_asic rv770_asic = {
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JG		 467 .init = &rv770_init,
468 .fini = &rv770_fini,
469 .suspend = &rv770_suspend,
470 .resume = &rv770_resume,
471 .cp_commit = &r600_cp_commit,
3ce0a23d 472 .gpu_reset = &rv770_gpu_reset,
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JG		 473 .gart_tlb_flush = &r600_pcie_gart_tlb_flush,
474 .gart_set_page = &rs600_gart_set_page,
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JG		 475 .ring_test = &r600_ring_test,
476 .ring_ib_execute = &r600_ring_ib_execute,
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JG		 477 .irq_set = &r600_irq_set,
478 .irq_process = &r600_irq_process,
479 .fence_ring_emit = &r600_fence_ring_emit,
480 .cs_parse = &r600_cs_parse,
481 .copy_blit = &r600_copy_blit,
482 .copy_dma = &r600_copy_blit,
a3812877 483 .copy = &r600_copy_blit,
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JG		 484 .set_engine_clock = &radeon_atom_set_engine_clock,
485 .set_memory_clock = &radeon_atom_set_memory_clock,
486 .set_pcie_lanes = NULL,
487 .set_clock_gating = &radeon_atom_set_clock_gating,
488 .set_surface_reg = r600_set_surface_reg,
489 .clear_surface_reg = r600_clear_surface_reg,
f0ed1f65 490 .bandwidth_update = &rv515_bandwidth_update,
3ce0a23d 491};
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JG		 492
493#endif
Clone of davem's net-next-2.6 tree