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drm/radeon/kms: simplify & improve GPU reset V2
[net-next-2.6.git] / drivers / gpu / drm / radeon / radeon_asic.c
CommitLineData
0a10c851
DV		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28
29#include <linux/console.h>
30#include <drm/drmP.h>
31#include <drm/drm_crtc_helper.h>
32#include <drm/radeon_drm.h>
33#include <linux/vgaarb.h>
34#include <linux/vga_switcheroo.h>
35#include "radeon_reg.h"
36#include "radeon.h"
37#include "radeon_asic.h"
38#include "atom.h"
39
40/*
41 * Registers accessors functions.
42 */
43static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
44{
45 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
46 BUG_ON(1);
47 return 0;
48}
49
50static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
51{
52 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
53 reg, v);
54 BUG_ON(1);
55}
56
57static void radeon_register_accessor_init(struct radeon_device *rdev)
58{
59 rdev->mc_rreg = &radeon_invalid_rreg;
60 rdev->mc_wreg = &radeon_invalid_wreg;
61 rdev->pll_rreg = &radeon_invalid_rreg;
62 rdev->pll_wreg = &radeon_invalid_wreg;
63 rdev->pciep_rreg = &radeon_invalid_rreg;
64 rdev->pciep_wreg = &radeon_invalid_wreg;
65
66 /* Don't change order as we are overridding accessor. */
67 if (rdev->family < CHIP_RV515) {
68 rdev->pcie_reg_mask = 0xff;
69 } else {
70 rdev->pcie_reg_mask = 0x7ff;
71 }
72 /* FIXME: not sure here */
73 if (rdev->family <= CHIP_R580) {
74 rdev->pll_rreg = &r100_pll_rreg;
75 rdev->pll_wreg = &r100_pll_wreg;
76 }
77 if (rdev->family >= CHIP_R420) {
78 rdev->mc_rreg = &r420_mc_rreg;
79 rdev->mc_wreg = &r420_mc_wreg;
80 }
81 if (rdev->family >= CHIP_RV515) {
82 rdev->mc_rreg = &rv515_mc_rreg;
83 rdev->mc_wreg = &rv515_mc_wreg;
84 }
85 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
86 rdev->mc_rreg = &rs400_mc_rreg;
87 rdev->mc_wreg = &rs400_mc_wreg;
88 }
89 if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
90 rdev->mc_rreg = &rs690_mc_rreg;
91 rdev->mc_wreg = &rs690_mc_wreg;
92 }
93 if (rdev->family == CHIP_RS600) {
94 rdev->mc_rreg = &rs600_mc_rreg;
95 rdev->mc_wreg = &rs600_mc_wreg;
96 }
97 if ((rdev->family >= CHIP_R600) && (rdev->family <= CHIP_RV740)) {
98 rdev->pciep_rreg = &r600_pciep_rreg;
99 rdev->pciep_wreg = &r600_pciep_wreg;
100 }
101}
102
103
104/* helper to disable agp */
105void radeon_agp_disable(struct radeon_device *rdev)
106{
107 rdev->flags &= ~RADEON_IS_AGP;
108 if (rdev->family >= CHIP_R600) {
109 DRM_INFO("Forcing AGP to PCIE mode\n");
110 rdev->flags |= RADEON_IS_PCIE;
111 } else if (rdev->family >= CHIP_RV515 ||
112 rdev->family == CHIP_RV380 ||
113 rdev->family == CHIP_RV410 ||
114 rdev->family == CHIP_R423) {
115 DRM_INFO("Forcing AGP to PCIE mode\n");
116 rdev->flags |= RADEON_IS_PCIE;
117 rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
118 rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
119 } else {
120 DRM_INFO("Forcing AGP to PCI mode\n");
121 rdev->flags |= RADEON_IS_PCI;
122 rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
123 rdev->asic->gart_set_page = &r100_pci_gart_set_page;
124 }
125 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
126}
127
128/*
129 * ASIC
130 */
48e7a5f1
DV		 131static struct radeon_asic r100_asic = {
132 .init = &r100_init,
133 .fini = &r100_fini,
134 .suspend = &r100_suspend,
135 .resume = &r100_resume,
136 .vga_set_state = &r100_vga_set_state,
225758d8 137 .gpu_is_lockup = &r100_gpu_is_lockup,
a2d07b74 138 .asic_reset = &r100_asic_reset,
48e7a5f1
DV		 139 .gart_tlb_flush = &r100_pci_gart_tlb_flush,
140 .gart_set_page = &r100_pci_gart_set_page,
141 .cp_commit = &r100_cp_commit,
142 .ring_start = &r100_ring_start,
143 .ring_test = &r100_ring_test,
144 .ring_ib_execute = &r100_ring_ib_execute,
145 .irq_set = &r100_irq_set,
146 .irq_process = &r100_irq_process,
147 .get_vblank_counter = &r100_get_vblank_counter,
148 .fence_ring_emit = &r100_fence_ring_emit,
149 .cs_parse = &r100_cs_parse,
150 .copy_blit = &r100_copy_blit,
151 .copy_dma = NULL,
152 .copy = &r100_copy_blit,
153 .get_engine_clock = &radeon_legacy_get_engine_clock,
154 .set_engine_clock = &radeon_legacy_set_engine_clock,
155 .get_memory_clock = &radeon_legacy_get_memory_clock,
156 .set_memory_clock = NULL,
157 .get_pcie_lanes = NULL,
158 .set_pcie_lanes = NULL,
159 .set_clock_gating = &radeon_legacy_set_clock_gating,
160 .set_surface_reg = r100_set_surface_reg,
161 .clear_surface_reg = r100_clear_surface_reg,
162 .bandwidth_update = &r100_bandwidth_update,
163 .hpd_init = &r100_hpd_init,
164 .hpd_fini = &r100_hpd_fini,
165 .hpd_sense = &r100_hpd_sense,
166 .hpd_set_polarity = &r100_hpd_set_polarity,
167 .ioctl_wait_idle = NULL,
168};
169
170static struct radeon_asic r200_asic = {
171 .init = &r100_init,
172 .fini = &r100_fini,
173 .suspend = &r100_suspend,
174 .resume = &r100_resume,
175 .vga_set_state = &r100_vga_set_state,
225758d8 176 .gpu_is_lockup = &r100_gpu_is_lockup,
a2d07b74 177 .asic_reset = &r100_asic_reset,
48e7a5f1
DV		 178 .gart_tlb_flush = &r100_pci_gart_tlb_flush,
179 .gart_set_page = &r100_pci_gart_set_page,
180 .cp_commit = &r100_cp_commit,
181 .ring_start = &r100_ring_start,
182 .ring_test = &r100_ring_test,
183 .ring_ib_execute = &r100_ring_ib_execute,
184 .irq_set = &r100_irq_set,
185 .irq_process = &r100_irq_process,
186 .get_vblank_counter = &r100_get_vblank_counter,
187 .fence_ring_emit = &r100_fence_ring_emit,
188 .cs_parse = &r100_cs_parse,
189 .copy_blit = &r100_copy_blit,
190 .copy_dma = &r200_copy_dma,
191 .copy = &r100_copy_blit,
192 .get_engine_clock = &radeon_legacy_get_engine_clock,
193 .set_engine_clock = &radeon_legacy_set_engine_clock,
194 .get_memory_clock = &radeon_legacy_get_memory_clock,
195 .set_memory_clock = NULL,
196 .set_pcie_lanes = NULL,
197 .set_clock_gating = &radeon_legacy_set_clock_gating,
198 .set_surface_reg = r100_set_surface_reg,
199 .clear_surface_reg = r100_clear_surface_reg,
200 .bandwidth_update = &r100_bandwidth_update,
201 .hpd_init = &r100_hpd_init,
202 .hpd_fini = &r100_hpd_fini,
203 .hpd_sense = &r100_hpd_sense,
204 .hpd_set_polarity = &r100_hpd_set_polarity,
205 .ioctl_wait_idle = NULL,
206};
207
208static struct radeon_asic r300_asic = {
209 .init = &r300_init,
210 .fini = &r300_fini,
211 .suspend = &r300_suspend,
212 .resume = &r300_resume,
213 .vga_set_state = &r100_vga_set_state,
225758d8 214 .gpu_is_lockup = &r300_gpu_is_lockup,
a2d07b74 215 .asic_reset = &r300_asic_reset,
48e7a5f1
DV		 216 .gart_tlb_flush = &r100_pci_gart_tlb_flush,
217 .gart_set_page = &r100_pci_gart_set_page,
218 .cp_commit = &r100_cp_commit,
219 .ring_start = &r300_ring_start,
220 .ring_test = &r100_ring_test,
221 .ring_ib_execute = &r100_ring_ib_execute,
222 .irq_set = &r100_irq_set,
223 .irq_process = &r100_irq_process,
224 .get_vblank_counter = &r100_get_vblank_counter,
225 .fence_ring_emit = &r300_fence_ring_emit,
226 .cs_parse = &r300_cs_parse,
227 .copy_blit = &r100_copy_blit,
228 .copy_dma = &r200_copy_dma,
229 .copy = &r100_copy_blit,
230 .get_engine_clock = &radeon_legacy_get_engine_clock,
231 .set_engine_clock = &radeon_legacy_set_engine_clock,
232 .get_memory_clock = &radeon_legacy_get_memory_clock,
233 .set_memory_clock = NULL,
234 .get_pcie_lanes = &rv370_get_pcie_lanes,
235 .set_pcie_lanes = &rv370_set_pcie_lanes,
236 .set_clock_gating = &radeon_legacy_set_clock_gating,
237 .set_surface_reg = r100_set_surface_reg,
238 .clear_surface_reg = r100_clear_surface_reg,
239 .bandwidth_update = &r100_bandwidth_update,
240 .hpd_init = &r100_hpd_init,
241 .hpd_fini = &r100_hpd_fini,
242 .hpd_sense = &r100_hpd_sense,
243 .hpd_set_polarity = &r100_hpd_set_polarity,
244 .ioctl_wait_idle = NULL,
245};
246
247static struct radeon_asic r300_asic_pcie = {
248 .init = &r300_init,
249 .fini = &r300_fini,
250 .suspend = &r300_suspend,
251 .resume = &r300_resume,
252 .vga_set_state = &r100_vga_set_state,
225758d8 253 .gpu_is_lockup = &r300_gpu_is_lockup,
a2d07b74 254 .asic_reset = &r300_asic_reset,
48e7a5f1
DV		 255 .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
256 .gart_set_page = &rv370_pcie_gart_set_page,
257 .cp_commit = &r100_cp_commit,
258 .ring_start = &r300_ring_start,
259 .ring_test = &r100_ring_test,
260 .ring_ib_execute = &r100_ring_ib_execute,
261 .irq_set = &r100_irq_set,
262 .irq_process = &r100_irq_process,
263 .get_vblank_counter = &r100_get_vblank_counter,
264 .fence_ring_emit = &r300_fence_ring_emit,
265 .cs_parse = &r300_cs_parse,
266 .copy_blit = &r100_copy_blit,
267 .copy_dma = &r200_copy_dma,
268 .copy = &r100_copy_blit,
269 .get_engine_clock = &radeon_legacy_get_engine_clock,
270 .set_engine_clock = &radeon_legacy_set_engine_clock,
271 .get_memory_clock = &radeon_legacy_get_memory_clock,
272 .set_memory_clock = NULL,
273 .set_pcie_lanes = &rv370_set_pcie_lanes,
274 .set_clock_gating = &radeon_legacy_set_clock_gating,
275 .set_surface_reg = r100_set_surface_reg,
276 .clear_surface_reg = r100_clear_surface_reg,
277 .bandwidth_update = &r100_bandwidth_update,
278 .hpd_init = &r100_hpd_init,
279 .hpd_fini = &r100_hpd_fini,
280 .hpd_sense = &r100_hpd_sense,
281 .hpd_set_polarity = &r100_hpd_set_polarity,
282 .ioctl_wait_idle = NULL,
283};
284
285static struct radeon_asic r420_asic = {
286 .init = &r420_init,
287 .fini = &r420_fini,
288 .suspend = &r420_suspend,
289 .resume = &r420_resume,
290 .vga_set_state = &r100_vga_set_state,
225758d8 291 .gpu_is_lockup = &r300_gpu_is_lockup,
a2d07b74 292 .asic_reset = &r300_asic_reset,
48e7a5f1
DV		 293 .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
294 .gart_set_page = &rv370_pcie_gart_set_page,
295 .cp_commit = &r100_cp_commit,
296 .ring_start = &r300_ring_start,
297 .ring_test = &r100_ring_test,
298 .ring_ib_execute = &r100_ring_ib_execute,
299 .irq_set = &r100_irq_set,
300 .irq_process = &r100_irq_process,
301 .get_vblank_counter = &r100_get_vblank_counter,
302 .fence_ring_emit = &r300_fence_ring_emit,
303 .cs_parse = &r300_cs_parse,
304 .copy_blit = &r100_copy_blit,
305 .copy_dma = &r200_copy_dma,
306 .copy = &r100_copy_blit,
307 .get_engine_clock = &radeon_atom_get_engine_clock,
308 .set_engine_clock = &radeon_atom_set_engine_clock,
309 .get_memory_clock = &radeon_atom_get_memory_clock,
310 .set_memory_clock = &radeon_atom_set_memory_clock,
311 .get_pcie_lanes = &rv370_get_pcie_lanes,
312 .set_pcie_lanes = &rv370_set_pcie_lanes,
313 .set_clock_gating = &radeon_atom_set_clock_gating,
314 .set_surface_reg = r100_set_surface_reg,
315 .clear_surface_reg = r100_clear_surface_reg,
316 .bandwidth_update = &r100_bandwidth_update,
317 .hpd_init = &r100_hpd_init,
318 .hpd_fini = &r100_hpd_fini,
319 .hpd_sense = &r100_hpd_sense,
320 .hpd_set_polarity = &r100_hpd_set_polarity,
321 .ioctl_wait_idle = NULL,
322};
323
324static struct radeon_asic rs400_asic = {
325 .init = &rs400_init,
326 .fini = &rs400_fini,
327 .suspend = &rs400_suspend,
328 .resume = &rs400_resume,
329 .vga_set_state = &r100_vga_set_state,
225758d8 330 .gpu_is_lockup = &r300_gpu_is_lockup,
a2d07b74 331 .asic_reset = &r300_asic_reset,
48e7a5f1
DV		 332 .gart_tlb_flush = &rs400_gart_tlb_flush,
333 .gart_set_page = &rs400_gart_set_page,
334 .cp_commit = &r100_cp_commit,
335 .ring_start = &r300_ring_start,
336 .ring_test = &r100_ring_test,
337 .ring_ib_execute = &r100_ring_ib_execute,
338 .irq_set = &r100_irq_set,
339 .irq_process = &r100_irq_process,
340 .get_vblank_counter = &r100_get_vblank_counter,
341 .fence_ring_emit = &r300_fence_ring_emit,
342 .cs_parse = &r300_cs_parse,
343 .copy_blit = &r100_copy_blit,
344 .copy_dma = &r200_copy_dma,
345 .copy = &r100_copy_blit,
346 .get_engine_clock = &radeon_legacy_get_engine_clock,
347 .set_engine_clock = &radeon_legacy_set_engine_clock,
348 .get_memory_clock = &radeon_legacy_get_memory_clock,
349 .set_memory_clock = NULL,
350 .get_pcie_lanes = NULL,
351 .set_pcie_lanes = NULL,
352 .set_clock_gating = &radeon_legacy_set_clock_gating,
353 .set_surface_reg = r100_set_surface_reg,
354 .clear_surface_reg = r100_clear_surface_reg,
355 .bandwidth_update = &r100_bandwidth_update,
356 .hpd_init = &r100_hpd_init,
357 .hpd_fini = &r100_hpd_fini,
358 .hpd_sense = &r100_hpd_sense,
359 .hpd_set_polarity = &r100_hpd_set_polarity,
360 .ioctl_wait_idle = NULL,
361};
362
363static struct radeon_asic rs600_asic = {
364 .init = &rs600_init,
365 .fini = &rs600_fini,
366 .suspend = &rs600_suspend,
367 .resume = &rs600_resume,
368 .vga_set_state = &r100_vga_set_state,
225758d8 369 .gpu_is_lockup = &r300_gpu_is_lockup,
90aca4d2 370 .asic_reset = &rs600_asic_reset,
48e7a5f1
DV		 371 .gart_tlb_flush = &rs600_gart_tlb_flush,
372 .gart_set_page = &rs600_gart_set_page,
373 .cp_commit = &r100_cp_commit,
374 .ring_start = &r300_ring_start,
375 .ring_test = &r100_ring_test,
376 .ring_ib_execute = &r100_ring_ib_execute,
377 .irq_set = &rs600_irq_set,
378 .irq_process = &rs600_irq_process,
379 .get_vblank_counter = &rs600_get_vblank_counter,
380 .fence_ring_emit = &r300_fence_ring_emit,
381 .cs_parse = &r300_cs_parse,
382 .copy_blit = &r100_copy_blit,
383 .copy_dma = &r200_copy_dma,
384 .copy = &r100_copy_blit,
385 .get_engine_clock = &radeon_atom_get_engine_clock,
386 .set_engine_clock = &radeon_atom_set_engine_clock,
387 .get_memory_clock = &radeon_atom_get_memory_clock,
388 .set_memory_clock = &radeon_atom_set_memory_clock,
389 .get_pcie_lanes = NULL,
390 .set_pcie_lanes = NULL,
391 .set_clock_gating = &radeon_atom_set_clock_gating,
392 .set_surface_reg = r100_set_surface_reg,
393 .clear_surface_reg = r100_clear_surface_reg,
394 .bandwidth_update = &rs600_bandwidth_update,
395 .hpd_init = &rs600_hpd_init,
396 .hpd_fini = &rs600_hpd_fini,
397 .hpd_sense = &rs600_hpd_sense,
398 .hpd_set_polarity = &rs600_hpd_set_polarity,
399 .ioctl_wait_idle = NULL,
400};
401
402static struct radeon_asic rs690_asic = {
403 .init = &rs690_init,
404 .fini = &rs690_fini,
405 .suspend = &rs690_suspend,
406 .resume = &rs690_resume,
407 .vga_set_state = &r100_vga_set_state,
225758d8 408 .gpu_is_lockup = &r300_gpu_is_lockup,
90aca4d2 409 .asic_reset = &rs600_asic_reset,
48e7a5f1
DV		 410 .gart_tlb_flush = &rs400_gart_tlb_flush,
411 .gart_set_page = &rs400_gart_set_page,
412 .cp_commit = &r100_cp_commit,
413 .ring_start = &r300_ring_start,
414 .ring_test = &r100_ring_test,
415 .ring_ib_execute = &r100_ring_ib_execute,
416 .irq_set = &rs600_irq_set,
417 .irq_process = &rs600_irq_process,
418 .get_vblank_counter = &rs600_get_vblank_counter,
419 .fence_ring_emit = &r300_fence_ring_emit,
420 .cs_parse = &r300_cs_parse,
421 .copy_blit = &r100_copy_blit,
422 .copy_dma = &r200_copy_dma,
423 .copy = &r200_copy_dma,
424 .get_engine_clock = &radeon_atom_get_engine_clock,
425 .set_engine_clock = &radeon_atom_set_engine_clock,
426 .get_memory_clock = &radeon_atom_get_memory_clock,
427 .set_memory_clock = &radeon_atom_set_memory_clock,
428 .get_pcie_lanes = NULL,
429 .set_pcie_lanes = NULL,
430 .set_clock_gating = &radeon_atom_set_clock_gating,
431 .set_surface_reg = r100_set_surface_reg,
432 .clear_surface_reg = r100_clear_surface_reg,
433 .bandwidth_update = &rs690_bandwidth_update,
434 .hpd_init = &rs600_hpd_init,
435 .hpd_fini = &rs600_hpd_fini,
436 .hpd_sense = &rs600_hpd_sense,
437 .hpd_set_polarity = &rs600_hpd_set_polarity,
438 .ioctl_wait_idle = NULL,
439};
440
441static struct radeon_asic rv515_asic = {
442 .init = &rv515_init,
443 .fini = &rv515_fini,
444 .suspend = &rv515_suspend,
445 .resume = &rv515_resume,
446 .vga_set_state = &r100_vga_set_state,
225758d8 447 .gpu_is_lockup = &r300_gpu_is_lockup,
90aca4d2 448 .asic_reset = &rs600_asic_reset,
48e7a5f1
DV		 449 .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
450 .gart_set_page = &rv370_pcie_gart_set_page,
451 .cp_commit = &r100_cp_commit,
452 .ring_start = &rv515_ring_start,
453 .ring_test = &r100_ring_test,
454 .ring_ib_execute = &r100_ring_ib_execute,
455 .irq_set = &rs600_irq_set,
456 .irq_process = &rs600_irq_process,
457 .get_vblank_counter = &rs600_get_vblank_counter,
458 .fence_ring_emit = &r300_fence_ring_emit,
459 .cs_parse = &r300_cs_parse,
460 .copy_blit = &r100_copy_blit,
461 .copy_dma = &r200_copy_dma,
462 .copy = &r100_copy_blit,
463 .get_engine_clock = &radeon_atom_get_engine_clock,
464 .set_engine_clock = &radeon_atom_set_engine_clock,
465 .get_memory_clock = &radeon_atom_get_memory_clock,
466 .set_memory_clock = &radeon_atom_set_memory_clock,
467 .get_pcie_lanes = &rv370_get_pcie_lanes,
468 .set_pcie_lanes = &rv370_set_pcie_lanes,
469 .set_clock_gating = &radeon_atom_set_clock_gating,
470 .set_surface_reg = r100_set_surface_reg,
471 .clear_surface_reg = r100_clear_surface_reg,
472 .bandwidth_update = &rv515_bandwidth_update,
473 .hpd_init = &rs600_hpd_init,
474 .hpd_fini = &rs600_hpd_fini,
475 .hpd_sense = &rs600_hpd_sense,
476 .hpd_set_polarity = &rs600_hpd_set_polarity,
477 .ioctl_wait_idle = NULL,
478};
479
480static struct radeon_asic r520_asic = {
481 .init = &r520_init,
482 .fini = &rv515_fini,
483 .suspend = &rv515_suspend,
484 .resume = &r520_resume,
485 .vga_set_state = &r100_vga_set_state,
225758d8 486 .gpu_is_lockup = &r300_gpu_is_lockup,
90aca4d2 487 .asic_reset = &rs600_asic_reset,
48e7a5f1
DV		 488 .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
489 .gart_set_page = &rv370_pcie_gart_set_page,
490 .cp_commit = &r100_cp_commit,
491 .ring_start = &rv515_ring_start,
492 .ring_test = &r100_ring_test,
493 .ring_ib_execute = &r100_ring_ib_execute,
494 .irq_set = &rs600_irq_set,
495 .irq_process = &rs600_irq_process,
496 .get_vblank_counter = &rs600_get_vblank_counter,
497 .fence_ring_emit = &r300_fence_ring_emit,
498 .cs_parse = &r300_cs_parse,
499 .copy_blit = &r100_copy_blit,
500 .copy_dma = &r200_copy_dma,
501 .copy = &r100_copy_blit,
502 .get_engine_clock = &radeon_atom_get_engine_clock,
503 .set_engine_clock = &radeon_atom_set_engine_clock,
504 .get_memory_clock = &radeon_atom_get_memory_clock,
505 .set_memory_clock = &radeon_atom_set_memory_clock,
506 .get_pcie_lanes = &rv370_get_pcie_lanes,
507 .set_pcie_lanes = &rv370_set_pcie_lanes,
508 .set_clock_gating = &radeon_atom_set_clock_gating,
509 .set_surface_reg = r100_set_surface_reg,
510 .clear_surface_reg = r100_clear_surface_reg,
511 .bandwidth_update = &rv515_bandwidth_update,
512 .hpd_init = &rs600_hpd_init,
513 .hpd_fini = &rs600_hpd_fini,
514 .hpd_sense = &rs600_hpd_sense,
515 .hpd_set_polarity = &rs600_hpd_set_polarity,
516 .ioctl_wait_idle = NULL,
517};
518
519static struct radeon_asic r600_asic = {
520 .init = &r600_init,
521 .fini = &r600_fini,
522 .suspend = &r600_suspend,
523 .resume = &r600_resume,
524 .cp_commit = &r600_cp_commit,
525 .vga_set_state = &r600_vga_set_state,
225758d8 526 .gpu_is_lockup = &r600_gpu_is_lockup,
a2d07b74 527 .asic_reset = &r600_asic_reset,
48e7a5f1
DV		 528 .gart_tlb_flush = &r600_pcie_gart_tlb_flush,
529 .gart_set_page = &rs600_gart_set_page,
530 .ring_test = &r600_ring_test,
531 .ring_ib_execute = &r600_ring_ib_execute,
532 .irq_set = &r600_irq_set,
533 .irq_process = &r600_irq_process,
534 .get_vblank_counter = &rs600_get_vblank_counter,
535 .fence_ring_emit = &r600_fence_ring_emit,
536 .cs_parse = &r600_cs_parse,
537 .copy_blit = &r600_copy_blit,
538 .copy_dma = &r600_copy_blit,
539 .copy = &r600_copy_blit,
540 .get_engine_clock = &radeon_atom_get_engine_clock,
541 .set_engine_clock = &radeon_atom_set_engine_clock,
542 .get_memory_clock = &radeon_atom_get_memory_clock,
543 .set_memory_clock = &radeon_atom_set_memory_clock,
544 .get_pcie_lanes = &rv370_get_pcie_lanes,
545 .set_pcie_lanes = NULL,
546 .set_clock_gating = NULL,
547 .set_surface_reg = r600_set_surface_reg,
548 .clear_surface_reg = r600_clear_surface_reg,
549 .bandwidth_update = &rv515_bandwidth_update,
550 .hpd_init = &r600_hpd_init,
551 .hpd_fini = &r600_hpd_fini,
552 .hpd_sense = &r600_hpd_sense,
553 .hpd_set_polarity = &r600_hpd_set_polarity,
554 .ioctl_wait_idle = r600_ioctl_wait_idle,
555};
556
f47299c5
AD		 557static struct radeon_asic rs780_asic = {
558 .init = &r600_init,
559 .fini = &r600_fini,
560 .suspend = &r600_suspend,
561 .resume = &r600_resume,
562 .cp_commit = &r600_cp_commit,
90aca4d2 563 .gpu_is_lockup = &r600_gpu_is_lockup,
f47299c5 564 .vga_set_state = &r600_vga_set_state,
a2d07b74 565 .asic_reset = &r600_asic_reset,
f47299c5
AD		 566 .gart_tlb_flush = &r600_pcie_gart_tlb_flush,
567 .gart_set_page = &rs600_gart_set_page,
568 .ring_test = &r600_ring_test,
569 .ring_ib_execute = &r600_ring_ib_execute,
570 .irq_set = &r600_irq_set,
571 .irq_process = &r600_irq_process,
572 .get_vblank_counter = &rs600_get_vblank_counter,
573 .fence_ring_emit = &r600_fence_ring_emit,
574 .cs_parse = &r600_cs_parse,
575 .copy_blit = &r600_copy_blit,
576 .copy_dma = &r600_copy_blit,
577 .copy = &r600_copy_blit,
578 .get_engine_clock = &radeon_atom_get_engine_clock,
579 .set_engine_clock = &radeon_atom_set_engine_clock,
580 .get_memory_clock = NULL,
581 .set_memory_clock = NULL,
582 .get_pcie_lanes = NULL,
583 .set_pcie_lanes = NULL,
584 .set_clock_gating = NULL,
585 .set_surface_reg = r600_set_surface_reg,
586 .clear_surface_reg = r600_clear_surface_reg,
587 .bandwidth_update = &rs690_bandwidth_update,
588 .hpd_init = &r600_hpd_init,
589 .hpd_fini = &r600_hpd_fini,
590 .hpd_sense = &r600_hpd_sense,
591 .hpd_set_polarity = &r600_hpd_set_polarity,
592 .ioctl_wait_idle = r600_ioctl_wait_idle,
593};
594
48e7a5f1
DV		 595static struct radeon_asic rv770_asic = {
596 .init = &rv770_init,
597 .fini = &rv770_fini,
598 .suspend = &rv770_suspend,
599 .resume = &rv770_resume,
600 .cp_commit = &r600_cp_commit,
a2d07b74 601 .asic_reset = &r600_asic_reset,
225758d8 602 .gpu_is_lockup = &r600_gpu_is_lockup,
48e7a5f1
DV		 603 .vga_set_state = &r600_vga_set_state,
604 .gart_tlb_flush = &r600_pcie_gart_tlb_flush,
605 .gart_set_page = &rs600_gart_set_page,
606 .ring_test = &r600_ring_test,
607 .ring_ib_execute = &r600_ring_ib_execute,
608 .irq_set = &r600_irq_set,
609 .irq_process = &r600_irq_process,
610 .get_vblank_counter = &rs600_get_vblank_counter,
611 .fence_ring_emit = &r600_fence_ring_emit,
612 .cs_parse = &r600_cs_parse,
613 .copy_blit = &r600_copy_blit,
614 .copy_dma = &r600_copy_blit,
615 .copy = &r600_copy_blit,
616 .get_engine_clock = &radeon_atom_get_engine_clock,
617 .set_engine_clock = &radeon_atom_set_engine_clock,
618 .get_memory_clock = &radeon_atom_get_memory_clock,
619 .set_memory_clock = &radeon_atom_set_memory_clock,
620 .get_pcie_lanes = &rv370_get_pcie_lanes,
621 .set_pcie_lanes = NULL,
622 .set_clock_gating = &radeon_atom_set_clock_gating,
623 .set_surface_reg = r600_set_surface_reg,
624 .clear_surface_reg = r600_clear_surface_reg,
625 .bandwidth_update = &rv515_bandwidth_update,
626 .hpd_init = &r600_hpd_init,
627 .hpd_fini = &r600_hpd_fini,
628 .hpd_sense = &r600_hpd_sense,
629 .hpd_set_polarity = &r600_hpd_set_polarity,
630 .ioctl_wait_idle = r600_ioctl_wait_idle,
631};
632
633static struct radeon_asic evergreen_asic = {
634 .init = &evergreen_init,
635 .fini = &evergreen_fini,
636 .suspend = &evergreen_suspend,
637 .resume = &evergreen_resume,
638 .cp_commit = NULL,
225758d8 639 .gpu_is_lockup = &evergreen_gpu_is_lockup,
a2d07b74 640 .asic_reset = &evergreen_asic_reset,
48e7a5f1
DV		 641 .vga_set_state = &r600_vga_set_state,
642 .gart_tlb_flush = &r600_pcie_gart_tlb_flush,
643 .gart_set_page = &rs600_gart_set_page,
644 .ring_test = NULL,
645 .ring_ib_execute = NULL,
646 .irq_set = NULL,
647 .irq_process = NULL,
648 .get_vblank_counter = NULL,
649 .fence_ring_emit = NULL,
650 .cs_parse = NULL,
651 .copy_blit = NULL,
652 .copy_dma = NULL,
653 .copy = NULL,
654 .get_engine_clock = &radeon_atom_get_engine_clock,
655 .set_engine_clock = &radeon_atom_set_engine_clock,
656 .get_memory_clock = &radeon_atom_get_memory_clock,
657 .set_memory_clock = &radeon_atom_set_memory_clock,
658 .set_pcie_lanes = NULL,
659 .set_clock_gating = NULL,
660 .set_surface_reg = r600_set_surface_reg,
661 .clear_surface_reg = r600_clear_surface_reg,
662 .bandwidth_update = &evergreen_bandwidth_update,
663 .hpd_init = &evergreen_hpd_init,
664 .hpd_fini = &evergreen_hpd_fini,
665 .hpd_sense = &evergreen_hpd_sense,
666 .hpd_set_polarity = &evergreen_hpd_set_polarity,
667};
668
0a10c851
DV		 669int radeon_asic_init(struct radeon_device *rdev)
670{
671 radeon_register_accessor_init(rdev);
672 switch (rdev->family) {
673 case CHIP_R100:
674 case CHIP_RV100:
675 case CHIP_RS100:
676 case CHIP_RV200:
677 case CHIP_RS200:
678 rdev->asic = &r100_asic;
679 break;
680 case CHIP_R200:
681 case CHIP_RV250:
682 case CHIP_RS300:
683 case CHIP_RV280:
684 rdev->asic = &r200_asic;
685 break;
686 case CHIP_R300:
687 case CHIP_R350:
688 case CHIP_RV350:
689 case CHIP_RV380:
690 if (rdev->flags & RADEON_IS_PCIE)
691 rdev->asic = &r300_asic_pcie;
692 else
693 rdev->asic = &r300_asic;
694 break;
695 case CHIP_R420:
696 case CHIP_R423:
697 case CHIP_RV410:
698 rdev->asic = &r420_asic;
699 break;
700 case CHIP_RS400:
701 case CHIP_RS480:
702 rdev->asic = &rs400_asic;
703 break;
704 case CHIP_RS600:
705 rdev->asic = &rs600_asic;
706 break;
707 case CHIP_RS690:
708 case CHIP_RS740:
709 rdev->asic = &rs690_asic;
710 break;
711 case CHIP_RV515:
712 rdev->asic = &rv515_asic;
713 break;
714 case CHIP_R520:
715 case CHIP_RV530:
716 case CHIP_RV560:
717 case CHIP_RV570:
718 case CHIP_R580:
719 rdev->asic = &r520_asic;
720 break;
721 case CHIP_R600:
722 case CHIP_RV610:
723 case CHIP_RV630:
724 case CHIP_RV620:
725 case CHIP_RV635:
726 case CHIP_RV670:
f47299c5
AD		 727 rdev->asic = &r600_asic;
728 break;
0a10c851
DV		 729 case CHIP_RS780:
730 case CHIP_RS880:
f47299c5 731 rdev->asic = &rs780_asic;
0a10c851
DV		 732 break;
733 case CHIP_RV770:
734 case CHIP_RV730:
735 case CHIP_RV710:
736 case CHIP_RV740:
737 rdev->asic = &rv770_asic;
738 break;
739 case CHIP_CEDAR:
740 case CHIP_REDWOOD:
741 case CHIP_JUNIPER:
742 case CHIP_CYPRESS:
743 case CHIP_HEMLOCK:
744 rdev->asic = &evergreen_asic;
745 break;
746 default:
747 /* FIXME: not supported yet */
748 return -EINVAL;
749 }
750
751 if (rdev->flags & RADEON_IS_IGP) {
752 rdev->asic->get_memory_clock = NULL;
753 rdev->asic->set_memory_clock = NULL;
754 }
755
9e7b414e
AD		 756 /* set the number of crtcs */
757 if (rdev->flags & RADEON_SINGLE_CRTC)
758 rdev->num_crtc = 1;
759 else {
760 if (ASIC_IS_DCE4(rdev))
761 rdev->num_crtc = 6;
762 else
763 rdev->num_crtc = 2;
764 }
765
0a10c851
DV		 766 return 0;
767}
768
769/*
770 * Wrapper around modesetting bits. Move to radeon_clocks.c?
771 */
772int radeon_clocks_init(struct radeon_device *rdev)
773{
774 int r;
775
776 r = radeon_static_clocks_init(rdev->ddev);
777 if (r) {
778 return r;
779 }
780 DRM_INFO("Clocks initialized !\n");
781 return 0;
782}
783
784void radeon_clocks_fini(struct radeon_device *rdev)
785{
786}
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