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Merge branch 'flock' of git://git.kernel.org/pub/scm/linux/kernel/git/arnd/bkl
[net-next-2.6.git] / drivers / gpu / drm / radeon / r600_cs.c
CommitLineData
3ce0a23d
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
40e2a5c1 28#include <linux/kernel.h>
3ce0a23d
JG		 29#include "drmP.h"
30#include "radeon.h"
3ce0a23d 31#include "r600d.h"
961fb597 32#include "r600_reg_safe.h"
3ce0a23d
JG		 33
34static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p,
35 struct radeon_cs_reloc **cs_reloc);
36static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p,
37 struct radeon_cs_reloc **cs_reloc);
38typedef int (*next_reloc_t)(struct radeon_cs_parser*, struct radeon_cs_reloc**);
39static next_reloc_t r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_mm;
961fb597
JG		 40extern void r600_cs_legacy_get_tiling_conf(struct drm_device *dev, u32 *npipes, u32 *nbanks, u32 *group_size);
41
3ce0a23d 42
c8c15ff1 43struct r600_cs_track {
961fb597
JG		 44 /* configuration we miror so that we use same code btw kms/ums */
45 u32 group_size;
46 u32 nbanks;
47 u32 npipes;
48 /* value we track */
5f77df36 49 u32 sq_config;
961fb597
JG		 50 u32 nsamples;
51 u32 cb_color_base_last[8];
52 struct radeon_bo *cb_color_bo[8];
53 u32 cb_color_bo_offset[8];
54 struct radeon_bo *cb_color_frag_bo[8];
55 struct radeon_bo *cb_color_tile_bo[8];
56 u32 cb_color_info[8];
57 u32 cb_color_size_idx[8];
58 u32 cb_target_mask;
59 u32 cb_shader_mask;
60 u32 cb_color_size[8];
61 u32 vgt_strmout_en;
62 u32 vgt_strmout_buffer_en;
63 u32 db_depth_control;
64 u32 db_depth_info;
65 u32 db_depth_size_idx;
66 u32 db_depth_view;
67 u32 db_depth_size;
68 u32 db_offset;
69 struct radeon_bo *db_bo;
c8c15ff1
JG		 70};
71
961fb597
JG		 72static inline int r600_bpe_from_format(u32 *bpe, u32 format)
73{
74 switch (format) {
75 case V_038004_COLOR_8:
76 case V_038004_COLOR_4_4:
77 case V_038004_COLOR_3_3_2:
78 case V_038004_FMT_1:
79 *bpe = 1;
80 break;
81 case V_038004_COLOR_16:
82 case V_038004_COLOR_16_FLOAT:
83 case V_038004_COLOR_8_8:
84 case V_038004_COLOR_5_6_5:
85 case V_038004_COLOR_6_5_5:
86 case V_038004_COLOR_1_5_5_5:
87 case V_038004_COLOR_4_4_4_4:
88 case V_038004_COLOR_5_5_5_1:
89 *bpe = 2;
90 break;
91 case V_038004_FMT_8_8_8:
92 *bpe = 3;
93 break;
94 case V_038004_COLOR_32:
95 case V_038004_COLOR_32_FLOAT:
96 case V_038004_COLOR_16_16:
97 case V_038004_COLOR_16_16_FLOAT:
98 case V_038004_COLOR_8_24:
99 case V_038004_COLOR_8_24_FLOAT:
100 case V_038004_COLOR_24_8:
101 case V_038004_COLOR_24_8_FLOAT:
102 case V_038004_COLOR_10_11_11:
103 case V_038004_COLOR_10_11_11_FLOAT:
104 case V_038004_COLOR_11_11_10:
105 case V_038004_COLOR_11_11_10_FLOAT:
106 case V_038004_COLOR_2_10_10_10:
107 case V_038004_COLOR_8_8_8_8:
108 case V_038004_COLOR_10_10_10_2:
109 case V_038004_FMT_5_9_9_9_SHAREDEXP:
110 case V_038004_FMT_32_AS_8:
111 case V_038004_FMT_32_AS_8_8:
112 *bpe = 4;
113 break;
114 case V_038004_COLOR_X24_8_32_FLOAT:
115 case V_038004_COLOR_32_32:
116 case V_038004_COLOR_32_32_FLOAT:
117 case V_038004_COLOR_16_16_16_16:
118 case V_038004_COLOR_16_16_16_16_FLOAT:
119 *bpe = 8;
120 break;
121 case V_038004_FMT_16_16_16:
122 case V_038004_FMT_16_16_16_FLOAT:
123 *bpe = 6;
124 break;
125 case V_038004_FMT_32_32_32:
126 case V_038004_FMT_32_32_32_FLOAT:
127 *bpe = 12;
128 break;
129 case V_038004_COLOR_32_32_32_32:
130 case V_038004_COLOR_32_32_32_32_FLOAT:
131 *bpe = 16;
132 break;
133 case V_038004_FMT_GB_GR:
134 case V_038004_FMT_BG_RG:
135 case V_038004_COLOR_INVALID:
618145ea 136 default:
961fb597
JG		 137 *bpe = 16;
138 return -EINVAL;
139 }
140 return 0;
141}
142
143static void r600_cs_track_init(struct r600_cs_track *track)
144{
145 int i;
146
5f77df36
AD		 147 /* assume DX9 mode */
148 track->sq_config = DX9_CONSTS;
961fb597
JG		 149 for (i = 0; i < 8; i++) {
150 track->cb_color_base_last[i] = 0;
151 track->cb_color_size[i] = 0;
152 track->cb_color_size_idx[i] = 0;
153 track->cb_color_info[i] = 0;
154 track->cb_color_bo[i] = NULL;
155 track->cb_color_bo_offset[i] = 0xFFFFFFFF;
156 }
157 track->cb_target_mask = 0xFFFFFFFF;
158 track->cb_shader_mask = 0xFFFFFFFF;
159 track->db_bo = NULL;
160 /* assume the biggest format and that htile is enabled */
161 track->db_depth_info = 7 | (1 << 25);
162 track->db_depth_view = 0xFFFFC000;
163 track->db_depth_size = 0xFFFFFFFF;
164 track->db_depth_size_idx = 0;
165 track->db_depth_control = 0xFFFFFFFF;
166}
167
168static inline int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
169{
170 struct r600_cs_track *track = p->track;
40e2a5c1 171 u32 bpe = 0, pitch, slice_tile_max, size, tmp, height, pitch_align;
961fb597 172 volatile u32 *ib = p->ib->ptr;
f30df2fa 173 unsigned array_mode;
961fb597
JG		 174
175 if (G_0280A0_TILE_MODE(track->cb_color_info[i])) {
176 dev_warn(p->dev, "FMASK or CMASK buffer are not supported by this kernel\n");
177 return -EINVAL;
178 }
1729dd33 179 size = radeon_bo_size(track->cb_color_bo[i]) - track->cb_color_bo_offset[i];
961fb597
JG		 180 if (r600_bpe_from_format(&bpe, G_0280A0_FORMAT(track->cb_color_info[i]))) {
181 dev_warn(p->dev, "%s:%d cb invalid format %d for %d (0x%08X)\n",
182 __func__, __LINE__, G_0280A0_FORMAT(track->cb_color_info[i]),
183 i, track->cb_color_info[i]);
184 return -EINVAL;
185 }
40e2a5c1
AD		 186 /* pitch is the number of 8x8 tiles per row */
187 pitch = G_028060_PITCH_TILE_MAX(track->cb_color_size[i]) + 1;
961fb597 188 slice_tile_max = G_028060_SLICE_TILE_MAX(track->cb_color_size[i]) + 1;
f30df2fa
DA		 189 slice_tile_max *= 64;
190 height = slice_tile_max / (pitch * 8);
961fb597
JG		 191 if (height > 8192)
192 height = 8192;
f30df2fa
DA		 193 array_mode = G_0280A0_ARRAY_MODE(track->cb_color_info[i]);
194 switch (array_mode) {
961fb597 195 case V_0280A0_ARRAY_LINEAR_GENERAL:
40e2a5c1
AD		 196 /* technically height & 0x7 */
197 break;
961fb597 198 case V_0280A0_ARRAY_LINEAR_ALIGNED:
40e2a5c1
AD		 199 pitch_align = max((u32)64, (u32)(track->group_size / bpe)) / 8;
200 if (!IS_ALIGNED(pitch, pitch_align)) {
201 dev_warn(p->dev, "%s:%d cb pitch (%d) invalid\n",
202 __func__, __LINE__, pitch);
961fb597
JG		 203 return -EINVAL;
204 }
40e2a5c1
AD		 205 if (!IS_ALIGNED(height, 8)) {
206 dev_warn(p->dev, "%s:%d cb height (%d) invalid\n",
207 __func__, __LINE__, height);
961fb597
JG		 208 return -EINVAL;
209 }
210 break;
211 case V_0280A0_ARRAY_1D_TILED_THIN1:
40e2a5c1
AD		 212 pitch_align = max((u32)8, (u32)(track->group_size / (8 * bpe * track->nsamples))) / 8;
213 if (!IS_ALIGNED(pitch, pitch_align)) {
961fb597 214 dev_warn(p->dev, "%s:%d cb pitch (%d) invalid\n",
40e2a5c1
AD		 215 __func__, __LINE__, pitch);
216 return -EINVAL;
217 }
8f895da5
AD		 218 /* avoid breaking userspace */
219 if (height > 7)
220 height &= ~0x7;
40e2a5c1
AD		 221 if (!IS_ALIGNED(height, 8)) {
222 dev_warn(p->dev, "%s:%d cb height (%d) invalid\n",
223 __func__, __LINE__, height);
961fb597
JG		 224 return -EINVAL;
225 }
961fb597
JG		 226 break;
227 case V_0280A0_ARRAY_2D_TILED_THIN1:
40e2a5c1 228 pitch_align = max((u32)track->nbanks,
f30df2fa 229 (u32)(((track->group_size / 8) / (bpe * track->nsamples)) * track->nbanks)) / 8;
40e2a5c1 230 if (!IS_ALIGNED(pitch, pitch_align)) {
961fb597
JG		 231 dev_warn(p->dev, "%s:%d cb pitch (%d) invalid\n",
232 __func__, __LINE__, pitch);
233 return -EINVAL;
234 }
354da653 235 if (!IS_ALIGNED((height / 8), track->npipes)) {
40e2a5c1
AD		 236 dev_warn(p->dev, "%s:%d cb height (%d) invalid\n",
237 __func__, __LINE__, height);
961fb597
JG		 238 return -EINVAL;
239 }
961fb597
JG		 240 break;
241 default:
242 dev_warn(p->dev, "%s invalid tiling %d for %d (0x%08X)\n", __func__,
243 G_0280A0_ARRAY_MODE(track->cb_color_info[i]), i,
244 track->cb_color_info[i]);
245 return -EINVAL;
246 }
247 /* check offset */
40e2a5c1 248 tmp = height * pitch * 8 * bpe;
961fb597 249 if ((tmp + track->cb_color_bo_offset[i]) > radeon_bo_size(track->cb_color_bo[i])) {
f30df2fa
DA		 250 if (array_mode == V_0280A0_ARRAY_LINEAR_GENERAL) {
251 /* the initial DDX does bad things with the CB size occasionally */
252 /* it rounds up height too far for slice tile max but the BO is smaller */
253 tmp = (height - 7) * 8 * bpe;
254 if ((tmp + track->cb_color_bo_offset[i]) > radeon_bo_size(track->cb_color_bo[i])) {
255 dev_warn(p->dev, "%s offset[%d] %d %d %lu too big\n", __func__, i, track->cb_color_bo_offset[i], tmp, radeon_bo_size(track->cb_color_bo[i]));
256 return -EINVAL;
257 }
258 } else {
259 dev_warn(p->dev, "%s offset[%d] %d %d %lu too big\n", __func__, i, track->cb_color_bo_offset[i], tmp, radeon_bo_size(track->cb_color_bo[i]));
260 return -EINVAL;
261 }
40e2a5c1
AD		 262 }
263 if (!IS_ALIGNED(track->cb_color_bo_offset[i], track->group_size)) {
264 dev_warn(p->dev, "%s offset[%d] %d not aligned\n", __func__, i, track->cb_color_bo_offset[i]);
961fb597
JG		 265 return -EINVAL;
266 }
267 /* limit max tile */
40e2a5c1 268 tmp = (height * pitch * 8) >> 6;
961fb597
JG		 269 if (tmp < slice_tile_max)
270 slice_tile_max = tmp;
40e2a5c1 271 tmp = S_028060_PITCH_TILE_MAX(pitch - 1) |
961fb597
JG		 272 S_028060_SLICE_TILE_MAX(slice_tile_max - 1);
273 ib[track->cb_color_size_idx[i]] = tmp;
274 return 0;
275}
276
277static int r600_cs_track_check(struct radeon_cs_parser *p)
278{
279 struct r600_cs_track *track = p->track;
280 u32 tmp;
281 int r, i;
282 volatile u32 *ib = p->ib->ptr;
283
284 /* on legacy kernel we don't perform advanced check */
285 if (p->rdev == NULL)
286 return 0;
287 /* we don't support out buffer yet */
288 if (track->vgt_strmout_en || track->vgt_strmout_buffer_en) {
289 dev_warn(p->dev, "this kernel doesn't support SMX output buffer\n");
290 return -EINVAL;
291 }
292 /* check that we have a cb for each enabled target, we don't check
293 * shader_mask because it seems mesa isn't always setting it :(
294 */
295 tmp = track->cb_target_mask;
296 for (i = 0; i < 8; i++) {
297 if ((tmp >> (i * 4)) & 0xF) {
298 /* at least one component is enabled */
299 if (track->cb_color_bo[i] == NULL) {
300 dev_warn(p->dev, "%s:%d mask 0x%08X | 0x%08X no cb for %d\n",
301 __func__, __LINE__, track->cb_target_mask, track->cb_shader_mask, i);
302 return -EINVAL;
303 }
304 /* perform rewrite of CB_COLOR[0-7]_SIZE */
305 r = r600_cs_track_validate_cb(p, i);
306 if (r)
307 return r;
308 }
309 }
310 /* Check depth buffer */
311 if (G_028800_STENCIL_ENABLE(track->db_depth_control) ||
312 G_028800_Z_ENABLE(track->db_depth_control)) {
40e2a5c1 313 u32 nviews, bpe, ntiles, pitch, pitch_align, height, size;
961fb597
JG		 314 if (track->db_bo == NULL) {
315 dev_warn(p->dev, "z/stencil with no depth buffer\n");
316 return -EINVAL;
317 }
318 if (G_028010_TILE_SURFACE_ENABLE(track->db_depth_info)) {
319 dev_warn(p->dev, "this kernel doesn't support z/stencil htile\n");
320 return -EINVAL;
321 }
322 switch (G_028010_FORMAT(track->db_depth_info)) {
323 case V_028010_DEPTH_16:
324 bpe = 2;
325 break;
326 case V_028010_DEPTH_X8_24:
327 case V_028010_DEPTH_8_24:
328 case V_028010_DEPTH_X8_24_FLOAT:
329 case V_028010_DEPTH_8_24_FLOAT:
330 case V_028010_DEPTH_32_FLOAT:
331 bpe = 4;
332 break;
333 case V_028010_DEPTH_X24_8_32_FLOAT:
334 bpe = 8;
335 break;
336 default:
337 dev_warn(p->dev, "z/stencil with invalid format %d\n", G_028010_FORMAT(track->db_depth_info));
338 return -EINVAL;
339 }
340 if ((track->db_depth_size & 0xFFFFFC00) == 0xFFFFFC00) {
341 if (!track->db_depth_size_idx) {
342 dev_warn(p->dev, "z/stencil buffer size not set\n");
343 return -EINVAL;
344 }
961fb597
JG		 345 tmp = radeon_bo_size(track->db_bo) - track->db_offset;
346 tmp = (tmp / bpe) >> 6;
347 if (!tmp) {
348 dev_warn(p->dev, "z/stencil buffer too small (0x%08X %d %d %ld)\n",
349 track->db_depth_size, bpe, track->db_offset,
350 radeon_bo_size(track->db_bo));
351 return -EINVAL;
352 }
353 ib[track->db_depth_size_idx] = S_028000_SLICE_TILE_MAX(tmp - 1) | (track->db_depth_size & 0x3FF);
354 } else {
40e2a5c1
AD		 355 size = radeon_bo_size(track->db_bo);
356 pitch = G_028000_PITCH_TILE_MAX(track->db_depth_size) + 1;
357 height = size / (pitch * 8 * bpe);
358 height &= ~0x7;
359 if (!height)
360 height = 8;
361
362 switch (G_028010_ARRAY_MODE(track->db_depth_info)) {
363 case V_028010_ARRAY_1D_TILED_THIN1:
364 pitch_align = (max((u32)8, (u32)(track->group_size / (8 * bpe))) / 8);
365 if (!IS_ALIGNED(pitch, pitch_align)) {
366 dev_warn(p->dev, "%s:%d db pitch (%d) invalid\n",
367 __func__, __LINE__, pitch);
368 return -EINVAL;
369 }
370 if (!IS_ALIGNED(height, 8)) {
371 dev_warn(p->dev, "%s:%d db height (%d) invalid\n",
372 __func__, __LINE__, height);
373 return -EINVAL;
374 }
375 break;
376 case V_028010_ARRAY_2D_TILED_THIN1:
377 pitch_align = max((u32)track->nbanks,
f30df2fa 378 (u32)(((track->group_size / 8) / bpe) * track->nbanks)) / 8;
40e2a5c1
AD		 379 if (!IS_ALIGNED(pitch, pitch_align)) {
380 dev_warn(p->dev, "%s:%d db pitch (%d) invalid\n",
381 __func__, __LINE__, pitch);
382 return -EINVAL;
383 }
354da653 384 if (!IS_ALIGNED((height / 8), track->npipes)) {
40e2a5c1
AD		 385 dev_warn(p->dev, "%s:%d db height (%d) invalid\n",
386 __func__, __LINE__, height);
387 return -EINVAL;
388 }
389 break;
390 default:
391 dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__,
392 G_028010_ARRAY_MODE(track->db_depth_info),
393 track->db_depth_info);
394 return -EINVAL;
395 }
396 if (!IS_ALIGNED(track->db_offset, track->group_size)) {
397 dev_warn(p->dev, "%s offset[%d] %d not aligned\n", __func__, i, track->db_offset);
398 return -EINVAL;
399 }
961fb597
JG		 400 ntiles = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1;
401 nviews = G_028004_SLICE_MAX(track->db_depth_view) + 1;
402 tmp = ntiles * bpe * 64 * nviews;
403 if ((tmp + track->db_offset) > radeon_bo_size(track->db_bo)) {
404 dev_warn(p->dev, "z/stencil buffer too small (0x%08X %d %d %d -> %d have %ld)\n",
405 track->db_depth_size, ntiles, nviews, bpe, tmp + track->db_offset,
406 radeon_bo_size(track->db_bo));
407 return -EINVAL;
408 }
409 }
410 }
411 return 0;
412}
413
3ce0a23d
JG		 414/**
415 * r600_cs_packet_parse() - parse cp packet and point ib index to next packet
416 * @parser: parser structure holding parsing context.
417 * @pkt: where to store packet informations
418 *
419 * Assume that chunk_ib_index is properly set. Will return -EINVAL
420 * if packet is bigger than remaining ib size. or if packets is unknown.
421 **/
422int r600_cs_packet_parse(struct radeon_cs_parser *p,
423 struct radeon_cs_packet *pkt,
424 unsigned idx)
425{
426 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
427 uint32_t header;
428
429 if (idx >= ib_chunk->length_dw) {
430 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
431 idx, ib_chunk->length_dw);
432 return -EINVAL;
433 }
513bcb46 434 header = radeon_get_ib_value(p, idx);
3ce0a23d
JG		 435 pkt->idx = idx;
436 pkt->type = CP_PACKET_GET_TYPE(header);
437 pkt->count = CP_PACKET_GET_COUNT(header);
438 pkt->one_reg_wr = 0;
439 switch (pkt->type) {
440 case PACKET_TYPE0:
441 pkt->reg = CP_PACKET0_GET_REG(header);
442 break;
443 case PACKET_TYPE3:
444 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
445 break;
446 case PACKET_TYPE2:
447 pkt->count = -1;
448 break;
449 default:
450 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
451 return -EINVAL;
452 }
453 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
454 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
455 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
456 return -EINVAL;
457 }
458 return 0;
459}
460
461/**
462 * r600_cs_packet_next_reloc_mm() - parse next packet which should be reloc packet3
463 * @parser: parser structure holding parsing context.
464 * @data: pointer to relocation data
465 * @offset_start: starting offset
466 * @offset_mask: offset mask (to align start offset on)
467 * @reloc: reloc informations
468 *
469 * Check next packet is relocation packet3, do bo validation and compute
470 * GPU offset using the provided start.
471 **/
472static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p,
473 struct radeon_cs_reloc **cs_reloc)
474{
3ce0a23d
JG		 475 struct radeon_cs_chunk *relocs_chunk;
476 struct radeon_cs_packet p3reloc;
477 unsigned idx;
478 int r;
479
480 if (p->chunk_relocs_idx == -1) {
481 DRM_ERROR("No relocation chunk !\n");
482 return -EINVAL;
483 }
484 *cs_reloc = NULL;
3ce0a23d
JG		 485 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
486 r = r600_cs_packet_parse(p, &p3reloc, p->idx);
487 if (r) {
488 return r;
489 }
490 p->idx += p3reloc.count + 2;
491 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
492 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
493 p3reloc.idx);
494 return -EINVAL;
495 }
513bcb46 496 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
3ce0a23d
JG		 497 if (idx >= relocs_chunk->length_dw) {
498 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
499 idx, relocs_chunk->length_dw);
500 return -EINVAL;
501 }
502 /* FIXME: we assume reloc size is 4 dwords */
503 *cs_reloc = p->relocs_ptr[(idx / 4)];
504 return 0;
505}
506
507/**
508 * r600_cs_packet_next_reloc_nomm() - parse next packet which should be reloc packet3
509 * @parser: parser structure holding parsing context.
510 * @data: pointer to relocation data
511 * @offset_start: starting offset
512 * @offset_mask: offset mask (to align start offset on)
513 * @reloc: reloc informations
514 *
515 * Check next packet is relocation packet3, do bo validation and compute
516 * GPU offset using the provided start.
517 **/
518static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p,
519 struct radeon_cs_reloc **cs_reloc)
520{
3ce0a23d
JG		 521 struct radeon_cs_chunk *relocs_chunk;
522 struct radeon_cs_packet p3reloc;
523 unsigned idx;
524 int r;
525
526 if (p->chunk_relocs_idx == -1) {
527 DRM_ERROR("No relocation chunk !\n");
528 return -EINVAL;
529 }
530 *cs_reloc = NULL;
3ce0a23d
JG		 531 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
532 r = r600_cs_packet_parse(p, &p3reloc, p->idx);
533 if (r) {
534 return r;
535 }
536 p->idx += p3reloc.count + 2;
537 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
538 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
539 p3reloc.idx);
540 return -EINVAL;
541 }
513bcb46 542 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
3ce0a23d
JG		 543 if (idx >= relocs_chunk->length_dw) {
544 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
545 idx, relocs_chunk->length_dw);
546 return -EINVAL;
547 }
e265f39e 548 *cs_reloc = p->relocs;
3ce0a23d
JG		 549 (*cs_reloc)->lobj.gpu_offset = (u64)relocs_chunk->kdata[idx + 3] << 32;
550 (*cs_reloc)->lobj.gpu_offset |= relocs_chunk->kdata[idx + 0];
551 return 0;
552}
553
c8c15ff1
JG		 554/**
555 * r600_cs_packet_next_is_pkt3_nop() - test if next packet is packet3 nop for reloc
556 * @parser: parser structure holding parsing context.
557 *
558 * Check next packet is relocation packet3, do bo validation and compute
559 * GPU offset using the provided start.
560 **/
561static inline int r600_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p)
562{
563 struct radeon_cs_packet p3reloc;
564 int r;
565
566 r = r600_cs_packet_parse(p, &p3reloc, p->idx);
567 if (r) {
568 return 0;
569 }
570 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
571 return 0;
572 }
573 return 1;
574}
575
2f67c6e0
AD		 576/**
577 * r600_cs_packet_next_vline() - parse userspace VLINE packet
578 * @parser: parser structure holding parsing context.
579 *
580 * Userspace sends a special sequence for VLINE waits.
581 * PACKET0 - VLINE_START_END + value
582 * PACKET3 - WAIT_REG_MEM poll vline status reg
583 * RELOC (P3) - crtc_id in reloc.
584 *
585 * This function parses this and relocates the VLINE START END
586 * and WAIT_REG_MEM packets to the correct crtc.
587 * It also detects a switched off crtc and nulls out the
588 * wait in that case.
589 */
590static int r600_cs_packet_parse_vline(struct radeon_cs_parser *p)
591{
592 struct drm_mode_object *obj;
593 struct drm_crtc *crtc;
594 struct radeon_crtc *radeon_crtc;
595 struct radeon_cs_packet p3reloc, wait_reg_mem;
596 int crtc_id;
597 int r;
598 uint32_t header, h_idx, reg, wait_reg_mem_info;
599 volatile uint32_t *ib;
600
601 ib = p->ib->ptr;
602
603 /* parse the WAIT_REG_MEM */
604 r = r600_cs_packet_parse(p, &wait_reg_mem, p->idx);
605 if (r)
606 return r;
607
608 /* check its a WAIT_REG_MEM */
609 if (wait_reg_mem.type != PACKET_TYPE3 ||
610 wait_reg_mem.opcode != PACKET3_WAIT_REG_MEM) {
611 DRM_ERROR("vline wait missing WAIT_REG_MEM segment\n");
612 r = -EINVAL;
613 return r;
614 }
615
616 wait_reg_mem_info = radeon_get_ib_value(p, wait_reg_mem.idx + 1);
617 /* bit 4 is reg (0) or mem (1) */
618 if (wait_reg_mem_info & 0x10) {
619 DRM_ERROR("vline WAIT_REG_MEM waiting on MEM rather than REG\n");
620 r = -EINVAL;
621 return r;
622 }
623 /* waiting for value to be equal */
624 if ((wait_reg_mem_info & 0x7) != 0x3) {
625 DRM_ERROR("vline WAIT_REG_MEM function not equal\n");
626 r = -EINVAL;
627 return r;
628 }
629 if ((radeon_get_ib_value(p, wait_reg_mem.idx + 2) << 2) != AVIVO_D1MODE_VLINE_STATUS) {
630 DRM_ERROR("vline WAIT_REG_MEM bad reg\n");
631 r = -EINVAL;
632 return r;
633 }
634
635 if (radeon_get_ib_value(p, wait_reg_mem.idx + 5) != AVIVO_D1MODE_VLINE_STAT) {
636 DRM_ERROR("vline WAIT_REG_MEM bad bit mask\n");
637 r = -EINVAL;
638 return r;
639 }
640
641 /* jump over the NOP */
642 r = r600_cs_packet_parse(p, &p3reloc, p->idx + wait_reg_mem.count + 2);
643 if (r)
644 return r;
645
646 h_idx = p->idx - 2;
647 p->idx += wait_reg_mem.count + 2;
648 p->idx += p3reloc.count + 2;
649
650 header = radeon_get_ib_value(p, h_idx);
651 crtc_id = radeon_get_ib_value(p, h_idx + 2 + 7 + 1);
d4ac6a05 652 reg = CP_PACKET0_GET_REG(header);
29508eb6 653
2f67c6e0
AD		 654 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
655 if (!obj) {
656 DRM_ERROR("cannot find crtc %d\n", crtc_id);
657 r = -EINVAL;
658 goto out;
659 }
660 crtc = obj_to_crtc(obj);
661 radeon_crtc = to_radeon_crtc(crtc);
662 crtc_id = radeon_crtc->crtc_id;
663
664 if (!crtc->enabled) {
665 /* if the CRTC isn't enabled - we need to nop out the WAIT_REG_MEM */
666 ib[h_idx + 2] = PACKET2(0);
667 ib[h_idx + 3] = PACKET2(0);
668 ib[h_idx + 4] = PACKET2(0);
669 ib[h_idx + 5] = PACKET2(0);
670 ib[h_idx + 6] = PACKET2(0);
671 ib[h_idx + 7] = PACKET2(0);
672 ib[h_idx + 8] = PACKET2(0);
673 } else if (crtc_id == 1) {
674 switch (reg) {
675 case AVIVO_D1MODE_VLINE_START_END:
676 header &= ~R600_CP_PACKET0_REG_MASK;
677 header |= AVIVO_D2MODE_VLINE_START_END >> 2;
678 break;
679 default:
680 DRM_ERROR("unknown crtc reloc\n");
681 r = -EINVAL;
682 goto out;
683 }
684 ib[h_idx] = header;
685 ib[h_idx + 4] = AVIVO_D2MODE_VLINE_STATUS >> 2;
686 }
687out:
2f67c6e0
AD		 688 return r;
689}
690
3ce0a23d
JG		 691static int r600_packet0_check(struct radeon_cs_parser *p,
692 struct radeon_cs_packet *pkt,
693 unsigned idx, unsigned reg)
694{
2f67c6e0
AD		 695 int r;
696
3ce0a23d
JG		 697 switch (reg) {
698 case AVIVO_D1MODE_VLINE_START_END:
2f67c6e0
AD		 699 r = r600_cs_packet_parse_vline(p);
700 if (r) {
701 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
702 idx, reg);
703 return r;
704 }
3ce0a23d
JG		 705 break;
706 default:
707 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
708 reg, idx);
709 return -EINVAL;
710 }
711 return 0;
712}
713
714static int r600_cs_parse_packet0(struct radeon_cs_parser *p,
715 struct radeon_cs_packet *pkt)
716{
717 unsigned reg, i;
718 unsigned idx;
719 int r;
720
721 idx = pkt->idx + 1;
722 reg = pkt->reg;
723 for (i = 0; i <= pkt->count; i++, idx++, reg += 4) {
724 r = r600_packet0_check(p, pkt, idx, reg);
725 if (r) {
726 return r;
727 }
728 }
729 return 0;
730}
731
961fb597
JG		 732/**
733 * r600_cs_check_reg() - check if register is authorized or not
734 * @parser: parser structure holding parsing context
735 * @reg: register we are testing
736 * @idx: index into the cs buffer
737 *
738 * This function will test against r600_reg_safe_bm and return 0
739 * if register is safe. If register is not flag as safe this function
740 * will test it against a list of register needind special handling.
741 */
742static inline int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
743{
744 struct r600_cs_track *track = (struct r600_cs_track *)p->track;
745 struct radeon_cs_reloc *reloc;
746 u32 last_reg = ARRAY_SIZE(r600_reg_safe_bm);
747 u32 m, i, tmp, *ib;
748 int r;
749
750 i = (reg >> 7);
751 if (i > last_reg) {
752 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
753 return -EINVAL;
754 }
755 m = 1 << ((reg >> 2) & 31);
756 if (!(r600_reg_safe_bm[i] & m))
757 return 0;
758 ib = p->ib->ptr;
759 switch (reg) {
760 /* force following reg to 0 in an attemp to disable out buffer
761 * which will need us to better understand how it works to perform
762 * security check on it (Jerome)
763 */
764 case R_0288A8_SQ_ESGS_RING_ITEMSIZE:
765 case R_008C44_SQ_ESGS_RING_SIZE:
766 case R_0288B0_SQ_ESTMP_RING_ITEMSIZE:
767 case R_008C54_SQ_ESTMP_RING_SIZE:
768 case R_0288C0_SQ_FBUF_RING_ITEMSIZE:
769 case R_008C74_SQ_FBUF_RING_SIZE:
770 case R_0288B4_SQ_GSTMP_RING_ITEMSIZE:
771 case R_008C5C_SQ_GSTMP_RING_SIZE:
772 case R_0288AC_SQ_GSVS_RING_ITEMSIZE:
773 case R_008C4C_SQ_GSVS_RING_SIZE:
774 case R_0288BC_SQ_PSTMP_RING_ITEMSIZE:
775 case R_008C6C_SQ_PSTMP_RING_SIZE:
776 case R_0288C4_SQ_REDUC_RING_ITEMSIZE:
777 case R_008C7C_SQ_REDUC_RING_SIZE:
778 case R_0288B8_SQ_VSTMP_RING_ITEMSIZE:
779 case R_008C64_SQ_VSTMP_RING_SIZE:
780 case R_0288C8_SQ_GS_VERT_ITEMSIZE:
781 /* get value to populate the IB don't remove */
782 tmp =radeon_get_ib_value(p, idx);
783 ib[idx] = 0;
784 break;
5f77df36
AD		 785 case SQ_CONFIG:
786 track->sq_config = radeon_get_ib_value(p, idx);
787 break;
961fb597
JG		 788 case R_028800_DB_DEPTH_CONTROL:
789 track->db_depth_control = radeon_get_ib_value(p, idx);
790 break;
791 case R_028010_DB_DEPTH_INFO:
7f813377
AD		 792 if (r600_cs_packet_next_is_pkt3_nop(p)) {
793 r = r600_cs_packet_next_reloc(p, &reloc);
794 if (r) {
795 dev_warn(p->dev, "bad SET_CONTEXT_REG "
796 "0x%04X\n", reg);
797 return -EINVAL;
798 }
799 track->db_depth_info = radeon_get_ib_value(p, idx);
800 ib[idx] &= C_028010_ARRAY_MODE;
801 track->db_depth_info &= C_028010_ARRAY_MODE;
802 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
803 ib[idx] |= S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1);
804 track->db_depth_info |= S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1);
805 } else {
806 ib[idx] |= S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1);
807 track->db_depth_info |= S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1);
808 }
809 } else
810 track->db_depth_info = radeon_get_ib_value(p, idx);
961fb597
JG		 811 break;
812 case R_028004_DB_DEPTH_VIEW:
813 track->db_depth_view = radeon_get_ib_value(p, idx);
814 break;
815 case R_028000_DB_DEPTH_SIZE:
816 track->db_depth_size = radeon_get_ib_value(p, idx);
817 track->db_depth_size_idx = idx;
818 break;
819 case R_028AB0_VGT_STRMOUT_EN:
820 track->vgt_strmout_en = radeon_get_ib_value(p, idx);
821 break;
822 case R_028B20_VGT_STRMOUT_BUFFER_EN:
823 track->vgt_strmout_buffer_en = radeon_get_ib_value(p, idx);
824 break;
825 case R_028238_CB_TARGET_MASK:
826 track->cb_target_mask = radeon_get_ib_value(p, idx);
827 break;
828 case R_02823C_CB_SHADER_MASK:
829 track->cb_shader_mask = radeon_get_ib_value(p, idx);
830 break;
831 case R_028C04_PA_SC_AA_CONFIG:
832 tmp = G_028C04_MSAA_NUM_SAMPLES(radeon_get_ib_value(p, idx));
833 track->nsamples = 1 << tmp;
834 break;
835 case R_0280A0_CB_COLOR0_INFO:
836 case R_0280A4_CB_COLOR1_INFO:
837 case R_0280A8_CB_COLOR2_INFO:
838 case R_0280AC_CB_COLOR3_INFO:
839 case R_0280B0_CB_COLOR4_INFO:
840 case R_0280B4_CB_COLOR5_INFO:
841 case R_0280B8_CB_COLOR6_INFO:
842 case R_0280BC_CB_COLOR7_INFO:
7f813377
AD		 843 if (r600_cs_packet_next_is_pkt3_nop(p)) {
844 r = r600_cs_packet_next_reloc(p, &reloc);
845 if (r) {
846 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
847 return -EINVAL;
848 }
849 tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4;
850 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
851 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
852 ib[idx] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1);
853 track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1);
854 } else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
855 ib[idx] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1);
856 track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1);
857 }
858 } else {
859 tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4;
860 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
861 }
961fb597
JG		 862 break;
863 case R_028060_CB_COLOR0_SIZE:
864 case R_028064_CB_COLOR1_SIZE:
865 case R_028068_CB_COLOR2_SIZE:
866 case R_02806C_CB_COLOR3_SIZE:
867 case R_028070_CB_COLOR4_SIZE:
868 case R_028074_CB_COLOR5_SIZE:
869 case R_028078_CB_COLOR6_SIZE:
870 case R_02807C_CB_COLOR7_SIZE:
871 tmp = (reg - R_028060_CB_COLOR0_SIZE) / 4;
872 track->cb_color_size[tmp] = radeon_get_ib_value(p, idx);
873 track->cb_color_size_idx[tmp] = idx;
874 break;
875 /* This register were added late, there is userspace
876 * which does provide relocation for those but set
877 * 0 offset. In order to avoid breaking old userspace
878 * we detect this and set address to point to last
879 * CB_COLOR0_BASE, note that if userspace doesn't set
880 * CB_COLOR0_BASE before this register we will report
881 * error. Old userspace always set CB_COLOR0_BASE
882 * before any of this.
883 */
884 case R_0280E0_CB_COLOR0_FRAG:
885 case R_0280E4_CB_COLOR1_FRAG:
886 case R_0280E8_CB_COLOR2_FRAG:
887 case R_0280EC_CB_COLOR3_FRAG:
888 case R_0280F0_CB_COLOR4_FRAG:
889 case R_0280F4_CB_COLOR5_FRAG:
890 case R_0280F8_CB_COLOR6_FRAG:
891 case R_0280FC_CB_COLOR7_FRAG:
892 tmp = (reg - R_0280E0_CB_COLOR0_FRAG) / 4;
893 if (!r600_cs_packet_next_is_pkt3_nop(p)) {
894 if (!track->cb_color_base_last[tmp]) {
895 dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg);
896 return -EINVAL;
897 }
898 ib[idx] = track->cb_color_base_last[tmp];
961fb597
JG		 899 track->cb_color_frag_bo[tmp] = track->cb_color_bo[tmp];
900 } else {
901 r = r600_cs_packet_next_reloc(p, &reloc);
902 if (r) {
903 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
904 return -EINVAL;
905 }
906 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
907 track->cb_color_frag_bo[tmp] = reloc->robj;
908 }
909 break;
910 case R_0280C0_CB_COLOR0_TILE:
911 case R_0280C4_CB_COLOR1_TILE:
912 case R_0280C8_CB_COLOR2_TILE:
913 case R_0280CC_CB_COLOR3_TILE:
914 case R_0280D0_CB_COLOR4_TILE:
915 case R_0280D4_CB_COLOR5_TILE:
916 case R_0280D8_CB_COLOR6_TILE:
917 case R_0280DC_CB_COLOR7_TILE:
918 tmp = (reg - R_0280C0_CB_COLOR0_TILE) / 4;
919 if (!r600_cs_packet_next_is_pkt3_nop(p)) {
920 if (!track->cb_color_base_last[tmp]) {
921 dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg);
922 return -EINVAL;
923 }
924 ib[idx] = track->cb_color_base_last[tmp];
961fb597
JG		 925 track->cb_color_tile_bo[tmp] = track->cb_color_bo[tmp];
926 } else {
927 r = r600_cs_packet_next_reloc(p, &reloc);
928 if (r) {
929 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
930 return -EINVAL;
931 }
932 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
933 track->cb_color_tile_bo[tmp] = reloc->robj;
934 }
935 break;
936 case CB_COLOR0_BASE:
937 case CB_COLOR1_BASE:
938 case CB_COLOR2_BASE:
939 case CB_COLOR3_BASE:
940 case CB_COLOR4_BASE:
941 case CB_COLOR5_BASE:
942 case CB_COLOR6_BASE:
943 case CB_COLOR7_BASE:
944 r = r600_cs_packet_next_reloc(p, &reloc);
945 if (r) {
946 dev_warn(p->dev, "bad SET_CONTEXT_REG "
947 "0x%04X\n", reg);
948 return -EINVAL;
949 }
7cb72ef4 950 tmp = (reg - CB_COLOR0_BASE) / 4;
1729dd33 951 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8;
961fb597 952 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
961fb597
JG		 953 track->cb_color_base_last[tmp] = ib[idx];
954 track->cb_color_bo[tmp] = reloc->robj;
955 break;
956 case DB_DEPTH_BASE:
957 r = r600_cs_packet_next_reloc(p, &reloc);
958 if (r) {
959 dev_warn(p->dev, "bad SET_CONTEXT_REG "
960 "0x%04X\n", reg);
961 return -EINVAL;
962 }
1729dd33 963 track->db_offset = radeon_get_ib_value(p, idx) << 8;
961fb597
JG		 964 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
965 track->db_bo = reloc->robj;
966 break;
967 case DB_HTILE_DATA_BASE:
968 case SQ_PGM_START_FS:
969 case SQ_PGM_START_ES:
970 case SQ_PGM_START_VS:
971 case SQ_PGM_START_GS:
972 case SQ_PGM_START_PS:
5f77df36
AD		 973 case SQ_ALU_CONST_CACHE_GS_0:
974 case SQ_ALU_CONST_CACHE_GS_1:
975 case SQ_ALU_CONST_CACHE_GS_2:
976 case SQ_ALU_CONST_CACHE_GS_3:
977 case SQ_ALU_CONST_CACHE_GS_4:
978 case SQ_ALU_CONST_CACHE_GS_5:
979 case SQ_ALU_CONST_CACHE_GS_6:
980 case SQ_ALU_CONST_CACHE_GS_7:
981 case SQ_ALU_CONST_CACHE_GS_8:
982 case SQ_ALU_CONST_CACHE_GS_9:
983 case SQ_ALU_CONST_CACHE_GS_10:
984 case SQ_ALU_CONST_CACHE_GS_11:
985 case SQ_ALU_CONST_CACHE_GS_12:
986 case SQ_ALU_CONST_CACHE_GS_13:
987 case SQ_ALU_CONST_CACHE_GS_14:
988 case SQ_ALU_CONST_CACHE_GS_15:
989 case SQ_ALU_CONST_CACHE_PS_0:
990 case SQ_ALU_CONST_CACHE_PS_1:
991 case SQ_ALU_CONST_CACHE_PS_2:
992 case SQ_ALU_CONST_CACHE_PS_3:
993 case SQ_ALU_CONST_CACHE_PS_4:
994 case SQ_ALU_CONST_CACHE_PS_5:
995 case SQ_ALU_CONST_CACHE_PS_6:
996 case SQ_ALU_CONST_CACHE_PS_7:
997 case SQ_ALU_CONST_CACHE_PS_8:
998 case SQ_ALU_CONST_CACHE_PS_9:
999 case SQ_ALU_CONST_CACHE_PS_10:
1000 case SQ_ALU_CONST_CACHE_PS_11:
1001 case SQ_ALU_CONST_CACHE_PS_12:
1002 case SQ_ALU_CONST_CACHE_PS_13:
1003 case SQ_ALU_CONST_CACHE_PS_14:
1004 case SQ_ALU_CONST_CACHE_PS_15:
1005 case SQ_ALU_CONST_CACHE_VS_0:
1006 case SQ_ALU_CONST_CACHE_VS_1:
1007 case SQ_ALU_CONST_CACHE_VS_2:
1008 case SQ_ALU_CONST_CACHE_VS_3:
1009 case SQ_ALU_CONST_CACHE_VS_4:
1010 case SQ_ALU_CONST_CACHE_VS_5:
1011 case SQ_ALU_CONST_CACHE_VS_6:
1012 case SQ_ALU_CONST_CACHE_VS_7:
1013 case SQ_ALU_CONST_CACHE_VS_8:
1014 case SQ_ALU_CONST_CACHE_VS_9:
1015 case SQ_ALU_CONST_CACHE_VS_10:
1016 case SQ_ALU_CONST_CACHE_VS_11:
1017 case SQ_ALU_CONST_CACHE_VS_12:
1018 case SQ_ALU_CONST_CACHE_VS_13:
1019 case SQ_ALU_CONST_CACHE_VS_14:
1020 case SQ_ALU_CONST_CACHE_VS_15:
961fb597
JG		 1021 r = r600_cs_packet_next_reloc(p, &reloc);
1022 if (r) {
1023 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1024 "0x%04X\n", reg);
1025 return -EINVAL;
1026 }
1027 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1028 break;
1029 default:
1030 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
1031 return -EINVAL;
1032 }
1033 return 0;
1034}
1035
1036static inline unsigned minify(unsigned size, unsigned levels)
1037{
1038 size = size >> levels;
1039 if (size < 1)
1040 size = 1;
1041 return size;
1042}
1043
1044static void r600_texture_size(unsigned nfaces, unsigned blevel, unsigned nlevels,
40e2a5c1
AD		 1045 unsigned w0, unsigned h0, unsigned d0, unsigned bpe,
1046 unsigned pitch_align,
1047 unsigned *l0_size, unsigned *mipmap_size)
961fb597
JG		 1048{
1049 unsigned offset, i, level, face;
1050 unsigned width, height, depth, rowstride, size;
1051
1052 w0 = minify(w0, 0);
1053 h0 = minify(h0, 0);
1054 d0 = minify(d0, 0);
1055 for(i = 0, offset = 0, level = blevel; i < nlevels; i++, level++) {
1056 width = minify(w0, i);
1057 height = minify(h0, i);
1058 depth = minify(d0, i);
1059 for(face = 0; face < nfaces; face++) {
40e2a5c1 1060 rowstride = ALIGN((width * bpe), pitch_align);
961fb597
JG		 1061 size = height * rowstride * depth;
1062 offset += size;
1063 offset = (offset + 0x1f) & ~0x1f;
1064 }
1065 }
40e2a5c1 1066 *l0_size = ALIGN((w0 * bpe), pitch_align) * h0 * d0;
961fb597 1067 *mipmap_size = offset;
961fb597
JG		 1068 if (!nlevels)
1069 *mipmap_size = *l0_size;
1729dd33
AD		 1070 if (!blevel)
1071 *mipmap_size -= *l0_size;
961fb597
JG		 1072}
1073
1074/**
1075 * r600_check_texture_resource() - check if register is authorized or not
1076 * @p: parser structure holding parsing context
1077 * @idx: index into the cs buffer
1078 * @texture: texture's bo structure
1079 * @mipmap: mipmap's bo structure
1080 *
1081 * This function will check that the resource has valid field and that
1082 * the texture and mipmap bo object are big enough to cover this resource.
1083 */
1084static inline int r600_check_texture_resource(struct radeon_cs_parser *p, u32 idx,
7f813377
AD		 1085 struct radeon_bo *texture,
1086 struct radeon_bo *mipmap,
1087 u32 tiling_flags)
961fb597 1088{
40e2a5c1 1089 struct r600_cs_track *track = p->track;
71b10d87 1090 u32 nfaces, nlevels, blevel, w0, h0, d0, bpe = 0;
40e2a5c1 1091 u32 word0, word1, l0_size, mipmap_size, pitch, pitch_align;
961fb597
JG		 1092
1093 /* on legacy kernel we don't perform advanced check */
1094 if (p->rdev == NULL)
1095 return 0;
7f813377 1096
961fb597 1097 word0 = radeon_get_ib_value(p, idx + 0);
7f813377
AD		 1098 if (tiling_flags & RADEON_TILING_MACRO)
1099 word0 |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1);
1100 else if (tiling_flags & RADEON_TILING_MICRO)
1101 word0 |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1);
961fb597
JG		 1102 word1 = radeon_get_ib_value(p, idx + 1);
1103 w0 = G_038000_TEX_WIDTH(word0) + 1;
1104 h0 = G_038004_TEX_HEIGHT(word1) + 1;
1105 d0 = G_038004_TEX_DEPTH(word1);
1106 nfaces = 1;
1107 switch (G_038000_DIM(word0)) {
1108 case V_038000_SQ_TEX_DIM_1D:
1109 case V_038000_SQ_TEX_DIM_2D:
1110 case V_038000_SQ_TEX_DIM_3D:
1111 break;
1112 case V_038000_SQ_TEX_DIM_CUBEMAP:
1113 nfaces = 6;
1114 break;
1115 case V_038000_SQ_TEX_DIM_1D_ARRAY:
1116 case V_038000_SQ_TEX_DIM_2D_ARRAY:
1117 case V_038000_SQ_TEX_DIM_2D_MSAA:
1118 case V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA:
1119 default:
1120 dev_warn(p->dev, "this kernel doesn't support %d texture dim\n", G_038000_DIM(word0));
1121 return -EINVAL;
1122 }
1123 if (r600_bpe_from_format(&bpe, G_038004_DATA_FORMAT(word1))) {
1124 dev_warn(p->dev, "%s:%d texture invalid format %d\n",
1125 __func__, __LINE__, G_038004_DATA_FORMAT(word1));
1126 return -EINVAL;
1127 }
40e2a5c1
AD		 1128
1129 pitch = G_038000_PITCH(word0) + 1;
1130 switch (G_038000_TILE_MODE(word0)) {
1131 case V_038000_ARRAY_LINEAR_GENERAL:
1132 pitch_align = 1;
1133 /* XXX check height align */
1134 break;
1135 case V_038000_ARRAY_LINEAR_ALIGNED:
1136 pitch_align = max((u32)64, (u32)(track->group_size / bpe)) / 8;
1137 if (!IS_ALIGNED(pitch, pitch_align)) {
1138 dev_warn(p->dev, "%s:%d tex pitch (%d) invalid\n",
1139 __func__, __LINE__, pitch);
1140 return -EINVAL;
1141 }
1142 /* XXX check height align */
1143 break;
1144 case V_038000_ARRAY_1D_TILED_THIN1:
1145 pitch_align = max((u32)8, (u32)(track->group_size / (8 * bpe))) / 8;
1146 if (!IS_ALIGNED(pitch, pitch_align)) {
1147 dev_warn(p->dev, "%s:%d tex pitch (%d) invalid\n",
1148 __func__, __LINE__, pitch);
1149 return -EINVAL;
1150 }
1151 /* XXX check height align */
1152 break;
1153 case V_038000_ARRAY_2D_TILED_THIN1:
1154 pitch_align = max((u32)track->nbanks,
f30df2fa 1155 (u32)(((track->group_size / 8) / bpe) * track->nbanks)) / 8;
40e2a5c1
AD		 1156 if (!IS_ALIGNED(pitch, pitch_align)) {
1157 dev_warn(p->dev, "%s:%d tex pitch (%d) invalid\n",
1158 __func__, __LINE__, pitch);
1159 return -EINVAL;
1160 }
1161 /* XXX check height align */
1162 break;
1163 default:
1164 dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__,
1165 G_038000_TILE_MODE(word0), word0);
1166 return -EINVAL;
1167 }
1168 /* XXX check offset align */
1169
961fb597
JG		 1170 word0 = radeon_get_ib_value(p, idx + 4);
1171 word1 = radeon_get_ib_value(p, idx + 5);
1172 blevel = G_038010_BASE_LEVEL(word0);
1173 nlevels = G_038014_LAST_LEVEL(word1);
40e2a5c1
AD		 1174 r600_texture_size(nfaces, blevel, nlevels, w0, h0, d0, bpe,
1175 (pitch_align * bpe),
1176 &l0_size, &mipmap_size);
961fb597 1177 /* using get ib will give us the offset into the texture bo */
1729dd33 1178 word0 = radeon_get_ib_value(p, idx + 2) << 8;
961fb597
JG		 1179 if ((l0_size + word0) > radeon_bo_size(texture)) {
1180 dev_warn(p->dev, "texture bo too small (%d %d %d %d -> %d have %ld)\n",
1181 w0, h0, bpe, word0, l0_size, radeon_bo_size(texture));
1182 return -EINVAL;
1183 }
1184 /* using get ib will give us the offset into the mipmap bo */
1729dd33 1185 word0 = radeon_get_ib_value(p, idx + 3) << 8;
961fb597 1186 if ((mipmap_size + word0) > radeon_bo_size(mipmap)) {
fe725d4f
AD		 1187 /*dev_warn(p->dev, "mipmap bo too small (%d %d %d %d %d %d -> %d have %ld)\n",
1188 w0, h0, bpe, blevel, nlevels, word0, mipmap_size, radeon_bo_size(texture));*/
961fb597
JG		 1189 }
1190 return 0;
1191}
1192
3ce0a23d
JG		 1193static int r600_packet3_check(struct radeon_cs_parser *p,
1194 struct radeon_cs_packet *pkt)
1195{
3ce0a23d 1196 struct radeon_cs_reloc *reloc;
c8c15ff1 1197 struct r600_cs_track *track;
3ce0a23d
JG		 1198 volatile u32 *ib;
1199 unsigned idx;
1200 unsigned i;
1201 unsigned start_reg, end_reg, reg;
1202 int r;
adea4796 1203 u32 idx_value;
3ce0a23d 1204
c8c15ff1 1205 track = (struct r600_cs_track *)p->track;
3ce0a23d 1206 ib = p->ib->ptr;
3ce0a23d 1207 idx = pkt->idx + 1;
adea4796 1208 idx_value = radeon_get_ib_value(p, idx);
513bcb46 1209
3ce0a23d
JG		 1210 switch (pkt->opcode) {
1211 case PACKET3_START_3D_CMDBUF:
1212 if (p->family >= CHIP_RV770 || pkt->count) {
1213 DRM_ERROR("bad START_3D\n");
1214 return -EINVAL;
1215 }
1216 break;
1217 case PACKET3_CONTEXT_CONTROL:
1218 if (pkt->count != 1) {
1219 DRM_ERROR("bad CONTEXT_CONTROL\n");
1220 return -EINVAL;
1221 }
1222 break;
1223 case PACKET3_INDEX_TYPE:
1224 case PACKET3_NUM_INSTANCES:
1225 if (pkt->count) {
1226 DRM_ERROR("bad INDEX_TYPE/NUM_INSTANCES\n");
1227 return -EINVAL;
1228 }
1229 break;
1230 case PACKET3_DRAW_INDEX:
1231 if (pkt->count != 3) {
1232 DRM_ERROR("bad DRAW_INDEX\n");
1233 return -EINVAL;
1234 }
1235 r = r600_cs_packet_next_reloc(p, &reloc);
1236 if (r) {
1237 DRM_ERROR("bad DRAW_INDEX\n");
1238 return -EINVAL;
1239 }
adea4796 1240 ib[idx+0] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff);
210bed8f 1241 ib[idx+1] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
961fb597
JG		 1242 r = r600_cs_track_check(p);
1243 if (r) {
1244 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1245 return r;
1246 }
3ce0a23d
JG		 1247 break;
1248 case PACKET3_DRAW_INDEX_AUTO:
1249 if (pkt->count != 1) {
1250 DRM_ERROR("bad DRAW_INDEX_AUTO\n");
1251 return -EINVAL;
1252 }
961fb597
JG		 1253 r = r600_cs_track_check(p);
1254 if (r) {
1255 dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx);
1256 return r;
1257 }
3ce0a23d
JG		 1258 break;
1259 case PACKET3_DRAW_INDEX_IMMD_BE:
1260 case PACKET3_DRAW_INDEX_IMMD:
1261 if (pkt->count < 2) {
1262 DRM_ERROR("bad DRAW_INDEX_IMMD\n");
1263 return -EINVAL;
1264 }
961fb597
JG		 1265 r = r600_cs_track_check(p);
1266 if (r) {
1267 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1268 return r;
1269 }
3ce0a23d
JG		 1270 break;
1271 case PACKET3_WAIT_REG_MEM:
1272 if (pkt->count != 5) {
1273 DRM_ERROR("bad WAIT_REG_MEM\n");
1274 return -EINVAL;
1275 }
1276 /* bit 4 is reg (0) or mem (1) */
adea4796 1277 if (idx_value & 0x10) {
3ce0a23d
JG		 1278 r = r600_cs_packet_next_reloc(p, &reloc);
1279 if (r) {
1280 DRM_ERROR("bad WAIT_REG_MEM\n");
1281 return -EINVAL;
1282 }
1283 ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
210bed8f 1284 ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
3ce0a23d
JG		 1285 }
1286 break;
1287 case PACKET3_SURFACE_SYNC:
1288 if (pkt->count != 3) {
1289 DRM_ERROR("bad SURFACE_SYNC\n");
1290 return -EINVAL;
1291 }
1292 /* 0xffffffff/0x0 is flush all cache flag */
513bcb46
DA		 1293 if (radeon_get_ib_value(p, idx + 1) != 0xffffffff ||
1294 radeon_get_ib_value(p, idx + 2) != 0) {
3ce0a23d
JG		 1295 r = r600_cs_packet_next_reloc(p, &reloc);
1296 if (r) {
1297 DRM_ERROR("bad SURFACE_SYNC\n");
1298 return -EINVAL;
1299 }
1300 ib[idx+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1301 }
1302 break;
1303 case PACKET3_EVENT_WRITE:
1304 if (pkt->count != 2 && pkt->count != 0) {
1305 DRM_ERROR("bad EVENT_WRITE\n");
1306 return -EINVAL;
1307 }
1308 if (pkt->count) {
1309 r = r600_cs_packet_next_reloc(p, &reloc);
1310 if (r) {
1311 DRM_ERROR("bad EVENT_WRITE\n");
1312 return -EINVAL;
1313 }
1314 ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
210bed8f 1315 ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
3ce0a23d
JG		 1316 }
1317 break;
1318 case PACKET3_EVENT_WRITE_EOP:
1319 if (pkt->count != 4) {
1320 DRM_ERROR("bad EVENT_WRITE_EOP\n");
1321 return -EINVAL;
1322 }
1323 r = r600_cs_packet_next_reloc(p, &reloc);
1324 if (r) {
1325 DRM_ERROR("bad EVENT_WRITE\n");
1326 return -EINVAL;
1327 }
1328 ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
210bed8f 1329 ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
3ce0a23d
JG		 1330 break;
1331 case PACKET3_SET_CONFIG_REG:
adea4796 1332 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_OFFSET;
3ce0a23d
JG		 1333 end_reg = 4 * pkt->count + start_reg - 4;
1334 if ((start_reg < PACKET3_SET_CONFIG_REG_OFFSET) ||
1335 (start_reg >= PACKET3_SET_CONFIG_REG_END) ||
1336 (end_reg >= PACKET3_SET_CONFIG_REG_END)) {
1337 DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n");
1338 return -EINVAL;
1339 }
1340 for (i = 0; i < pkt->count; i++) {
1341 reg = start_reg + (4 * i);
961fb597
JG		 1342 r = r600_cs_check_reg(p, reg, idx+1+i);
1343 if (r)
1344 return r;
3ce0a23d
JG		 1345 }
1346 break;
1347 case PACKET3_SET_CONTEXT_REG:
adea4796 1348 start_reg = (idx_value << 2) + PACKET3_SET_CONTEXT_REG_OFFSET;
3ce0a23d
JG		 1349 end_reg = 4 * pkt->count + start_reg - 4;
1350 if ((start_reg < PACKET3_SET_CONTEXT_REG_OFFSET) ||
1351 (start_reg >= PACKET3_SET_CONTEXT_REG_END) ||
1352 (end_reg >= PACKET3_SET_CONTEXT_REG_END)) {
1353 DRM_ERROR("bad PACKET3_SET_CONTEXT_REG\n");
1354 return -EINVAL;
1355 }
1356 for (i = 0; i < pkt->count; i++) {
1357 reg = start_reg + (4 * i);
961fb597
JG		 1358 r = r600_cs_check_reg(p, reg, idx+1+i);
1359 if (r)
1360 return r;
3ce0a23d
JG		 1361 }
1362 break;
1363 case PACKET3_SET_RESOURCE:
1364 if (pkt->count % 7) {
1365 DRM_ERROR("bad SET_RESOURCE\n");
1366 return -EINVAL;
1367 }
adea4796 1368 start_reg = (idx_value << 2) + PACKET3_SET_RESOURCE_OFFSET;
3ce0a23d
JG		 1369 end_reg = 4 * pkt->count + start_reg - 4;
1370 if ((start_reg < PACKET3_SET_RESOURCE_OFFSET) ||
1371 (start_reg >= PACKET3_SET_RESOURCE_END) ||
1372 (end_reg >= PACKET3_SET_RESOURCE_END)) {
1373 DRM_ERROR("bad SET_RESOURCE\n");
1374 return -EINVAL;
1375 }
1376 for (i = 0; i < (pkt->count / 7); i++) {
961fb597 1377 struct radeon_bo *texture, *mipmap;
1729dd33 1378 u32 size, offset, base_offset, mip_offset;
961fb597 1379
adea4796 1380 switch (G__SQ_VTX_CONSTANT_TYPE(radeon_get_ib_value(p, idx+(i*7)+6+1))) {
3ce0a23d
JG		 1381 case SQ_TEX_VTX_VALID_TEXTURE:
1382 /* tex base */
1383 r = r600_cs_packet_next_reloc(p, &reloc);
1384 if (r) {
1385 DRM_ERROR("bad SET_RESOURCE\n");
1386 return -EINVAL;
1387 }
1729dd33 1388 base_offset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
7f813377
AD		 1389 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1390 ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1);
1391 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1392 ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1);
961fb597 1393 texture = reloc->robj;
3ce0a23d
JG		 1394 /* tex mip base */
1395 r = r600_cs_packet_next_reloc(p, &reloc);
1396 if (r) {
1397 DRM_ERROR("bad SET_RESOURCE\n");
1398 return -EINVAL;
1399 }
1729dd33 1400 mip_offset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
961fb597
JG		 1401 mipmap = reloc->robj;
1402 r = r600_check_texture_resource(p, idx+(i*7)+1,
7f813377 1403 texture, mipmap, reloc->lobj.tiling_flags);
961fb597
JG		 1404 if (r)
1405 return r;
1729dd33
AD		 1406 ib[idx+1+(i*7)+2] += base_offset;
1407 ib[idx+1+(i*7)+3] += mip_offset;
3ce0a23d
JG		 1408 break;
1409 case SQ_TEX_VTX_VALID_BUFFER:
1410 /* vtx base */
1411 r = r600_cs_packet_next_reloc(p, &reloc);
1412 if (r) {
1413 DRM_ERROR("bad SET_RESOURCE\n");
1414 return -EINVAL;
1415 }
961fb597 1416 offset = radeon_get_ib_value(p, idx+1+(i*7)+0);
1729dd33 1417 size = radeon_get_ib_value(p, idx+1+(i*7)+1) + 1;
961fb597
JG		 1418 if (p->rdev && (size + offset) > radeon_bo_size(reloc->robj)) {
1419 /* force size to size of the buffer */
1729dd33
AD		 1420 dev_warn(p->dev, "vbo resource seems too big (%d) for the bo (%ld)\n",
1421 size + offset, radeon_bo_size(reloc->robj));
961fb597
JG		 1422 ib[idx+1+(i*7)+1] = radeon_bo_size(reloc->robj);
1423 }
3ce0a23d 1424 ib[idx+1+(i*7)+0] += (u32)((reloc->lobj.gpu_offset) & 0xffffffff);
210bed8f 1425 ib[idx+1+(i*7)+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
3ce0a23d
JG		 1426 break;
1427 case SQ_TEX_VTX_INVALID_TEXTURE:
1428 case SQ_TEX_VTX_INVALID_BUFFER:
1429 default:
1430 DRM_ERROR("bad SET_RESOURCE\n");
1431 return -EINVAL;
1432 }
1433 }
1434 break;
1435 case PACKET3_SET_ALU_CONST:
5f77df36
AD		 1436 if (track->sq_config & DX9_CONSTS) {
1437 start_reg = (idx_value << 2) + PACKET3_SET_ALU_CONST_OFFSET;
1438 end_reg = 4 * pkt->count + start_reg - 4;
1439 if ((start_reg < PACKET3_SET_ALU_CONST_OFFSET) ||
1440 (start_reg >= PACKET3_SET_ALU_CONST_END) ||
1441 (end_reg >= PACKET3_SET_ALU_CONST_END)) {
1442 DRM_ERROR("bad SET_ALU_CONST\n");
1443 return -EINVAL;
1444 }
3ce0a23d
JG		 1445 }
1446 break;
1447 case PACKET3_SET_BOOL_CONST:
adea4796 1448 start_reg = (idx_value << 2) + PACKET3_SET_BOOL_CONST_OFFSET;
3ce0a23d
JG		 1449 end_reg = 4 * pkt->count + start_reg - 4;
1450 if ((start_reg < PACKET3_SET_BOOL_CONST_OFFSET) ||
1451 (start_reg >= PACKET3_SET_BOOL_CONST_END) ||
1452 (end_reg >= PACKET3_SET_BOOL_CONST_END)) {
1453 DRM_ERROR("bad SET_BOOL_CONST\n");
1454 return -EINVAL;
1455 }
1456 break;
1457 case PACKET3_SET_LOOP_CONST:
adea4796 1458 start_reg = (idx_value << 2) + PACKET3_SET_LOOP_CONST_OFFSET;
3ce0a23d
JG		 1459 end_reg = 4 * pkt->count + start_reg - 4;
1460 if ((start_reg < PACKET3_SET_LOOP_CONST_OFFSET) ||
1461 (start_reg >= PACKET3_SET_LOOP_CONST_END) ||
1462 (end_reg >= PACKET3_SET_LOOP_CONST_END)) {
1463 DRM_ERROR("bad SET_LOOP_CONST\n");
1464 return -EINVAL;
1465 }
1466 break;
1467 case PACKET3_SET_CTL_CONST:
adea4796 1468 start_reg = (idx_value << 2) + PACKET3_SET_CTL_CONST_OFFSET;
3ce0a23d
JG		 1469 end_reg = 4 * pkt->count + start_reg - 4;
1470 if ((start_reg < PACKET3_SET_CTL_CONST_OFFSET) ||
1471 (start_reg >= PACKET3_SET_CTL_CONST_END) ||
1472 (end_reg >= PACKET3_SET_CTL_CONST_END)) {
1473 DRM_ERROR("bad SET_CTL_CONST\n");
1474 return -EINVAL;
1475 }
1476 break;
1477 case PACKET3_SET_SAMPLER:
1478 if (pkt->count % 3) {
1479 DRM_ERROR("bad SET_SAMPLER\n");
1480 return -EINVAL;
1481 }
adea4796 1482 start_reg = (idx_value << 2) + PACKET3_SET_SAMPLER_OFFSET;
3ce0a23d
JG		 1483 end_reg = 4 * pkt->count + start_reg - 4;
1484 if ((start_reg < PACKET3_SET_SAMPLER_OFFSET) ||
1485 (start_reg >= PACKET3_SET_SAMPLER_END) ||
1486 (end_reg >= PACKET3_SET_SAMPLER_END)) {
1487 DRM_ERROR("bad SET_SAMPLER\n");
1488 return -EINVAL;
1489 }
1490 break;
1491 case PACKET3_SURFACE_BASE_UPDATE:
1492 if (p->family >= CHIP_RV770 || p->family == CHIP_R600) {
1493 DRM_ERROR("bad SURFACE_BASE_UPDATE\n");
1494 return -EINVAL;
1495 }
1496 if (pkt->count) {
1497 DRM_ERROR("bad SURFACE_BASE_UPDATE\n");
1498 return -EINVAL;
1499 }
1500 break;
1501 case PACKET3_NOP:
1502 break;
1503 default:
1504 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1505 return -EINVAL;
1506 }
1507 return 0;
1508}
1509
1510int r600_cs_parse(struct radeon_cs_parser *p)
1511{
1512 struct radeon_cs_packet pkt;
c8c15ff1 1513 struct r600_cs_track *track;
3ce0a23d
JG		 1514 int r;
1515
961fb597
JG		 1516 if (p->track == NULL) {
1517 /* initialize tracker, we are in kms */
1518 track = kzalloc(sizeof(*track), GFP_KERNEL);
1519 if (track == NULL)
1520 return -ENOMEM;
1521 r600_cs_track_init(track);
1522 if (p->rdev->family < CHIP_RV770) {
1523 track->npipes = p->rdev->config.r600.tiling_npipes;
1524 track->nbanks = p->rdev->config.r600.tiling_nbanks;
1525 track->group_size = p->rdev->config.r600.tiling_group_size;
1526 } else if (p->rdev->family <= CHIP_RV740) {
1527 track->npipes = p->rdev->config.rv770.tiling_npipes;
1528 track->nbanks = p->rdev->config.rv770.tiling_nbanks;
1529 track->group_size = p->rdev->config.rv770.tiling_group_size;
1530 }
1531 p->track = track;
1532 }
3ce0a23d
JG		 1533 do {
1534 r = r600_cs_packet_parse(p, &pkt, p->idx);
1535 if (r) {
7cb72ef4
JG		 1536 kfree(p->track);
1537 p->track = NULL;
3ce0a23d
JG		 1538 return r;
1539 }
1540 p->idx += pkt.count + 2;
1541 switch (pkt.type) {
1542 case PACKET_TYPE0:
1543 r = r600_cs_parse_packet0(p, &pkt);
1544 break;
1545 case PACKET_TYPE2:
1546 break;
1547 case PACKET_TYPE3:
1548 r = r600_packet3_check(p, &pkt);
1549 break;
1550 default:
1551 DRM_ERROR("Unknown packet type %d !\n", pkt.type);
961fb597 1552 kfree(p->track);
7cb72ef4 1553 p->track = NULL;
3ce0a23d
JG		 1554 return -EINVAL;
1555 }
1556 if (r) {
961fb597 1557 kfree(p->track);
7cb72ef4 1558 p->track = NULL;
3ce0a23d
JG		 1559 return r;
1560 }
1561 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1562#if 0
1563 for (r = 0; r < p->ib->length_dw; r++) {
1564 printk(KERN_INFO "%05d 0x%08X\n", r, p->ib->ptr[r]);
1565 mdelay(1);
1566 }
1567#endif
961fb597 1568 kfree(p->track);
7cb72ef4 1569 p->track = NULL;
3ce0a23d
JG		 1570 return 0;
1571}
1572
1573static int r600_cs_parser_relocs_legacy(struct radeon_cs_parser *p)
1574{
1575 if (p->chunk_relocs_idx == -1) {
1576 return 0;
1577 }
e265f39e 1578 p->relocs = kzalloc(sizeof(struct radeon_cs_reloc), GFP_KERNEL);
3ce0a23d
JG		 1579 if (p->relocs == NULL) {
1580 return -ENOMEM;
1581 }
1582 return 0;
1583}
1584
1585/**
1586 * cs_parser_fini() - clean parser states
1587 * @parser: parser structure holding parsing context.
1588 * @error: error number
1589 *
1590 * If error is set than unvalidate buffer, otherwise just free memory
1591 * used by parsing context.
1592 **/
1593static void r600_cs_parser_fini(struct radeon_cs_parser *parser, int error)
1594{
1595 unsigned i;
1596
1597 kfree(parser->relocs);
1598 for (i = 0; i < parser->nchunks; i++) {
1599 kfree(parser->chunks[i].kdata);
4c57edba
DA		 1600 kfree(parser->chunks[i].kpage[0]);
1601 kfree(parser->chunks[i].kpage[1]);
3ce0a23d
JG		 1602 }
1603 kfree(parser->chunks);
1604 kfree(parser->chunks_array);
1605}
1606
1607int r600_cs_legacy(struct drm_device *dev, void *data, struct drm_file *filp,
1608 unsigned family, u32 *ib, int *l)
1609{
1610 struct radeon_cs_parser parser;
1611 struct radeon_cs_chunk *ib_chunk;
961fb597
JG		 1612 struct radeon_ib fake_ib;
1613 struct r600_cs_track *track;
3ce0a23d
JG		 1614 int r;
1615
961fb597
JG		 1616 /* initialize tracker */
1617 track = kzalloc(sizeof(*track), GFP_KERNEL);
1618 if (track == NULL)
1619 return -ENOMEM;
1620 r600_cs_track_init(track);
1621 r600_cs_legacy_get_tiling_conf(dev, &track->npipes, &track->nbanks, &track->group_size);
3ce0a23d
JG		 1622 /* initialize parser */
1623 memset(&parser, 0, sizeof(struct radeon_cs_parser));
1624 parser.filp = filp;
c8c15ff1 1625 parser.dev = &dev->pdev->dev;
3ce0a23d
JG		 1626 parser.rdev = NULL;
1627 parser.family = family;
1628 parser.ib = &fake_ib;
961fb597 1629 parser.track = track;
3ce0a23d
JG		 1630 fake_ib.ptr = ib;
1631 r = radeon_cs_parser_init(&parser, data);
1632 if (r) {
1633 DRM_ERROR("Failed to initialize parser !\n");
1634 r600_cs_parser_fini(&parser, r);
1635 return r;
1636 }
1637 r = r600_cs_parser_relocs_legacy(&parser);
1638 if (r) {
1639 DRM_ERROR("Failed to parse relocation !\n");
1640 r600_cs_parser_fini(&parser, r);
1641 return r;
1642 }
1643 /* Copy the packet into the IB, the parser will read from the
1644 * input memory (cached) and write to the IB (which can be
1645 * uncached). */
1646 ib_chunk = &parser.chunks[parser.chunk_ib_idx];
1647 parser.ib->length_dw = ib_chunk->length_dw;
3ce0a23d
JG		 1648 *l = parser.ib->length_dw;
1649 r = r600_cs_parse(&parser);
1650 if (r) {
1651 DRM_ERROR("Invalid command stream !\n");
1652 r600_cs_parser_fini(&parser, r);
1653 return r;
1654 }
513bcb46
DA		 1655 r = radeon_cs_finish_pages(&parser);
1656 if (r) {
1657 DRM_ERROR("Invalid command stream !\n");
1658 r600_cs_parser_fini(&parser, r);
1659 return r;
1660 }
3ce0a23d
JG		 1661 r600_cs_parser_fini(&parser, r);
1662 return r;
1663}
1664
1665void r600_cs_legacy_init(void)
1666{
1667 r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_nomm;
1668}
Clone of davem's net-next-2.6 tree