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drm/radeon/kms: fix CS alignment checking for tiling (v2)
[net-next-2.6.git] / drivers / gpu / drm / radeon / r600_cs.c
CommitLineData
3ce0a23d
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
40e2a5c1 28#include <linux/kernel.h>
3ce0a23d
JG		 29#include "drmP.h"
30#include "radeon.h"
3ce0a23d 31#include "r600d.h"
961fb597 32#include "r600_reg_safe.h"
3ce0a23d
JG		 33
34static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p,
35 struct radeon_cs_reloc **cs_reloc);
36static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p,
37 struct radeon_cs_reloc **cs_reloc);
38typedef int (*next_reloc_t)(struct radeon_cs_parser*, struct radeon_cs_reloc**);
39static next_reloc_t r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_mm;
961fb597
JG		 40extern void r600_cs_legacy_get_tiling_conf(struct drm_device *dev, u32 *npipes, u32 *nbanks, u32 *group_size);
41
3ce0a23d 42
c8c15ff1 43struct r600_cs_track {
961fb597
JG		 44 /* configuration we miror so that we use same code btw kms/ums */
45 u32 group_size;
46 u32 nbanks;
47 u32 npipes;
48 /* value we track */
5f77df36 49 u32 sq_config;
961fb597
JG		 50 u32 nsamples;
51 u32 cb_color_base_last[8];
52 struct radeon_bo *cb_color_bo[8];
53 u32 cb_color_bo_offset[8];
54 struct radeon_bo *cb_color_frag_bo[8];
55 struct radeon_bo *cb_color_tile_bo[8];
56 u32 cb_color_info[8];
57 u32 cb_color_size_idx[8];
58 u32 cb_target_mask;
59 u32 cb_shader_mask;
60 u32 cb_color_size[8];
61 u32 vgt_strmout_en;
62 u32 vgt_strmout_buffer_en;
63 u32 db_depth_control;
64 u32 db_depth_info;
65 u32 db_depth_size_idx;
66 u32 db_depth_view;
67 u32 db_depth_size;
68 u32 db_offset;
69 struct radeon_bo *db_bo;
c8c15ff1
JG		 70};
71
961fb597
JG		 72static inline int r600_bpe_from_format(u32 *bpe, u32 format)
73{
74 switch (format) {
75 case V_038004_COLOR_8:
76 case V_038004_COLOR_4_4:
77 case V_038004_COLOR_3_3_2:
78 case V_038004_FMT_1:
79 *bpe = 1;
80 break;
81 case V_038004_COLOR_16:
82 case V_038004_COLOR_16_FLOAT:
83 case V_038004_COLOR_8_8:
84 case V_038004_COLOR_5_6_5:
85 case V_038004_COLOR_6_5_5:
86 case V_038004_COLOR_1_5_5_5:
87 case V_038004_COLOR_4_4_4_4:
88 case V_038004_COLOR_5_5_5_1:
89 *bpe = 2;
90 break;
91 case V_038004_FMT_8_8_8:
92 *bpe = 3;
93 break;
94 case V_038004_COLOR_32:
95 case V_038004_COLOR_32_FLOAT:
96 case V_038004_COLOR_16_16:
97 case V_038004_COLOR_16_16_FLOAT:
98 case V_038004_COLOR_8_24:
99 case V_038004_COLOR_8_24_FLOAT:
100 case V_038004_COLOR_24_8:
101 case V_038004_COLOR_24_8_FLOAT:
102 case V_038004_COLOR_10_11_11:
103 case V_038004_COLOR_10_11_11_FLOAT:
104 case V_038004_COLOR_11_11_10:
105 case V_038004_COLOR_11_11_10_FLOAT:
106 case V_038004_COLOR_2_10_10_10:
107 case V_038004_COLOR_8_8_8_8:
108 case V_038004_COLOR_10_10_10_2:
109 case V_038004_FMT_5_9_9_9_SHAREDEXP:
110 case V_038004_FMT_32_AS_8:
111 case V_038004_FMT_32_AS_8_8:
112 *bpe = 4;
113 break;
114 case V_038004_COLOR_X24_8_32_FLOAT:
115 case V_038004_COLOR_32_32:
116 case V_038004_COLOR_32_32_FLOAT:
117 case V_038004_COLOR_16_16_16_16:
118 case V_038004_COLOR_16_16_16_16_FLOAT:
119 *bpe = 8;
120 break;
121 case V_038004_FMT_16_16_16:
122 case V_038004_FMT_16_16_16_FLOAT:
123 *bpe = 6;
124 break;
125 case V_038004_FMT_32_32_32:
126 case V_038004_FMT_32_32_32_FLOAT:
127 *bpe = 12;
128 break;
129 case V_038004_COLOR_32_32_32_32:
130 case V_038004_COLOR_32_32_32_32_FLOAT:
131 *bpe = 16;
132 break;
133 case V_038004_FMT_GB_GR:
134 case V_038004_FMT_BG_RG:
135 case V_038004_COLOR_INVALID:
136 *bpe = 16;
137 return -EINVAL;
138 }
139 return 0;
140}
141
142static void r600_cs_track_init(struct r600_cs_track *track)
143{
144 int i;
145
5f77df36
AD		 146 /* assume DX9 mode */
147 track->sq_config = DX9_CONSTS;
961fb597
JG		 148 for (i = 0; i < 8; i++) {
149 track->cb_color_base_last[i] = 0;
150 track->cb_color_size[i] = 0;
151 track->cb_color_size_idx[i] = 0;
152 track->cb_color_info[i] = 0;
153 track->cb_color_bo[i] = NULL;
154 track->cb_color_bo_offset[i] = 0xFFFFFFFF;
155 }
156 track->cb_target_mask = 0xFFFFFFFF;
157 track->cb_shader_mask = 0xFFFFFFFF;
158 track->db_bo = NULL;
159 /* assume the biggest format and that htile is enabled */
160 track->db_depth_info = 7 | (1 << 25);
161 track->db_depth_view = 0xFFFFC000;
162 track->db_depth_size = 0xFFFFFFFF;
163 track->db_depth_size_idx = 0;
164 track->db_depth_control = 0xFFFFFFFF;
165}
166
167static inline int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
168{
169 struct r600_cs_track *track = p->track;
40e2a5c1 170 u32 bpe = 0, pitch, slice_tile_max, size, tmp, height, pitch_align;
961fb597
JG		 171 volatile u32 *ib = p->ib->ptr;
172
173 if (G_0280A0_TILE_MODE(track->cb_color_info[i])) {
174 dev_warn(p->dev, "FMASK or CMASK buffer are not supported by this kernel\n");
175 return -EINVAL;
176 }
177 size = radeon_bo_size(track->cb_color_bo[i]);
178 if (r600_bpe_from_format(&bpe, G_0280A0_FORMAT(track->cb_color_info[i]))) {
179 dev_warn(p->dev, "%s:%d cb invalid format %d for %d (0x%08X)\n",
180 __func__, __LINE__, G_0280A0_FORMAT(track->cb_color_info[i]),
181 i, track->cb_color_info[i]);
182 return -EINVAL;
183 }
40e2a5c1
AD		 184 /* pitch is the number of 8x8 tiles per row */
185 pitch = G_028060_PITCH_TILE_MAX(track->cb_color_size[i]) + 1;
961fb597 186 slice_tile_max = G_028060_SLICE_TILE_MAX(track->cb_color_size[i]) + 1;
40e2a5c1 187 height = size / (pitch * 8 * bpe);
961fb597
JG		 188 if (height > 8192)
189 height = 8192;
40e2a5c1
AD		 190 if (height > 7)
191 height &= ~0x7;
961fb597
JG		 192 switch (G_0280A0_ARRAY_MODE(track->cb_color_info[i])) {
193 case V_0280A0_ARRAY_LINEAR_GENERAL:
40e2a5c1
AD		 194 /* technically height & 0x7 */
195 break;
961fb597 196 case V_0280A0_ARRAY_LINEAR_ALIGNED:
40e2a5c1
AD		 197 pitch_align = max((u32)64, (u32)(track->group_size / bpe)) / 8;
198 if (!IS_ALIGNED(pitch, pitch_align)) {
199 dev_warn(p->dev, "%s:%d cb pitch (%d) invalid\n",
200 __func__, __LINE__, pitch);
961fb597
JG		 201 return -EINVAL;
202 }
40e2a5c1
AD		 203 if (!IS_ALIGNED(height, 8)) {
204 dev_warn(p->dev, "%s:%d cb height (%d) invalid\n",
205 __func__, __LINE__, height);
961fb597
JG		 206 return -EINVAL;
207 }
208 break;
209 case V_0280A0_ARRAY_1D_TILED_THIN1:
40e2a5c1
AD		 210 pitch_align = max((u32)8, (u32)(track->group_size / (8 * bpe * track->nsamples))) / 8;
211 if (!IS_ALIGNED(pitch, pitch_align)) {
961fb597 212 dev_warn(p->dev, "%s:%d cb pitch (%d) invalid\n",
40e2a5c1
AD		 213 __func__, __LINE__, pitch);
214 return -EINVAL;
215 }
216 if (!IS_ALIGNED(height, 8)) {
217 dev_warn(p->dev, "%s:%d cb height (%d) invalid\n",
218 __func__, __LINE__, height);
961fb597
JG		 219 return -EINVAL;
220 }
961fb597
JG		 221 break;
222 case V_0280A0_ARRAY_2D_TILED_THIN1:
40e2a5c1
AD		 223 pitch_align = max((u32)track->nbanks,
224 (u32)(((track->group_size / 8) / (bpe * track->nsamples)) * track->nbanks));
225 if (!IS_ALIGNED(pitch, pitch_align)) {
961fb597
JG		 226 dev_warn(p->dev, "%s:%d cb pitch (%d) invalid\n",
227 __func__, __LINE__, pitch);
228 return -EINVAL;
229 }
40e2a5c1
AD		 230 if (!IS_ALIGNED((height / 8), track->nbanks)) {
231 dev_warn(p->dev, "%s:%d cb height (%d) invalid\n",
232 __func__, __LINE__, height);
961fb597
JG		 233 return -EINVAL;
234 }
961fb597
JG		 235 break;
236 default:
237 dev_warn(p->dev, "%s invalid tiling %d for %d (0x%08X)\n", __func__,
238 G_0280A0_ARRAY_MODE(track->cb_color_info[i]), i,
239 track->cb_color_info[i]);
240 return -EINVAL;
241 }
242 /* check offset */
40e2a5c1 243 tmp = height * pitch * 8 * bpe;
961fb597 244 if ((tmp + track->cb_color_bo_offset[i]) > radeon_bo_size(track->cb_color_bo[i])) {
40e2a5c1
AD		 245 dev_warn(p->dev, "%s offset[%d] %d too big\n", __func__, i, track->cb_color_bo_offset[i]);
246 return -EINVAL;
247 }
248 if (!IS_ALIGNED(track->cb_color_bo_offset[i], track->group_size)) {
249 dev_warn(p->dev, "%s offset[%d] %d not aligned\n", __func__, i, track->cb_color_bo_offset[i]);
961fb597
JG		 250 return -EINVAL;
251 }
252 /* limit max tile */
40e2a5c1 253 tmp = (height * pitch * 8) >> 6;
961fb597
JG		 254 if (tmp < slice_tile_max)
255 slice_tile_max = tmp;
40e2a5c1 256 tmp = S_028060_PITCH_TILE_MAX(pitch - 1) |
961fb597
JG		 257 S_028060_SLICE_TILE_MAX(slice_tile_max - 1);
258 ib[track->cb_color_size_idx[i]] = tmp;
259 return 0;
260}
261
262static int r600_cs_track_check(struct radeon_cs_parser *p)
263{
264 struct r600_cs_track *track = p->track;
265 u32 tmp;
266 int r, i;
267 volatile u32 *ib = p->ib->ptr;
268
269 /* on legacy kernel we don't perform advanced check */
270 if (p->rdev == NULL)
271 return 0;
272 /* we don't support out buffer yet */
273 if (track->vgt_strmout_en || track->vgt_strmout_buffer_en) {
274 dev_warn(p->dev, "this kernel doesn't support SMX output buffer\n");
275 return -EINVAL;
276 }
277 /* check that we have a cb for each enabled target, we don't check
278 * shader_mask because it seems mesa isn't always setting it :(
279 */
280 tmp = track->cb_target_mask;
281 for (i = 0; i < 8; i++) {
282 if ((tmp >> (i * 4)) & 0xF) {
283 /* at least one component is enabled */
284 if (track->cb_color_bo[i] == NULL) {
285 dev_warn(p->dev, "%s:%d mask 0x%08X | 0x%08X no cb for %d\n",
286 __func__, __LINE__, track->cb_target_mask, track->cb_shader_mask, i);
287 return -EINVAL;
288 }
289 /* perform rewrite of CB_COLOR[0-7]_SIZE */
290 r = r600_cs_track_validate_cb(p, i);
291 if (r)
292 return r;
293 }
294 }
295 /* Check depth buffer */
296 if (G_028800_STENCIL_ENABLE(track->db_depth_control) ||
297 G_028800_Z_ENABLE(track->db_depth_control)) {
40e2a5c1 298 u32 nviews, bpe, ntiles, pitch, pitch_align, height, size;
961fb597
JG		 299 if (track->db_bo == NULL) {
300 dev_warn(p->dev, "z/stencil with no depth buffer\n");
301 return -EINVAL;
302 }
303 if (G_028010_TILE_SURFACE_ENABLE(track->db_depth_info)) {
304 dev_warn(p->dev, "this kernel doesn't support z/stencil htile\n");
305 return -EINVAL;
306 }
307 switch (G_028010_FORMAT(track->db_depth_info)) {
308 case V_028010_DEPTH_16:
309 bpe = 2;
310 break;
311 case V_028010_DEPTH_X8_24:
312 case V_028010_DEPTH_8_24:
313 case V_028010_DEPTH_X8_24_FLOAT:
314 case V_028010_DEPTH_8_24_FLOAT:
315 case V_028010_DEPTH_32_FLOAT:
316 bpe = 4;
317 break;
318 case V_028010_DEPTH_X24_8_32_FLOAT:
319 bpe = 8;
320 break;
321 default:
322 dev_warn(p->dev, "z/stencil with invalid format %d\n", G_028010_FORMAT(track->db_depth_info));
323 return -EINVAL;
324 }
325 if ((track->db_depth_size & 0xFFFFFC00) == 0xFFFFFC00) {
326 if (!track->db_depth_size_idx) {
327 dev_warn(p->dev, "z/stencil buffer size not set\n");
328 return -EINVAL;
329 }
330 printk_once(KERN_WARNING "You have old & broken userspace please consider updating mesa\n");
331 tmp = radeon_bo_size(track->db_bo) - track->db_offset;
332 tmp = (tmp / bpe) >> 6;
333 if (!tmp) {
334 dev_warn(p->dev, "z/stencil buffer too small (0x%08X %d %d %ld)\n",
335 track->db_depth_size, bpe, track->db_offset,
336 radeon_bo_size(track->db_bo));
337 return -EINVAL;
338 }
339 ib[track->db_depth_size_idx] = S_028000_SLICE_TILE_MAX(tmp - 1) | (track->db_depth_size & 0x3FF);
340 } else {
40e2a5c1
AD		 341 size = radeon_bo_size(track->db_bo);
342 pitch = G_028000_PITCH_TILE_MAX(track->db_depth_size) + 1;
343 height = size / (pitch * 8 * bpe);
344 height &= ~0x7;
345 if (!height)
346 height = 8;
347
348 switch (G_028010_ARRAY_MODE(track->db_depth_info)) {
349 case V_028010_ARRAY_1D_TILED_THIN1:
350 pitch_align = (max((u32)8, (u32)(track->group_size / (8 * bpe))) / 8);
351 if (!IS_ALIGNED(pitch, pitch_align)) {
352 dev_warn(p->dev, "%s:%d db pitch (%d) invalid\n",
353 __func__, __LINE__, pitch);
354 return -EINVAL;
355 }
356 if (!IS_ALIGNED(height, 8)) {
357 dev_warn(p->dev, "%s:%d db height (%d) invalid\n",
358 __func__, __LINE__, height);
359 return -EINVAL;
360 }
361 break;
362 case V_028010_ARRAY_2D_TILED_THIN1:
363 pitch_align = max((u32)track->nbanks,
364 (u32)(((track->group_size / 8) / bpe) * track->nbanks));
365 if (!IS_ALIGNED(pitch, pitch_align)) {
366 dev_warn(p->dev, "%s:%d db pitch (%d) invalid\n",
367 __func__, __LINE__, pitch);
368 return -EINVAL;
369 }
370 if ((height / 8) & (track->nbanks - 1)) {
371 dev_warn(p->dev, "%s:%d db height (%d) invalid\n",
372 __func__, __LINE__, height);
373 return -EINVAL;
374 }
375 break;
376 default:
377 dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__,
378 G_028010_ARRAY_MODE(track->db_depth_info),
379 track->db_depth_info);
380 return -EINVAL;
381 }
382 if (!IS_ALIGNED(track->db_offset, track->group_size)) {
383 dev_warn(p->dev, "%s offset[%d] %d not aligned\n", __func__, i, track->db_offset);
384 return -EINVAL;
385 }
961fb597
JG		 386 ntiles = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1;
387 nviews = G_028004_SLICE_MAX(track->db_depth_view) + 1;
388 tmp = ntiles * bpe * 64 * nviews;
389 if ((tmp + track->db_offset) > radeon_bo_size(track->db_bo)) {
390 dev_warn(p->dev, "z/stencil buffer too small (0x%08X %d %d %d -> %d have %ld)\n",
391 track->db_depth_size, ntiles, nviews, bpe, tmp + track->db_offset,
392 radeon_bo_size(track->db_bo));
393 return -EINVAL;
394 }
395 }
396 }
397 return 0;
398}
399
3ce0a23d
JG		 400/**
401 * r600_cs_packet_parse() - parse cp packet and point ib index to next packet
402 * @parser: parser structure holding parsing context.
403 * @pkt: where to store packet informations
404 *
405 * Assume that chunk_ib_index is properly set. Will return -EINVAL
406 * if packet is bigger than remaining ib size. or if packets is unknown.
407 **/
408int r600_cs_packet_parse(struct radeon_cs_parser *p,
409 struct radeon_cs_packet *pkt,
410 unsigned idx)
411{
412 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
413 uint32_t header;
414
415 if (idx >= ib_chunk->length_dw) {
416 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
417 idx, ib_chunk->length_dw);
418 return -EINVAL;
419 }
513bcb46 420 header = radeon_get_ib_value(p, idx);
3ce0a23d
JG		 421 pkt->idx = idx;
422 pkt->type = CP_PACKET_GET_TYPE(header);
423 pkt->count = CP_PACKET_GET_COUNT(header);
424 pkt->one_reg_wr = 0;
425 switch (pkt->type) {
426 case PACKET_TYPE0:
427 pkt->reg = CP_PACKET0_GET_REG(header);
428 break;
429 case PACKET_TYPE3:
430 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
431 break;
432 case PACKET_TYPE2:
433 pkt->count = -1;
434 break;
435 default:
436 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
437 return -EINVAL;
438 }
439 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
440 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
441 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
442 return -EINVAL;
443 }
444 return 0;
445}
446
447/**
448 * r600_cs_packet_next_reloc_mm() - parse next packet which should be reloc packet3
449 * @parser: parser structure holding parsing context.
450 * @data: pointer to relocation data
451 * @offset_start: starting offset
452 * @offset_mask: offset mask (to align start offset on)
453 * @reloc: reloc informations
454 *
455 * Check next packet is relocation packet3, do bo validation and compute
456 * GPU offset using the provided start.
457 **/
458static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p,
459 struct radeon_cs_reloc **cs_reloc)
460{
3ce0a23d
JG		 461 struct radeon_cs_chunk *relocs_chunk;
462 struct radeon_cs_packet p3reloc;
463 unsigned idx;
464 int r;
465
466 if (p->chunk_relocs_idx == -1) {
467 DRM_ERROR("No relocation chunk !\n");
468 return -EINVAL;
469 }
470 *cs_reloc = NULL;
3ce0a23d
JG		 471 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
472 r = r600_cs_packet_parse(p, &p3reloc, p->idx);
473 if (r) {
474 return r;
475 }
476 p->idx += p3reloc.count + 2;
477 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
478 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
479 p3reloc.idx);
480 return -EINVAL;
481 }
513bcb46 482 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
3ce0a23d
JG		 483 if (idx >= relocs_chunk->length_dw) {
484 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
485 idx, relocs_chunk->length_dw);
486 return -EINVAL;
487 }
488 /* FIXME: we assume reloc size is 4 dwords */
489 *cs_reloc = p->relocs_ptr[(idx / 4)];
490 return 0;
491}
492
493/**
494 * r600_cs_packet_next_reloc_nomm() - parse next packet which should be reloc packet3
495 * @parser: parser structure holding parsing context.
496 * @data: pointer to relocation data
497 * @offset_start: starting offset
498 * @offset_mask: offset mask (to align start offset on)
499 * @reloc: reloc informations
500 *
501 * Check next packet is relocation packet3, do bo validation and compute
502 * GPU offset using the provided start.
503 **/
504static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p,
505 struct radeon_cs_reloc **cs_reloc)
506{
3ce0a23d
JG		 507 struct radeon_cs_chunk *relocs_chunk;
508 struct radeon_cs_packet p3reloc;
509 unsigned idx;
510 int r;
511
512 if (p->chunk_relocs_idx == -1) {
513 DRM_ERROR("No relocation chunk !\n");
514 return -EINVAL;
515 }
516 *cs_reloc = NULL;
3ce0a23d
JG		 517 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
518 r = r600_cs_packet_parse(p, &p3reloc, p->idx);
519 if (r) {
520 return r;
521 }
522 p->idx += p3reloc.count + 2;
523 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
524 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
525 p3reloc.idx);
526 return -EINVAL;
527 }
513bcb46 528 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
3ce0a23d
JG		 529 if (idx >= relocs_chunk->length_dw) {
530 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
531 idx, relocs_chunk->length_dw);
532 return -EINVAL;
533 }
e265f39e 534 *cs_reloc = p->relocs;
3ce0a23d
JG		 535 (*cs_reloc)->lobj.gpu_offset = (u64)relocs_chunk->kdata[idx + 3] << 32;
536 (*cs_reloc)->lobj.gpu_offset |= relocs_chunk->kdata[idx + 0];
537 return 0;
538}
539
c8c15ff1
JG		 540/**
541 * r600_cs_packet_next_is_pkt3_nop() - test if next packet is packet3 nop for reloc
542 * @parser: parser structure holding parsing context.
543 *
544 * Check next packet is relocation packet3, do bo validation and compute
545 * GPU offset using the provided start.
546 **/
547static inline int r600_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p)
548{
549 struct radeon_cs_packet p3reloc;
550 int r;
551
552 r = r600_cs_packet_parse(p, &p3reloc, p->idx);
553 if (r) {
554 return 0;
555 }
556 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
557 return 0;
558 }
559 return 1;
560}
561
2f67c6e0
AD		 562/**
563 * r600_cs_packet_next_vline() - parse userspace VLINE packet
564 * @parser: parser structure holding parsing context.
565 *
566 * Userspace sends a special sequence for VLINE waits.
567 * PACKET0 - VLINE_START_END + value
568 * PACKET3 - WAIT_REG_MEM poll vline status reg
569 * RELOC (P3) - crtc_id in reloc.
570 *
571 * This function parses this and relocates the VLINE START END
572 * and WAIT_REG_MEM packets to the correct crtc.
573 * It also detects a switched off crtc and nulls out the
574 * wait in that case.
575 */
576static int r600_cs_packet_parse_vline(struct radeon_cs_parser *p)
577{
578 struct drm_mode_object *obj;
579 struct drm_crtc *crtc;
580 struct radeon_crtc *radeon_crtc;
581 struct radeon_cs_packet p3reloc, wait_reg_mem;
582 int crtc_id;
583 int r;
584 uint32_t header, h_idx, reg, wait_reg_mem_info;
585 volatile uint32_t *ib;
586
587 ib = p->ib->ptr;
588
589 /* parse the WAIT_REG_MEM */
590 r = r600_cs_packet_parse(p, &wait_reg_mem, p->idx);
591 if (r)
592 return r;
593
594 /* check its a WAIT_REG_MEM */
595 if (wait_reg_mem.type != PACKET_TYPE3 ||
596 wait_reg_mem.opcode != PACKET3_WAIT_REG_MEM) {
597 DRM_ERROR("vline wait missing WAIT_REG_MEM segment\n");
598 r = -EINVAL;
599 return r;
600 }
601
602 wait_reg_mem_info = radeon_get_ib_value(p, wait_reg_mem.idx + 1);
603 /* bit 4 is reg (0) or mem (1) */
604 if (wait_reg_mem_info & 0x10) {
605 DRM_ERROR("vline WAIT_REG_MEM waiting on MEM rather than REG\n");
606 r = -EINVAL;
607 return r;
608 }
609 /* waiting for value to be equal */
610 if ((wait_reg_mem_info & 0x7) != 0x3) {
611 DRM_ERROR("vline WAIT_REG_MEM function not equal\n");
612 r = -EINVAL;
613 return r;
614 }
615 if ((radeon_get_ib_value(p, wait_reg_mem.idx + 2) << 2) != AVIVO_D1MODE_VLINE_STATUS) {
616 DRM_ERROR("vline WAIT_REG_MEM bad reg\n");
617 r = -EINVAL;
618 return r;
619 }
620
621 if (radeon_get_ib_value(p, wait_reg_mem.idx + 5) != AVIVO_D1MODE_VLINE_STAT) {
622 DRM_ERROR("vline WAIT_REG_MEM bad bit mask\n");
623 r = -EINVAL;
624 return r;
625 }
626
627 /* jump over the NOP */
628 r = r600_cs_packet_parse(p, &p3reloc, p->idx + wait_reg_mem.count + 2);
629 if (r)
630 return r;
631
632 h_idx = p->idx - 2;
633 p->idx += wait_reg_mem.count + 2;
634 p->idx += p3reloc.count + 2;
635
636 header = radeon_get_ib_value(p, h_idx);
637 crtc_id = radeon_get_ib_value(p, h_idx + 2 + 7 + 1);
d4ac6a05 638 reg = CP_PACKET0_GET_REG(header);
2f67c6e0
AD		 639 mutex_lock(&p->rdev->ddev->mode_config.mutex);
640 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
641 if (!obj) {
642 DRM_ERROR("cannot find crtc %d\n", crtc_id);
643 r = -EINVAL;
644 goto out;
645 }
646 crtc = obj_to_crtc(obj);
647 radeon_crtc = to_radeon_crtc(crtc);
648 crtc_id = radeon_crtc->crtc_id;
649
650 if (!crtc->enabled) {
651 /* if the CRTC isn't enabled - we need to nop out the WAIT_REG_MEM */
652 ib[h_idx + 2] = PACKET2(0);
653 ib[h_idx + 3] = PACKET2(0);
654 ib[h_idx + 4] = PACKET2(0);
655 ib[h_idx + 5] = PACKET2(0);
656 ib[h_idx + 6] = PACKET2(0);
657 ib[h_idx + 7] = PACKET2(0);
658 ib[h_idx + 8] = PACKET2(0);
659 } else if (crtc_id == 1) {
660 switch (reg) {
661 case AVIVO_D1MODE_VLINE_START_END:
662 header &= ~R600_CP_PACKET0_REG_MASK;
663 header |= AVIVO_D2MODE_VLINE_START_END >> 2;
664 break;
665 default:
666 DRM_ERROR("unknown crtc reloc\n");
667 r = -EINVAL;
668 goto out;
669 }
670 ib[h_idx] = header;
671 ib[h_idx + 4] = AVIVO_D2MODE_VLINE_STATUS >> 2;
672 }
673out:
674 mutex_unlock(&p->rdev->ddev->mode_config.mutex);
675 return r;
676}
677
3ce0a23d
JG		 678static int r600_packet0_check(struct radeon_cs_parser *p,
679 struct radeon_cs_packet *pkt,
680 unsigned idx, unsigned reg)
681{
2f67c6e0
AD		 682 int r;
683
3ce0a23d
JG		 684 switch (reg) {
685 case AVIVO_D1MODE_VLINE_START_END:
2f67c6e0
AD		 686 r = r600_cs_packet_parse_vline(p);
687 if (r) {
688 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
689 idx, reg);
690 return r;
691 }
3ce0a23d
JG		 692 break;
693 default:
694 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
695 reg, idx);
696 return -EINVAL;
697 }
698 return 0;
699}
700
701static int r600_cs_parse_packet0(struct radeon_cs_parser *p,
702 struct radeon_cs_packet *pkt)
703{
704 unsigned reg, i;
705 unsigned idx;
706 int r;
707
708 idx = pkt->idx + 1;
709 reg = pkt->reg;
710 for (i = 0; i <= pkt->count; i++, idx++, reg += 4) {
711 r = r600_packet0_check(p, pkt, idx, reg);
712 if (r) {
713 return r;
714 }
715 }
716 return 0;
717}
718
961fb597
JG		 719/**
720 * r600_cs_check_reg() - check if register is authorized or not
721 * @parser: parser structure holding parsing context
722 * @reg: register we are testing
723 * @idx: index into the cs buffer
724 *
725 * This function will test against r600_reg_safe_bm and return 0
726 * if register is safe. If register is not flag as safe this function
727 * will test it against a list of register needind special handling.
728 */
729static inline int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
730{
731 struct r600_cs_track *track = (struct r600_cs_track *)p->track;
732 struct radeon_cs_reloc *reloc;
733 u32 last_reg = ARRAY_SIZE(r600_reg_safe_bm);
734 u32 m, i, tmp, *ib;
735 int r;
736
737 i = (reg >> 7);
738 if (i > last_reg) {
739 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
740 return -EINVAL;
741 }
742 m = 1 << ((reg >> 2) & 31);
743 if (!(r600_reg_safe_bm[i] & m))
744 return 0;
745 ib = p->ib->ptr;
746 switch (reg) {
747 /* force following reg to 0 in an attemp to disable out buffer
748 * which will need us to better understand how it works to perform
749 * security check on it (Jerome)
750 */
751 case R_0288A8_SQ_ESGS_RING_ITEMSIZE:
752 case R_008C44_SQ_ESGS_RING_SIZE:
753 case R_0288B0_SQ_ESTMP_RING_ITEMSIZE:
754 case R_008C54_SQ_ESTMP_RING_SIZE:
755 case R_0288C0_SQ_FBUF_RING_ITEMSIZE:
756 case R_008C74_SQ_FBUF_RING_SIZE:
757 case R_0288B4_SQ_GSTMP_RING_ITEMSIZE:
758 case R_008C5C_SQ_GSTMP_RING_SIZE:
759 case R_0288AC_SQ_GSVS_RING_ITEMSIZE:
760 case R_008C4C_SQ_GSVS_RING_SIZE:
761 case R_0288BC_SQ_PSTMP_RING_ITEMSIZE:
762 case R_008C6C_SQ_PSTMP_RING_SIZE:
763 case R_0288C4_SQ_REDUC_RING_ITEMSIZE:
764 case R_008C7C_SQ_REDUC_RING_SIZE:
765 case R_0288B8_SQ_VSTMP_RING_ITEMSIZE:
766 case R_008C64_SQ_VSTMP_RING_SIZE:
767 case R_0288C8_SQ_GS_VERT_ITEMSIZE:
768 /* get value to populate the IB don't remove */
769 tmp =radeon_get_ib_value(p, idx);
770 ib[idx] = 0;
771 break;
5f77df36
AD		 772 case SQ_CONFIG:
773 track->sq_config = radeon_get_ib_value(p, idx);
774 break;
961fb597
JG		 775 case R_028800_DB_DEPTH_CONTROL:
776 track->db_depth_control = radeon_get_ib_value(p, idx);
777 break;
778 case R_028010_DB_DEPTH_INFO:
7f813377
AD		 779 if (r600_cs_packet_next_is_pkt3_nop(p)) {
780 r = r600_cs_packet_next_reloc(p, &reloc);
781 if (r) {
782 dev_warn(p->dev, "bad SET_CONTEXT_REG "
783 "0x%04X\n", reg);
784 return -EINVAL;
785 }
786 track->db_depth_info = radeon_get_ib_value(p, idx);
787 ib[idx] &= C_028010_ARRAY_MODE;
788 track->db_depth_info &= C_028010_ARRAY_MODE;
789 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
790 ib[idx] |= S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1);
791 track->db_depth_info |= S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1);
792 } else {
793 ib[idx] |= S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1);
794 track->db_depth_info |= S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1);
795 }
796 } else
797 track->db_depth_info = radeon_get_ib_value(p, idx);
961fb597
JG		 798 break;
799 case R_028004_DB_DEPTH_VIEW:
800 track->db_depth_view = radeon_get_ib_value(p, idx);
801 break;
802 case R_028000_DB_DEPTH_SIZE:
803 track->db_depth_size = radeon_get_ib_value(p, idx);
804 track->db_depth_size_idx = idx;
805 break;
806 case R_028AB0_VGT_STRMOUT_EN:
807 track->vgt_strmout_en = radeon_get_ib_value(p, idx);
808 break;
809 case R_028B20_VGT_STRMOUT_BUFFER_EN:
810 track->vgt_strmout_buffer_en = radeon_get_ib_value(p, idx);
811 break;
812 case R_028238_CB_TARGET_MASK:
813 track->cb_target_mask = radeon_get_ib_value(p, idx);
814 break;
815 case R_02823C_CB_SHADER_MASK:
816 track->cb_shader_mask = radeon_get_ib_value(p, idx);
817 break;
818 case R_028C04_PA_SC_AA_CONFIG:
819 tmp = G_028C04_MSAA_NUM_SAMPLES(radeon_get_ib_value(p, idx));
820 track->nsamples = 1 << tmp;
821 break;
822 case R_0280A0_CB_COLOR0_INFO:
823 case R_0280A4_CB_COLOR1_INFO:
824 case R_0280A8_CB_COLOR2_INFO:
825 case R_0280AC_CB_COLOR3_INFO:
826 case R_0280B0_CB_COLOR4_INFO:
827 case R_0280B4_CB_COLOR5_INFO:
828 case R_0280B8_CB_COLOR6_INFO:
829 case R_0280BC_CB_COLOR7_INFO:
7f813377
AD		 830 if (r600_cs_packet_next_is_pkt3_nop(p)) {
831 r = r600_cs_packet_next_reloc(p, &reloc);
832 if (r) {
833 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
834 return -EINVAL;
835 }
836 tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4;
837 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
838 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
839 ib[idx] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1);
840 track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1);
841 } else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
842 ib[idx] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1);
843 track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1);
844 }
845 } else {
846 tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4;
847 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
848 }
961fb597
JG		 849 break;
850 case R_028060_CB_COLOR0_SIZE:
851 case R_028064_CB_COLOR1_SIZE:
852 case R_028068_CB_COLOR2_SIZE:
853 case R_02806C_CB_COLOR3_SIZE:
854 case R_028070_CB_COLOR4_SIZE:
855 case R_028074_CB_COLOR5_SIZE:
856 case R_028078_CB_COLOR6_SIZE:
857 case R_02807C_CB_COLOR7_SIZE:
858 tmp = (reg - R_028060_CB_COLOR0_SIZE) / 4;
859 track->cb_color_size[tmp] = radeon_get_ib_value(p, idx);
860 track->cb_color_size_idx[tmp] = idx;
861 break;
862 /* This register were added late, there is userspace
863 * which does provide relocation for those but set
864 * 0 offset. In order to avoid breaking old userspace
865 * we detect this and set address to point to last
866 * CB_COLOR0_BASE, note that if userspace doesn't set
867 * CB_COLOR0_BASE before this register we will report
868 * error. Old userspace always set CB_COLOR0_BASE
869 * before any of this.
870 */
871 case R_0280E0_CB_COLOR0_FRAG:
872 case R_0280E4_CB_COLOR1_FRAG:
873 case R_0280E8_CB_COLOR2_FRAG:
874 case R_0280EC_CB_COLOR3_FRAG:
875 case R_0280F0_CB_COLOR4_FRAG:
876 case R_0280F4_CB_COLOR5_FRAG:
877 case R_0280F8_CB_COLOR6_FRAG:
878 case R_0280FC_CB_COLOR7_FRAG:
879 tmp = (reg - R_0280E0_CB_COLOR0_FRAG) / 4;
880 if (!r600_cs_packet_next_is_pkt3_nop(p)) {
881 if (!track->cb_color_base_last[tmp]) {
882 dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg);
883 return -EINVAL;
884 }
885 ib[idx] = track->cb_color_base_last[tmp];
886 printk_once(KERN_WARNING "You have old & broken userspace "
887 "please consider updating mesa & xf86-video-ati\n");
888 track->cb_color_frag_bo[tmp] = track->cb_color_bo[tmp];
889 } else {
890 r = r600_cs_packet_next_reloc(p, &reloc);
891 if (r) {
892 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
893 return -EINVAL;
894 }
895 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
896 track->cb_color_frag_bo[tmp] = reloc->robj;
897 }
898 break;
899 case R_0280C0_CB_COLOR0_TILE:
900 case R_0280C4_CB_COLOR1_TILE:
901 case R_0280C8_CB_COLOR2_TILE:
902 case R_0280CC_CB_COLOR3_TILE:
903 case R_0280D0_CB_COLOR4_TILE:
904 case R_0280D4_CB_COLOR5_TILE:
905 case R_0280D8_CB_COLOR6_TILE:
906 case R_0280DC_CB_COLOR7_TILE:
907 tmp = (reg - R_0280C0_CB_COLOR0_TILE) / 4;
908 if (!r600_cs_packet_next_is_pkt3_nop(p)) {
909 if (!track->cb_color_base_last[tmp]) {
910 dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg);
911 return -EINVAL;
912 }
913 ib[idx] = track->cb_color_base_last[tmp];
914 printk_once(KERN_WARNING "You have old & broken userspace "
915 "please consider updating mesa & xf86-video-ati\n");
916 track->cb_color_tile_bo[tmp] = track->cb_color_bo[tmp];
917 } else {
918 r = r600_cs_packet_next_reloc(p, &reloc);
919 if (r) {
920 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
921 return -EINVAL;
922 }
923 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
924 track->cb_color_tile_bo[tmp] = reloc->robj;
925 }
926 break;
927 case CB_COLOR0_BASE:
928 case CB_COLOR1_BASE:
929 case CB_COLOR2_BASE:
930 case CB_COLOR3_BASE:
931 case CB_COLOR4_BASE:
932 case CB_COLOR5_BASE:
933 case CB_COLOR6_BASE:
934 case CB_COLOR7_BASE:
935 r = r600_cs_packet_next_reloc(p, &reloc);
936 if (r) {
937 dev_warn(p->dev, "bad SET_CONTEXT_REG "
938 "0x%04X\n", reg);
939 return -EINVAL;
940 }
7cb72ef4 941 tmp = (reg - CB_COLOR0_BASE) / 4;
961fb597
JG		 942 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx);
943 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
961fb597
JG		 944 track->cb_color_base_last[tmp] = ib[idx];
945 track->cb_color_bo[tmp] = reloc->robj;
946 break;
947 case DB_DEPTH_BASE:
948 r = r600_cs_packet_next_reloc(p, &reloc);
949 if (r) {
950 dev_warn(p->dev, "bad SET_CONTEXT_REG "
951 "0x%04X\n", reg);
952 return -EINVAL;
953 }
954 track->db_offset = radeon_get_ib_value(p, idx);
955 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
956 track->db_bo = reloc->robj;
957 break;
958 case DB_HTILE_DATA_BASE:
959 case SQ_PGM_START_FS:
960 case SQ_PGM_START_ES:
961 case SQ_PGM_START_VS:
962 case SQ_PGM_START_GS:
963 case SQ_PGM_START_PS:
5f77df36
AD		 964 case SQ_ALU_CONST_CACHE_GS_0:
965 case SQ_ALU_CONST_CACHE_GS_1:
966 case SQ_ALU_CONST_CACHE_GS_2:
967 case SQ_ALU_CONST_CACHE_GS_3:
968 case SQ_ALU_CONST_CACHE_GS_4:
969 case SQ_ALU_CONST_CACHE_GS_5:
970 case SQ_ALU_CONST_CACHE_GS_6:
971 case SQ_ALU_CONST_CACHE_GS_7:
972 case SQ_ALU_CONST_CACHE_GS_8:
973 case SQ_ALU_CONST_CACHE_GS_9:
974 case SQ_ALU_CONST_CACHE_GS_10:
975 case SQ_ALU_CONST_CACHE_GS_11:
976 case SQ_ALU_CONST_CACHE_GS_12:
977 case SQ_ALU_CONST_CACHE_GS_13:
978 case SQ_ALU_CONST_CACHE_GS_14:
979 case SQ_ALU_CONST_CACHE_GS_15:
980 case SQ_ALU_CONST_CACHE_PS_0:
981 case SQ_ALU_CONST_CACHE_PS_1:
982 case SQ_ALU_CONST_CACHE_PS_2:
983 case SQ_ALU_CONST_CACHE_PS_3:
984 case SQ_ALU_CONST_CACHE_PS_4:
985 case SQ_ALU_CONST_CACHE_PS_5:
986 case SQ_ALU_CONST_CACHE_PS_6:
987 case SQ_ALU_CONST_CACHE_PS_7:
988 case SQ_ALU_CONST_CACHE_PS_8:
989 case SQ_ALU_CONST_CACHE_PS_9:
990 case SQ_ALU_CONST_CACHE_PS_10:
991 case SQ_ALU_CONST_CACHE_PS_11:
992 case SQ_ALU_CONST_CACHE_PS_12:
993 case SQ_ALU_CONST_CACHE_PS_13:
994 case SQ_ALU_CONST_CACHE_PS_14:
995 case SQ_ALU_CONST_CACHE_PS_15:
996 case SQ_ALU_CONST_CACHE_VS_0:
997 case SQ_ALU_CONST_CACHE_VS_1:
998 case SQ_ALU_CONST_CACHE_VS_2:
999 case SQ_ALU_CONST_CACHE_VS_3:
1000 case SQ_ALU_CONST_CACHE_VS_4:
1001 case SQ_ALU_CONST_CACHE_VS_5:
1002 case SQ_ALU_CONST_CACHE_VS_6:
1003 case SQ_ALU_CONST_CACHE_VS_7:
1004 case SQ_ALU_CONST_CACHE_VS_8:
1005 case SQ_ALU_CONST_CACHE_VS_9:
1006 case SQ_ALU_CONST_CACHE_VS_10:
1007 case SQ_ALU_CONST_CACHE_VS_11:
1008 case SQ_ALU_CONST_CACHE_VS_12:
1009 case SQ_ALU_CONST_CACHE_VS_13:
1010 case SQ_ALU_CONST_CACHE_VS_14:
1011 case SQ_ALU_CONST_CACHE_VS_15:
961fb597
JG		 1012 r = r600_cs_packet_next_reloc(p, &reloc);
1013 if (r) {
1014 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1015 "0x%04X\n", reg);
1016 return -EINVAL;
1017 }
1018 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1019 break;
1020 default:
1021 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
1022 return -EINVAL;
1023 }
1024 return 0;
1025}
1026
1027static inline unsigned minify(unsigned size, unsigned levels)
1028{
1029 size = size >> levels;
1030 if (size < 1)
1031 size = 1;
1032 return size;
1033}
1034
1035static void r600_texture_size(unsigned nfaces, unsigned blevel, unsigned nlevels,
40e2a5c1
AD		 1036 unsigned w0, unsigned h0, unsigned d0, unsigned bpe,
1037 unsigned pitch_align,
1038 unsigned *l0_size, unsigned *mipmap_size)
961fb597
JG		 1039{
1040 unsigned offset, i, level, face;
1041 unsigned width, height, depth, rowstride, size;
1042
1043 w0 = minify(w0, 0);
1044 h0 = minify(h0, 0);
1045 d0 = minify(d0, 0);
1046 for(i = 0, offset = 0, level = blevel; i < nlevels; i++, level++) {
1047 width = minify(w0, i);
1048 height = minify(h0, i);
1049 depth = minify(d0, i);
1050 for(face = 0; face < nfaces; face++) {
40e2a5c1 1051 rowstride = ALIGN((width * bpe), pitch_align);
961fb597
JG		 1052 size = height * rowstride * depth;
1053 offset += size;
1054 offset = (offset + 0x1f) & ~0x1f;
1055 }
1056 }
40e2a5c1 1057 *l0_size = ALIGN((w0 * bpe), pitch_align) * h0 * d0;
961fb597
JG		 1058 *mipmap_size = offset;
1059 if (!blevel)
1060 *mipmap_size -= *l0_size;
1061 if (!nlevels)
1062 *mipmap_size = *l0_size;
1063}
1064
1065/**
1066 * r600_check_texture_resource() - check if register is authorized or not
1067 * @p: parser structure holding parsing context
1068 * @idx: index into the cs buffer
1069 * @texture: texture's bo structure
1070 * @mipmap: mipmap's bo structure
1071 *
1072 * This function will check that the resource has valid field and that
1073 * the texture and mipmap bo object are big enough to cover this resource.
1074 */
1075static inline int r600_check_texture_resource(struct radeon_cs_parser *p, u32 idx,
7f813377
AD		 1076 struct radeon_bo *texture,
1077 struct radeon_bo *mipmap,
1078 u32 tiling_flags)
961fb597 1079{
40e2a5c1 1080 struct r600_cs_track *track = p->track;
71b10d87 1081 u32 nfaces, nlevels, blevel, w0, h0, d0, bpe = 0;
40e2a5c1 1082 u32 word0, word1, l0_size, mipmap_size, pitch, pitch_align;
961fb597
JG		 1083
1084 /* on legacy kernel we don't perform advanced check */
1085 if (p->rdev == NULL)
1086 return 0;
7f813377 1087
961fb597 1088 word0 = radeon_get_ib_value(p, idx + 0);
7f813377
AD		 1089 if (tiling_flags & RADEON_TILING_MACRO)
1090 word0 |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1);
1091 else if (tiling_flags & RADEON_TILING_MICRO)
1092 word0 |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1);
961fb597
JG		 1093 word1 = radeon_get_ib_value(p, idx + 1);
1094 w0 = G_038000_TEX_WIDTH(word0) + 1;
1095 h0 = G_038004_TEX_HEIGHT(word1) + 1;
1096 d0 = G_038004_TEX_DEPTH(word1);
1097 nfaces = 1;
1098 switch (G_038000_DIM(word0)) {
1099 case V_038000_SQ_TEX_DIM_1D:
1100 case V_038000_SQ_TEX_DIM_2D:
1101 case V_038000_SQ_TEX_DIM_3D:
1102 break;
1103 case V_038000_SQ_TEX_DIM_CUBEMAP:
1104 nfaces = 6;
1105 break;
1106 case V_038000_SQ_TEX_DIM_1D_ARRAY:
1107 case V_038000_SQ_TEX_DIM_2D_ARRAY:
1108 case V_038000_SQ_TEX_DIM_2D_MSAA:
1109 case V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA:
1110 default:
1111 dev_warn(p->dev, "this kernel doesn't support %d texture dim\n", G_038000_DIM(word0));
1112 return -EINVAL;
1113 }
1114 if (r600_bpe_from_format(&bpe, G_038004_DATA_FORMAT(word1))) {
1115 dev_warn(p->dev, "%s:%d texture invalid format %d\n",
1116 __func__, __LINE__, G_038004_DATA_FORMAT(word1));
1117 return -EINVAL;
1118 }
40e2a5c1
AD		 1119
1120 pitch = G_038000_PITCH(word0) + 1;
1121 switch (G_038000_TILE_MODE(word0)) {
1122 case V_038000_ARRAY_LINEAR_GENERAL:
1123 pitch_align = 1;
1124 /* XXX check height align */
1125 break;
1126 case V_038000_ARRAY_LINEAR_ALIGNED:
1127 pitch_align = max((u32)64, (u32)(track->group_size / bpe)) / 8;
1128 if (!IS_ALIGNED(pitch, pitch_align)) {
1129 dev_warn(p->dev, "%s:%d tex pitch (%d) invalid\n",
1130 __func__, __LINE__, pitch);
1131 return -EINVAL;
1132 }
1133 /* XXX check height align */
1134 break;
1135 case V_038000_ARRAY_1D_TILED_THIN1:
1136 pitch_align = max((u32)8, (u32)(track->group_size / (8 * bpe))) / 8;
1137 if (!IS_ALIGNED(pitch, pitch_align)) {
1138 dev_warn(p->dev, "%s:%d tex pitch (%d) invalid\n",
1139 __func__, __LINE__, pitch);
1140 return -EINVAL;
1141 }
1142 /* XXX check height align */
1143 break;
1144 case V_038000_ARRAY_2D_TILED_THIN1:
1145 pitch_align = max((u32)track->nbanks,
1146 (u32)(((track->group_size / 8) / bpe) * track->nbanks));
1147 if (!IS_ALIGNED(pitch, pitch_align)) {
1148 dev_warn(p->dev, "%s:%d tex pitch (%d) invalid\n",
1149 __func__, __LINE__, pitch);
1150 return -EINVAL;
1151 }
1152 /* XXX check height align */
1153 break;
1154 default:
1155 dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__,
1156 G_038000_TILE_MODE(word0), word0);
1157 return -EINVAL;
1158 }
1159 /* XXX check offset align */
1160
961fb597
JG		 1161 word0 = radeon_get_ib_value(p, idx + 4);
1162 word1 = radeon_get_ib_value(p, idx + 5);
1163 blevel = G_038010_BASE_LEVEL(word0);
1164 nlevels = G_038014_LAST_LEVEL(word1);
40e2a5c1
AD		 1165 r600_texture_size(nfaces, blevel, nlevels, w0, h0, d0, bpe,
1166 (pitch_align * bpe),
1167 &l0_size, &mipmap_size);
961fb597
JG		 1168 /* using get ib will give us the offset into the texture bo */
1169 word0 = radeon_get_ib_value(p, idx + 2);
1170 if ((l0_size + word0) > radeon_bo_size(texture)) {
1171 dev_warn(p->dev, "texture bo too small (%d %d %d %d -> %d have %ld)\n",
1172 w0, h0, bpe, word0, l0_size, radeon_bo_size(texture));
1173 return -EINVAL;
1174 }
1175 /* using get ib will give us the offset into the mipmap bo */
1176 word0 = radeon_get_ib_value(p, idx + 3);
1177 if ((mipmap_size + word0) > radeon_bo_size(mipmap)) {
1178 dev_warn(p->dev, "mipmap bo too small (%d %d %d %d %d %d -> %d have %ld)\n",
1179 w0, h0, bpe, blevel, nlevels, word0, mipmap_size, radeon_bo_size(texture));
1180 return -EINVAL;
1181 }
1182 return 0;
1183}
1184
3ce0a23d
JG		 1185static int r600_packet3_check(struct radeon_cs_parser *p,
1186 struct radeon_cs_packet *pkt)
1187{
3ce0a23d 1188 struct radeon_cs_reloc *reloc;
c8c15ff1 1189 struct r600_cs_track *track;
3ce0a23d
JG		 1190 volatile u32 *ib;
1191 unsigned idx;
1192 unsigned i;
1193 unsigned start_reg, end_reg, reg;
1194 int r;
adea4796 1195 u32 idx_value;
3ce0a23d 1196
c8c15ff1 1197 track = (struct r600_cs_track *)p->track;
3ce0a23d 1198 ib = p->ib->ptr;
3ce0a23d 1199 idx = pkt->idx + 1;
adea4796 1200 idx_value = radeon_get_ib_value(p, idx);
513bcb46 1201
3ce0a23d
JG		 1202 switch (pkt->opcode) {
1203 case PACKET3_START_3D_CMDBUF:
1204 if (p->family >= CHIP_RV770 || pkt->count) {
1205 DRM_ERROR("bad START_3D\n");
1206 return -EINVAL;
1207 }
1208 break;
1209 case PACKET3_CONTEXT_CONTROL:
1210 if (pkt->count != 1) {
1211 DRM_ERROR("bad CONTEXT_CONTROL\n");
1212 return -EINVAL;
1213 }
1214 break;
1215 case PACKET3_INDEX_TYPE:
1216 case PACKET3_NUM_INSTANCES:
1217 if (pkt->count) {
1218 DRM_ERROR("bad INDEX_TYPE/NUM_INSTANCES\n");
1219 return -EINVAL;
1220 }
1221 break;
1222 case PACKET3_DRAW_INDEX:
1223 if (pkt->count != 3) {
1224 DRM_ERROR("bad DRAW_INDEX\n");
1225 return -EINVAL;
1226 }
1227 r = r600_cs_packet_next_reloc(p, &reloc);
1228 if (r) {
1229 DRM_ERROR("bad DRAW_INDEX\n");
1230 return -EINVAL;
1231 }
adea4796 1232 ib[idx+0] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff);
210bed8f 1233 ib[idx+1] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
961fb597
JG		 1234 r = r600_cs_track_check(p);
1235 if (r) {
1236 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1237 return r;
1238 }
3ce0a23d
JG		 1239 break;
1240 case PACKET3_DRAW_INDEX_AUTO:
1241 if (pkt->count != 1) {
1242 DRM_ERROR("bad DRAW_INDEX_AUTO\n");
1243 return -EINVAL;
1244 }
961fb597
JG		 1245 r = r600_cs_track_check(p);
1246 if (r) {
1247 dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx);
1248 return r;
1249 }
3ce0a23d
JG		 1250 break;
1251 case PACKET3_DRAW_INDEX_IMMD_BE:
1252 case PACKET3_DRAW_INDEX_IMMD:
1253 if (pkt->count < 2) {
1254 DRM_ERROR("bad DRAW_INDEX_IMMD\n");
1255 return -EINVAL;
1256 }
961fb597
JG		 1257 r = r600_cs_track_check(p);
1258 if (r) {
1259 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1260 return r;
1261 }
3ce0a23d
JG		 1262 break;
1263 case PACKET3_WAIT_REG_MEM:
1264 if (pkt->count != 5) {
1265 DRM_ERROR("bad WAIT_REG_MEM\n");
1266 return -EINVAL;
1267 }
1268 /* bit 4 is reg (0) or mem (1) */
adea4796 1269 if (idx_value & 0x10) {
3ce0a23d
JG		 1270 r = r600_cs_packet_next_reloc(p, &reloc);
1271 if (r) {
1272 DRM_ERROR("bad WAIT_REG_MEM\n");
1273 return -EINVAL;
1274 }
1275 ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
210bed8f 1276 ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
3ce0a23d
JG		 1277 }
1278 break;
1279 case PACKET3_SURFACE_SYNC:
1280 if (pkt->count != 3) {
1281 DRM_ERROR("bad SURFACE_SYNC\n");
1282 return -EINVAL;
1283 }
1284 /* 0xffffffff/0x0 is flush all cache flag */
513bcb46
DA		 1285 if (radeon_get_ib_value(p, idx + 1) != 0xffffffff ||
1286 radeon_get_ib_value(p, idx + 2) != 0) {
3ce0a23d
JG		 1287 r = r600_cs_packet_next_reloc(p, &reloc);
1288 if (r) {
1289 DRM_ERROR("bad SURFACE_SYNC\n");
1290 return -EINVAL;
1291 }
1292 ib[idx+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1293 }
1294 break;
1295 case PACKET3_EVENT_WRITE:
1296 if (pkt->count != 2 && pkt->count != 0) {
1297 DRM_ERROR("bad EVENT_WRITE\n");
1298 return -EINVAL;
1299 }
1300 if (pkt->count) {
1301 r = r600_cs_packet_next_reloc(p, &reloc);
1302 if (r) {
1303 DRM_ERROR("bad EVENT_WRITE\n");
1304 return -EINVAL;
1305 }
1306 ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
210bed8f 1307 ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
3ce0a23d
JG		 1308 }
1309 break;
1310 case PACKET3_EVENT_WRITE_EOP:
1311 if (pkt->count != 4) {
1312 DRM_ERROR("bad EVENT_WRITE_EOP\n");
1313 return -EINVAL;
1314 }
1315 r = r600_cs_packet_next_reloc(p, &reloc);
1316 if (r) {
1317 DRM_ERROR("bad EVENT_WRITE\n");
1318 return -EINVAL;
1319 }
1320 ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
210bed8f 1321 ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
3ce0a23d
JG		 1322 break;
1323 case PACKET3_SET_CONFIG_REG:
adea4796 1324 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_OFFSET;
3ce0a23d
JG		 1325 end_reg = 4 * pkt->count + start_reg - 4;
1326 if ((start_reg < PACKET3_SET_CONFIG_REG_OFFSET) ||
1327 (start_reg >= PACKET3_SET_CONFIG_REG_END) ||
1328 (end_reg >= PACKET3_SET_CONFIG_REG_END)) {
1329 DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n");
1330 return -EINVAL;
1331 }
1332 for (i = 0; i < pkt->count; i++) {
1333 reg = start_reg + (4 * i);
961fb597
JG		 1334 r = r600_cs_check_reg(p, reg, idx+1+i);
1335 if (r)
1336 return r;
3ce0a23d
JG		 1337 }
1338 break;
1339 case PACKET3_SET_CONTEXT_REG:
adea4796 1340 start_reg = (idx_value << 2) + PACKET3_SET_CONTEXT_REG_OFFSET;
3ce0a23d
JG		 1341 end_reg = 4 * pkt->count + start_reg - 4;
1342 if ((start_reg < PACKET3_SET_CONTEXT_REG_OFFSET) ||
1343 (start_reg >= PACKET3_SET_CONTEXT_REG_END) ||
1344 (end_reg >= PACKET3_SET_CONTEXT_REG_END)) {
1345 DRM_ERROR("bad PACKET3_SET_CONTEXT_REG\n");
1346 return -EINVAL;
1347 }
1348 for (i = 0; i < pkt->count; i++) {
1349 reg = start_reg + (4 * i);
961fb597
JG		 1350 r = r600_cs_check_reg(p, reg, idx+1+i);
1351 if (r)
1352 return r;
3ce0a23d
JG		 1353 }
1354 break;
1355 case PACKET3_SET_RESOURCE:
1356 if (pkt->count % 7) {
1357 DRM_ERROR("bad SET_RESOURCE\n");
1358 return -EINVAL;
1359 }
adea4796 1360 start_reg = (idx_value << 2) + PACKET3_SET_RESOURCE_OFFSET;
3ce0a23d
JG		 1361 end_reg = 4 * pkt->count + start_reg - 4;
1362 if ((start_reg < PACKET3_SET_RESOURCE_OFFSET) ||
1363 (start_reg >= PACKET3_SET_RESOURCE_END) ||
1364 (end_reg >= PACKET3_SET_RESOURCE_END)) {
1365 DRM_ERROR("bad SET_RESOURCE\n");
1366 return -EINVAL;
1367 }
1368 for (i = 0; i < (pkt->count / 7); i++) {
961fb597
JG		 1369 struct radeon_bo *texture, *mipmap;
1370 u32 size, offset;
1371
adea4796 1372 switch (G__SQ_VTX_CONSTANT_TYPE(radeon_get_ib_value(p, idx+(i*7)+6+1))) {
3ce0a23d
JG		 1373 case SQ_TEX_VTX_VALID_TEXTURE:
1374 /* tex base */
1375 r = r600_cs_packet_next_reloc(p, &reloc);
1376 if (r) {
1377 DRM_ERROR("bad SET_RESOURCE\n");
1378 return -EINVAL;
1379 }
1380 ib[idx+1+(i*7)+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
7f813377
AD		 1381 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1382 ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1);
1383 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1384 ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1);
961fb597 1385 texture = reloc->robj;
3ce0a23d
JG		 1386 /* tex mip base */
1387 r = r600_cs_packet_next_reloc(p, &reloc);
1388 if (r) {
1389 DRM_ERROR("bad SET_RESOURCE\n");
1390 return -EINVAL;
1391 }
1392 ib[idx+1+(i*7)+3] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
961fb597
JG		 1393 mipmap = reloc->robj;
1394 r = r600_check_texture_resource(p, idx+(i*7)+1,
7f813377 1395 texture, mipmap, reloc->lobj.tiling_flags);
961fb597
JG		 1396 if (r)
1397 return r;
3ce0a23d
JG		 1398 break;
1399 case SQ_TEX_VTX_VALID_BUFFER:
1400 /* vtx base */
1401 r = r600_cs_packet_next_reloc(p, &reloc);
1402 if (r) {
1403 DRM_ERROR("bad SET_RESOURCE\n");
1404 return -EINVAL;
1405 }
961fb597
JG		 1406 offset = radeon_get_ib_value(p, idx+1+(i*7)+0);
1407 size = radeon_get_ib_value(p, idx+1+(i*7)+1);
1408 if (p->rdev && (size + offset) > radeon_bo_size(reloc->robj)) {
1409 /* force size to size of the buffer */
1410 dev_warn(p->dev, "vbo resource seems too big for the bo\n");
1411 ib[idx+1+(i*7)+1] = radeon_bo_size(reloc->robj);
1412 }
3ce0a23d 1413 ib[idx+1+(i*7)+0] += (u32)((reloc->lobj.gpu_offset) & 0xffffffff);
210bed8f 1414 ib[idx+1+(i*7)+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
3ce0a23d
JG		 1415 break;
1416 case SQ_TEX_VTX_INVALID_TEXTURE:
1417 case SQ_TEX_VTX_INVALID_BUFFER:
1418 default:
1419 DRM_ERROR("bad SET_RESOURCE\n");
1420 return -EINVAL;
1421 }
1422 }
1423 break;
1424 case PACKET3_SET_ALU_CONST:
5f77df36
AD		 1425 if (track->sq_config & DX9_CONSTS) {
1426 start_reg = (idx_value << 2) + PACKET3_SET_ALU_CONST_OFFSET;
1427 end_reg = 4 * pkt->count + start_reg - 4;
1428 if ((start_reg < PACKET3_SET_ALU_CONST_OFFSET) ||
1429 (start_reg >= PACKET3_SET_ALU_CONST_END) ||
1430 (end_reg >= PACKET3_SET_ALU_CONST_END)) {
1431 DRM_ERROR("bad SET_ALU_CONST\n");
1432 return -EINVAL;
1433 }
3ce0a23d
JG		 1434 }
1435 break;
1436 case PACKET3_SET_BOOL_CONST:
adea4796 1437 start_reg = (idx_value << 2) + PACKET3_SET_BOOL_CONST_OFFSET;
3ce0a23d
JG		 1438 end_reg = 4 * pkt->count + start_reg - 4;
1439 if ((start_reg < PACKET3_SET_BOOL_CONST_OFFSET) ||
1440 (start_reg >= PACKET3_SET_BOOL_CONST_END) ||
1441 (end_reg >= PACKET3_SET_BOOL_CONST_END)) {
1442 DRM_ERROR("bad SET_BOOL_CONST\n");
1443 return -EINVAL;
1444 }
1445 break;
1446 case PACKET3_SET_LOOP_CONST:
adea4796 1447 start_reg = (idx_value << 2) + PACKET3_SET_LOOP_CONST_OFFSET;
3ce0a23d
JG		 1448 end_reg = 4 * pkt->count + start_reg - 4;
1449 if ((start_reg < PACKET3_SET_LOOP_CONST_OFFSET) ||
1450 (start_reg >= PACKET3_SET_LOOP_CONST_END) ||
1451 (end_reg >= PACKET3_SET_LOOP_CONST_END)) {
1452 DRM_ERROR("bad SET_LOOP_CONST\n");
1453 return -EINVAL;
1454 }
1455 break;
1456 case PACKET3_SET_CTL_CONST:
adea4796 1457 start_reg = (idx_value << 2) + PACKET3_SET_CTL_CONST_OFFSET;
3ce0a23d
JG		 1458 end_reg = 4 * pkt->count + start_reg - 4;
1459 if ((start_reg < PACKET3_SET_CTL_CONST_OFFSET) ||
1460 (start_reg >= PACKET3_SET_CTL_CONST_END) ||
1461 (end_reg >= PACKET3_SET_CTL_CONST_END)) {
1462 DRM_ERROR("bad SET_CTL_CONST\n");
1463 return -EINVAL;
1464 }
1465 break;
1466 case PACKET3_SET_SAMPLER:
1467 if (pkt->count % 3) {
1468 DRM_ERROR("bad SET_SAMPLER\n");
1469 return -EINVAL;
1470 }
adea4796 1471 start_reg = (idx_value << 2) + PACKET3_SET_SAMPLER_OFFSET;
3ce0a23d
JG		 1472 end_reg = 4 * pkt->count + start_reg - 4;
1473 if ((start_reg < PACKET3_SET_SAMPLER_OFFSET) ||
1474 (start_reg >= PACKET3_SET_SAMPLER_END) ||
1475 (end_reg >= PACKET3_SET_SAMPLER_END)) {
1476 DRM_ERROR("bad SET_SAMPLER\n");
1477 return -EINVAL;
1478 }
1479 break;
1480 case PACKET3_SURFACE_BASE_UPDATE:
1481 if (p->family >= CHIP_RV770 || p->family == CHIP_R600) {
1482 DRM_ERROR("bad SURFACE_BASE_UPDATE\n");
1483 return -EINVAL;
1484 }
1485 if (pkt->count) {
1486 DRM_ERROR("bad SURFACE_BASE_UPDATE\n");
1487 return -EINVAL;
1488 }
1489 break;
1490 case PACKET3_NOP:
1491 break;
1492 default:
1493 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1494 return -EINVAL;
1495 }
1496 return 0;
1497}
1498
1499int r600_cs_parse(struct radeon_cs_parser *p)
1500{
1501 struct radeon_cs_packet pkt;
c8c15ff1 1502 struct r600_cs_track *track;
3ce0a23d
JG		 1503 int r;
1504
961fb597
JG		 1505 if (p->track == NULL) {
1506 /* initialize tracker, we are in kms */
1507 track = kzalloc(sizeof(*track), GFP_KERNEL);
1508 if (track == NULL)
1509 return -ENOMEM;
1510 r600_cs_track_init(track);
1511 if (p->rdev->family < CHIP_RV770) {
1512 track->npipes = p->rdev->config.r600.tiling_npipes;
1513 track->nbanks = p->rdev->config.r600.tiling_nbanks;
1514 track->group_size = p->rdev->config.r600.tiling_group_size;
1515 } else if (p->rdev->family <= CHIP_RV740) {
1516 track->npipes = p->rdev->config.rv770.tiling_npipes;
1517 track->nbanks = p->rdev->config.rv770.tiling_nbanks;
1518 track->group_size = p->rdev->config.rv770.tiling_group_size;
1519 }
1520 p->track = track;
1521 }
3ce0a23d
JG		 1522 do {
1523 r = r600_cs_packet_parse(p, &pkt, p->idx);
1524 if (r) {
7cb72ef4
JG		 1525 kfree(p->track);
1526 p->track = NULL;
3ce0a23d
JG		 1527 return r;
1528 }
1529 p->idx += pkt.count + 2;
1530 switch (pkt.type) {
1531 case PACKET_TYPE0:
1532 r = r600_cs_parse_packet0(p, &pkt);
1533 break;
1534 case PACKET_TYPE2:
1535 break;
1536 case PACKET_TYPE3:
1537 r = r600_packet3_check(p, &pkt);
1538 break;
1539 default:
1540 DRM_ERROR("Unknown packet type %d !\n", pkt.type);
961fb597 1541 kfree(p->track);
7cb72ef4 1542 p->track = NULL;
3ce0a23d
JG		 1543 return -EINVAL;
1544 }
1545 if (r) {
961fb597 1546 kfree(p->track);
7cb72ef4 1547 p->track = NULL;
3ce0a23d
JG		 1548 return r;
1549 }
1550 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1551#if 0
1552 for (r = 0; r < p->ib->length_dw; r++) {
1553 printk(KERN_INFO "%05d 0x%08X\n", r, p->ib->ptr[r]);
1554 mdelay(1);
1555 }
1556#endif
961fb597 1557 kfree(p->track);
7cb72ef4 1558 p->track = NULL;
3ce0a23d
JG		 1559 return 0;
1560}
1561
1562static int r600_cs_parser_relocs_legacy(struct radeon_cs_parser *p)
1563{
1564 if (p->chunk_relocs_idx == -1) {
1565 return 0;
1566 }
e265f39e 1567 p->relocs = kzalloc(sizeof(struct radeon_cs_reloc), GFP_KERNEL);
3ce0a23d
JG		 1568 if (p->relocs == NULL) {
1569 return -ENOMEM;
1570 }
1571 return 0;
1572}
1573
1574/**
1575 * cs_parser_fini() - clean parser states
1576 * @parser: parser structure holding parsing context.
1577 * @error: error number
1578 *
1579 * If error is set than unvalidate buffer, otherwise just free memory
1580 * used by parsing context.
1581 **/
1582static void r600_cs_parser_fini(struct radeon_cs_parser *parser, int error)
1583{
1584 unsigned i;
1585
1586 kfree(parser->relocs);
1587 for (i = 0; i < parser->nchunks; i++) {
1588 kfree(parser->chunks[i].kdata);
4c57edba
DA		 1589 kfree(parser->chunks[i].kpage[0]);
1590 kfree(parser->chunks[i].kpage[1]);
3ce0a23d
JG		 1591 }
1592 kfree(parser->chunks);
1593 kfree(parser->chunks_array);
1594}
1595
1596int r600_cs_legacy(struct drm_device *dev, void *data, struct drm_file *filp,
1597 unsigned family, u32 *ib, int *l)
1598{
1599 struct radeon_cs_parser parser;
1600 struct radeon_cs_chunk *ib_chunk;
961fb597
JG		 1601 struct radeon_ib fake_ib;
1602 struct r600_cs_track *track;
3ce0a23d
JG		 1603 int r;
1604
961fb597
JG		 1605 /* initialize tracker */
1606 track = kzalloc(sizeof(*track), GFP_KERNEL);
1607 if (track == NULL)
1608 return -ENOMEM;
1609 r600_cs_track_init(track);
1610 r600_cs_legacy_get_tiling_conf(dev, &track->npipes, &track->nbanks, &track->group_size);
3ce0a23d
JG		 1611 /* initialize parser */
1612 memset(&parser, 0, sizeof(struct radeon_cs_parser));
1613 parser.filp = filp;
c8c15ff1 1614 parser.dev = &dev->pdev->dev;
3ce0a23d
JG		 1615 parser.rdev = NULL;
1616 parser.family = family;
1617 parser.ib = &fake_ib;
961fb597 1618 parser.track = track;
3ce0a23d
JG		 1619 fake_ib.ptr = ib;
1620 r = radeon_cs_parser_init(&parser, data);
1621 if (r) {
1622 DRM_ERROR("Failed to initialize parser !\n");
1623 r600_cs_parser_fini(&parser, r);
1624 return r;
1625 }
1626 r = r600_cs_parser_relocs_legacy(&parser);
1627 if (r) {
1628 DRM_ERROR("Failed to parse relocation !\n");
1629 r600_cs_parser_fini(&parser, r);
1630 return r;
1631 }
1632 /* Copy the packet into the IB, the parser will read from the
1633 * input memory (cached) and write to the IB (which can be
1634 * uncached). */
1635 ib_chunk = &parser.chunks[parser.chunk_ib_idx];
1636 parser.ib->length_dw = ib_chunk->length_dw;
3ce0a23d
JG		 1637 *l = parser.ib->length_dw;
1638 r = r600_cs_parse(&parser);
1639 if (r) {
1640 DRM_ERROR("Invalid command stream !\n");
1641 r600_cs_parser_fini(&parser, r);
1642 return r;
1643 }
513bcb46
DA		 1644 r = radeon_cs_finish_pages(&parser);
1645 if (r) {
1646 DRM_ERROR("Invalid command stream !\n");
1647 r600_cs_parser_fini(&parser, r);
1648 return r;
1649 }
3ce0a23d
JG		 1650 r600_cs_parser_fini(&parser, r);
1651 return r;
1652}
1653
1654void r600_cs_legacy_init(void)
1655{
1656 r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_nomm;
1657}
Clone of davem's net-next-2.6 tree