]> bbs.cooldavid.org Git - net-next-2.6.git/blame - drivers/gpu/drm/radeon/r600_cp.c
git://bbs.cooldavid.org / net-next-2.6.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/radeon/kms: r600/r700 command stream checker
[net-next-2.6.git] / drivers / gpu / drm / radeon / r600_cp.c
CommitLineData
c05ce083
AD		 1/*
2 * Copyright 2008-2009 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Dave Airlie <airlied@redhat.com>
26 * Alex Deucher <alexander.deucher@amd.com>
27 */
28
29#include "drmP.h"
30#include "drm.h"
31#include "radeon_drm.h"
32#include "radeon_drv.h"
33
70967ab9
BH		 34#define PFP_UCODE_SIZE 576
35#define PM4_UCODE_SIZE 1792
36#define R700_PFP_UCODE_SIZE 848
37#define R700_PM4_UCODE_SIZE 1360
38
39/* Firmware Names */
40MODULE_FIRMWARE("radeon/R600_pfp.bin");
41MODULE_FIRMWARE("radeon/R600_me.bin");
42MODULE_FIRMWARE("radeon/RV610_pfp.bin");
43MODULE_FIRMWARE("radeon/RV610_me.bin");
44MODULE_FIRMWARE("radeon/RV630_pfp.bin");
45MODULE_FIRMWARE("radeon/RV630_me.bin");
46MODULE_FIRMWARE("radeon/RV620_pfp.bin");
47MODULE_FIRMWARE("radeon/RV620_me.bin");
48MODULE_FIRMWARE("radeon/RV635_pfp.bin");
49MODULE_FIRMWARE("radeon/RV635_me.bin");
50MODULE_FIRMWARE("radeon/RV670_pfp.bin");
51MODULE_FIRMWARE("radeon/RV670_me.bin");
52MODULE_FIRMWARE("radeon/RS780_pfp.bin");
53MODULE_FIRMWARE("radeon/RS780_me.bin");
54MODULE_FIRMWARE("radeon/RV770_pfp.bin");
55MODULE_FIRMWARE("radeon/RV770_me.bin");
56MODULE_FIRMWARE("radeon/RV730_pfp.bin");
57MODULE_FIRMWARE("radeon/RV730_me.bin");
58MODULE_FIRMWARE("radeon/RV710_pfp.bin");
59MODULE_FIRMWARE("radeon/RV710_me.bin");
c05ce083 60
3ce0a23d
JG		 61
62int r600_cs_legacy(struct drm_device *dev, void *data, struct drm_file *filp,
63 unsigned family, u32 *ib, int *l);
64void r600_cs_legacy_init(void);
65
66
c05ce083
AD		 67# define ATI_PCIGART_PAGE_SIZE 4096 /**< PCI GART page size */
68# define ATI_PCIGART_PAGE_MASK (~(ATI_PCIGART_PAGE_SIZE-1))
69
70#define R600_PTE_VALID (1 << 0)
71#define R600_PTE_SYSTEM (1 << 1)
72#define R600_PTE_SNOOPED (1 << 2)
73#define R600_PTE_READABLE (1 << 5)
74#define R600_PTE_WRITEABLE (1 << 6)
75
76/* MAX values used for gfx init */
77#define R6XX_MAX_SH_GPRS 256
78#define R6XX_MAX_TEMP_GPRS 16
79#define R6XX_MAX_SH_THREADS 256
80#define R6XX_MAX_SH_STACK_ENTRIES 4096
81#define R6XX_MAX_BACKENDS 8
82#define R6XX_MAX_BACKENDS_MASK 0xff
83#define R6XX_MAX_SIMDS 8
84#define R6XX_MAX_SIMDS_MASK 0xff
85#define R6XX_MAX_PIPES 8
86#define R6XX_MAX_PIPES_MASK 0xff
87
88#define R7XX_MAX_SH_GPRS 256
89#define R7XX_MAX_TEMP_GPRS 16
90#define R7XX_MAX_SH_THREADS 256
91#define R7XX_MAX_SH_STACK_ENTRIES 4096
92#define R7XX_MAX_BACKENDS 8
93#define R7XX_MAX_BACKENDS_MASK 0xff
94#define R7XX_MAX_SIMDS 16
95#define R7XX_MAX_SIMDS_MASK 0xffff
96#define R7XX_MAX_PIPES 8
97#define R7XX_MAX_PIPES_MASK 0xff
98
99static int r600_do_wait_for_fifo(drm_radeon_private_t *dev_priv, int entries)
100{
101 int i;
102
103 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
104
105 for (i = 0; i < dev_priv->usec_timeout; i++) {
106 int slots;
107 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
108 slots = (RADEON_READ(R600_GRBM_STATUS)
109 & R700_CMDFIFO_AVAIL_MASK);
110 else
111 slots = (RADEON_READ(R600_GRBM_STATUS)
112 & R600_CMDFIFO_AVAIL_MASK);
113 if (slots >= entries)
114 return 0;
115 DRM_UDELAY(1);
116 }
117 DRM_INFO("wait for fifo failed status : 0x%08X 0x%08X\n",
118 RADEON_READ(R600_GRBM_STATUS),
119 RADEON_READ(R600_GRBM_STATUS2));
120
121 return -EBUSY;
122}
123
124static int r600_do_wait_for_idle(drm_radeon_private_t *dev_priv)
125{
126 int i, ret;
127
128 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
129
130 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
131 ret = r600_do_wait_for_fifo(dev_priv, 8);
132 else
133 ret = r600_do_wait_for_fifo(dev_priv, 16);
134 if (ret)
135 return ret;
136 for (i = 0; i < dev_priv->usec_timeout; i++) {
137 if (!(RADEON_READ(R600_GRBM_STATUS) & R600_GUI_ACTIVE))
138 return 0;
139 DRM_UDELAY(1);
140 }
141 DRM_INFO("wait idle failed status : 0x%08X 0x%08X\n",
142 RADEON_READ(R600_GRBM_STATUS),
143 RADEON_READ(R600_GRBM_STATUS2));
144
145 return -EBUSY;
146}
147
c1556f71 148void r600_page_table_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info)
c05ce083
AD		 149{
150 struct drm_sg_mem *entry = dev->sg;
151 int max_pages;
152 int pages;
153 int i;
154
08932156
AD		 155 if (!entry)
156 return;
157
c05ce083 158 if (gart_info->bus_addr) {
06f0a488 159 max_pages = (gart_info->table_size / sizeof(u64));
c05ce083
AD		 160 pages = (entry->pages <= max_pages)
161 ? entry->pages : max_pages;
162
163 for (i = 0; i < pages; i++) {
164 if (!entry->busaddr[i])
165 break;
a763d7dc
DA		 166 pci_unmap_page(dev->pdev, entry->busaddr[i],
167 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
c05ce083
AD		 168 }
169 if (gart_info->gart_table_location == DRM_ATI_GART_MAIN)
170 gart_info->bus_addr = 0;
171 }
172}
173
174/* R600 has page table setup */
175int r600_page_table_init(struct drm_device *dev)
176{
177 drm_radeon_private_t *dev_priv = dev->dev_private;
178 struct drm_ati_pcigart_info *gart_info = &dev_priv->gart_info;
eb1d9195 179 struct drm_local_map *map = &gart_info->mapping;
c05ce083
AD		 180 struct drm_sg_mem *entry = dev->sg;
181 int ret = 0;
182 int i, j;
eb1d9195
DA		 183 int pages;
184 u64 page_base;
c05ce083 185 dma_addr_t entry_addr;
eb1d9195 186 int max_ati_pages, max_real_pages, gart_idx;
c05ce083
AD		 187
188 /* okay page table is available - lets rock */
eb1d9195
DA		 189 max_ati_pages = (gart_info->table_size / sizeof(u64));
190 max_real_pages = max_ati_pages / (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE);
c05ce083 191
eb1d9195
DA		 192 pages = (entry->pages <= max_real_pages) ?
193 entry->pages : max_real_pages;
c05ce083 194
eb1d9195 195 memset_io((void __iomem *)map->handle, 0, max_ati_pages * sizeof(u64));
c05ce083 196
eb1d9195 197 gart_idx = 0;
c05ce083 198 for (i = 0; i < pages; i++) {
a763d7dc
DA		 199 entry->busaddr[i] = pci_map_page(dev->pdev,
200 entry->pagelist[i], 0,
201 PAGE_SIZE,
202 PCI_DMA_BIDIRECTIONAL);
c05ce083
AD		 203 if (entry->busaddr[i] == 0) {
204 DRM_ERROR("unable to map PCIGART pages!\n");
205 r600_page_table_cleanup(dev, gart_info);
c05ce083
AD		 206 goto done;
207 }
208 entry_addr = entry->busaddr[i];
209 for (j = 0; j < (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE); j++) {
210 page_base = (u64) entry_addr & ATI_PCIGART_PAGE_MASK;
211 page_base |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED;
212 page_base |= R600_PTE_READABLE | R600_PTE_WRITEABLE;
213
eb1d9195
DA		 214 DRM_WRITE64(map, gart_idx * sizeof(u64), page_base);
215
216 gart_idx++;
c05ce083
AD		 217
218 if ((i % 128) == 0)
219 DRM_DEBUG("page entry %d: 0x%016llx\n",
220 i, (unsigned long long)page_base);
c05ce083
AD		 221 entry_addr += ATI_PCIGART_PAGE_SIZE;
222 }
223 }
41f13fe8 224 ret = 1;
c05ce083
AD		 225done:
226 return ret;
227}
228
229static void r600_vm_flush_gart_range(struct drm_device *dev)
230{
231 drm_radeon_private_t *dev_priv = dev->dev_private;
232 u32 resp, countdown = 1000;
233 RADEON_WRITE(R600_VM_CONTEXT0_INVALIDATION_LOW_ADDR, dev_priv->gart_vm_start >> 12);
234 RADEON_WRITE(R600_VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
235 RADEON_WRITE(R600_VM_CONTEXT0_REQUEST_RESPONSE, 2);
236
237 do {
238 resp = RADEON_READ(R600_VM_CONTEXT0_REQUEST_RESPONSE);
239 countdown--;
240 DRM_UDELAY(1);
241 } while (((resp & 0xf0) == 0) && countdown);
242}
243
244static void r600_vm_init(struct drm_device *dev)
245{
246 drm_radeon_private_t *dev_priv = dev->dev_private;
247 /* initialise the VM to use the page table we constructed up there */
248 u32 vm_c0, i;
249 u32 mc_rd_a;
250 u32 vm_l2_cntl, vm_l2_cntl3;
251 /* okay set up the PCIE aperture type thingo */
252 RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR, dev_priv->gart_vm_start >> 12);
253 RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
254 RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
255
256 /* setup MC RD a */
257 mc_rd_a = R600_MCD_L1_TLB | R600_MCD_L1_FRAG_PROC | R600_MCD_SYSTEM_ACCESS_MODE_IN_SYS |
258 R600_MCD_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | R600_MCD_EFFECTIVE_L1_TLB_SIZE(5) |
259 R600_MCD_EFFECTIVE_L1_QUEUE_SIZE(5) | R600_MCD_WAIT_L2_QUERY;
260
261 RADEON_WRITE(R600_MCD_RD_A_CNTL, mc_rd_a);
262 RADEON_WRITE(R600_MCD_RD_B_CNTL, mc_rd_a);
263
264 RADEON_WRITE(R600_MCD_WR_A_CNTL, mc_rd_a);
265 RADEON_WRITE(R600_MCD_WR_B_CNTL, mc_rd_a);
266
267 RADEON_WRITE(R600_MCD_RD_GFX_CNTL, mc_rd_a);
268 RADEON_WRITE(R600_MCD_WR_GFX_CNTL, mc_rd_a);
269
270 RADEON_WRITE(R600_MCD_RD_SYS_CNTL, mc_rd_a);
271 RADEON_WRITE(R600_MCD_WR_SYS_CNTL, mc_rd_a);
272
273 RADEON_WRITE(R600_MCD_RD_HDP_CNTL, mc_rd_a | R600_MCD_L1_STRICT_ORDERING);
274 RADEON_WRITE(R600_MCD_WR_HDP_CNTL, mc_rd_a /*| R600_MCD_L1_STRICT_ORDERING*/);
275
276 RADEON_WRITE(R600_MCD_RD_PDMA_CNTL, mc_rd_a);
277 RADEON_WRITE(R600_MCD_WR_PDMA_CNTL, mc_rd_a);
278
279 RADEON_WRITE(R600_MCD_RD_SEM_CNTL, mc_rd_a | R600_MCD_SEMAPHORE_MODE);
280 RADEON_WRITE(R600_MCD_WR_SEM_CNTL, mc_rd_a);
281
282 vm_l2_cntl = R600_VM_L2_CACHE_EN | R600_VM_L2_FRAG_PROC | R600_VM_ENABLE_PTE_CACHE_LRU_W;
283 vm_l2_cntl |= R600_VM_L2_CNTL_QUEUE_SIZE(7);
284 RADEON_WRITE(R600_VM_L2_CNTL, vm_l2_cntl);
285
286 RADEON_WRITE(R600_VM_L2_CNTL2, 0);
287 vm_l2_cntl3 = (R600_VM_L2_CNTL3_BANK_SELECT_0(0) |
288 R600_VM_L2_CNTL3_BANK_SELECT_1(1) |
289 R600_VM_L2_CNTL3_CACHE_UPDATE_MODE(2));
290 RADEON_WRITE(R600_VM_L2_CNTL3, vm_l2_cntl3);
291
292 vm_c0 = R600_VM_ENABLE_CONTEXT | R600_VM_PAGE_TABLE_DEPTH_FLAT;
293
294 RADEON_WRITE(R600_VM_CONTEXT0_CNTL, vm_c0);
295
296 vm_c0 &= ~R600_VM_ENABLE_CONTEXT;
297
298 /* disable all other contexts */
299 for (i = 1; i < 8; i++)
300 RADEON_WRITE(R600_VM_CONTEXT0_CNTL + (i * 4), vm_c0);
301
302 RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, dev_priv->gart_info.bus_addr >> 12);
303 RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_START_ADDR, dev_priv->gart_vm_start >> 12);
304 RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_END_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
305
306 r600_vm_flush_gart_range(dev);
307}
308
70967ab9
BH		 309static int r600_cp_init_microcode(drm_radeon_private_t *dev_priv)
310{
311 struct platform_device *pdev;
312 const char *chip_name;
313 size_t pfp_req_size, me_req_size;
314 char fw_name[30];
315 int err;
316
317 pdev = platform_device_register_simple("r600_cp", 0, NULL, 0);
318 err = IS_ERR(pdev);
319 if (err) {
320 printk(KERN_ERR "r600_cp: Failed to register firmware\n");
321 return -EINVAL;
322 }
323
324 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
325 case CHIP_R600: chip_name = "R600"; break;
326 case CHIP_RV610: chip_name = "RV610"; break;
327 case CHIP_RV630: chip_name = "RV630"; break;
328 case CHIP_RV620: chip_name = "RV620"; break;
329 case CHIP_RV635: chip_name = "RV635"; break;
330 case CHIP_RV670: chip_name = "RV670"; break;
331 case CHIP_RS780:
332 case CHIP_RS880: chip_name = "RS780"; break;
333 case CHIP_RV770: chip_name = "RV770"; break;
334 case CHIP_RV730:
335 case CHIP_RV740: chip_name = "RV730"; break;
336 case CHIP_RV710: chip_name = "RV710"; break;
337 default: BUG();
338 }
339
340 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) {
341 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
342 me_req_size = R700_PM4_UCODE_SIZE * 4;
343 } else {
344 pfp_req_size = PFP_UCODE_SIZE * 4;
345 me_req_size = PM4_UCODE_SIZE * 12;
346 }
347
348 DRM_INFO("Loading %s CP Microcode\n", chip_name);
349
350 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
351 err = request_firmware(&dev_priv->pfp_fw, fw_name, &pdev->dev);
352 if (err)
353 goto out;
354 if (dev_priv->pfp_fw->size != pfp_req_size) {
355 printk(KERN_ERR
356 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
357 dev_priv->pfp_fw->size, fw_name);
358 err = -EINVAL;
359 goto out;
360 }
361
362 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
363 err = request_firmware(&dev_priv->me_fw, fw_name, &pdev->dev);
364 if (err)
365 goto out;
366 if (dev_priv->me_fw->size != me_req_size) {
367 printk(KERN_ERR
368 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
369 dev_priv->me_fw->size, fw_name);
370 err = -EINVAL;
371 }
372out:
373 platform_device_unregister(pdev);
374
375 if (err) {
376 if (err != -EINVAL)
377 printk(KERN_ERR
378 "r600_cp: Failed to load firmware \"%s\"\n",
379 fw_name);
380 release_firmware(dev_priv->pfp_fw);
381 dev_priv->pfp_fw = NULL;
382 release_firmware(dev_priv->me_fw);
383 dev_priv->me_fw = NULL;
384 }
385 return err;
386}
387
c05ce083
AD		 388static void r600_cp_load_microcode(drm_radeon_private_t *dev_priv)
389{
70967ab9 390 const __be32 *fw_data;
c05ce083
AD		 391 int i;
392
70967ab9
BH		 393 if (!dev_priv->me_fw || !dev_priv->pfp_fw)
394 return;
395
c05ce083
AD		 396 r600_do_cp_stop(dev_priv);
397
398 RADEON_WRITE(R600_CP_RB_CNTL,
399 R600_RB_NO_UPDATE |
400 R600_RB_BLKSZ(15) |
401 R600_RB_BUFSZ(3));
402
403 RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP);
404 RADEON_READ(R600_GRBM_SOFT_RESET);
405 DRM_UDELAY(15000);
406 RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
407
70967ab9 408 fw_data = (const __be32 *)dev_priv->me_fw->data;
c05ce083 409 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
70967ab9
BH		 410 for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
411 RADEON_WRITE(R600_CP_ME_RAM_DATA,
412 be32_to_cpup(fw_data++));
c05ce083 413
70967ab9
BH		 414 fw_data = (const __be32 *)dev_priv->pfp_fw->data;
415 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
416 for (i = 0; i < PFP_UCODE_SIZE; i++)
417 RADEON_WRITE(R600_CP_PFP_UCODE_DATA,
418 be32_to_cpup(fw_data++));
c05ce083 419
c05ce083
AD		 420 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
421 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
422 RADEON_WRITE(R600_CP_ME_RAM_RADDR, 0);
423
424}
425
426static void r700_vm_init(struct drm_device *dev)
427{
428 drm_radeon_private_t *dev_priv = dev->dev_private;
429 /* initialise the VM to use the page table we constructed up there */
430 u32 vm_c0, i;
431 u32 mc_vm_md_l1;
432 u32 vm_l2_cntl, vm_l2_cntl3;
433 /* okay set up the PCIE aperture type thingo */
434 RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR, dev_priv->gart_vm_start >> 12);
435 RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
436 RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
437
438 mc_vm_md_l1 = R700_ENABLE_L1_TLB |
439 R700_ENABLE_L1_FRAGMENT_PROCESSING |
440 R700_SYSTEM_ACCESS_MODE_IN_SYS |
441 R700_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
442 R700_EFFECTIVE_L1_TLB_SIZE(5) |
443 R700_EFFECTIVE_L1_QUEUE_SIZE(5);
444
445 RADEON_WRITE(R700_MC_VM_MD_L1_TLB0_CNTL, mc_vm_md_l1);
446 RADEON_WRITE(R700_MC_VM_MD_L1_TLB1_CNTL, mc_vm_md_l1);
447 RADEON_WRITE(R700_MC_VM_MD_L1_TLB2_CNTL, mc_vm_md_l1);
448 RADEON_WRITE(R700_MC_VM_MB_L1_TLB0_CNTL, mc_vm_md_l1);
449 RADEON_WRITE(R700_MC_VM_MB_L1_TLB1_CNTL, mc_vm_md_l1);
450 RADEON_WRITE(R700_MC_VM_MB_L1_TLB2_CNTL, mc_vm_md_l1);
451 RADEON_WRITE(R700_MC_VM_MB_L1_TLB3_CNTL, mc_vm_md_l1);
452
453 vm_l2_cntl = R600_VM_L2_CACHE_EN | R600_VM_L2_FRAG_PROC | R600_VM_ENABLE_PTE_CACHE_LRU_W;
454 vm_l2_cntl |= R700_VM_L2_CNTL_QUEUE_SIZE(7);
455 RADEON_WRITE(R600_VM_L2_CNTL, vm_l2_cntl);
456
457 RADEON_WRITE(R600_VM_L2_CNTL2, 0);
458 vm_l2_cntl3 = R700_VM_L2_CNTL3_BANK_SELECT(0) | R700_VM_L2_CNTL3_CACHE_UPDATE_MODE(2);
459 RADEON_WRITE(R600_VM_L2_CNTL3, vm_l2_cntl3);
460
461 vm_c0 = R600_VM_ENABLE_CONTEXT | R600_VM_PAGE_TABLE_DEPTH_FLAT;
462
463 RADEON_WRITE(R600_VM_CONTEXT0_CNTL, vm_c0);
464
465 vm_c0 &= ~R600_VM_ENABLE_CONTEXT;
466
467 /* disable all other contexts */
468 for (i = 1; i < 8; i++)
469 RADEON_WRITE(R600_VM_CONTEXT0_CNTL + (i * 4), vm_c0);
470
471 RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, dev_priv->gart_info.bus_addr >> 12);
472 RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_START_ADDR, dev_priv->gart_vm_start >> 12);
473 RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_END_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
474
475 r600_vm_flush_gart_range(dev);
476}
477
c05ce083
AD		 478static void r700_cp_load_microcode(drm_radeon_private_t *dev_priv)
479{
70967ab9 480 const __be32 *fw_data;
c05ce083
AD		 481 int i;
482
70967ab9
BH		 483 if (!dev_priv->me_fw || !dev_priv->pfp_fw)
484 return;
485
c05ce083
AD		 486 r600_do_cp_stop(dev_priv);
487
488 RADEON_WRITE(R600_CP_RB_CNTL,
489 R600_RB_NO_UPDATE |
490 (15 << 8) |
491 (3 << 0));
492
493 RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP);
494 RADEON_READ(R600_GRBM_SOFT_RESET);
495 DRM_UDELAY(15000);
496 RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
497
70967ab9
BH		 498 fw_data = (const __be32 *)dev_priv->pfp_fw->data;
499 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
500 for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
501 RADEON_WRITE(R600_CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
502 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
c05ce083 503
70967ab9
BH		 504 fw_data = (const __be32 *)dev_priv->me_fw->data;
505 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
506 for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
507 RADEON_WRITE(R600_CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
508 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
c05ce083 509
c05ce083
AD		 510 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
511 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
512 RADEON_WRITE(R600_CP_ME_RAM_RADDR, 0);
513
514}
515
516static void r600_test_writeback(drm_radeon_private_t *dev_priv)
517{
518 u32 tmp;
519
520 /* Start with assuming that writeback doesn't work */
521 dev_priv->writeback_works = 0;
522
523 /* Writeback doesn't seem to work everywhere, test it here and possibly
524 * enable it if it appears to work
525 */
526 radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(1), 0);
527
528 RADEON_WRITE(R600_SCRATCH_REG1, 0xdeadbeef);
529
530 for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
531 u32 val;
532
533 val = radeon_read_ring_rptr(dev_priv, R600_SCRATCHOFF(1));
534 if (val == 0xdeadbeef)
535 break;
536 DRM_UDELAY(1);
537 }
538
539 if (tmp < dev_priv->usec_timeout) {
540 dev_priv->writeback_works = 1;
541 DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
542 } else {
543 dev_priv->writeback_works = 0;
544 DRM_INFO("writeback test failed\n");
545 }
546 if (radeon_no_wb == 1) {
547 dev_priv->writeback_works = 0;
548 DRM_INFO("writeback forced off\n");
549 }
550
551 if (!dev_priv->writeback_works) {
552 /* Disable writeback to avoid unnecessary bus master transfer */
553 RADEON_WRITE(R600_CP_RB_CNTL, RADEON_READ(R600_CP_RB_CNTL) |
554 RADEON_RB_NO_UPDATE);
555 RADEON_WRITE(R600_SCRATCH_UMSK, 0);
556 }
557}
558
559int r600_do_engine_reset(struct drm_device *dev)
560{
561 drm_radeon_private_t *dev_priv = dev->dev_private;
562 u32 cp_ptr, cp_me_cntl, cp_rb_cntl;
563
564 DRM_INFO("Resetting GPU\n");
565
566 cp_ptr = RADEON_READ(R600_CP_RB_WPTR);
567 cp_me_cntl = RADEON_READ(R600_CP_ME_CNTL);
568 RADEON_WRITE(R600_CP_ME_CNTL, R600_CP_ME_HALT);
569
570 RADEON_WRITE(R600_GRBM_SOFT_RESET, 0x7fff);
571 RADEON_READ(R600_GRBM_SOFT_RESET);
572 DRM_UDELAY(50);
573 RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
574 RADEON_READ(R600_GRBM_SOFT_RESET);
575
576 RADEON_WRITE(R600_CP_RB_WPTR_DELAY, 0);
577 cp_rb_cntl = RADEON_READ(R600_CP_RB_CNTL);
578 RADEON_WRITE(R600_CP_RB_CNTL, R600_RB_RPTR_WR_ENA);
579
580 RADEON_WRITE(R600_CP_RB_RPTR_WR, cp_ptr);
581 RADEON_WRITE(R600_CP_RB_WPTR, cp_ptr);
582 RADEON_WRITE(R600_CP_RB_CNTL, cp_rb_cntl);
583 RADEON_WRITE(R600_CP_ME_CNTL, cp_me_cntl);
584
585 /* Reset the CP ring */
586 r600_do_cp_reset(dev_priv);
587
588 /* The CP is no longer running after an engine reset */
589 dev_priv->cp_running = 0;
590
591 /* Reset any pending vertex, indirect buffers */
592 radeon_freelist_reset(dev);
593
594 return 0;
595
596}
597
598static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
599 u32 num_backends,
600 u32 backend_disable_mask)
601{
602 u32 backend_map = 0;
603 u32 enabled_backends_mask;
604 u32 enabled_backends_count;
605 u32 cur_pipe;
606 u32 swizzle_pipe[R6XX_MAX_PIPES];
607 u32 cur_backend;
608 u32 i;
609
610 if (num_tile_pipes > R6XX_MAX_PIPES)
611 num_tile_pipes = R6XX_MAX_PIPES;
612 if (num_tile_pipes < 1)
613 num_tile_pipes = 1;
614 if (num_backends > R6XX_MAX_BACKENDS)
615 num_backends = R6XX_MAX_BACKENDS;
616 if (num_backends < 1)
617 num_backends = 1;
618
619 enabled_backends_mask = 0;
620 enabled_backends_count = 0;
621 for (i = 0; i < R6XX_MAX_BACKENDS; ++i) {
622 if (((backend_disable_mask >> i) & 1) == 0) {
623 enabled_backends_mask |= (1 << i);
624 ++enabled_backends_count;
625 }
626 if (enabled_backends_count == num_backends)
627 break;
628 }
629
630 if (enabled_backends_count == 0) {
631 enabled_backends_mask = 1;
632 enabled_backends_count = 1;
633 }
634
635 if (enabled_backends_count != num_backends)
636 num_backends = enabled_backends_count;
637
638 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES);
639 switch (num_tile_pipes) {
640 case 1:
641 swizzle_pipe[0] = 0;
642 break;
643 case 2:
644 swizzle_pipe[0] = 0;
645 swizzle_pipe[1] = 1;
646 break;
647 case 3:
648 swizzle_pipe[0] = 0;
649 swizzle_pipe[1] = 1;
650 swizzle_pipe[2] = 2;
651 break;
652 case 4:
653 swizzle_pipe[0] = 0;
654 swizzle_pipe[1] = 1;
655 swizzle_pipe[2] = 2;
656 swizzle_pipe[3] = 3;
657 break;
658 case 5:
659 swizzle_pipe[0] = 0;
660 swizzle_pipe[1] = 1;
661 swizzle_pipe[2] = 2;
662 swizzle_pipe[3] = 3;
663 swizzle_pipe[4] = 4;
664 break;
665 case 6:
666 swizzle_pipe[0] = 0;
667 swizzle_pipe[1] = 2;
668 swizzle_pipe[2] = 4;
669 swizzle_pipe[3] = 5;
670 swizzle_pipe[4] = 1;
671 swizzle_pipe[5] = 3;
672 break;
673 case 7:
674 swizzle_pipe[0] = 0;
675 swizzle_pipe[1] = 2;
676 swizzle_pipe[2] = 4;
677 swizzle_pipe[3] = 6;
678 swizzle_pipe[4] = 1;
679 swizzle_pipe[5] = 3;
680 swizzle_pipe[6] = 5;
681 break;
682 case 8:
683 swizzle_pipe[0] = 0;
684 swizzle_pipe[1] = 2;
685 swizzle_pipe[2] = 4;
686 swizzle_pipe[3] = 6;
687 swizzle_pipe[4] = 1;
688 swizzle_pipe[5] = 3;
689 swizzle_pipe[6] = 5;
690 swizzle_pipe[7] = 7;
691 break;
692 }
693
694 cur_backend = 0;
695 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
696 while (((1 << cur_backend) & enabled_backends_mask) == 0)
697 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
698
699 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
700
701 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
702 }
703
704 return backend_map;
705}
706
707static int r600_count_pipe_bits(uint32_t val)
708{
709 int i, ret = 0;
710 for (i = 0; i < 32; i++) {
711 ret += val & 1;
712 val >>= 1;
713 }
714 return ret;
715}
716
717static void r600_gfx_init(struct drm_device *dev,
718 drm_radeon_private_t *dev_priv)
719{
720 int i, j, num_qd_pipes;
721 u32 sx_debug_1;
722 u32 tc_cntl;
723 u32 arb_pop;
724 u32 num_gs_verts_per_thread;
725 u32 vgt_gs_per_es;
726 u32 gs_prim_buffer_depth = 0;
727 u32 sq_ms_fifo_sizes;
728 u32 sq_config;
729 u32 sq_gpr_resource_mgmt_1 = 0;
730 u32 sq_gpr_resource_mgmt_2 = 0;
731 u32 sq_thread_resource_mgmt = 0;
732 u32 sq_stack_resource_mgmt_1 = 0;
733 u32 sq_stack_resource_mgmt_2 = 0;
734 u32 hdp_host_path_cntl;
735 u32 backend_map;
736 u32 gb_tiling_config = 0;
737 u32 cc_rb_backend_disable = 0;
738 u32 cc_gc_shader_pipe_config = 0;
739 u32 ramcfg;
740
741 /* setup chip specs */
742 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
743 case CHIP_R600:
744 dev_priv->r600_max_pipes = 4;
745 dev_priv->r600_max_tile_pipes = 8;
746 dev_priv->r600_max_simds = 4;
747 dev_priv->r600_max_backends = 4;
748 dev_priv->r600_max_gprs = 256;
749 dev_priv->r600_max_threads = 192;
750 dev_priv->r600_max_stack_entries = 256;
751 dev_priv->r600_max_hw_contexts = 8;
752 dev_priv->r600_max_gs_threads = 16;
753 dev_priv->r600_sx_max_export_size = 128;
754 dev_priv->r600_sx_max_export_pos_size = 16;
755 dev_priv->r600_sx_max_export_smx_size = 128;
756 dev_priv->r600_sq_num_cf_insts = 2;
757 break;
758 case CHIP_RV630:
759 case CHIP_RV635:
760 dev_priv->r600_max_pipes = 2;
761 dev_priv->r600_max_tile_pipes = 2;
762 dev_priv->r600_max_simds = 3;
763 dev_priv->r600_max_backends = 1;
764 dev_priv->r600_max_gprs = 128;
765 dev_priv->r600_max_threads = 192;
766 dev_priv->r600_max_stack_entries = 128;
767 dev_priv->r600_max_hw_contexts = 8;
768 dev_priv->r600_max_gs_threads = 4;
769 dev_priv->r600_sx_max_export_size = 128;
770 dev_priv->r600_sx_max_export_pos_size = 16;
771 dev_priv->r600_sx_max_export_smx_size = 128;
772 dev_priv->r600_sq_num_cf_insts = 2;
773 break;
774 case CHIP_RV610:
775 case CHIP_RS780:
6502fbfa 776 case CHIP_RS880:
c05ce083
AD		 777 case CHIP_RV620:
778 dev_priv->r600_max_pipes = 1;
779 dev_priv->r600_max_tile_pipes = 1;
780 dev_priv->r600_max_simds = 2;
781 dev_priv->r600_max_backends = 1;
782 dev_priv->r600_max_gprs = 128;
783 dev_priv->r600_max_threads = 192;
784 dev_priv->r600_max_stack_entries = 128;
785 dev_priv->r600_max_hw_contexts = 4;
786 dev_priv->r600_max_gs_threads = 4;
787 dev_priv->r600_sx_max_export_size = 128;
788 dev_priv->r600_sx_max_export_pos_size = 16;
789 dev_priv->r600_sx_max_export_smx_size = 128;
790 dev_priv->r600_sq_num_cf_insts = 1;
791 break;
792 case CHIP_RV670:
793 dev_priv->r600_max_pipes = 4;
794 dev_priv->r600_max_tile_pipes = 4;
795 dev_priv->r600_max_simds = 4;
796 dev_priv->r600_max_backends = 4;
797 dev_priv->r600_max_gprs = 192;
798 dev_priv->r600_max_threads = 192;
799 dev_priv->r600_max_stack_entries = 256;
800 dev_priv->r600_max_hw_contexts = 8;
801 dev_priv->r600_max_gs_threads = 16;
802 dev_priv->r600_sx_max_export_size = 128;
803 dev_priv->r600_sx_max_export_pos_size = 16;
804 dev_priv->r600_sx_max_export_smx_size = 128;
805 dev_priv->r600_sq_num_cf_insts = 2;
806 break;
807 default:
808 break;
809 }
810
811 /* Initialize HDP */
812 j = 0;
813 for (i = 0; i < 32; i++) {
814 RADEON_WRITE((0x2c14 + j), 0x00000000);
815 RADEON_WRITE((0x2c18 + j), 0x00000000);
816 RADEON_WRITE((0x2c1c + j), 0x00000000);
817 RADEON_WRITE((0x2c20 + j), 0x00000000);
818 RADEON_WRITE((0x2c24 + j), 0x00000000);
819 j += 0x18;
820 }
821
822 RADEON_WRITE(R600_GRBM_CNTL, R600_GRBM_READ_TIMEOUT(0xff));
823
824 /* setup tiling, simd, pipe config */
825 ramcfg = RADEON_READ(R600_RAMCFG);
826
827 switch (dev_priv->r600_max_tile_pipes) {
828 case 1:
829 gb_tiling_config |= R600_PIPE_TILING(0);
830 break;
831 case 2:
832 gb_tiling_config |= R600_PIPE_TILING(1);
833 break;
834 case 4:
835 gb_tiling_config |= R600_PIPE_TILING(2);
836 break;
837 case 8:
838 gb_tiling_config |= R600_PIPE_TILING(3);
839 break;
840 default:
841 break;
842 }
843
844 gb_tiling_config |= R600_BANK_TILING((ramcfg >> R600_NOOFBANK_SHIFT) & R600_NOOFBANK_MASK);
845
846 gb_tiling_config |= R600_GROUP_SIZE(0);
847
848 if (((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK) > 3) {
849 gb_tiling_config |= R600_ROW_TILING(3);
850 gb_tiling_config |= R600_SAMPLE_SPLIT(3);
851 } else {
852 gb_tiling_config |=
853 R600_ROW_TILING(((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK));
854 gb_tiling_config |=
855 R600_SAMPLE_SPLIT(((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK));
856 }
857
858 gb_tiling_config |= R600_BANK_SWAPS(1);
859
860 backend_map = r600_get_tile_pipe_to_backend_map(dev_priv->r600_max_tile_pipes,
861 dev_priv->r600_max_backends,
862 (0xff << dev_priv->r600_max_backends) & 0xff);
863 gb_tiling_config |= R600_BACKEND_MAP(backend_map);
864
865 cc_gc_shader_pipe_config =
866 R600_INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << dev_priv->r600_max_pipes) & R6XX_MAX_PIPES_MASK);
867 cc_gc_shader_pipe_config |=
868 R600_INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << dev_priv->r600_max_simds) & R6XX_MAX_SIMDS_MASK);
869
870 cc_rb_backend_disable =
871 R600_BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << dev_priv->r600_max_backends) & R6XX_MAX_BACKENDS_MASK);
872
873 RADEON_WRITE(R600_GB_TILING_CONFIG, gb_tiling_config);
874 RADEON_WRITE(R600_DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
875 RADEON_WRITE(R600_HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
961fb597
JG		 876 if (gb_tiling_config & 0xc0) {
877 dev_priv->r600_group_size = 512;
878 } else {
879 dev_priv->r600_group_size = 256;
880 }
881 dev_priv->r600_npipes = 1 << ((gb_tiling_config >> 1) & 0x7);
882 if (gb_tiling_config & 0x30) {
883 dev_priv->r600_nbanks = 8;
884 } else {
885 dev_priv->r600_nbanks = 4;
886 }
c05ce083
AD		 887
888 RADEON_WRITE(R600_CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
889 RADEON_WRITE(R600_CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
890 RADEON_WRITE(R600_GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
891
892 num_qd_pipes =
893 R6XX_MAX_BACKENDS - r600_count_pipe_bits(cc_gc_shader_pipe_config & R600_INACTIVE_QD_PIPES_MASK);
894 RADEON_WRITE(R600_VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & R600_DEALLOC_DIST_MASK);
895 RADEON_WRITE(R600_VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & R600_VTX_REUSE_DEPTH_MASK);
896
897 /* set HW defaults for 3D engine */
898 RADEON_WRITE(R600_CP_QUEUE_THRESHOLDS, (R600_ROQ_IB1_START(0x16) |
899 R600_ROQ_IB2_START(0x2b)));
900
901 RADEON_WRITE(R600_CP_MEQ_THRESHOLDS, (R600_MEQ_END(0x40) |
902 R600_ROQ_END(0x40)));
903
904 RADEON_WRITE(R600_TA_CNTL_AUX, (R600_DISABLE_CUBE_ANISO |
905 R600_SYNC_GRADIENT |
906 R600_SYNC_WALKER |
907 R600_SYNC_ALIGNER));
908
909 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV670)
910 RADEON_WRITE(R600_ARB_GDEC_RD_CNTL, 0x00000021);
911
912 sx_debug_1 = RADEON_READ(R600_SX_DEBUG_1);
913 sx_debug_1 |= R600_SMX_EVENT_RELEASE;
914 if (((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_R600))
915 sx_debug_1 |= R600_ENABLE_NEW_SMX_ADDRESS;
916 RADEON_WRITE(R600_SX_DEBUG_1, sx_debug_1);
917
918 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) ||
919 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630) ||
920 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
921 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
6502fbfa
AD		 922 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
923 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880))
c05ce083
AD		 924 RADEON_WRITE(R600_DB_DEBUG, R600_PREZ_MUST_WAIT_FOR_POSTZ_DONE);
925 else
926 RADEON_WRITE(R600_DB_DEBUG, 0);
927
928 RADEON_WRITE(R600_DB_WATERMARKS, (R600_DEPTH_FREE(4) |
929 R600_DEPTH_FLUSH(16) |
930 R600_DEPTH_PENDING_FREE(4) |
931 R600_DEPTH_CACHELINE_FREE(16)));
932 RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0);
933 RADEON_WRITE(R600_VGT_NUM_INSTANCES, 0);
934
935 RADEON_WRITE(R600_SPI_CONFIG_CNTL, R600_GPR_WRITE_PRIORITY(0));
936 RADEON_WRITE(R600_SPI_CONFIG_CNTL_1, R600_VTX_DONE_DELAY(0));
937
938 sq_ms_fifo_sizes = RADEON_READ(R600_SQ_MS_FIFO_SIZES);
939 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
940 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
6502fbfa
AD		 941 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
942 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) {
c05ce083
AD		 943 sq_ms_fifo_sizes = (R600_CACHE_FIFO_SIZE(0xa) |
944 R600_FETCH_FIFO_HIWATER(0xa) |
945 R600_DONE_FIFO_HIWATER(0xe0) |
946 R600_ALU_UPDATE_FIFO_HIWATER(0x8));
947 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) ||
948 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630)) {
949 sq_ms_fifo_sizes &= ~R600_DONE_FIFO_HIWATER(0xff);
950 sq_ms_fifo_sizes |= R600_DONE_FIFO_HIWATER(0x4);
951 }
952 RADEON_WRITE(R600_SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
953
954 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
955 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
956 */
957 sq_config = RADEON_READ(R600_SQ_CONFIG);
958 sq_config &= ~(R600_PS_PRIO(3) |
959 R600_VS_PRIO(3) |
960 R600_GS_PRIO(3) |
961 R600_ES_PRIO(3));
962 sq_config |= (R600_DX9_CONSTS |
963 R600_VC_ENABLE |
964 R600_PS_PRIO(0) |
965 R600_VS_PRIO(1) |
966 R600_GS_PRIO(2) |
967 R600_ES_PRIO(3));
968
969 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) {
970 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(124) |
971 R600_NUM_VS_GPRS(124) |
972 R600_NUM_CLAUSE_TEMP_GPRS(4));
973 sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(0) |
974 R600_NUM_ES_GPRS(0));
975 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(136) |
976 R600_NUM_VS_THREADS(48) |
977 R600_NUM_GS_THREADS(4) |
978 R600_NUM_ES_THREADS(4));
979 sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(128) |
980 R600_NUM_VS_STACK_ENTRIES(128));
981 sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(0) |
982 R600_NUM_ES_STACK_ENTRIES(0));
983 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
984 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
6502fbfa
AD		 985 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
986 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) {
c05ce083
AD		 987 /* no vertex cache */
988 sq_config &= ~R600_VC_ENABLE;
989
990 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) |
991 R600_NUM_VS_GPRS(44) |
992 R600_NUM_CLAUSE_TEMP_GPRS(2));
993 sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(17) |
994 R600_NUM_ES_GPRS(17));
995 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) |
996 R600_NUM_VS_THREADS(78) |
997 R600_NUM_GS_THREADS(4) |
998 R600_NUM_ES_THREADS(31));
999 sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(40) |
1000 R600_NUM_VS_STACK_ENTRIES(40));
1001 sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(32) |
1002 R600_NUM_ES_STACK_ENTRIES(16));
1003 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630) ||
1004 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV635)) {
1005 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) |
1006 R600_NUM_VS_GPRS(44) |
1007 R600_NUM_CLAUSE_TEMP_GPRS(2));
1008 sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(18) |
1009 R600_NUM_ES_GPRS(18));
1010 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) |
1011 R600_NUM_VS_THREADS(78) |
1012 R600_NUM_GS_THREADS(4) |
1013 R600_NUM_ES_THREADS(31));
1014 sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(40) |
1015 R600_NUM_VS_STACK_ENTRIES(40));
1016 sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(32) |
1017 R600_NUM_ES_STACK_ENTRIES(16));
1018 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV670) {
1019 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) |
1020 R600_NUM_VS_GPRS(44) |
1021 R600_NUM_CLAUSE_TEMP_GPRS(2));
1022 sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(17) |
1023 R600_NUM_ES_GPRS(17));
1024 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) |
1025 R600_NUM_VS_THREADS(78) |
1026 R600_NUM_GS_THREADS(4) |
1027 R600_NUM_ES_THREADS(31));
1028 sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(64) |
1029 R600_NUM_VS_STACK_ENTRIES(64));
1030 sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(64) |
1031 R600_NUM_ES_STACK_ENTRIES(64));
1032 }
1033
1034 RADEON_WRITE(R600_SQ_CONFIG, sq_config);
1035 RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
1036 RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
1037 RADEON_WRITE(R600_SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1038 RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1039 RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1040
1041 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
1042 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
6502fbfa
AD		 1043 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
1044 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880))
c05ce083
AD		 1045 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, R600_CACHE_INVALIDATION(R600_TC_ONLY));
1046 else
1047 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, R600_CACHE_INVALIDATION(R600_VC_AND_TC));
1048
1049 RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_2S, (R600_S0_X(0xc) |
1050 R600_S0_Y(0x4) |
1051 R600_S1_X(0x4) |
1052 R600_S1_Y(0xc)));
1053 RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_4S, (R600_S0_X(0xe) |
1054 R600_S0_Y(0xe) |
1055 R600_S1_X(0x2) |
1056 R600_S1_Y(0x2) |
1057 R600_S2_X(0xa) |
1058 R600_S2_Y(0x6) |
1059 R600_S3_X(0x6) |
1060 R600_S3_Y(0xa)));
1061 RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_8S_WD0, (R600_S0_X(0xe) |
1062 R600_S0_Y(0xb) |
1063 R600_S1_X(0x4) |
1064 R600_S1_Y(0xc) |
1065 R600_S2_X(0x1) |
1066 R600_S2_Y(0x6) |
1067 R600_S3_X(0xa) |
1068 R600_S3_Y(0xe)));
1069 RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_8S_WD1, (R600_S4_X(0x6) |
1070 R600_S4_Y(0x1) |
1071 R600_S5_X(0x0) |
1072 R600_S5_Y(0x0) |
1073 R600_S6_X(0xb) |
1074 R600_S6_Y(0x4) |
1075 R600_S7_X(0x7) |
1076 R600_S7_Y(0x8)));
1077
1078
1079 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1080 case CHIP_R600:
1081 case CHIP_RV630:
1082 case CHIP_RV635:
1083 gs_prim_buffer_depth = 0;
1084 break;
1085 case CHIP_RV610:
1086 case CHIP_RS780:
6502fbfa 1087 case CHIP_RS880:
c05ce083
AD		 1088 case CHIP_RV620:
1089 gs_prim_buffer_depth = 32;
1090 break;
1091 case CHIP_RV670:
1092 gs_prim_buffer_depth = 128;
1093 break;
1094 default:
1095 break;
1096 }
1097
1098 num_gs_verts_per_thread = dev_priv->r600_max_pipes * 16;
1099 vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
1100 /* Max value for this is 256 */
1101 if (vgt_gs_per_es > 256)
1102 vgt_gs_per_es = 256;
1103
1104 RADEON_WRITE(R600_VGT_ES_PER_GS, 128);
1105 RADEON_WRITE(R600_VGT_GS_PER_ES, vgt_gs_per_es);
1106 RADEON_WRITE(R600_VGT_GS_PER_VS, 2);
1107 RADEON_WRITE(R600_VGT_GS_VERTEX_REUSE, 16);
1108
1109 /* more default values. 2D/3D driver should adjust as needed */
1110 RADEON_WRITE(R600_PA_SC_LINE_STIPPLE_STATE, 0);
1111 RADEON_WRITE(R600_VGT_STRMOUT_EN, 0);
1112 RADEON_WRITE(R600_SX_MISC, 0);
1113 RADEON_WRITE(R600_PA_SC_MODE_CNTL, 0);
1114 RADEON_WRITE(R600_PA_SC_AA_CONFIG, 0);
1115 RADEON_WRITE(R600_PA_SC_LINE_STIPPLE, 0);
1116 RADEON_WRITE(R600_SPI_INPUT_Z, 0);
1117 RADEON_WRITE(R600_SPI_PS_IN_CONTROL_0, R600_NUM_INTERP(2));
1118 RADEON_WRITE(R600_CB_COLOR7_FRAG, 0);
1119
1120 /* clear render buffer base addresses */
1121 RADEON_WRITE(R600_CB_COLOR0_BASE, 0);
1122 RADEON_WRITE(R600_CB_COLOR1_BASE, 0);
1123 RADEON_WRITE(R600_CB_COLOR2_BASE, 0);
1124 RADEON_WRITE(R600_CB_COLOR3_BASE, 0);
1125 RADEON_WRITE(R600_CB_COLOR4_BASE, 0);
1126 RADEON_WRITE(R600_CB_COLOR5_BASE, 0);
1127 RADEON_WRITE(R600_CB_COLOR6_BASE, 0);
1128 RADEON_WRITE(R600_CB_COLOR7_BASE, 0);
1129
1130 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1131 case CHIP_RV610:
1132 case CHIP_RS780:
6502fbfa 1133 case CHIP_RS880:
c05ce083
AD		 1134 case CHIP_RV620:
1135 tc_cntl = R600_TC_L2_SIZE(8);
1136 break;
1137 case CHIP_RV630:
1138 case CHIP_RV635:
1139 tc_cntl = R600_TC_L2_SIZE(4);
1140 break;
1141 case CHIP_R600:
1142 tc_cntl = R600_TC_L2_SIZE(0) | R600_L2_DISABLE_LATE_HIT;
1143 break;
1144 default:
1145 tc_cntl = R600_TC_L2_SIZE(0);
1146 break;
1147 }
1148
1149 RADEON_WRITE(R600_TC_CNTL, tc_cntl);
1150
1151 hdp_host_path_cntl = RADEON_READ(R600_HDP_HOST_PATH_CNTL);
1152 RADEON_WRITE(R600_HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1153
1154 arb_pop = RADEON_READ(R600_ARB_POP);
1155 arb_pop |= R600_ENABLE_TC128;
1156 RADEON_WRITE(R600_ARB_POP, arb_pop);
1157
1158 RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0);
1159 RADEON_WRITE(R600_PA_CL_ENHANCE, (R600_CLIP_VTX_REORDER_ENA |
1160 R600_NUM_CLIP_SEQ(3)));
1161 RADEON_WRITE(R600_PA_SC_ENHANCE, R600_FORCE_EOV_MAX_CLK_CNT(4095));
1162
1163}
1164
1165static u32 r700_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
1166 u32 num_backends,
1167 u32 backend_disable_mask)
1168{
1169 u32 backend_map = 0;
1170 u32 enabled_backends_mask;
1171 u32 enabled_backends_count;
1172 u32 cur_pipe;
1173 u32 swizzle_pipe[R7XX_MAX_PIPES];
1174 u32 cur_backend;
1175 u32 i;
1176
1177 if (num_tile_pipes > R7XX_MAX_PIPES)
1178 num_tile_pipes = R7XX_MAX_PIPES;
1179 if (num_tile_pipes < 1)
1180 num_tile_pipes = 1;
1181 if (num_backends > R7XX_MAX_BACKENDS)
1182 num_backends = R7XX_MAX_BACKENDS;
1183 if (num_backends < 1)
1184 num_backends = 1;
1185
1186 enabled_backends_mask = 0;
1187 enabled_backends_count = 0;
1188 for (i = 0; i < R7XX_MAX_BACKENDS; ++i) {
1189 if (((backend_disable_mask >> i) & 1) == 0) {
1190 enabled_backends_mask |= (1 << i);
1191 ++enabled_backends_count;
1192 }
1193 if (enabled_backends_count == num_backends)
1194 break;
1195 }
1196
1197 if (enabled_backends_count == 0) {
1198 enabled_backends_mask = 1;
1199 enabled_backends_count = 1;
1200 }
1201
1202 if (enabled_backends_count != num_backends)
1203 num_backends = enabled_backends_count;
1204
1205 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R7XX_MAX_PIPES);
1206 switch (num_tile_pipes) {
1207 case 1:
1208 swizzle_pipe[0] = 0;
1209 break;
1210 case 2:
1211 swizzle_pipe[0] = 0;
1212 swizzle_pipe[1] = 1;
1213 break;
1214 case 3:
1215 swizzle_pipe[0] = 0;
1216 swizzle_pipe[1] = 2;
1217 swizzle_pipe[2] = 1;
1218 break;
1219 case 4:
1220 swizzle_pipe[0] = 0;
1221 swizzle_pipe[1] = 2;
1222 swizzle_pipe[2] = 3;
1223 swizzle_pipe[3] = 1;
1224 break;
1225 case 5:
1226 swizzle_pipe[0] = 0;
1227 swizzle_pipe[1] = 2;
1228 swizzle_pipe[2] = 4;
1229 swizzle_pipe[3] = 1;
1230 swizzle_pipe[4] = 3;
1231 break;
1232 case 6:
1233 swizzle_pipe[0] = 0;
1234 swizzle_pipe[1] = 2;
1235 swizzle_pipe[2] = 4;
1236 swizzle_pipe[3] = 5;
1237 swizzle_pipe[4] = 3;
1238 swizzle_pipe[5] = 1;
1239 break;
1240 case 7:
1241 swizzle_pipe[0] = 0;
1242 swizzle_pipe[1] = 2;
1243 swizzle_pipe[2] = 4;
1244 swizzle_pipe[3] = 6;
1245 swizzle_pipe[4] = 3;
1246 swizzle_pipe[5] = 1;
1247 swizzle_pipe[6] = 5;
1248 break;
1249 case 8:
1250 swizzle_pipe[0] = 0;
1251 swizzle_pipe[1] = 2;
1252 swizzle_pipe[2] = 4;
1253 swizzle_pipe[3] = 6;
1254 swizzle_pipe[4] = 3;
1255 swizzle_pipe[5] = 1;
1256 swizzle_pipe[6] = 7;
1257 swizzle_pipe[7] = 5;
1258 break;
1259 }
1260
1261 cur_backend = 0;
1262 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1263 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1264 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
1265
1266 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
1267
1268 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
1269 }
1270
1271 return backend_map;
1272}
1273
1274static void r700_gfx_init(struct drm_device *dev,
1275 drm_radeon_private_t *dev_priv)
1276{
1277 int i, j, num_qd_pipes;
1278 u32 sx_debug_1;
1279 u32 smx_dc_ctl0;
1280 u32 num_gs_verts_per_thread;
1281 u32 vgt_gs_per_es;
1282 u32 gs_prim_buffer_depth = 0;
1283 u32 sq_ms_fifo_sizes;
1284 u32 sq_config;
1285 u32 sq_thread_resource_mgmt;
1286 u32 hdp_host_path_cntl;
1287 u32 sq_dyn_gpr_size_simd_ab_0;
1288 u32 backend_map;
1289 u32 gb_tiling_config = 0;
1290 u32 cc_rb_backend_disable = 0;
1291 u32 cc_gc_shader_pipe_config = 0;
1292 u32 mc_arb_ramcfg;
1293 u32 db_debug4;
1294
1295 /* setup chip specs */
1296 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1297 case CHIP_RV770:
1298 dev_priv->r600_max_pipes = 4;
1299 dev_priv->r600_max_tile_pipes = 8;
1300 dev_priv->r600_max_simds = 10;
1301 dev_priv->r600_max_backends = 4;
1302 dev_priv->r600_max_gprs = 256;
1303 dev_priv->r600_max_threads = 248;
1304 dev_priv->r600_max_stack_entries = 512;
1305 dev_priv->r600_max_hw_contexts = 8;
1306 dev_priv->r600_max_gs_threads = 16 * 2;
1307 dev_priv->r600_sx_max_export_size = 128;
1308 dev_priv->r600_sx_max_export_pos_size = 16;
1309 dev_priv->r600_sx_max_export_smx_size = 112;
1310 dev_priv->r600_sq_num_cf_insts = 2;
1311
1312 dev_priv->r700_sx_num_of_sets = 7;
1313 dev_priv->r700_sc_prim_fifo_size = 0xF9;
1314 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
1315 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
1316 break;
1317 case CHIP_RV730:
1318 dev_priv->r600_max_pipes = 2;
1319 dev_priv->r600_max_tile_pipes = 4;
1320 dev_priv->r600_max_simds = 8;
1321 dev_priv->r600_max_backends = 2;
1322 dev_priv->r600_max_gprs = 128;
1323 dev_priv->r600_max_threads = 248;
1324 dev_priv->r600_max_stack_entries = 256;
1325 dev_priv->r600_max_hw_contexts = 8;
1326 dev_priv->r600_max_gs_threads = 16 * 2;
1327 dev_priv->r600_sx_max_export_size = 256;
1328 dev_priv->r600_sx_max_export_pos_size = 32;
1329 dev_priv->r600_sx_max_export_smx_size = 224;
1330 dev_priv->r600_sq_num_cf_insts = 2;
1331
1332 dev_priv->r700_sx_num_of_sets = 7;
1333 dev_priv->r700_sc_prim_fifo_size = 0xf9;
1334 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
1335 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
2a71ebcd
AD		 1336 if (dev_priv->r600_sx_max_export_pos_size > 16) {
1337 dev_priv->r600_sx_max_export_pos_size -= 16;
1338 dev_priv->r600_sx_max_export_smx_size += 16;
1339 }
c05ce083
AD		 1340 break;
1341 case CHIP_RV710:
1342 dev_priv->r600_max_pipes = 2;
1343 dev_priv->r600_max_tile_pipes = 2;
1344 dev_priv->r600_max_simds = 2;
1345 dev_priv->r600_max_backends = 1;
1346 dev_priv->r600_max_gprs = 256;
1347 dev_priv->r600_max_threads = 192;
1348 dev_priv->r600_max_stack_entries = 256;
1349 dev_priv->r600_max_hw_contexts = 4;
1350 dev_priv->r600_max_gs_threads = 8 * 2;
1351 dev_priv->r600_sx_max_export_size = 128;
1352 dev_priv->r600_sx_max_export_pos_size = 16;
1353 dev_priv->r600_sx_max_export_smx_size = 112;
1354 dev_priv->r600_sq_num_cf_insts = 1;
1355
1356 dev_priv->r700_sx_num_of_sets = 7;
1357 dev_priv->r700_sc_prim_fifo_size = 0x40;
1358 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
1359 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
1360 break;
2a71ebcd
AD		 1361 case CHIP_RV740:
1362 dev_priv->r600_max_pipes = 4;
1363 dev_priv->r600_max_tile_pipes = 4;
1364 dev_priv->r600_max_simds = 8;
1365 dev_priv->r600_max_backends = 4;
1366 dev_priv->r600_max_gprs = 256;
1367 dev_priv->r600_max_threads = 248;
1368 dev_priv->r600_max_stack_entries = 512;
1369 dev_priv->r600_max_hw_contexts = 8;
1370 dev_priv->r600_max_gs_threads = 16 * 2;
1371 dev_priv->r600_sx_max_export_size = 256;
1372 dev_priv->r600_sx_max_export_pos_size = 32;
1373 dev_priv->r600_sx_max_export_smx_size = 224;
1374 dev_priv->r600_sq_num_cf_insts = 2;
1375
1376 dev_priv->r700_sx_num_of_sets = 7;
1377 dev_priv->r700_sc_prim_fifo_size = 0x100;
1378 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
1379 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
1380
1381 if (dev_priv->r600_sx_max_export_pos_size > 16) {
1382 dev_priv->r600_sx_max_export_pos_size -= 16;
1383 dev_priv->r600_sx_max_export_smx_size += 16;
1384 }
1385 break;
c05ce083
AD		 1386 default:
1387 break;
1388 }
1389
1390 /* Initialize HDP */
1391 j = 0;
1392 for (i = 0; i < 32; i++) {
1393 RADEON_WRITE((0x2c14 + j), 0x00000000);
1394 RADEON_WRITE((0x2c18 + j), 0x00000000);
1395 RADEON_WRITE((0x2c1c + j), 0x00000000);
1396 RADEON_WRITE((0x2c20 + j), 0x00000000);
1397 RADEON_WRITE((0x2c24 + j), 0x00000000);
1398 j += 0x18;
1399 }
1400
1401 RADEON_WRITE(R600_GRBM_CNTL, R600_GRBM_READ_TIMEOUT(0xff));
1402
1403 /* setup tiling, simd, pipe config */
1404 mc_arb_ramcfg = RADEON_READ(R700_MC_ARB_RAMCFG);
1405
1406 switch (dev_priv->r600_max_tile_pipes) {
1407 case 1:
1408 gb_tiling_config |= R600_PIPE_TILING(0);
1409 break;
1410 case 2:
1411 gb_tiling_config |= R600_PIPE_TILING(1);
1412 break;
1413 case 4:
1414 gb_tiling_config |= R600_PIPE_TILING(2);
1415 break;
1416 case 8:
1417 gb_tiling_config |= R600_PIPE_TILING(3);
1418 break;
1419 default:
1420 break;
1421 }
1422
1423 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV770)
1424 gb_tiling_config |= R600_BANK_TILING(1);
1425 else
1426 gb_tiling_config |= R600_BANK_TILING((mc_arb_ramcfg >> R700_NOOFBANK_SHIFT) & R700_NOOFBANK_MASK);
1427
1428 gb_tiling_config |= R600_GROUP_SIZE(0);
1429
1430 if (((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK) > 3) {
1431 gb_tiling_config |= R600_ROW_TILING(3);
1432 gb_tiling_config |= R600_SAMPLE_SPLIT(3);
1433 } else {
1434 gb_tiling_config |=
1435 R600_ROW_TILING(((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK));
1436 gb_tiling_config |=
1437 R600_SAMPLE_SPLIT(((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK));
1438 }
1439
1440 gb_tiling_config |= R600_BANK_SWAPS(1);
1441
1442 backend_map = r700_get_tile_pipe_to_backend_map(dev_priv->r600_max_tile_pipes,
1443 dev_priv->r600_max_backends,
1444 (0xff << dev_priv->r600_max_backends) & 0xff);
1445 gb_tiling_config |= R600_BACKEND_MAP(backend_map);
1446
1447 cc_gc_shader_pipe_config =
1448 R600_INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << dev_priv->r600_max_pipes) & R7XX_MAX_PIPES_MASK);
1449 cc_gc_shader_pipe_config |=
1450 R600_INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << dev_priv->r600_max_simds) & R7XX_MAX_SIMDS_MASK);
1451
1452 cc_rb_backend_disable =
1453 R600_BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << dev_priv->r600_max_backends) & R7XX_MAX_BACKENDS_MASK);
1454
1455 RADEON_WRITE(R600_GB_TILING_CONFIG, gb_tiling_config);
1456 RADEON_WRITE(R600_DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
1457 RADEON_WRITE(R600_HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
961fb597
JG		 1458 if (gb_tiling_config & 0xc0) {
1459 dev_priv->r600_group_size = 512;
1460 } else {
1461 dev_priv->r600_group_size = 256;
1462 }
1463 dev_priv->r600_npipes = 1 << ((gb_tiling_config >> 1) & 0x7);
1464 if (gb_tiling_config & 0x30) {
1465 dev_priv->r600_nbanks = 8;
1466 } else {
1467 dev_priv->r600_nbanks = 4;
1468 }
c05ce083
AD		 1469
1470 RADEON_WRITE(R600_CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
1471 RADEON_WRITE(R600_CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
1472 RADEON_WRITE(R600_GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
1473
1474 RADEON_WRITE(R700_CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
1475 RADEON_WRITE(R700_CGTS_SYS_TCC_DISABLE, 0);
1476 RADEON_WRITE(R700_CGTS_TCC_DISABLE, 0);
1477 RADEON_WRITE(R700_CGTS_USER_SYS_TCC_DISABLE, 0);
1478 RADEON_WRITE(R700_CGTS_USER_TCC_DISABLE, 0);
1479
1480 num_qd_pipes =
1481 R7XX_MAX_BACKENDS - r600_count_pipe_bits(cc_gc_shader_pipe_config & R600_INACTIVE_QD_PIPES_MASK);
1482 RADEON_WRITE(R600_VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & R600_DEALLOC_DIST_MASK);
1483 RADEON_WRITE(R600_VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & R600_VTX_REUSE_DEPTH_MASK);
1484
1485 /* set HW defaults for 3D engine */
1486 RADEON_WRITE(R600_CP_QUEUE_THRESHOLDS, (R600_ROQ_IB1_START(0x16) |
1487 R600_ROQ_IB2_START(0x2b)));
1488
1489 RADEON_WRITE(R600_CP_MEQ_THRESHOLDS, R700_STQ_SPLIT(0x30));
1490
1491 RADEON_WRITE(R600_TA_CNTL_AUX, (R600_DISABLE_CUBE_ANISO |
1492 R600_SYNC_GRADIENT |
1493 R600_SYNC_WALKER |
1494 R600_SYNC_ALIGNER));
1495
1496 sx_debug_1 = RADEON_READ(R700_SX_DEBUG_1);
1497 sx_debug_1 |= R700_ENABLE_NEW_SMX_ADDRESS;
1498 RADEON_WRITE(R700_SX_DEBUG_1, sx_debug_1);
1499
1500 smx_dc_ctl0 = RADEON_READ(R600_SMX_DC_CTL0);
1501 smx_dc_ctl0 &= ~R700_CACHE_DEPTH(0x1ff);
1502 smx_dc_ctl0 |= R700_CACHE_DEPTH((dev_priv->r700_sx_num_of_sets * 64) - 1);
1503 RADEON_WRITE(R600_SMX_DC_CTL0, smx_dc_ctl0);
1504
1505 RADEON_WRITE(R700_SMX_EVENT_CTL, (R700_ES_FLUSH_CTL(4) |
1506 R700_GS_FLUSH_CTL(4) |
1507 R700_ACK_FLUSH_CTL(3) |
1508 R700_SYNC_FLUSH_CTL));
1509
1510 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV770)
1511 RADEON_WRITE(R700_DB_DEBUG3, R700_DB_CLK_OFF_DELAY(0x1f));
1512 else {
1513 db_debug4 = RADEON_READ(RV700_DB_DEBUG4);
1514 db_debug4 |= RV700_DISABLE_TILE_COVERED_FOR_PS_ITER;
1515 RADEON_WRITE(RV700_DB_DEBUG4, db_debug4);
1516 }
1517
1518 RADEON_WRITE(R600_SX_EXPORT_BUFFER_SIZES, (R600_COLOR_BUFFER_SIZE((dev_priv->r600_sx_max_export_size / 4) - 1) |
1519 R600_POSITION_BUFFER_SIZE((dev_priv->r600_sx_max_export_pos_size / 4) - 1) |
1520 R600_SMX_BUFFER_SIZE((dev_priv->r600_sx_max_export_smx_size / 4) - 1)));
1521
1522 RADEON_WRITE(R700_PA_SC_FIFO_SIZE_R7XX, (R700_SC_PRIM_FIFO_SIZE(dev_priv->r700_sc_prim_fifo_size) |
1523 R700_SC_HIZ_TILE_FIFO_SIZE(dev_priv->r700_sc_hiz_tile_fifo_size) |
1524 R700_SC_EARLYZ_TILE_FIFO_SIZE(dev_priv->r700_sc_earlyz_tile_fifo_fize)));
1525
1526 RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0);
1527
1528 RADEON_WRITE(R600_VGT_NUM_INSTANCES, 1);
1529
1530 RADEON_WRITE(R600_SPI_CONFIG_CNTL, R600_GPR_WRITE_PRIORITY(0));
1531
1532 RADEON_WRITE(R600_SPI_CONFIG_CNTL_1, R600_VTX_DONE_DELAY(4));
1533
1534 RADEON_WRITE(R600_CP_PERFMON_CNTL, 0);
1535
1536 sq_ms_fifo_sizes = (R600_CACHE_FIFO_SIZE(16 * dev_priv->r600_sq_num_cf_insts) |
1537 R600_DONE_FIFO_HIWATER(0xe0) |
1538 R600_ALU_UPDATE_FIFO_HIWATER(0x8));
1539 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1540 case CHIP_RV770:
1541 sq_ms_fifo_sizes |= R600_FETCH_FIFO_HIWATER(0x1);
1542 break;
1543 case CHIP_RV730:
1544 case CHIP_RV710:
2a71ebcd 1545 case CHIP_RV740:
c05ce083
AD		 1546 default:
1547 sq_ms_fifo_sizes |= R600_FETCH_FIFO_HIWATER(0x4);
1548 break;
1549 }
1550 RADEON_WRITE(R600_SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
1551
1552 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1553 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
1554 */
1555 sq_config = RADEON_READ(R600_SQ_CONFIG);
1556 sq_config &= ~(R600_PS_PRIO(3) |
1557 R600_VS_PRIO(3) |
1558 R600_GS_PRIO(3) |
1559 R600_ES_PRIO(3));
1560 sq_config |= (R600_DX9_CONSTS |
1561 R600_VC_ENABLE |
1562 R600_EXPORT_SRC_C |
1563 R600_PS_PRIO(0) |
1564 R600_VS_PRIO(1) |
1565 R600_GS_PRIO(2) |
1566 R600_ES_PRIO(3));
1567 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710)
1568 /* no vertex cache */
1569 sq_config &= ~R600_VC_ENABLE;
1570
1571 RADEON_WRITE(R600_SQ_CONFIG, sq_config);
1572
1573 RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_1, (R600_NUM_PS_GPRS((dev_priv->r600_max_gprs * 24)/64) |
1574 R600_NUM_VS_GPRS((dev_priv->r600_max_gprs * 24)/64) |
1575 R600_NUM_CLAUSE_TEMP_GPRS(((dev_priv->r600_max_gprs * 24)/64)/2)));
1576
1577 RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_2, (R600_NUM_GS_GPRS((dev_priv->r600_max_gprs * 7)/64) |
1578 R600_NUM_ES_GPRS((dev_priv->r600_max_gprs * 7)/64)));
1579
1580 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS((dev_priv->r600_max_threads * 4)/8) |
1581 R600_NUM_VS_THREADS((dev_priv->r600_max_threads * 2)/8) |
1582 R600_NUM_ES_THREADS((dev_priv->r600_max_threads * 1)/8));
1583 if (((dev_priv->r600_max_threads * 1) / 8) > dev_priv->r600_max_gs_threads)
1584 sq_thread_resource_mgmt |= R600_NUM_GS_THREADS(dev_priv->r600_max_gs_threads);
1585 else
1586 sq_thread_resource_mgmt |= R600_NUM_GS_THREADS((dev_priv->r600_max_gs_threads * 1)/8);
1587 RADEON_WRITE(R600_SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1588
1589 RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_1, (R600_NUM_PS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4) |
1590 R600_NUM_VS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4)));
1591
1592 RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_2, (R600_NUM_GS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4) |
1593 R600_NUM_ES_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4)));
1594
1595 sq_dyn_gpr_size_simd_ab_0 = (R700_SIMDA_RING0((dev_priv->r600_max_gprs * 38)/64) |
1596 R700_SIMDA_RING1((dev_priv->r600_max_gprs * 38)/64) |
1597 R700_SIMDB_RING0((dev_priv->r600_max_gprs * 38)/64) |
1598 R700_SIMDB_RING1((dev_priv->r600_max_gprs * 38)/64));
1599
1600 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0);
1601 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0);
1602 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0);
1603 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0);
1604 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0);
1605 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0);
1606 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0);
1607 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0);
1608
1609 RADEON_WRITE(R700_PA_SC_FORCE_EOV_MAX_CNTS, (R700_FORCE_EOV_MAX_CLK_CNT(4095) |
1610 R700_FORCE_EOV_MAX_REZ_CNT(255)));
1611
1612 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710)
1613 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, (R600_CACHE_INVALIDATION(R600_TC_ONLY) |
1614 R700_AUTO_INVLD_EN(R700_ES_AND_GS_AUTO)));
1615 else
1616 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, (R600_CACHE_INVALIDATION(R600_VC_AND_TC) |
1617 R700_AUTO_INVLD_EN(R700_ES_AND_GS_AUTO)));
1618
1619 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1620 case CHIP_RV770:
1621 case CHIP_RV730:
2a71ebcd 1622 case CHIP_RV740:
c05ce083
AD		 1623 gs_prim_buffer_depth = 384;
1624 break;
1625 case CHIP_RV710:
1626 gs_prim_buffer_depth = 128;
1627 break;
1628 default:
1629 break;
1630 }
1631
1632 num_gs_verts_per_thread = dev_priv->r600_max_pipes * 16;
1633 vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
1634 /* Max value for this is 256 */
1635 if (vgt_gs_per_es > 256)
1636 vgt_gs_per_es = 256;
1637
1638 RADEON_WRITE(R600_VGT_ES_PER_GS, 128);
1639 RADEON_WRITE(R600_VGT_GS_PER_ES, vgt_gs_per_es);
1640 RADEON_WRITE(R600_VGT_GS_PER_VS, 2);
1641
1642 /* more default values. 2D/3D driver should adjust as needed */
1643 RADEON_WRITE(R600_VGT_GS_VERTEX_REUSE, 16);
1644 RADEON_WRITE(R600_PA_SC_LINE_STIPPLE_STATE, 0);
1645 RADEON_WRITE(R600_VGT_STRMOUT_EN, 0);
1646 RADEON_WRITE(R600_SX_MISC, 0);
1647 RADEON_WRITE(R600_PA_SC_MODE_CNTL, 0);
1648 RADEON_WRITE(R700_PA_SC_EDGERULE, 0xaaaaaaaa);
1649 RADEON_WRITE(R600_PA_SC_AA_CONFIG, 0);
1650 RADEON_WRITE(R600_PA_SC_CLIPRECT_RULE, 0xffff);
1651 RADEON_WRITE(R600_PA_SC_LINE_STIPPLE, 0);
1652 RADEON_WRITE(R600_SPI_INPUT_Z, 0);
1653 RADEON_WRITE(R600_SPI_PS_IN_CONTROL_0, R600_NUM_INTERP(2));
1654 RADEON_WRITE(R600_CB_COLOR7_FRAG, 0);
1655
1656 /* clear render buffer base addresses */
1657 RADEON_WRITE(R600_CB_COLOR0_BASE, 0);
1658 RADEON_WRITE(R600_CB_COLOR1_BASE, 0);
1659 RADEON_WRITE(R600_CB_COLOR2_BASE, 0);
1660 RADEON_WRITE(R600_CB_COLOR3_BASE, 0);
1661 RADEON_WRITE(R600_CB_COLOR4_BASE, 0);
1662 RADEON_WRITE(R600_CB_COLOR5_BASE, 0);
1663 RADEON_WRITE(R600_CB_COLOR6_BASE, 0);
1664 RADEON_WRITE(R600_CB_COLOR7_BASE, 0);
1665
1666 RADEON_WRITE(R700_TCP_CNTL, 0);
1667
1668 hdp_host_path_cntl = RADEON_READ(R600_HDP_HOST_PATH_CNTL);
1669 RADEON_WRITE(R600_HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1670
1671 RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0);
1672
1673 RADEON_WRITE(R600_PA_CL_ENHANCE, (R600_CLIP_VTX_REORDER_ENA |
1674 R600_NUM_CLIP_SEQ(3)));
1675
1676}
1677
1678static void r600_cp_init_ring_buffer(struct drm_device *dev,
1679 drm_radeon_private_t *dev_priv,
1680 struct drm_file *file_priv)
1681{
1682 struct drm_radeon_master_private *master_priv;
1683 u32 ring_start;
6546bf6d 1684 u64 rptr_addr;
c05ce083
AD		 1685
1686 if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770))
1687 r700_gfx_init(dev, dev_priv);
1688 else
1689 r600_gfx_init(dev, dev_priv);
1690
1691 RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP);
1692 RADEON_READ(R600_GRBM_SOFT_RESET);
1693 DRM_UDELAY(15000);
1694 RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
1695
1696
1697 /* Set ring buffer size */
1698#ifdef __BIG_ENDIAN
1699 RADEON_WRITE(R600_CP_RB_CNTL,
1700 RADEON_BUF_SWAP_32BIT |
1701 RADEON_RB_NO_UPDATE |
1702 (dev_priv->ring.rptr_update_l2qw << 8) |
1703 dev_priv->ring.size_l2qw);
1704#else
1705 RADEON_WRITE(R600_CP_RB_CNTL,
1706 RADEON_RB_NO_UPDATE |
1707 (dev_priv->ring.rptr_update_l2qw << 8) |
1708 dev_priv->ring.size_l2qw);
1709#endif
1710
1711 RADEON_WRITE(R600_CP_SEM_WAIT_TIMER, 0x4);
1712
1713 /* Set the write pointer delay */
1714 RADEON_WRITE(R600_CP_RB_WPTR_DELAY, 0);
1715
1716#ifdef __BIG_ENDIAN
1717 RADEON_WRITE(R600_CP_RB_CNTL,
1718 RADEON_BUF_SWAP_32BIT |
1719 RADEON_RB_NO_UPDATE |
1720 RADEON_RB_RPTR_WR_ENA |
1721 (dev_priv->ring.rptr_update_l2qw << 8) |
1722 dev_priv->ring.size_l2qw);
1723#else
1724 RADEON_WRITE(R600_CP_RB_CNTL,
1725 RADEON_RB_NO_UPDATE |
1726 RADEON_RB_RPTR_WR_ENA |
1727 (dev_priv->ring.rptr_update_l2qw << 8) |
1728 dev_priv->ring.size_l2qw);
1729#endif
1730
1731 /* Initialize the ring buffer's read and write pointers */
1732 RADEON_WRITE(R600_CP_RB_RPTR_WR, 0);
1733 RADEON_WRITE(R600_CP_RB_WPTR, 0);
1734 SET_RING_HEAD(dev_priv, 0);
1735 dev_priv->ring.tail = 0;
1736
1737#if __OS_HAS_AGP
1738 if (dev_priv->flags & RADEON_IS_AGP) {
6546bf6d
DA		 1739 rptr_addr = dev_priv->ring_rptr->offset
1740 - dev->agp->base +
1741 dev_priv->gart_vm_start;
c05ce083
AD		 1742 } else
1743#endif
1744 {
6546bf6d
DA		 1745 rptr_addr = dev_priv->ring_rptr->offset
1746 - ((unsigned long) dev->sg->virtual)
1747 + dev_priv->gart_vm_start;
c05ce083 1748 }
6546bf6d
DA		 1749 RADEON_WRITE(R600_CP_RB_RPTR_ADDR,
1750 rptr_addr & 0xffffffff);
1751 RADEON_WRITE(R600_CP_RB_RPTR_ADDR_HI,
1752 upper_32_bits(rptr_addr));
c05ce083
AD		 1753
1754#ifdef __BIG_ENDIAN
1755 RADEON_WRITE(R600_CP_RB_CNTL,
1756 RADEON_BUF_SWAP_32BIT |
1757 (dev_priv->ring.rptr_update_l2qw << 8) |
1758 dev_priv->ring.size_l2qw);
1759#else
1760 RADEON_WRITE(R600_CP_RB_CNTL,
1761 (dev_priv->ring.rptr_update_l2qw << 8) |
1762 dev_priv->ring.size_l2qw);
1763#endif
1764
1765#if __OS_HAS_AGP
1766 if (dev_priv->flags & RADEON_IS_AGP) {
1767 /* XXX */
1768 radeon_write_agp_base(dev_priv, dev->agp->base);
1769
1770 /* XXX */
1771 radeon_write_agp_location(dev_priv,
1772 (((dev_priv->gart_vm_start - 1 +
1773 dev_priv->gart_size) & 0xffff0000) |
1774 (dev_priv->gart_vm_start >> 16)));
1775
1776 ring_start = (dev_priv->cp_ring->offset
1777 - dev->agp->base
1778 + dev_priv->gart_vm_start);
1779 } else
1780#endif
1781 ring_start = (dev_priv->cp_ring->offset
1782 - (unsigned long)dev->sg->virtual
1783 + dev_priv->gart_vm_start);
1784
1785 RADEON_WRITE(R600_CP_RB_BASE, ring_start >> 8);
1786
1787 RADEON_WRITE(R600_CP_ME_CNTL, 0xff);
1788
1789 RADEON_WRITE(R600_CP_DEBUG, (1 << 27) | (1 << 28));
1790
c05ce083
AD		 1791 /* Initialize the scratch register pointer. This will cause
1792 * the scratch register values to be written out to memory
1793 * whenever they are updated.
1794 *
1795 * We simply put this behind the ring read pointer, this works
1796 * with PCI GART as well as (whatever kind of) AGP GART
1797 */
6546bf6d
DA		 1798 {
1799 u64 scratch_addr;
1800
1801 scratch_addr = RADEON_READ(R600_CP_RB_RPTR_ADDR);
1802 scratch_addr |= ((u64)RADEON_READ(R600_CP_RB_RPTR_ADDR_HI)) << 32;
1803 scratch_addr += R600_SCRATCH_REG_OFFSET;
1804 scratch_addr >>= 8;
1805 scratch_addr &= 0xffffffff;
1806
1807 RADEON_WRITE(R600_SCRATCH_ADDR, (uint32_t)scratch_addr);
1808 }
c05ce083
AD		 1809
1810 RADEON_WRITE(R600_SCRATCH_UMSK, 0x7);
1811
1812 /* Turn on bus mastering */
1813 radeon_enable_bm(dev_priv);
1814
1815 radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(0), 0);
1816 RADEON_WRITE(R600_LAST_FRAME_REG, 0);
1817
1818 radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(1), 0);
1819 RADEON_WRITE(R600_LAST_DISPATCH_REG, 0);
1820
1821 radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(2), 0);
1822 RADEON_WRITE(R600_LAST_CLEAR_REG, 0);
1823
1824 /* reset sarea copies of these */
1825 master_priv = file_priv->master->driver_priv;
1826 if (master_priv->sarea_priv) {
1827 master_priv->sarea_priv->last_frame = 0;
1828 master_priv->sarea_priv->last_dispatch = 0;
1829 master_priv->sarea_priv->last_clear = 0;
1830 }
1831
1832 r600_do_wait_for_idle(dev_priv);
1833
1834}
1835
1836int r600_do_cleanup_cp(struct drm_device *dev)
1837{
1838 drm_radeon_private_t *dev_priv = dev->dev_private;
1839 DRM_DEBUG("\n");
1840
1841 /* Make sure interrupts are disabled here because the uninstall ioctl
1842 * may not have been called from userspace and after dev_private
1843 * is freed, it's too late.
1844 */
1845 if (dev->irq_enabled)
1846 drm_irq_uninstall(dev);
1847
1848#if __OS_HAS_AGP
1849 if (dev_priv->flags & RADEON_IS_AGP) {
1850 if (dev_priv->cp_ring != NULL) {
1851 drm_core_ioremapfree(dev_priv->cp_ring, dev);
1852 dev_priv->cp_ring = NULL;
1853 }
1854 if (dev_priv->ring_rptr != NULL) {
1855 drm_core_ioremapfree(dev_priv->ring_rptr, dev);
1856 dev_priv->ring_rptr = NULL;
1857 }
1858 if (dev->agp_buffer_map != NULL) {
1859 drm_core_ioremapfree(dev->agp_buffer_map, dev);
1860 dev->agp_buffer_map = NULL;
1861 }
1862 } else
1863#endif
1864 {
1865
1866 if (dev_priv->gart_info.bus_addr)
1867 r600_page_table_cleanup(dev, &dev_priv->gart_info);
1868
1869 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB) {
1870 drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
8f497aad 1871 dev_priv->gart_info.addr = NULL;
c05ce083
AD		 1872 }
1873 }
1874 /* only clear to the start of flags */
1875 memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1876
1877 return 0;
1878}
1879
1880int r600_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
1881 struct drm_file *file_priv)
1882{
1883 drm_radeon_private_t *dev_priv = dev->dev_private;
1884 struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv;
1885
1886 DRM_DEBUG("\n");
1887
3ce0a23d
JG		 1888 mutex_init(&dev_priv->cs_mutex);
1889 r600_cs_legacy_init();
c05ce083
AD		 1890 /* if we require new memory map but we don't have it fail */
1891 if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
1892 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
1893 r600_do_cleanup_cp(dev);
1894 return -EINVAL;
1895 }
1896
1897 if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) {
1898 DRM_DEBUG("Forcing AGP card to PCI mode\n");
1899 dev_priv->flags &= ~RADEON_IS_AGP;
1900 /* The writeback test succeeds, but when writeback is enabled,
1901 * the ring buffer read ptr update fails after first 128 bytes.
1902 */
1903 radeon_no_wb = 1;
1904 } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
1905 && !init->is_pci) {
1906 DRM_DEBUG("Restoring AGP flag\n");
1907 dev_priv->flags |= RADEON_IS_AGP;
1908 }
1909
1910 dev_priv->usec_timeout = init->usec_timeout;
1911 if (dev_priv->usec_timeout < 1 ||
1912 dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
1913 DRM_DEBUG("TIMEOUT problem!\n");
1914 r600_do_cleanup_cp(dev);
1915 return -EINVAL;
1916 }
1917
1918 /* Enable vblank on CRTC1 for older X servers
1919 */
1920 dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
3ce0a23d 1921 dev_priv->do_boxes = 0;
c05ce083
AD		 1922 dev_priv->cp_mode = init->cp_mode;
1923
1924 /* We don't support anything other than bus-mastering ring mode,
1925 * but the ring can be in either AGP or PCI space for the ring
1926 * read pointer.
1927 */
1928 if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
1929 (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
1930 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
1931 r600_do_cleanup_cp(dev);
1932 return -EINVAL;
1933 }
1934
1935 switch (init->fb_bpp) {
1936 case 16:
1937 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
1938 break;
1939 case 32:
1940 default:
1941 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
1942 break;
1943 }
1944 dev_priv->front_offset = init->front_offset;
1945 dev_priv->front_pitch = init->front_pitch;
1946 dev_priv->back_offset = init->back_offset;
1947 dev_priv->back_pitch = init->back_pitch;
1948
1949 dev_priv->ring_offset = init->ring_offset;
1950 dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1951 dev_priv->buffers_offset = init->buffers_offset;
1952 dev_priv->gart_textures_offset = init->gart_textures_offset;
1953
1954 master_priv->sarea = drm_getsarea(dev);
1955 if (!master_priv->sarea) {
1956 DRM_ERROR("could not find sarea!\n");
1957 r600_do_cleanup_cp(dev);
1958 return -EINVAL;
1959 }
1960
1961 dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
1962 if (!dev_priv->cp_ring) {
1963 DRM_ERROR("could not find cp ring region!\n");
1964 r600_do_cleanup_cp(dev);
1965 return -EINVAL;
1966 }
1967 dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
1968 if (!dev_priv->ring_rptr) {
1969 DRM_ERROR("could not find ring read pointer!\n");
1970 r600_do_cleanup_cp(dev);
1971 return -EINVAL;
1972 }
1973 dev->agp_buffer_token = init->buffers_offset;
1974 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
1975 if (!dev->agp_buffer_map) {
1976 DRM_ERROR("could not find dma buffer region!\n");
1977 r600_do_cleanup_cp(dev);
1978 return -EINVAL;
1979 }
1980
1981 if (init->gart_textures_offset) {
1982 dev_priv->gart_textures =
1983 drm_core_findmap(dev, init->gart_textures_offset);
1984 if (!dev_priv->gart_textures) {
1985 DRM_ERROR("could not find GART texture region!\n");
1986 r600_do_cleanup_cp(dev);
1987 return -EINVAL;
1988 }
1989 }
1990
1991#if __OS_HAS_AGP
1992 /* XXX */
1993 if (dev_priv->flags & RADEON_IS_AGP) {
7659e980
AD		 1994 drm_core_ioremap_wc(dev_priv->cp_ring, dev);
1995 drm_core_ioremap_wc(dev_priv->ring_rptr, dev);
1996 drm_core_ioremap_wc(dev->agp_buffer_map, dev);
c05ce083
AD		 1997 if (!dev_priv->cp_ring->handle ||
1998 !dev_priv->ring_rptr->handle ||
1999 !dev->agp_buffer_map->handle) {
2000 DRM_ERROR("could not find ioremap agp regions!\n");
2001 r600_do_cleanup_cp(dev);
2002 return -EINVAL;
2003 }
2004 } else
2005#endif
2006 {
3ce0a23d 2007 dev_priv->cp_ring->handle = (void *)(unsigned long)dev_priv->cp_ring->offset;
c05ce083 2008 dev_priv->ring_rptr->handle =
3ce0a23d 2009 (void *)(unsigned long)dev_priv->ring_rptr->offset;
c05ce083 2010 dev->agp_buffer_map->handle =
3ce0a23d 2011 (void *)(unsigned long)dev->agp_buffer_map->offset;
c05ce083
AD		 2012
2013 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
2014 dev_priv->cp_ring->handle);
2015 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
2016 dev_priv->ring_rptr->handle);
2017 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
2018 dev->agp_buffer_map->handle);
2019 }
2020
2021 dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 24;
2022 dev_priv->fb_size =
2023 (((radeon_read_fb_location(dev_priv) & 0xffff0000u) << 8) + 0x1000000)
2024 - dev_priv->fb_location;
2025
2026 dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
2027 ((dev_priv->front_offset
2028 + dev_priv->fb_location) >> 10));
2029
2030 dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
2031 ((dev_priv->back_offset
2032 + dev_priv->fb_location) >> 10));
2033
2034 dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
2035 ((dev_priv->depth_offset
2036 + dev_priv->fb_location) >> 10));
2037
2038 dev_priv->gart_size = init->gart_size;
2039
2040 /* New let's set the memory map ... */
2041 if (dev_priv->new_memmap) {
2042 u32 base = 0;
2043
2044 DRM_INFO("Setting GART location based on new memory map\n");
2045
2046 /* If using AGP, try to locate the AGP aperture at the same
2047 * location in the card and on the bus, though we have to
2048 * align it down.
2049 */
2050#if __OS_HAS_AGP
2051 /* XXX */
2052 if (dev_priv->flags & RADEON_IS_AGP) {
2053 base = dev->agp->base;
2054 /* Check if valid */
2055 if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
2056 base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
2057 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
2058 dev->agp->base);
2059 base = 0;
2060 }
2061 }
2062#endif
2063 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
2064 if (base == 0) {
2065 base = dev_priv->fb_location + dev_priv->fb_size;
2066 if (base < dev_priv->fb_location ||
2067 ((base + dev_priv->gart_size) & 0xfffffffful) < base)
2068 base = dev_priv->fb_location
2069 - dev_priv->gart_size;
2070 }
2071 dev_priv->gart_vm_start = base & 0xffc00000u;
2072 if (dev_priv->gart_vm_start != base)
2073 DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
2074 base, dev_priv->gart_vm_start);
2075 }
2076
2077#if __OS_HAS_AGP
2078 /* XXX */
2079 if (dev_priv->flags & RADEON_IS_AGP)
2080 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
2081 - dev->agp->base
2082 + dev_priv->gart_vm_start);
2083 else
2084#endif
2085 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
2086 - (unsigned long)dev->sg->virtual
2087 + dev_priv->gart_vm_start);
2088
2089 DRM_DEBUG("fb 0x%08x size %d\n",
2090 (unsigned int) dev_priv->fb_location,
2091 (unsigned int) dev_priv->fb_size);
2092 DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
2093 DRM_DEBUG("dev_priv->gart_vm_start 0x%08x\n",
2094 (unsigned int) dev_priv->gart_vm_start);
2095 DRM_DEBUG("dev_priv->gart_buffers_offset 0x%08lx\n",
2096 dev_priv->gart_buffers_offset);
2097
2098 dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
2099 dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
2100 + init->ring_size / sizeof(u32));
2101 dev_priv->ring.size = init->ring_size;
2102 dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
2103
2104 dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
2105 dev_priv->ring.rptr_update_l2qw = drm_order(/* init->rptr_update */ 4096 / 8);
2106
2107 dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
2108 dev_priv->ring.fetch_size_l2ow = drm_order(/* init->fetch_size */ 32 / 16);
2109
2110 dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
2111
2112 dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
2113
2114#if __OS_HAS_AGP
2115 if (dev_priv->flags & RADEON_IS_AGP) {
2116 /* XXX turn off pcie gart */
2117 } else
2118#endif
2119 {
2120 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
2121 /* if we have an offset set from userspace */
2122 if (!dev_priv->pcigart_offset_set) {
2123 DRM_ERROR("Need gart offset from userspace\n");
2124 r600_do_cleanup_cp(dev);
2125 return -EINVAL;
2126 }
2127
2128 DRM_DEBUG("Using gart offset 0x%08lx\n", dev_priv->pcigart_offset);
2129
2130 dev_priv->gart_info.bus_addr =
2131 dev_priv->pcigart_offset + dev_priv->fb_location;
2132 dev_priv->gart_info.mapping.offset =
2133 dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
2134 dev_priv->gart_info.mapping.size =
2135 dev_priv->gart_info.table_size;
2136
2137 drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev);
2138 if (!dev_priv->gart_info.mapping.handle) {
2139 DRM_ERROR("ioremap failed.\n");
2140 r600_do_cleanup_cp(dev);
2141 return -EINVAL;
2142 }
2143
2144 dev_priv->gart_info.addr =
2145 dev_priv->gart_info.mapping.handle;
2146
2147 DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
2148 dev_priv->gart_info.addr,
2149 dev_priv->pcigart_offset);
2150
41f13fe8 2151 if (!r600_page_table_init(dev)) {
c05ce083
AD		 2152 DRM_ERROR("Failed to init GART table\n");
2153 r600_do_cleanup_cp(dev);
2154 return -EINVAL;
2155 }
2156
2157 if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770))
2158 r700_vm_init(dev);
2159 else
2160 r600_vm_init(dev);
2161 }
2162
70967ab9
BH		 2163 if (!dev_priv->me_fw || !dev_priv->pfp_fw) {
2164 int err = r600_cp_init_microcode(dev_priv);
2165 if (err) {
2166 DRM_ERROR("Failed to load firmware!\n");
2167 r600_do_cleanup_cp(dev);
2168 return err;
2169 }
2170 }
c05ce083
AD		 2171 if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770))
2172 r700_cp_load_microcode(dev_priv);
2173 else
2174 r600_cp_load_microcode(dev_priv);
2175
2176 r600_cp_init_ring_buffer(dev, dev_priv, file_priv);
2177
2178 dev_priv->last_buf = 0;
2179
2180 r600_do_engine_reset(dev);
2181 r600_test_writeback(dev_priv);
2182
2183 return 0;
2184}
2185
2186int r600_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv)
2187{
2188 drm_radeon_private_t *dev_priv = dev->dev_private;
2189
2190 DRM_DEBUG("\n");
2191 if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)) {
2192 r700_vm_init(dev);
2193 r700_cp_load_microcode(dev_priv);
2194 } else {
2195 r600_vm_init(dev);
2196 r600_cp_load_microcode(dev_priv);
2197 }
2198 r600_cp_init_ring_buffer(dev, dev_priv, file_priv);
2199 r600_do_engine_reset(dev);
2200
2201 return 0;
2202}
2203
2204/* Wait for the CP to go idle.
2205 */
2206int r600_do_cp_idle(drm_radeon_private_t *dev_priv)
2207{
2208 RING_LOCALS;
2209 DRM_DEBUG("\n");
2210
2211 BEGIN_RING(5);
2212 OUT_RING(CP_PACKET3(R600_IT_EVENT_WRITE, 0));
2213 OUT_RING(R600_CACHE_FLUSH_AND_INV_EVENT);
2214 /* wait for 3D idle clean */
2215 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1));
2216 OUT_RING((R600_WAIT_UNTIL - R600_SET_CONFIG_REG_OFFSET) >> 2);
2217 OUT_RING(RADEON_WAIT_3D_IDLE | RADEON_WAIT_3D_IDLECLEAN);
2218
2219 ADVANCE_RING();
2220 COMMIT_RING();
2221
2222 return r600_do_wait_for_idle(dev_priv);
2223}
2224
2225/* Start the Command Processor.
2226 */
2227void r600_do_cp_start(drm_radeon_private_t *dev_priv)
2228{
2229 u32 cp_me;
2230 RING_LOCALS;
2231 DRM_DEBUG("\n");
2232
2233 BEGIN_RING(7);
2234 OUT_RING(CP_PACKET3(R600_IT_ME_INITIALIZE, 5));
2235 OUT_RING(0x00000001);
2236 if (((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV770))
2237 OUT_RING(0x00000003);
2238 else
2239 OUT_RING(0x00000000);
2240 OUT_RING((dev_priv->r600_max_hw_contexts - 1));
2241 OUT_RING(R600_ME_INITIALIZE_DEVICE_ID(1));
2242 OUT_RING(0x00000000);
2243 OUT_RING(0x00000000);
2244 ADVANCE_RING();
2245 COMMIT_RING();
2246
2247 /* set the mux and reset the halt bit */
2248 cp_me = 0xff;
2249 RADEON_WRITE(R600_CP_ME_CNTL, cp_me);
2250
2251 dev_priv->cp_running = 1;
2252
2253}
2254
2255void r600_do_cp_reset(drm_radeon_private_t *dev_priv)
2256{
2257 u32 cur_read_ptr;
2258 DRM_DEBUG("\n");
2259
2260 cur_read_ptr = RADEON_READ(R600_CP_RB_RPTR);
2261 RADEON_WRITE(R600_CP_RB_WPTR, cur_read_ptr);
2262 SET_RING_HEAD(dev_priv, cur_read_ptr);
2263 dev_priv->ring.tail = cur_read_ptr;
2264}
2265
2266void r600_do_cp_stop(drm_radeon_private_t *dev_priv)
2267{
2268 uint32_t cp_me;
2269
2270 DRM_DEBUG("\n");
2271
2272 cp_me = 0xff | R600_CP_ME_HALT;
2273
2274 RADEON_WRITE(R600_CP_ME_CNTL, cp_me);
2275
2276 dev_priv->cp_running = 0;
2277}
2278
2279int r600_cp_dispatch_indirect(struct drm_device *dev,
2280 struct drm_buf *buf, int start, int end)
2281{
2282 drm_radeon_private_t *dev_priv = dev->dev_private;
2283 RING_LOCALS;
2284
2285 if (start != end) {
2286 unsigned long offset = (dev_priv->gart_buffers_offset
2287 + buf->offset + start);
2288 int dwords = (end - start + 3) / sizeof(u32);
2289
2290 DRM_DEBUG("dwords:%d\n", dwords);
2291 DRM_DEBUG("offset 0x%lx\n", offset);
2292
2293
2294 /* Indirect buffer data must be a multiple of 16 dwords.
2295 * pad the data with a Type-2 CP packet.
2296 */
2297 while (dwords & 0xf) {
2298 u32 *data = (u32 *)
2299 ((char *)dev->agp_buffer_map->handle
2300 + buf->offset + start);
2301 data[dwords++] = RADEON_CP_PACKET2;
2302 }
2303
2304 /* Fire off the indirect buffer */
2305 BEGIN_RING(4);
2306 OUT_RING(CP_PACKET3(R600_IT_INDIRECT_BUFFER, 2));
2307 OUT_RING((offset & 0xfffffffc));
2308 OUT_RING((upper_32_bits(offset) & 0xff));
2309 OUT_RING(dwords);
2310 ADVANCE_RING();
2311 }
2312
2313 return 0;
2314}
3ce0a23d
JG		 2315
2316void r600_cp_dispatch_swap(struct drm_device *dev, struct drm_file *file_priv)
2317{
2318 drm_radeon_private_t *dev_priv = dev->dev_private;
2319 struct drm_master *master = file_priv->master;
2320 struct drm_radeon_master_private *master_priv = master->driver_priv;
2321 drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv;
2322 int nbox = sarea_priv->nbox;
2323 struct drm_clip_rect *pbox = sarea_priv->boxes;
2324 int i, cpp, src_pitch, dst_pitch;
2325 uint64_t src, dst;
2326 RING_LOCALS;
2327 DRM_DEBUG("\n");
2328
2329 if (dev_priv->color_fmt == RADEON_COLOR_FORMAT_ARGB8888)
2330 cpp = 4;
2331 else
2332 cpp = 2;
2333
2334 if (sarea_priv->pfCurrentPage == 0) {
2335 src_pitch = dev_priv->back_pitch;
2336 dst_pitch = dev_priv->front_pitch;
2337 src = dev_priv->back_offset + dev_priv->fb_location;
2338 dst = dev_priv->front_offset + dev_priv->fb_location;
2339 } else {
2340 src_pitch = dev_priv->front_pitch;
2341 dst_pitch = dev_priv->back_pitch;
2342 src = dev_priv->front_offset + dev_priv->fb_location;
2343 dst = dev_priv->back_offset + dev_priv->fb_location;
2344 }
2345
2346 if (r600_prepare_blit_copy(dev, file_priv)) {
2347 DRM_ERROR("unable to allocate vertex buffer for swap buffer\n");
2348 return;
2349 }
2350 for (i = 0; i < nbox; i++) {
2351 int x = pbox[i].x1;
2352 int y = pbox[i].y1;
2353 int w = pbox[i].x2 - x;
2354 int h = pbox[i].y2 - y;
2355
2356 DRM_DEBUG("%d,%d-%d,%d\n", x, y, w, h);
2357
2358 r600_blit_swap(dev,
2359 src, dst,
2360 x, y, x, y, w, h,
2361 src_pitch, dst_pitch, cpp);
2362 }
2363 r600_done_blit_copy(dev);
2364
2365 /* Increment the frame counter. The client-side 3D driver must
2366 * throttle the framerate by waiting for this value before
2367 * performing the swapbuffer ioctl.
2368 */
2369 sarea_priv->last_frame++;
2370
2371 BEGIN_RING(3);
2372 R600_FRAME_AGE(sarea_priv->last_frame);
2373 ADVANCE_RING();
2374}
2375
2376int r600_cp_dispatch_texture(struct drm_device *dev,
2377 struct drm_file *file_priv,
2378 drm_radeon_texture_t *tex,
2379 drm_radeon_tex_image_t *image)
2380{
2381 drm_radeon_private_t *dev_priv = dev->dev_private;
2382 struct drm_buf *buf;
2383 u32 *buffer;
2384 const u8 __user *data;
2385 int size, pass_size;
2386 u64 src_offset, dst_offset;
2387
2388 if (!radeon_check_offset(dev_priv, tex->offset)) {
2389 DRM_ERROR("Invalid destination offset\n");
2390 return -EINVAL;
2391 }
2392
2393 /* this might fail for zero-sized uploads - are those illegal? */
2394 if (!radeon_check_offset(dev_priv, tex->offset + tex->height * tex->pitch - 1)) {
2395 DRM_ERROR("Invalid final destination offset\n");
2396 return -EINVAL;
2397 }
2398
2399 size = tex->height * tex->pitch;
2400
2401 if (size == 0)
2402 return 0;
2403
2404 dst_offset = tex->offset;
2405
2406 if (r600_prepare_blit_copy(dev, file_priv)) {
2407 DRM_ERROR("unable to allocate vertex buffer for swap buffer\n");
2408 return -EAGAIN;
2409 }
2410 do {
2411 data = (const u8 __user *)image->data;
2412 pass_size = size;
2413
2414 buf = radeon_freelist_get(dev);
2415 if (!buf) {
2416 DRM_DEBUG("EAGAIN\n");
2417 if (DRM_COPY_TO_USER(tex->image, image, sizeof(*image)))
2418 return -EFAULT;
2419 return -EAGAIN;
2420 }
2421
2422 if (pass_size > buf->total)
2423 pass_size = buf->total;
2424
2425 /* Dispatch the indirect buffer.
2426 */
2427 buffer =
2428 (u32 *) ((char *)dev->agp_buffer_map->handle + buf->offset);
2429
2430 if (DRM_COPY_FROM_USER(buffer, data, pass_size)) {
2431 DRM_ERROR("EFAULT on pad, %d bytes\n", pass_size);
2432 return -EFAULT;
2433 }
2434
2435 buf->file_priv = file_priv;
2436 buf->used = pass_size;
2437 src_offset = dev_priv->gart_buffers_offset + buf->offset;
2438
2439 r600_blit_copy(dev, src_offset, dst_offset, pass_size);
2440
2441 radeon_cp_discard_buffer(dev, file_priv->master, buf);
2442
2443 /* Update the input parameters for next time */
2444 image->data = (const u8 __user *)image->data + pass_size;
2445 dst_offset += pass_size;
2446 size -= pass_size;
2447 } while (size > 0);
2448 r600_done_blit_copy(dev);
2449
2450 return 0;
2451}
2452
2453/*
2454 * Legacy cs ioctl
2455 */
2456static u32 radeon_cs_id_get(struct drm_radeon_private *radeon)
2457{
2458 /* FIXME: check if wrap affect last reported wrap & sequence */
2459 radeon->cs_id_scnt = (radeon->cs_id_scnt + 1) & 0x00FFFFFF;
2460 if (!radeon->cs_id_scnt) {
2461 /* increment wrap counter */
2462 radeon->cs_id_wcnt += 0x01000000;
2463 /* valid sequence counter start at 1 */
2464 radeon->cs_id_scnt = 1;
2465 }
2466 return (radeon->cs_id_scnt | radeon->cs_id_wcnt);
2467}
2468
2469static void r600_cs_id_emit(drm_radeon_private_t *dev_priv, u32 *id)
2470{
2471 RING_LOCALS;
2472
2473 *id = radeon_cs_id_get(dev_priv);
2474
2475 /* SCRATCH 2 */
2476 BEGIN_RING(3);
2477 R600_CLEAR_AGE(*id);
2478 ADVANCE_RING();
2479 COMMIT_RING();
2480}
2481
2482static int r600_ib_get(struct drm_device *dev,
2483 struct drm_file *fpriv,
2484 struct drm_buf **buffer)
2485{
2486 struct drm_buf *buf;
2487
2488 *buffer = NULL;
2489 buf = radeon_freelist_get(dev);
2490 if (!buf) {
2491 return -EBUSY;
2492 }
2493 buf->file_priv = fpriv;
2494 *buffer = buf;
2495 return 0;
2496}
2497
2498static void r600_ib_free(struct drm_device *dev, struct drm_buf *buf,
2499 struct drm_file *fpriv, int l, int r)
2500{
2501 drm_radeon_private_t *dev_priv = dev->dev_private;
2502
2503 if (buf) {
2504 if (!r)
2505 r600_cp_dispatch_indirect(dev, buf, 0, l * 4);
2506 radeon_cp_discard_buffer(dev, fpriv->master, buf);
2507 COMMIT_RING();
2508 }
2509}
2510
2511int r600_cs_legacy_ioctl(struct drm_device *dev, void *data, struct drm_file *fpriv)
2512{
2513 struct drm_radeon_private *dev_priv = dev->dev_private;
2514 struct drm_radeon_cs *cs = data;
2515 struct drm_buf *buf;
2516 unsigned family;
2517 int l, r = 0;
2518 u32 *ib, cs_id = 0;
2519
2520 if (dev_priv == NULL) {
2521 DRM_ERROR("called with no initialization\n");
2522 return -EINVAL;
2523 }
2524 family = dev_priv->flags & RADEON_FAMILY_MASK;
2525 if (family < CHIP_R600) {
2526 DRM_ERROR("cs ioctl valid only for R6XX & R7XX in legacy mode\n");
2527 return -EINVAL;
2528 }
2529 mutex_lock(&dev_priv->cs_mutex);
2530 /* get ib */
2531 r = r600_ib_get(dev, fpriv, &buf);
2532 if (r) {
2533 DRM_ERROR("ib_get failed\n");
2534 goto out;
2535 }
2536 ib = dev->agp_buffer_map->handle + buf->offset;
2537 /* now parse command stream */
2538 r = r600_cs_legacy(dev, data, fpriv, family, ib, &l);
2539 if (r) {
2540 goto out;
2541 }
2542
2543out:
2544 r600_ib_free(dev, buf, fpriv, l, r);
2545 /* emit cs id sequence */
2546 r600_cs_id_emit(dev_priv, &cs_id);
2547 cs->cs_id = cs_id;
2548 mutex_unlock(&dev_priv->cs_mutex);
2549 return r;
2550}
961fb597
JG		 2551
2552void r600_cs_legacy_get_tiling_conf(struct drm_device *dev, u32 *npipes, u32 *nbanks, u32 *group_size)
2553{
2554 struct drm_radeon_private *dev_priv = dev->dev_private;
2555
2556 *npipes = dev_priv->r600_npipes;
2557 *nbanks = dev_priv->r600_nbanks;
2558 *group_size = dev_priv->r600_group_size;
2559}
Clone of davem's net-next-2.6 tree