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drm/radeon/kms/pm: add asic specific callbacks for getting power state (v2)
[net-next-2.6.git] / drivers / gpu / drm / radeon / r600.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
5a0e3ad6 28#include <linux/slab.h>
3ce0a23d
JG		 29#include <linux/seq_file.h>
30#include <linux/firmware.h>
31#include <linux/platform_device.h>
771fe6b9 32#include "drmP.h"
3ce0a23d 33#include "radeon_drm.h"
771fe6b9 34#include "radeon.h"
e6990375 35#include "radeon_asic.h"
3ce0a23d 36#include "radeon_mode.h"
3ce0a23d 37#include "r600d.h"
3ce0a23d 38#include "atom.h"
d39c3b89 39#include "avivod.h"
771fe6b9 40
3ce0a23d
JG		 41#define PFP_UCODE_SIZE 576
42#define PM4_UCODE_SIZE 1792
d8f60cfc 43#define RLC_UCODE_SIZE 768
3ce0a23d
JG		 44#define R700_PFP_UCODE_SIZE 848
45#define R700_PM4_UCODE_SIZE 1360
d8f60cfc 46#define R700_RLC_UCODE_SIZE 1024
fe251e2f
AD		 47#define EVERGREEN_PFP_UCODE_SIZE 1120
48#define EVERGREEN_PM4_UCODE_SIZE 1376
45f9a39b 49#define EVERGREEN_RLC_UCODE_SIZE 768
3ce0a23d
JG		 50
51/* Firmware Names */
52MODULE_FIRMWARE("radeon/R600_pfp.bin");
53MODULE_FIRMWARE("radeon/R600_me.bin");
54MODULE_FIRMWARE("radeon/RV610_pfp.bin");
55MODULE_FIRMWARE("radeon/RV610_me.bin");
56MODULE_FIRMWARE("radeon/RV630_pfp.bin");
57MODULE_FIRMWARE("radeon/RV630_me.bin");
58MODULE_FIRMWARE("radeon/RV620_pfp.bin");
59MODULE_FIRMWARE("radeon/RV620_me.bin");
60MODULE_FIRMWARE("radeon/RV635_pfp.bin");
61MODULE_FIRMWARE("radeon/RV635_me.bin");
62MODULE_FIRMWARE("radeon/RV670_pfp.bin");
63MODULE_FIRMWARE("radeon/RV670_me.bin");
64MODULE_FIRMWARE("radeon/RS780_pfp.bin");
65MODULE_FIRMWARE("radeon/RS780_me.bin");
66MODULE_FIRMWARE("radeon/RV770_pfp.bin");
67MODULE_FIRMWARE("radeon/RV770_me.bin");
68MODULE_FIRMWARE("radeon/RV730_pfp.bin");
69MODULE_FIRMWARE("radeon/RV730_me.bin");
70MODULE_FIRMWARE("radeon/RV710_pfp.bin");
71MODULE_FIRMWARE("radeon/RV710_me.bin");
d8f60cfc
AD		 72MODULE_FIRMWARE("radeon/R600_rlc.bin");
73MODULE_FIRMWARE("radeon/R700_rlc.bin");
fe251e2f
AD		 74MODULE_FIRMWARE("radeon/CEDAR_pfp.bin");
75MODULE_FIRMWARE("radeon/CEDAR_me.bin");
45f9a39b 76MODULE_FIRMWARE("radeon/CEDAR_rlc.bin");
fe251e2f
AD		 77MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin");
78MODULE_FIRMWARE("radeon/REDWOOD_me.bin");
45f9a39b 79MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin");
fe251e2f
AD		 80MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin");
81MODULE_FIRMWARE("radeon/JUNIPER_me.bin");
45f9a39b 82MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin");
a7433742 83MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin");
fe251e2f 84MODULE_FIRMWARE("radeon/CYPRESS_me.bin");
45f9a39b 85MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin");
3ce0a23d
JG		 86
87int r600_debugfs_mc_info_init(struct radeon_device *rdev);
771fe6b9 88
1a029b76 89/* r600,rv610,rv630,rv620,rv635,rv670 */
771fe6b9
JG		 90int r600_mc_wait_for_idle(struct radeon_device *rdev);
91void r600_gpu_init(struct radeon_device *rdev);
3ce0a23d 92void r600_fini(struct radeon_device *rdev);
45f9a39b 93void r600_irq_disable(struct radeon_device *rdev);
771fe6b9 94
a48b9b4e
AD		 95void r600_get_power_state(struct radeon_device *rdev,
96 enum radeon_pm_action action)
97{
98 int i;
99
100 rdev->pm.can_upclock = true;
101 rdev->pm.can_downclock = true;
102
103 /* power state array is low to high, default is first */
104 if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) {
105 int min_power_state_index = 0;
106
107 if (rdev->pm.num_power_states > 2)
108 min_power_state_index = 1;
109
110 switch (action) {
111 case PM_ACTION_MINIMUM:
112 rdev->pm.requested_power_state_index = min_power_state_index;
113 rdev->pm.requested_clock_mode_index = 0;
114 rdev->pm.can_downclock = false;
115 break;
116 case PM_ACTION_DOWNCLOCK:
117 if (rdev->pm.current_power_state_index == min_power_state_index) {
118 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
119 rdev->pm.can_downclock = false;
120 } else {
121 if (rdev->pm.active_crtc_count > 1) {
122 for (i = 0; i < rdev->pm.num_power_states; i++) {
123 if (rdev->pm.power_state[i].flags & RADEON_PM_SINGLE_DISPLAY_ONLY)
124 continue;
125 else if (i >= rdev->pm.current_power_state_index) {
126 rdev->pm.requested_power_state_index =
127 rdev->pm.current_power_state_index;
128 break;
129 } else {
130 rdev->pm.requested_power_state_index = i;
131 break;
132 }
133 }
134 } else
135 rdev->pm.requested_power_state_index =
136 rdev->pm.current_power_state_index - 1;
137 }
138 rdev->pm.requested_clock_mode_index = 0;
139 break;
140 case PM_ACTION_UPCLOCK:
141 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
142 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
143 rdev->pm.can_upclock = false;
144 } else {
145 if (rdev->pm.active_crtc_count > 1) {
146 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
147 if (rdev->pm.power_state[i].flags & RADEON_PM_SINGLE_DISPLAY_ONLY)
148 continue;
149 else if (i <= rdev->pm.current_power_state_index) {
150 rdev->pm.requested_power_state_index =
151 rdev->pm.current_power_state_index;
152 break;
153 } else {
154 rdev->pm.requested_power_state_index = i;
155 break;
156 }
157 }
158 } else
159 rdev->pm.requested_power_state_index =
160 rdev->pm.current_power_state_index + 1;
161 }
162 rdev->pm.requested_clock_mode_index = 0;
163 break;
164 case PM_ACTION_NONE:
165 default:
166 DRM_ERROR("Requested mode for not defined action\n");
167 return;
168 }
169 } else {
170 /* XXX select a power state based on AC/DC, single/dualhead, etc. */
171 /* for now just select the first power state and switch between clock modes */
172 /* power state array is low to high, default is first (0) */
173 if (rdev->pm.active_crtc_count > 1) {
174 rdev->pm.requested_power_state_index = -1;
175 /* start at 1 as we don't want the default mode */
176 for (i = 1; i < rdev->pm.num_power_states; i++) {
177 if (rdev->pm.power_state[i].flags & RADEON_PM_SINGLE_DISPLAY_ONLY)
178 continue;
179 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) ||
180 (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) {
181 rdev->pm.requested_power_state_index = i;
182 break;
183 }
184 }
185 /* if nothing selected, grab the default state. */
186 if (rdev->pm.requested_power_state_index == -1)
187 rdev->pm.requested_power_state_index = 0;
188 } else
189 rdev->pm.requested_power_state_index = 1;
190
191 switch (action) {
192 case PM_ACTION_MINIMUM:
193 rdev->pm.requested_clock_mode_index = 0;
194 rdev->pm.can_downclock = false;
195 break;
196 case PM_ACTION_DOWNCLOCK:
197 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
198 if (rdev->pm.current_clock_mode_index == 0) {
199 rdev->pm.requested_clock_mode_index = 0;
200 rdev->pm.can_downclock = false;
201 } else
202 rdev->pm.requested_clock_mode_index =
203 rdev->pm.current_clock_mode_index - 1;
204 } else {
205 rdev->pm.requested_clock_mode_index = 0;
206 rdev->pm.can_downclock = false;
207 }
208 break;
209 case PM_ACTION_UPCLOCK:
210 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
211 if (rdev->pm.current_clock_mode_index ==
212 (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) {
213 rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index;
214 rdev->pm.can_upclock = false;
215 } else
216 rdev->pm.requested_clock_mode_index =
217 rdev->pm.current_clock_mode_index + 1;
218 } else {
219 rdev->pm.requested_clock_mode_index =
220 rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1;
221 rdev->pm.can_upclock = false;
222 }
223 break;
224 case PM_ACTION_NONE:
225 default:
226 DRM_ERROR("Requested mode for not defined action\n");
227 return;
228 }
229 }
230
231 DRM_INFO("Requested: e: %d m: %d p: %d\n",
232 rdev->pm.power_state[rdev->pm.requested_power_state_index].
233 clock_info[rdev->pm.requested_clock_mode_index].sclk,
234 rdev->pm.power_state[rdev->pm.requested_power_state_index].
235 clock_info[rdev->pm.requested_clock_mode_index].mclk,
236 rdev->pm.power_state[rdev->pm.requested_power_state_index].
237 non_clock_info.pcie_lanes);
238}
239
bae6b562
AD		 240void r600_set_power_state(struct radeon_device *rdev)
241{
a48b9b4e
AD		 242 u32 sclk, mclk;
243
244 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
245 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
bae6b562
AD		 246 return;
247
a48b9b4e 248 if (radeon_gui_idle(rdev)) {
bae6b562 249
a48b9b4e
AD		 250 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
251 clock_info[rdev->pm.requested_clock_mode_index].sclk;
252 if (sclk > rdev->clock.default_sclk)
253 sclk = rdev->clock.default_sclk;
bae6b562 254
a48b9b4e
AD		 255 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
256 clock_info[rdev->pm.requested_clock_mode_index].mclk;
257 if (mclk > rdev->clock.default_mclk)
258 mclk = rdev->clock.default_mclk;
259 /* don't change the mclk with multiple crtcs */
260 if (rdev->pm.active_crtc_count > 1)
261 mclk = rdev->clock.default_mclk;
bae6b562 262
a48b9b4e
AD		 263 /* set pcie lanes */
264 /* TODO */
265
266 /* set voltage */
267 /* TODO */
268
269 /* set engine clock */
270 if (sclk != rdev->pm.current_sclk) {
271 radeon_sync_with_vblank(rdev);
272 radeon_pm_debug_check_in_vbl(rdev, false);
273 radeon_set_engine_clock(rdev, sclk);
274 radeon_pm_debug_check_in_vbl(rdev, true);
275 rdev->pm.current_sclk = sclk;
276 DRM_INFO("Setting: e: %d\n", sclk);
277 }
bae6b562
AD		 278
279#if 0
a48b9b4e
AD		 280 /* set memory clock */
281 if (rdev->asic->set_memory_clock && (mclk != rdev->pm.current_mclk)) {
282 radeon_sync_with_vblank(rdev);
283 radeon_pm_debug_check_in_vbl(rdev, false);
284 radeon_set_memory_clock(rdev, mclk);
285 radeon_pm_debug_check_in_vbl(rdev, true);
286 rdev->pm.current_mclk = mclk;
287 DRM_INFO("Setting: m: %d\n", mclk);
288 }
bae6b562
AD		 289#endif
290
a48b9b4e
AD		 291 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
292 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
293 } else
294 DRM_INFO("GUI not idle!!!\n");
bae6b562
AD		 295}
296
def9ba9c
AD		 297bool r600_gui_idle(struct radeon_device *rdev)
298{
299 if (RREG32(GRBM_STATUS) & GUI_ACTIVE)
300 return false;
301 else
302 return true;
303}
304
e0df1ac5
AD		 305/* hpd for digital panel detect/disconnect */
306bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
307{
308 bool connected = false;
309
310 if (ASIC_IS_DCE3(rdev)) {
311 switch (hpd) {
312 case RADEON_HPD_1:
313 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
314 connected = true;
315 break;
316 case RADEON_HPD_2:
317 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
318 connected = true;
319 break;
320 case RADEON_HPD_3:
321 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
322 connected = true;
323 break;
324 case RADEON_HPD_4:
325 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
326 connected = true;
327 break;
328 /* DCE 3.2 */
329 case RADEON_HPD_5:
330 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
331 connected = true;
332 break;
333 case RADEON_HPD_6:
334 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
335 connected = true;
336 break;
337 default:
338 break;
339 }
340 } else {
341 switch (hpd) {
342 case RADEON_HPD_1:
343 if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
344 connected = true;
345 break;
346 case RADEON_HPD_2:
347 if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
348 connected = true;
349 break;
350 case RADEON_HPD_3:
351 if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
352 connected = true;
353 break;
354 default:
355 break;
356 }
357 }
358 return connected;
359}
360
361void r600_hpd_set_polarity(struct radeon_device *rdev,
429770b3 362 enum radeon_hpd_id hpd)
e0df1ac5
AD		 363{
364 u32 tmp;
365 bool connected = r600_hpd_sense(rdev, hpd);
366
367 if (ASIC_IS_DCE3(rdev)) {
368 switch (hpd) {
369 case RADEON_HPD_1:
370 tmp = RREG32(DC_HPD1_INT_CONTROL);
371 if (connected)
372 tmp &= ~DC_HPDx_INT_POLARITY;
373 else
374 tmp |= DC_HPDx_INT_POLARITY;
375 WREG32(DC_HPD1_INT_CONTROL, tmp);
376 break;
377 case RADEON_HPD_2:
378 tmp = RREG32(DC_HPD2_INT_CONTROL);
379 if (connected)
380 tmp &= ~DC_HPDx_INT_POLARITY;
381 else
382 tmp |= DC_HPDx_INT_POLARITY;
383 WREG32(DC_HPD2_INT_CONTROL, tmp);
384 break;
385 case RADEON_HPD_3:
386 tmp = RREG32(DC_HPD3_INT_CONTROL);
387 if (connected)
388 tmp &= ~DC_HPDx_INT_POLARITY;
389 else
390 tmp |= DC_HPDx_INT_POLARITY;
391 WREG32(DC_HPD3_INT_CONTROL, tmp);
392 break;
393 case RADEON_HPD_4:
394 tmp = RREG32(DC_HPD4_INT_CONTROL);
395 if (connected)
396 tmp &= ~DC_HPDx_INT_POLARITY;
397 else
398 tmp |= DC_HPDx_INT_POLARITY;
399 WREG32(DC_HPD4_INT_CONTROL, tmp);
400 break;
401 case RADEON_HPD_5:
402 tmp = RREG32(DC_HPD5_INT_CONTROL);
403 if (connected)
404 tmp &= ~DC_HPDx_INT_POLARITY;
405 else
406 tmp |= DC_HPDx_INT_POLARITY;
407 WREG32(DC_HPD5_INT_CONTROL, tmp);
408 break;
409 /* DCE 3.2 */
410 case RADEON_HPD_6:
411 tmp = RREG32(DC_HPD6_INT_CONTROL);
412 if (connected)
413 tmp &= ~DC_HPDx_INT_POLARITY;
414 else
415 tmp |= DC_HPDx_INT_POLARITY;
416 WREG32(DC_HPD6_INT_CONTROL, tmp);
417 break;
418 default:
419 break;
420 }
421 } else {
422 switch (hpd) {
423 case RADEON_HPD_1:
424 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
425 if (connected)
426 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
427 else
428 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
429 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
430 break;
431 case RADEON_HPD_2:
432 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
433 if (connected)
434 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
435 else
436 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
437 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
438 break;
439 case RADEON_HPD_3:
440 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
441 if (connected)
442 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
443 else
444 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
445 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
446 break;
447 default:
448 break;
449 }
450 }
451}
452
453void r600_hpd_init(struct radeon_device *rdev)
454{
455 struct drm_device *dev = rdev->ddev;
456 struct drm_connector *connector;
457
458 if (ASIC_IS_DCE3(rdev)) {
459 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
460 if (ASIC_IS_DCE32(rdev))
461 tmp |= DC_HPDx_EN;
462
463 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
464 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
465 switch (radeon_connector->hpd.hpd) {
466 case RADEON_HPD_1:
467 WREG32(DC_HPD1_CONTROL, tmp);
468 rdev->irq.hpd[0] = true;
469 break;
470 case RADEON_HPD_2:
471 WREG32(DC_HPD2_CONTROL, tmp);
472 rdev->irq.hpd[1] = true;
473 break;
474 case RADEON_HPD_3:
475 WREG32(DC_HPD3_CONTROL, tmp);
476 rdev->irq.hpd[2] = true;
477 break;
478 case RADEON_HPD_4:
479 WREG32(DC_HPD4_CONTROL, tmp);
480 rdev->irq.hpd[3] = true;
481 break;
482 /* DCE 3.2 */
483 case RADEON_HPD_5:
484 WREG32(DC_HPD5_CONTROL, tmp);
485 rdev->irq.hpd[4] = true;
486 break;
487 case RADEON_HPD_6:
488 WREG32(DC_HPD6_CONTROL, tmp);
489 rdev->irq.hpd[5] = true;
490 break;
491 default:
492 break;
493 }
494 }
495 } else {
496 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
497 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
498 switch (radeon_connector->hpd.hpd) {
499 case RADEON_HPD_1:
500 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);
501 rdev->irq.hpd[0] = true;
502 break;
503 case RADEON_HPD_2:
504 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);
505 rdev->irq.hpd[1] = true;
506 break;
507 case RADEON_HPD_3:
508 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);
509 rdev->irq.hpd[2] = true;
510 break;
511 default:
512 break;
513 }
514 }
515 }
003e69f9
JG		 516 if (rdev->irq.installed)
517 r600_irq_set(rdev);
e0df1ac5
AD		 518}
519
520void r600_hpd_fini(struct radeon_device *rdev)
521{
522 struct drm_device *dev = rdev->ddev;
523 struct drm_connector *connector;
524
525 if (ASIC_IS_DCE3(rdev)) {
526 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
527 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
528 switch (radeon_connector->hpd.hpd) {
529 case RADEON_HPD_1:
530 WREG32(DC_HPD1_CONTROL, 0);
531 rdev->irq.hpd[0] = false;
532 break;
533 case RADEON_HPD_2:
534 WREG32(DC_HPD2_CONTROL, 0);
535 rdev->irq.hpd[1] = false;
536 break;
537 case RADEON_HPD_3:
538 WREG32(DC_HPD3_CONTROL, 0);
539 rdev->irq.hpd[2] = false;
540 break;
541 case RADEON_HPD_4:
542 WREG32(DC_HPD4_CONTROL, 0);
543 rdev->irq.hpd[3] = false;
544 break;
545 /* DCE 3.2 */
546 case RADEON_HPD_5:
547 WREG32(DC_HPD5_CONTROL, 0);
548 rdev->irq.hpd[4] = false;
549 break;
550 case RADEON_HPD_6:
551 WREG32(DC_HPD6_CONTROL, 0);
552 rdev->irq.hpd[5] = false;
553 break;
554 default:
555 break;
556 }
557 }
558 } else {
559 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
560 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
561 switch (radeon_connector->hpd.hpd) {
562 case RADEON_HPD_1:
563 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);
564 rdev->irq.hpd[0] = false;
565 break;
566 case RADEON_HPD_2:
567 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);
568 rdev->irq.hpd[1] = false;
569 break;
570 case RADEON_HPD_3:
571 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);
572 rdev->irq.hpd[2] = false;
573 break;
574 default:
575 break;
576 }
577 }
578 }
579}
580
771fe6b9 581/*
3ce0a23d 582 * R600 PCIE GART
771fe6b9 583 */
3ce0a23d
JG		 584void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
585{
586 unsigned i;
587 u32 tmp;
588
2e98f10a
DA		 589 /* flush hdp cache so updates hit vram */
590 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
591
3ce0a23d
JG		 592 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
593 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
594 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
595 for (i = 0; i < rdev->usec_timeout; i++) {
596 /* read MC_STATUS */
597 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
598 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
599 if (tmp == 2) {
600 printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
601 return;
602 }
603 if (tmp) {
604 return;
605 }
606 udelay(1);
607 }
608}
609
4aac0473 610int r600_pcie_gart_init(struct radeon_device *rdev)
3ce0a23d 611{
4aac0473 612 int r;
3ce0a23d 613
4aac0473
JG		 614 if (rdev->gart.table.vram.robj) {
615 WARN(1, "R600 PCIE GART already initialized.\n");
616 return 0;
617 }
3ce0a23d
JG		 618 /* Initialize common gart structure */
619 r = radeon_gart_init(rdev);
4aac0473 620 if (r)
3ce0a23d 621 return r;
3ce0a23d 622 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
4aac0473
JG		 623 return radeon_gart_table_vram_alloc(rdev);
624}
625
626int r600_pcie_gart_enable(struct radeon_device *rdev)
627{
628 u32 tmp;
629 int r, i;
630
631 if (rdev->gart.table.vram.robj == NULL) {
632 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
633 return -EINVAL;
771fe6b9 634 }
4aac0473
JG		 635 r = radeon_gart_table_vram_pin(rdev);
636 if (r)
637 return r;
82568565 638 radeon_gart_restore(rdev);
bc1a631e 639
3ce0a23d
JG		 640 /* Setup L2 cache */
641 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
642 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
643 EFFECTIVE_L2_QUEUE_SIZE(7));
644 WREG32(VM_L2_CNTL2, 0);
645 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
646 /* Setup TLB control */
647 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
648 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
649 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
650 ENABLE_WAIT_L2_QUERY;
651 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
652 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
653 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
654 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
655 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
656 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
657 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
658 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
659 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
660 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
661 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
662 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
663 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
664 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
665 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
1a029b76 666 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
3ce0a23d
JG		 667 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
668 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
669 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
670 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
671 (u32)(rdev->dummy_page.addr >> 12));
672 for (i = 1; i < 7; i++)
673 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
771fe6b9 674
3ce0a23d
JG		 675 r600_pcie_gart_tlb_flush(rdev);
676 rdev->gart.ready = true;
771fe6b9
JG		 677 return 0;
678}
679
3ce0a23d 680void r600_pcie_gart_disable(struct radeon_device *rdev)
771fe6b9 681{
3ce0a23d 682 u32 tmp;
4c788679 683 int i, r;
771fe6b9 684
3ce0a23d
JG		 685 /* Disable all tables */
686 for (i = 0; i < 7; i++)
687 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
771fe6b9 688
3ce0a23d
JG		 689 /* Disable L2 cache */
690 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
691 EFFECTIVE_L2_QUEUE_SIZE(7));
692 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
693 /* Setup L1 TLB control */
694 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
695 ENABLE_WAIT_L2_QUERY;
696 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
697 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
698 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
699 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
700 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
701 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
702 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
703 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
704 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
705 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
706 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
707 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
708 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
709 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
4aac0473 710 if (rdev->gart.table.vram.robj) {
4c788679
JG		 711 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
712 if (likely(r == 0)) {
713 radeon_bo_kunmap(rdev->gart.table.vram.robj);
714 radeon_bo_unpin(rdev->gart.table.vram.robj);
715 radeon_bo_unreserve(rdev->gart.table.vram.robj);
716 }
4aac0473
JG		 717 }
718}
719
720void r600_pcie_gart_fini(struct radeon_device *rdev)
721{
f9274562 722 radeon_gart_fini(rdev);
4aac0473
JG		 723 r600_pcie_gart_disable(rdev);
724 radeon_gart_table_vram_free(rdev);
771fe6b9
JG		 725}
726
1a029b76
JG		 727void r600_agp_enable(struct radeon_device *rdev)
728{
729 u32 tmp;
730 int i;
731
732 /* Setup L2 cache */
733 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
734 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
735 EFFECTIVE_L2_QUEUE_SIZE(7));
736 WREG32(VM_L2_CNTL2, 0);
737 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
738 /* Setup TLB control */
739 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
740 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
741 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
742 ENABLE_WAIT_L2_QUERY;
743 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
744 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
745 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
746 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
747 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
748 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
749 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
750 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
751 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
752 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
753 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
754 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
755 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
756 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
757 for (i = 0; i < 7; i++)
758 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
759}
760
771fe6b9
JG		 761int r600_mc_wait_for_idle(struct radeon_device *rdev)
762{
3ce0a23d
JG		 763 unsigned i;
764 u32 tmp;
765
766 for (i = 0; i < rdev->usec_timeout; i++) {
767 /* read MC_STATUS */
768 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
769 if (!tmp)
770 return 0;
771 udelay(1);
772 }
773 return -1;
771fe6b9
JG		 774}
775
a3c1945a 776static void r600_mc_program(struct radeon_device *rdev)
771fe6b9 777{
a3c1945a 778 struct rv515_mc_save save;
3ce0a23d
JG		 779 u32 tmp;
780 int i, j;
771fe6b9 781
3ce0a23d
JG		 782 /* Initialize HDP */
783 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
784 WREG32((0x2c14 + j), 0x00000000);
785 WREG32((0x2c18 + j), 0x00000000);
786 WREG32((0x2c1c + j), 0x00000000);
787 WREG32((0x2c20 + j), 0x00000000);
788 WREG32((0x2c24 + j), 0x00000000);
789 }
790 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
771fe6b9 791
a3c1945a 792 rv515_mc_stop(rdev, &save);
3ce0a23d 793 if (r600_mc_wait_for_idle(rdev)) {
a3c1945a 794 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
3ce0a23d 795 }
a3c1945a 796 /* Lockout access through VGA aperture (doesn't exist before R600) */
3ce0a23d 797 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
3ce0a23d 798 /* Update configuration */
1a029b76
JG		 799 if (rdev->flags & RADEON_IS_AGP) {
800 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
801 /* VRAM before AGP */
802 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
803 rdev->mc.vram_start >> 12);
804 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
805 rdev->mc.gtt_end >> 12);
806 } else {
807 /* VRAM after AGP */
808 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
809 rdev->mc.gtt_start >> 12);
810 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
811 rdev->mc.vram_end >> 12);
812 }
813 } else {
814 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
815 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
816 }
3ce0a23d 817 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
1a029b76 818 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
3ce0a23d
JG		 819 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
820 WREG32(MC_VM_FB_LOCATION, tmp);
821 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
822 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
1a029b76 823 WREG32(HDP_NONSURFACE_SIZE, rdev->mc.mc_vram_size | 0x3FF);
3ce0a23d 824 if (rdev->flags & RADEON_IS_AGP) {
1a029b76
JG		 825 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
826 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
3ce0a23d
JG		 827 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
828 } else {
829 WREG32(MC_VM_AGP_BASE, 0);
830 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
831 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
832 }
3ce0a23d 833 if (r600_mc_wait_for_idle(rdev)) {
a3c1945a 834 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
3ce0a23d 835 }
a3c1945a 836 rv515_mc_resume(rdev, &save);
698443d9
DA		 837 /* we need to own VRAM, so turn off the VGA renderer here
838 * to stop it overwriting our objects */
d39c3b89 839 rv515_vga_render_disable(rdev);
3ce0a23d
JG		 840}
841
d594e46a
JG		 842/**
843 * r600_vram_gtt_location - try to find VRAM & GTT location
844 * @rdev: radeon device structure holding all necessary informations
845 * @mc: memory controller structure holding memory informations
846 *
847 * Function will place try to place VRAM at same place as in CPU (PCI)
848 * address space as some GPU seems to have issue when we reprogram at
849 * different address space.
850 *
851 * If there is not enough space to fit the unvisible VRAM after the
852 * aperture then we limit the VRAM size to the aperture.
853 *
854 * If we are using AGP then place VRAM adjacent to AGP aperture are we need
855 * them to be in one from GPU point of view so that we can program GPU to
856 * catch access outside them (weird GPU policy see ??).
857 *
858 * This function will never fails, worst case are limiting VRAM or GTT.
859 *
860 * Note: GTT start, end, size should be initialized before calling this
861 * function on AGP platform.
862 */
863void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
864{
865 u64 size_bf, size_af;
866
867 if (mc->mc_vram_size > 0xE0000000) {
868 /* leave room for at least 512M GTT */
869 dev_warn(rdev->dev, "limiting VRAM\n");
870 mc->real_vram_size = 0xE0000000;
871 mc->mc_vram_size = 0xE0000000;
872 }
873 if (rdev->flags & RADEON_IS_AGP) {
874 size_bf = mc->gtt_start;
875 size_af = 0xFFFFFFFF - mc->gtt_end + 1;
876 if (size_bf > size_af) {
877 if (mc->mc_vram_size > size_bf) {
878 dev_warn(rdev->dev, "limiting VRAM\n");
879 mc->real_vram_size = size_bf;
880 mc->mc_vram_size = size_bf;
881 }
882 mc->vram_start = mc->gtt_start - mc->mc_vram_size;
883 } else {
884 if (mc->mc_vram_size > size_af) {
885 dev_warn(rdev->dev, "limiting VRAM\n");
886 mc->real_vram_size = size_af;
887 mc->mc_vram_size = size_af;
888 }
889 mc->vram_start = mc->gtt_end;
890 }
891 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
892 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
893 mc->mc_vram_size >> 20, mc->vram_start,
894 mc->vram_end, mc->real_vram_size >> 20);
895 } else {
896 u64 base = 0;
897 if (rdev->flags & RADEON_IS_IGP)
898 base = (RREG32(MC_VM_FB_LOCATION) & 0xFFFF) << 24;
899 radeon_vram_location(rdev, &rdev->mc, base);
900 radeon_gtt_location(rdev, mc);
901 }
902}
903
3ce0a23d 904int r600_mc_init(struct radeon_device *rdev)
771fe6b9 905{
3ce0a23d 906 u32 tmp;
5885b7a9 907 int chansize, numchan;
771fe6b9 908
3ce0a23d 909 /* Get VRAM informations */
771fe6b9 910 rdev->mc.vram_is_ddr = true;
3ce0a23d
JG		 911 tmp = RREG32(RAMCFG);
912 if (tmp & CHANSIZE_OVERRIDE) {
771fe6b9 913 chansize = 16;
3ce0a23d 914 } else if (tmp & CHANSIZE_MASK) {
771fe6b9
JG		 915 chansize = 64;
916 } else {
917 chansize = 32;
918 }
5885b7a9
AD		 919 tmp = RREG32(CHMAP);
920 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
921 case 0:
922 default:
923 numchan = 1;
924 break;
925 case 1:
926 numchan = 2;
927 break;
928 case 2:
929 numchan = 4;
930 break;
931 case 3:
932 numchan = 8;
933 break;
771fe6b9 934 }
5885b7a9 935 rdev->mc.vram_width = numchan * chansize;
3ce0a23d
JG		 936 /* Could aper size report 0 ? */
937 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
938 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
939 /* Setup GPU memory space */
940 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
941 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
51e5fcd3 942 rdev->mc.visible_vram_size = rdev->mc.aper_size;
d594e46a 943 r600_vram_gtt_location(rdev, &rdev->mc);
f47299c5 944
06b6476d
AD		 945 if (rdev->flags & RADEON_IS_IGP)
946 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
f47299c5 947 radeon_update_bandwidth_info(rdev);
3ce0a23d 948 return 0;
771fe6b9
JG		 949}
950
3ce0a23d
JG		 951/* We doesn't check that the GPU really needs a reset we simply do the
952 * reset, it's up to the caller to determine if the GPU needs one. We
953 * might add an helper function to check that.
954 */
955int r600_gpu_soft_reset(struct radeon_device *rdev)
771fe6b9 956{
a3c1945a 957 struct rv515_mc_save save;
3ce0a23d
JG		 958 u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) |
959 S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) |
960 S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) |
961 S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) |
962 S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) |
963 S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) |
964 S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) |
965 S_008010_GUI_ACTIVE(1);
966 u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) |
967 S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) |
968 S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) |
969 S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) |
970 S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) |
971 S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) |
972 S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) |
973 S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1);
a3c1945a 974 u32 tmp;
771fe6b9 975
1a029b76
JG		 976 dev_info(rdev->dev, "GPU softreset \n");
977 dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n",
978 RREG32(R_008010_GRBM_STATUS));
979 dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n",
a3c1945a 980 RREG32(R_008014_GRBM_STATUS2));
1a029b76
JG		 981 dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n",
982 RREG32(R_000E50_SRBM_STATUS));
a3c1945a
JG		 983 rv515_mc_stop(rdev, &save);
984 if (r600_mc_wait_for_idle(rdev)) {
985 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
986 }
3ce0a23d 987 /* Disable CP parsing/prefetching */
90aca4d2 988 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
3ce0a23d
JG		 989 /* Check if any of the rendering block is busy and reset it */
990 if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) ||
991 (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) {
a3c1945a 992 tmp = S_008020_SOFT_RESET_CR(1) |
3ce0a23d
JG		 993 S_008020_SOFT_RESET_DB(1) |
994 S_008020_SOFT_RESET_CB(1) |
995 S_008020_SOFT_RESET_PA(1) |
996 S_008020_SOFT_RESET_SC(1) |
997 S_008020_SOFT_RESET_SMX(1) |
998 S_008020_SOFT_RESET_SPI(1) |
999 S_008020_SOFT_RESET_SX(1) |
1000 S_008020_SOFT_RESET_SH(1) |
1001 S_008020_SOFT_RESET_TC(1) |
1002 S_008020_SOFT_RESET_TA(1) |
1003 S_008020_SOFT_RESET_VC(1) |
a3c1945a 1004 S_008020_SOFT_RESET_VGT(1);
1a029b76 1005 dev_info(rdev->dev, " R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
a3c1945a 1006 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
90aca4d2
JG		 1007 RREG32(R_008020_GRBM_SOFT_RESET);
1008 mdelay(15);
3ce0a23d 1009 WREG32(R_008020_GRBM_SOFT_RESET, 0);
3ce0a23d
JG		 1010 }
1011 /* Reset CP (we always reset CP) */
a3c1945a
JG		 1012 tmp = S_008020_SOFT_RESET_CP(1);
1013 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1014 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
90aca4d2
JG		 1015 RREG32(R_008020_GRBM_SOFT_RESET);
1016 mdelay(15);
3ce0a23d 1017 WREG32(R_008020_GRBM_SOFT_RESET, 0);
3ce0a23d 1018 /* Wait a little for things to settle down */
225758d8 1019 mdelay(1);
1a029b76
JG		 1020 dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n",
1021 RREG32(R_008010_GRBM_STATUS));
1022 dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n",
1023 RREG32(R_008014_GRBM_STATUS2));
1024 dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n",
1025 RREG32(R_000E50_SRBM_STATUS));
a3c1945a 1026 rv515_mc_resume(rdev, &save);
3ce0a23d
JG		 1027 return 0;
1028}
1029
225758d8
JG		 1030bool r600_gpu_is_lockup(struct radeon_device *rdev)
1031{
1032 u32 srbm_status;
1033 u32 grbm_status;
1034 u32 grbm_status2;
1035 int r;
1036
1037 srbm_status = RREG32(R_000E50_SRBM_STATUS);
1038 grbm_status = RREG32(R_008010_GRBM_STATUS);
1039 grbm_status2 = RREG32(R_008014_GRBM_STATUS2);
1040 if (!G_008010_GUI_ACTIVE(grbm_status)) {
1041 r100_gpu_lockup_update(&rdev->config.r300.lockup, &rdev->cp);
1042 return false;
1043 }
1044 /* force CP activities */
1045 r = radeon_ring_lock(rdev, 2);
1046 if (!r) {
1047 /* PACKET2 NOP */
1048 radeon_ring_write(rdev, 0x80000000);
1049 radeon_ring_write(rdev, 0x80000000);
1050 radeon_ring_unlock_commit(rdev);
1051 }
1052 rdev->cp.rptr = RREG32(R600_CP_RB_RPTR);
1053 return r100_gpu_cp_is_lockup(rdev, &rdev->config.r300.lockup, &rdev->cp);
1054}
1055
a2d07b74 1056int r600_asic_reset(struct radeon_device *rdev)
3ce0a23d
JG		 1057{
1058 return r600_gpu_soft_reset(rdev);
1059}
1060
1061static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
1062 u32 num_backends,
1063 u32 backend_disable_mask)
1064{
1065 u32 backend_map = 0;
1066 u32 enabled_backends_mask;
1067 u32 enabled_backends_count;
1068 u32 cur_pipe;
1069 u32 swizzle_pipe[R6XX_MAX_PIPES];
1070 u32 cur_backend;
1071 u32 i;
1072
1073 if (num_tile_pipes > R6XX_MAX_PIPES)
1074 num_tile_pipes = R6XX_MAX_PIPES;
1075 if (num_tile_pipes < 1)
1076 num_tile_pipes = 1;
1077 if (num_backends > R6XX_MAX_BACKENDS)
1078 num_backends = R6XX_MAX_BACKENDS;
1079 if (num_backends < 1)
1080 num_backends = 1;
1081
1082 enabled_backends_mask = 0;
1083 enabled_backends_count = 0;
1084 for (i = 0; i < R6XX_MAX_BACKENDS; ++i) {
1085 if (((backend_disable_mask >> i) & 1) == 0) {
1086 enabled_backends_mask |= (1 << i);
1087 ++enabled_backends_count;
1088 }
1089 if (enabled_backends_count == num_backends)
1090 break;
1091 }
1092
1093 if (enabled_backends_count == 0) {
1094 enabled_backends_mask = 1;
1095 enabled_backends_count = 1;
1096 }
1097
1098 if (enabled_backends_count != num_backends)
1099 num_backends = enabled_backends_count;
1100
1101 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES);
1102 switch (num_tile_pipes) {
1103 case 1:
1104 swizzle_pipe[0] = 0;
1105 break;
1106 case 2:
1107 swizzle_pipe[0] = 0;
1108 swizzle_pipe[1] = 1;
1109 break;
1110 case 3:
1111 swizzle_pipe[0] = 0;
1112 swizzle_pipe[1] = 1;
1113 swizzle_pipe[2] = 2;
1114 break;
1115 case 4:
1116 swizzle_pipe[0] = 0;
1117 swizzle_pipe[1] = 1;
1118 swizzle_pipe[2] = 2;
1119 swizzle_pipe[3] = 3;
1120 break;
1121 case 5:
1122 swizzle_pipe[0] = 0;
1123 swizzle_pipe[1] = 1;
1124 swizzle_pipe[2] = 2;
1125 swizzle_pipe[3] = 3;
1126 swizzle_pipe[4] = 4;
1127 break;
1128 case 6:
1129 swizzle_pipe[0] = 0;
1130 swizzle_pipe[1] = 2;
1131 swizzle_pipe[2] = 4;
1132 swizzle_pipe[3] = 5;
1133 swizzle_pipe[4] = 1;
1134 swizzle_pipe[5] = 3;
1135 break;
1136 case 7:
1137 swizzle_pipe[0] = 0;
1138 swizzle_pipe[1] = 2;
1139 swizzle_pipe[2] = 4;
1140 swizzle_pipe[3] = 6;
1141 swizzle_pipe[4] = 1;
1142 swizzle_pipe[5] = 3;
1143 swizzle_pipe[6] = 5;
1144 break;
1145 case 8:
1146 swizzle_pipe[0] = 0;
1147 swizzle_pipe[1] = 2;
1148 swizzle_pipe[2] = 4;
1149 swizzle_pipe[3] = 6;
1150 swizzle_pipe[4] = 1;
1151 swizzle_pipe[5] = 3;
1152 swizzle_pipe[6] = 5;
1153 swizzle_pipe[7] = 7;
1154 break;
1155 }
1156
1157 cur_backend = 0;
1158 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1159 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1160 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
1161
1162 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
1163
1164 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
1165 }
1166
1167 return backend_map;
1168}
1169
1170int r600_count_pipe_bits(uint32_t val)
1171{
1172 int i, ret = 0;
1173
1174 for (i = 0; i < 32; i++) {
1175 ret += val & 1;
1176 val >>= 1;
1177 }
1178 return ret;
771fe6b9
JG		 1179}
1180
3ce0a23d
JG		 1181void r600_gpu_init(struct radeon_device *rdev)
1182{
1183 u32 tiling_config;
1184 u32 ramcfg;
d03f5d59
AD		 1185 u32 backend_map;
1186 u32 cc_rb_backend_disable;
1187 u32 cc_gc_shader_pipe_config;
3ce0a23d
JG		 1188 u32 tmp;
1189 int i, j;
1190 u32 sq_config;
1191 u32 sq_gpr_resource_mgmt_1 = 0;
1192 u32 sq_gpr_resource_mgmt_2 = 0;
1193 u32 sq_thread_resource_mgmt = 0;
1194 u32 sq_stack_resource_mgmt_1 = 0;
1195 u32 sq_stack_resource_mgmt_2 = 0;
1196
1197 /* FIXME: implement */
1198 switch (rdev->family) {
1199 case CHIP_R600:
1200 rdev->config.r600.max_pipes = 4;
1201 rdev->config.r600.max_tile_pipes = 8;
1202 rdev->config.r600.max_simds = 4;
1203 rdev->config.r600.max_backends = 4;
1204 rdev->config.r600.max_gprs = 256;
1205 rdev->config.r600.max_threads = 192;
1206 rdev->config.r600.max_stack_entries = 256;
1207 rdev->config.r600.max_hw_contexts = 8;
1208 rdev->config.r600.max_gs_threads = 16;
1209 rdev->config.r600.sx_max_export_size = 128;
1210 rdev->config.r600.sx_max_export_pos_size = 16;
1211 rdev->config.r600.sx_max_export_smx_size = 128;
1212 rdev->config.r600.sq_num_cf_insts = 2;
1213 break;
1214 case CHIP_RV630:
1215 case CHIP_RV635:
1216 rdev->config.r600.max_pipes = 2;
1217 rdev->config.r600.max_tile_pipes = 2;
1218 rdev->config.r600.max_simds = 3;
1219 rdev->config.r600.max_backends = 1;
1220 rdev->config.r600.max_gprs = 128;
1221 rdev->config.r600.max_threads = 192;
1222 rdev->config.r600.max_stack_entries = 128;
1223 rdev->config.r600.max_hw_contexts = 8;
1224 rdev->config.r600.max_gs_threads = 4;
1225 rdev->config.r600.sx_max_export_size = 128;
1226 rdev->config.r600.sx_max_export_pos_size = 16;
1227 rdev->config.r600.sx_max_export_smx_size = 128;
1228 rdev->config.r600.sq_num_cf_insts = 2;
1229 break;
1230 case CHIP_RV610:
1231 case CHIP_RV620:
1232 case CHIP_RS780:
1233 case CHIP_RS880:
1234 rdev->config.r600.max_pipes = 1;
1235 rdev->config.r600.max_tile_pipes = 1;
1236 rdev->config.r600.max_simds = 2;
1237 rdev->config.r600.max_backends = 1;
1238 rdev->config.r600.max_gprs = 128;
1239 rdev->config.r600.max_threads = 192;
1240 rdev->config.r600.max_stack_entries = 128;
1241 rdev->config.r600.max_hw_contexts = 4;
1242 rdev->config.r600.max_gs_threads = 4;
1243 rdev->config.r600.sx_max_export_size = 128;
1244 rdev->config.r600.sx_max_export_pos_size = 16;
1245 rdev->config.r600.sx_max_export_smx_size = 128;
1246 rdev->config.r600.sq_num_cf_insts = 1;
1247 break;
1248 case CHIP_RV670:
1249 rdev->config.r600.max_pipes = 4;
1250 rdev->config.r600.max_tile_pipes = 4;
1251 rdev->config.r600.max_simds = 4;
1252 rdev->config.r600.max_backends = 4;
1253 rdev->config.r600.max_gprs = 192;
1254 rdev->config.r600.max_threads = 192;
1255 rdev->config.r600.max_stack_entries = 256;
1256 rdev->config.r600.max_hw_contexts = 8;
1257 rdev->config.r600.max_gs_threads = 16;
1258 rdev->config.r600.sx_max_export_size = 128;
1259 rdev->config.r600.sx_max_export_pos_size = 16;
1260 rdev->config.r600.sx_max_export_smx_size = 128;
1261 rdev->config.r600.sq_num_cf_insts = 2;
1262 break;
1263 default:
1264 break;
1265 }
1266
1267 /* Initialize HDP */
1268 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1269 WREG32((0x2c14 + j), 0x00000000);
1270 WREG32((0x2c18 + j), 0x00000000);
1271 WREG32((0x2c1c + j), 0x00000000);
1272 WREG32((0x2c20 + j), 0x00000000);
1273 WREG32((0x2c24 + j), 0x00000000);
1274 }
1275
1276 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1277
1278 /* Setup tiling */
1279 tiling_config = 0;
1280 ramcfg = RREG32(RAMCFG);
1281 switch (rdev->config.r600.max_tile_pipes) {
1282 case 1:
1283 tiling_config |= PIPE_TILING(0);
1284 break;
1285 case 2:
1286 tiling_config |= PIPE_TILING(1);
1287 break;
1288 case 4:
1289 tiling_config |= PIPE_TILING(2);
1290 break;
1291 case 8:
1292 tiling_config |= PIPE_TILING(3);
1293 break;
1294 default:
1295 break;
1296 }
d03f5d59 1297 rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes;
961fb597 1298 rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
3ce0a23d
JG		 1299 tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1300 tiling_config |= GROUP_SIZE(0);
961fb597 1301 rdev->config.r600.tiling_group_size = 256;
3ce0a23d
JG		 1302 tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
1303 if (tmp > 3) {
1304 tiling_config |= ROW_TILING(3);
1305 tiling_config |= SAMPLE_SPLIT(3);
1306 } else {
1307 tiling_config |= ROW_TILING(tmp);
1308 tiling_config |= SAMPLE_SPLIT(tmp);
1309 }
1310 tiling_config |= BANK_SWAPS(1);
d03f5d59
AD		 1311
1312 cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
1313 cc_rb_backend_disable |=
1314 BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MASK);
1315
1316 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
1317 cc_gc_shader_pipe_config |=
1318 INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK);
1319 cc_gc_shader_pipe_config |=
1320 INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK);
1321
1322 backend_map = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes,
1323 (R6XX_MAX_BACKENDS -
1324 r600_count_pipe_bits((cc_rb_backend_disable &
1325 R6XX_MAX_BACKENDS_MASK) >> 16)),
1326 (cc_rb_backend_disable >> 16));
1327
1328 tiling_config |= BACKEND_MAP(backend_map);
3ce0a23d
JG		 1329 WREG32(GB_TILING_CONFIG, tiling_config);
1330 WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
1331 WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
1332
3ce0a23d 1333 /* Setup pipes */
d03f5d59
AD		 1334 WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
1335 WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
f867c60d 1336 WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
3ce0a23d 1337
d03f5d59 1338 tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
3ce0a23d
JG		 1339 WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
1340 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
1341
1342 /* Setup some CP states */
1343 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
1344 WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
1345
1346 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
1347 SYNC_WALKER | SYNC_ALIGNER));
1348 /* Setup various GPU states */
1349 if (rdev->family == CHIP_RV670)
1350 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
1351
1352 tmp = RREG32(SX_DEBUG_1);
1353 tmp |= SMX_EVENT_RELEASE;
1354 if ((rdev->family > CHIP_R600))
1355 tmp |= ENABLE_NEW_SMX_ADDRESS;
1356 WREG32(SX_DEBUG_1, tmp);
1357
1358 if (((rdev->family) == CHIP_R600) ||
1359 ((rdev->family) == CHIP_RV630) ||
1360 ((rdev->family) == CHIP_RV610) ||
1361 ((rdev->family) == CHIP_RV620) ||
ee59f2b4
AD		 1362 ((rdev->family) == CHIP_RS780) ||
1363 ((rdev->family) == CHIP_RS880)) {
3ce0a23d
JG		 1364 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
1365 } else {
1366 WREG32(DB_DEBUG, 0);
1367 }
1368 WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
1369 DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
1370
1371 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1372 WREG32(VGT_NUM_INSTANCES, 0);
1373
1374 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
1375 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
1376
1377 tmp = RREG32(SQ_MS_FIFO_SIZES);
1378 if (((rdev->family) == CHIP_RV610) ||
1379 ((rdev->family) == CHIP_RV620) ||
ee59f2b4
AD		 1380 ((rdev->family) == CHIP_RS780) ||
1381 ((rdev->family) == CHIP_RS880)) {
3ce0a23d
JG		 1382 tmp = (CACHE_FIFO_SIZE(0xa) |
1383 FETCH_FIFO_HIWATER(0xa) |
1384 DONE_FIFO_HIWATER(0xe0) |
1385 ALU_UPDATE_FIFO_HIWATER(0x8));
1386 } else if (((rdev->family) == CHIP_R600) ||
1387 ((rdev->family) == CHIP_RV630)) {
1388 tmp &= ~DONE_FIFO_HIWATER(0xff);
1389 tmp |= DONE_FIFO_HIWATER(0x4);
1390 }
1391 WREG32(SQ_MS_FIFO_SIZES, tmp);
1392
1393 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1394 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
1395 */
1396 sq_config = RREG32(SQ_CONFIG);
1397 sq_config &= ~(PS_PRIO(3) |
1398 VS_PRIO(3) |
1399 GS_PRIO(3) |
1400 ES_PRIO(3));
1401 sq_config |= (DX9_CONSTS |
1402 VC_ENABLE |
1403 PS_PRIO(0) |
1404 VS_PRIO(1) |
1405 GS_PRIO(2) |
1406 ES_PRIO(3));
1407
1408 if ((rdev->family) == CHIP_R600) {
1409 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
1410 NUM_VS_GPRS(124) |
1411 NUM_CLAUSE_TEMP_GPRS(4));
1412 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
1413 NUM_ES_GPRS(0));
1414 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
1415 NUM_VS_THREADS(48) |
1416 NUM_GS_THREADS(4) |
1417 NUM_ES_THREADS(4));
1418 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
1419 NUM_VS_STACK_ENTRIES(128));
1420 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
1421 NUM_ES_STACK_ENTRIES(0));
1422 } else if (((rdev->family) == CHIP_RV610) ||
1423 ((rdev->family) == CHIP_RV620) ||
ee59f2b4
AD		 1424 ((rdev->family) == CHIP_RS780) ||
1425 ((rdev->family) == CHIP_RS880)) {
3ce0a23d
JG		 1426 /* no vertex cache */
1427 sq_config &= ~VC_ENABLE;
1428
1429 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1430 NUM_VS_GPRS(44) |
1431 NUM_CLAUSE_TEMP_GPRS(2));
1432 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1433 NUM_ES_GPRS(17));
1434 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1435 NUM_VS_THREADS(78) |
1436 NUM_GS_THREADS(4) |
1437 NUM_ES_THREADS(31));
1438 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1439 NUM_VS_STACK_ENTRIES(40));
1440 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1441 NUM_ES_STACK_ENTRIES(16));
1442 } else if (((rdev->family) == CHIP_RV630) ||
1443 ((rdev->family) == CHIP_RV635)) {
1444 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1445 NUM_VS_GPRS(44) |
1446 NUM_CLAUSE_TEMP_GPRS(2));
1447 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
1448 NUM_ES_GPRS(18));
1449 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1450 NUM_VS_THREADS(78) |
1451 NUM_GS_THREADS(4) |
1452 NUM_ES_THREADS(31));
1453 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1454 NUM_VS_STACK_ENTRIES(40));
1455 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1456 NUM_ES_STACK_ENTRIES(16));
1457 } else if ((rdev->family) == CHIP_RV670) {
1458 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1459 NUM_VS_GPRS(44) |
1460 NUM_CLAUSE_TEMP_GPRS(2));
1461 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1462 NUM_ES_GPRS(17));
1463 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1464 NUM_VS_THREADS(78) |
1465 NUM_GS_THREADS(4) |
1466 NUM_ES_THREADS(31));
1467 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
1468 NUM_VS_STACK_ENTRIES(64));
1469 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
1470 NUM_ES_STACK_ENTRIES(64));
1471 }
1472
1473 WREG32(SQ_CONFIG, sq_config);
1474 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
1475 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
1476 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1477 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1478 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1479
1480 if (((rdev->family) == CHIP_RV610) ||
1481 ((rdev->family) == CHIP_RV620) ||
ee59f2b4
AD		 1482 ((rdev->family) == CHIP_RS780) ||
1483 ((rdev->family) == CHIP_RS880)) {
3ce0a23d
JG		 1484 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
1485 } else {
1486 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
1487 }
1488
1489 /* More default values. 2D/3D driver should adjust as needed */
1490 WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
1491 S1_X(0x4) | S1_Y(0xc)));
1492 WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
1493 S1_X(0x2) | S1_Y(0x2) |
1494 S2_X(0xa) | S2_Y(0x6) |
1495 S3_X(0x6) | S3_Y(0xa)));
1496 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
1497 S1_X(0x4) | S1_Y(0xc) |
1498 S2_X(0x1) | S2_Y(0x6) |
1499 S3_X(0xa) | S3_Y(0xe)));
1500 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
1501 S5_X(0x0) | S5_Y(0x0) |
1502 S6_X(0xb) | S6_Y(0x4) |
1503 S7_X(0x7) | S7_Y(0x8)));
1504
1505 WREG32(VGT_STRMOUT_EN, 0);
1506 tmp = rdev->config.r600.max_pipes * 16;
1507 switch (rdev->family) {
1508 case CHIP_RV610:
3ce0a23d 1509 case CHIP_RV620:
ee59f2b4
AD		 1510 case CHIP_RS780:
1511 case CHIP_RS880:
3ce0a23d
JG		 1512 tmp += 32;
1513 break;
1514 case CHIP_RV670:
1515 tmp += 128;
1516 break;
1517 default:
1518 break;
1519 }
1520 if (tmp > 256) {
1521 tmp = 256;
1522 }
1523 WREG32(VGT_ES_PER_GS, 128);
1524 WREG32(VGT_GS_PER_ES, tmp);
1525 WREG32(VGT_GS_PER_VS, 2);
1526 WREG32(VGT_GS_VERTEX_REUSE, 16);
1527
1528 /* more default values. 2D/3D driver should adjust as needed */
1529 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1530 WREG32(VGT_STRMOUT_EN, 0);
1531 WREG32(SX_MISC, 0);
1532 WREG32(PA_SC_MODE_CNTL, 0);
1533 WREG32(PA_SC_AA_CONFIG, 0);
1534 WREG32(PA_SC_LINE_STIPPLE, 0);
1535 WREG32(SPI_INPUT_Z, 0);
1536 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
1537 WREG32(CB_COLOR7_FRAG, 0);
1538
1539 /* Clear render buffer base addresses */
1540 WREG32(CB_COLOR0_BASE, 0);
1541 WREG32(CB_COLOR1_BASE, 0);
1542 WREG32(CB_COLOR2_BASE, 0);
1543 WREG32(CB_COLOR3_BASE, 0);
1544 WREG32(CB_COLOR4_BASE, 0);
1545 WREG32(CB_COLOR5_BASE, 0);
1546 WREG32(CB_COLOR6_BASE, 0);
1547 WREG32(CB_COLOR7_BASE, 0);
1548 WREG32(CB_COLOR7_FRAG, 0);
1549
1550 switch (rdev->family) {
1551 case CHIP_RV610:
3ce0a23d 1552 case CHIP_RV620:
ee59f2b4
AD		 1553 case CHIP_RS780:
1554 case CHIP_RS880:
3ce0a23d
JG		 1555 tmp = TC_L2_SIZE(8);
1556 break;
1557 case CHIP_RV630:
1558 case CHIP_RV635:
1559 tmp = TC_L2_SIZE(4);
1560 break;
1561 case CHIP_R600:
1562 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
1563 break;
1564 default:
1565 tmp = TC_L2_SIZE(0);
1566 break;
1567 }
1568 WREG32(TC_CNTL, tmp);
1569
1570 tmp = RREG32(HDP_HOST_PATH_CNTL);
1571 WREG32(HDP_HOST_PATH_CNTL, tmp);
1572
1573 tmp = RREG32(ARB_POP);
1574 tmp |= ENABLE_TC128;
1575 WREG32(ARB_POP, tmp);
1576
1577 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1578 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
1579 NUM_CLIP_SEQ(3)));
1580 WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
1581}
1582
1583
771fe6b9
JG		 1584/*
1585 * Indirect registers accessor
1586 */
3ce0a23d
JG		 1587u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
1588{
1589 u32 r;
1590
1591 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1592 (void)RREG32(PCIE_PORT_INDEX);
1593 r = RREG32(PCIE_PORT_DATA);
1594 return r;
1595}
1596
1597void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1598{
1599 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1600 (void)RREG32(PCIE_PORT_INDEX);
1601 WREG32(PCIE_PORT_DATA, (v));
1602 (void)RREG32(PCIE_PORT_DATA);
1603}
1604
3ce0a23d
JG		 1605/*
1606 * CP & Ring
1607 */
1608void r600_cp_stop(struct radeon_device *rdev)
1609{
1610 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1611}
1612
d8f60cfc 1613int r600_init_microcode(struct radeon_device *rdev)
3ce0a23d
JG		 1614{
1615 struct platform_device *pdev;
1616 const char *chip_name;
d8f60cfc
AD		 1617 const char *rlc_chip_name;
1618 size_t pfp_req_size, me_req_size, rlc_req_size;
3ce0a23d
JG		 1619 char fw_name[30];
1620 int err;
1621
1622 DRM_DEBUG("\n");
1623
1624 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
1625 err = IS_ERR(pdev);
1626 if (err) {
1627 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
1628 return -EINVAL;
1629 }
1630
1631 switch (rdev->family) {
d8f60cfc
AD		 1632 case CHIP_R600:
1633 chip_name = "R600";
1634 rlc_chip_name = "R600";
1635 break;
1636 case CHIP_RV610:
1637 chip_name = "RV610";
1638 rlc_chip_name = "R600";
1639 break;
1640 case CHIP_RV630:
1641 chip_name = "RV630";
1642 rlc_chip_name = "R600";
1643 break;
1644 case CHIP_RV620:
1645 chip_name = "RV620";
1646 rlc_chip_name = "R600";
1647 break;
1648 case CHIP_RV635:
1649 chip_name = "RV635";
1650 rlc_chip_name = "R600";
1651 break;
1652 case CHIP_RV670:
1653 chip_name = "RV670";
1654 rlc_chip_name = "R600";
1655 break;
3ce0a23d 1656 case CHIP_RS780:
d8f60cfc
AD		 1657 case CHIP_RS880:
1658 chip_name = "RS780";
1659 rlc_chip_name = "R600";
1660 break;
1661 case CHIP_RV770:
1662 chip_name = "RV770";
1663 rlc_chip_name = "R700";
1664 break;
3ce0a23d 1665 case CHIP_RV730:
d8f60cfc
AD		 1666 case CHIP_RV740:
1667 chip_name = "RV730";
1668 rlc_chip_name = "R700";
1669 break;
1670 case CHIP_RV710:
1671 chip_name = "RV710";
1672 rlc_chip_name = "R700";
1673 break;
fe251e2f
AD		 1674 case CHIP_CEDAR:
1675 chip_name = "CEDAR";
45f9a39b 1676 rlc_chip_name = "CEDAR";
fe251e2f
AD		 1677 break;
1678 case CHIP_REDWOOD:
1679 chip_name = "REDWOOD";
45f9a39b 1680 rlc_chip_name = "REDWOOD";
fe251e2f
AD		 1681 break;
1682 case CHIP_JUNIPER:
1683 chip_name = "JUNIPER";
45f9a39b 1684 rlc_chip_name = "JUNIPER";
fe251e2f
AD		 1685 break;
1686 case CHIP_CYPRESS:
1687 case CHIP_HEMLOCK:
1688 chip_name = "CYPRESS";
45f9a39b 1689 rlc_chip_name = "CYPRESS";
fe251e2f 1690 break;
3ce0a23d
JG		 1691 default: BUG();
1692 }
1693
fe251e2f
AD		 1694 if (rdev->family >= CHIP_CEDAR) {
1695 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
1696 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
45f9a39b 1697 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
fe251e2f 1698 } else if (rdev->family >= CHIP_RV770) {
3ce0a23d
JG		 1699 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
1700 me_req_size = R700_PM4_UCODE_SIZE * 4;
d8f60cfc 1701 rlc_req_size = R700_RLC_UCODE_SIZE * 4;
3ce0a23d
JG		 1702 } else {
1703 pfp_req_size = PFP_UCODE_SIZE * 4;
1704 me_req_size = PM4_UCODE_SIZE * 12;
d8f60cfc 1705 rlc_req_size = RLC_UCODE_SIZE * 4;
3ce0a23d
JG		 1706 }
1707
d8f60cfc 1708 DRM_INFO("Loading %s Microcode\n", chip_name);
3ce0a23d
JG		 1709
1710 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
1711 err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
1712 if (err)
1713 goto out;
1714 if (rdev->pfp_fw->size != pfp_req_size) {
1715 printk(KERN_ERR
1716 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
1717 rdev->pfp_fw->size, fw_name);
1718 err = -EINVAL;
1719 goto out;
1720 }
1721
1722 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
1723 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
1724 if (err)
1725 goto out;
1726 if (rdev->me_fw->size != me_req_size) {
1727 printk(KERN_ERR
1728 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
1729 rdev->me_fw->size, fw_name);
1730 err = -EINVAL;
1731 }
d8f60cfc
AD		 1732
1733 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
1734 err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
1735 if (err)
1736 goto out;
1737 if (rdev->rlc_fw->size != rlc_req_size) {
1738 printk(KERN_ERR
1739 "r600_rlc: Bogus length %zu in firmware \"%s\"\n",
1740 rdev->rlc_fw->size, fw_name);
1741 err = -EINVAL;
1742 }
1743
3ce0a23d
JG		 1744out:
1745 platform_device_unregister(pdev);
1746
1747 if (err) {
1748 if (err != -EINVAL)
1749 printk(KERN_ERR
1750 "r600_cp: Failed to load firmware \"%s\"\n",
1751 fw_name);
1752 release_firmware(rdev->pfp_fw);
1753 rdev->pfp_fw = NULL;
1754 release_firmware(rdev->me_fw);
1755 rdev->me_fw = NULL;
d8f60cfc
AD		 1756 release_firmware(rdev->rlc_fw);
1757 rdev->rlc_fw = NULL;
3ce0a23d
JG		 1758 }
1759 return err;
1760}
1761
1762static int r600_cp_load_microcode(struct radeon_device *rdev)
1763{
1764 const __be32 *fw_data;
1765 int i;
1766
1767 if (!rdev->me_fw || !rdev->pfp_fw)
1768 return -EINVAL;
1769
1770 r600_cp_stop(rdev);
1771
1772 WREG32(CP_RB_CNTL, RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
1773
1774 /* Reset cp */
1775 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
1776 RREG32(GRBM_SOFT_RESET);
1777 mdelay(15);
1778 WREG32(GRBM_SOFT_RESET, 0);
1779
1780 WREG32(CP_ME_RAM_WADDR, 0);
1781
1782 fw_data = (const __be32 *)rdev->me_fw->data;
1783 WREG32(CP_ME_RAM_WADDR, 0);
1784 for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
1785 WREG32(CP_ME_RAM_DATA,
1786 be32_to_cpup(fw_data++));
1787
1788 fw_data = (const __be32 *)rdev->pfp_fw->data;
1789 WREG32(CP_PFP_UCODE_ADDR, 0);
1790 for (i = 0; i < PFP_UCODE_SIZE; i++)
1791 WREG32(CP_PFP_UCODE_DATA,
1792 be32_to_cpup(fw_data++));
1793
1794 WREG32(CP_PFP_UCODE_ADDR, 0);
1795 WREG32(CP_ME_RAM_WADDR, 0);
1796 WREG32(CP_ME_RAM_RADDR, 0);
1797 return 0;
1798}
1799
1800int r600_cp_start(struct radeon_device *rdev)
1801{
1802 int r;
1803 uint32_t cp_me;
1804
1805 r = radeon_ring_lock(rdev, 7);
1806 if (r) {
1807 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1808 return r;
1809 }
1810 radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
1811 radeon_ring_write(rdev, 0x1);
fe251e2f
AD		 1812 if (rdev->family >= CHIP_CEDAR) {
1813 radeon_ring_write(rdev, 0x0);
1814 radeon_ring_write(rdev, rdev->config.evergreen.max_hw_contexts - 1);
1815 } else if (rdev->family >= CHIP_RV770) {
3ce0a23d
JG		 1816 radeon_ring_write(rdev, 0x0);
1817 radeon_ring_write(rdev, rdev->config.rv770.max_hw_contexts - 1);
fe251e2f
AD		 1818 } else {
1819 radeon_ring_write(rdev, 0x3);
1820 radeon_ring_write(rdev, rdev->config.r600.max_hw_contexts - 1);
3ce0a23d
JG		 1821 }
1822 radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1823 radeon_ring_write(rdev, 0);
1824 radeon_ring_write(rdev, 0);
1825 radeon_ring_unlock_commit(rdev);
1826
1827 cp_me = 0xff;
1828 WREG32(R_0086D8_CP_ME_CNTL, cp_me);
1829 return 0;
1830}
1831
1832int r600_cp_resume(struct radeon_device *rdev)
1833{
1834 u32 tmp;
1835 u32 rb_bufsz;
1836 int r;
1837
1838 /* Reset cp */
1839 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
1840 RREG32(GRBM_SOFT_RESET);
1841 mdelay(15);
1842 WREG32(GRBM_SOFT_RESET, 0);
1843
1844 /* Set ring buffer size */
1845 rb_bufsz = drm_order(rdev->cp.ring_size / 8);
d6f28938 1846 tmp = RB_NO_UPDATE | (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
3ce0a23d 1847#ifdef __BIG_ENDIAN
d6f28938 1848 tmp |= BUF_SWAP_32BIT;
3ce0a23d 1849#endif
d6f28938 1850 WREG32(CP_RB_CNTL, tmp);
3ce0a23d
JG		 1851 WREG32(CP_SEM_WAIT_TIMER, 0x4);
1852
1853 /* Set the write pointer delay */
1854 WREG32(CP_RB_WPTR_DELAY, 0);
1855
1856 /* Initialize the ring buffer's read and write pointers */
3ce0a23d
JG		 1857 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
1858 WREG32(CP_RB_RPTR_WR, 0);
1859 WREG32(CP_RB_WPTR, 0);
1860 WREG32(CP_RB_RPTR_ADDR, rdev->cp.gpu_addr & 0xFFFFFFFF);
1861 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->cp.gpu_addr));
1862 mdelay(1);
1863 WREG32(CP_RB_CNTL, tmp);
1864
1865 WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
1866 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
1867
1868 rdev->cp.rptr = RREG32(CP_RB_RPTR);
1869 rdev->cp.wptr = RREG32(CP_RB_WPTR);
1870
1871 r600_cp_start(rdev);
1872 rdev->cp.ready = true;
1873 r = radeon_ring_test(rdev);
1874 if (r) {
1875 rdev->cp.ready = false;
1876 return r;
1877 }
1878 return 0;
1879}
1880
1881void r600_cp_commit(struct radeon_device *rdev)
1882{
1883 WREG32(CP_RB_WPTR, rdev->cp.wptr);
1884 (void)RREG32(CP_RB_WPTR);
1885}
1886
1887void r600_ring_init(struct radeon_device *rdev, unsigned ring_size)
1888{
1889 u32 rb_bufsz;
1890
1891 /* Align ring size */
1892 rb_bufsz = drm_order(ring_size / 8);
1893 ring_size = (1 << (rb_bufsz + 1)) * 4;
1894 rdev->cp.ring_size = ring_size;
1895 rdev->cp.align_mask = 16 - 1;
1896}
1897
655efd3d
JG		 1898void r600_cp_fini(struct radeon_device *rdev)
1899{
1900 r600_cp_stop(rdev);
1901 radeon_ring_fini(rdev);
1902}
1903
3ce0a23d
JG		 1904
1905/*
1906 * GPU scratch registers helpers function.
1907 */
1908void r600_scratch_init(struct radeon_device *rdev)
1909{
1910 int i;
1911
1912 rdev->scratch.num_reg = 7;
1913 for (i = 0; i < rdev->scratch.num_reg; i++) {
1914 rdev->scratch.free[i] = true;
1915 rdev->scratch.reg[i] = SCRATCH_REG0 + (i * 4);
1916 }
1917}
1918
1919int r600_ring_test(struct radeon_device *rdev)
1920{
1921 uint32_t scratch;
1922 uint32_t tmp = 0;
1923 unsigned i;
1924 int r;
1925
1926 r = radeon_scratch_get(rdev, &scratch);
1927 if (r) {
1928 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
1929 return r;
1930 }
1931 WREG32(scratch, 0xCAFEDEAD);
1932 r = radeon_ring_lock(rdev, 3);
1933 if (r) {
1934 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1935 radeon_scratch_free(rdev, scratch);
1936 return r;
1937 }
1938 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1939 radeon_ring_write(rdev, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
1940 radeon_ring_write(rdev, 0xDEADBEEF);
1941 radeon_ring_unlock_commit(rdev);
1942 for (i = 0; i < rdev->usec_timeout; i++) {
1943 tmp = RREG32(scratch);
1944 if (tmp == 0xDEADBEEF)
1945 break;
1946 DRM_UDELAY(1);
1947 }
1948 if (i < rdev->usec_timeout) {
1949 DRM_INFO("ring test succeeded in %d usecs\n", i);
1950 } else {
1951 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
1952 scratch, tmp);
1953 r = -EINVAL;
1954 }
1955 radeon_scratch_free(rdev, scratch);
1956 return r;
1957}
1958
81cc35bf
JG		 1959void r600_wb_disable(struct radeon_device *rdev)
1960{
4c788679
JG		 1961 int r;
1962
81cc35bf
JG		 1963 WREG32(SCRATCH_UMSK, 0);
1964 if (rdev->wb.wb_obj) {
4c788679
JG		 1965 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
1966 if (unlikely(r != 0))
1967 return;
1968 radeon_bo_kunmap(rdev->wb.wb_obj);
1969 radeon_bo_unpin(rdev->wb.wb_obj);
1970 radeon_bo_unreserve(rdev->wb.wb_obj);
81cc35bf
JG		 1971 }
1972}
1973
1974void r600_wb_fini(struct radeon_device *rdev)
1975{
1976 r600_wb_disable(rdev);
1977 if (rdev->wb.wb_obj) {
4c788679 1978 radeon_bo_unref(&rdev->wb.wb_obj);
81cc35bf
JG		 1979 rdev->wb.wb = NULL;
1980 rdev->wb.wb_obj = NULL;
1981 }
1982}
1983
1984int r600_wb_enable(struct radeon_device *rdev)
3ce0a23d
JG		 1985{
1986 int r;
1987
1988 if (rdev->wb.wb_obj == NULL) {
4c788679
JG		 1989 r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true,
1990 RADEON_GEM_DOMAIN_GTT, &rdev->wb.wb_obj);
3ce0a23d 1991 if (r) {
4c788679 1992 dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);
3ce0a23d
JG		 1993 return r;
1994 }
4c788679
JG		 1995 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
1996 if (unlikely(r != 0)) {
1997 r600_wb_fini(rdev);
3ce0a23d
JG		 1998 return r;
1999 }
4c788679 2000 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
81cc35bf 2001 &rdev->wb.gpu_addr);
3ce0a23d 2002 if (r) {
4c788679
JG		 2003 radeon_bo_unreserve(rdev->wb.wb_obj);
2004 dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r);
81cc35bf 2005 r600_wb_fini(rdev);
3ce0a23d
JG		 2006 return r;
2007 }
4c788679
JG		 2008 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
2009 radeon_bo_unreserve(rdev->wb.wb_obj);
3ce0a23d 2010 if (r) {
4c788679 2011 dev_warn(rdev->dev, "(%d) map WB bo failed\n", r);
81cc35bf 2012 r600_wb_fini(rdev);
3ce0a23d
JG		 2013 return r;
2014 }
2015 }
2016 WREG32(SCRATCH_ADDR, (rdev->wb.gpu_addr >> 8) & 0xFFFFFFFF);
2017 WREG32(CP_RB_RPTR_ADDR, (rdev->wb.gpu_addr + 1024) & 0xFFFFFFFC);
2018 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + 1024) & 0xFF);
2019 WREG32(SCRATCH_UMSK, 0xff);
2020 return 0;
2021}
2022
3ce0a23d
JG		 2023void r600_fence_ring_emit(struct radeon_device *rdev,
2024 struct radeon_fence *fence)
2025{
d8f60cfc 2026 /* Also consider EVENT_WRITE_EOP. it handles the interrupts + timestamps + events */
44224c3f
AD		 2027
2028 radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0));
2029 radeon_ring_write(rdev, CACHE_FLUSH_AND_INV_EVENT);
2030 /* wait for 3D idle clean */
2031 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2032 radeon_ring_write(rdev, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2033 radeon_ring_write(rdev, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
3ce0a23d
JG		 2034 /* Emit fence sequence & fire IRQ */
2035 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2036 radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2037 radeon_ring_write(rdev, fence->seq);
d8f60cfc
AD		 2038 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
2039 radeon_ring_write(rdev, PACKET0(CP_INT_STATUS, 0));
2040 radeon_ring_write(rdev, RB_INT_STAT);
3ce0a23d
JG		 2041}
2042
3ce0a23d
JG		 2043int r600_copy_blit(struct radeon_device *rdev,
2044 uint64_t src_offset, uint64_t dst_offset,
2045 unsigned num_pages, struct radeon_fence *fence)
2046{
ff82f052
JG		 2047 int r;
2048
2049 mutex_lock(&rdev->r600_blit.mutex);
2050 rdev->r600_blit.vb_ib = NULL;
2051 r = r600_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE);
2052 if (r) {
2053 if (rdev->r600_blit.vb_ib)
2054 radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
2055 mutex_unlock(&rdev->r600_blit.mutex);
2056 return r;
2057 }
a77f1718 2058 r600_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE);
3ce0a23d 2059 r600_blit_done_copy(rdev, fence);
ff82f052 2060 mutex_unlock(&rdev->r600_blit.mutex);
3ce0a23d
JG		 2061 return 0;
2062}
2063
3ce0a23d
JG		 2064int r600_set_surface_reg(struct radeon_device *rdev, int reg,
2065 uint32_t tiling_flags, uint32_t pitch,
2066 uint32_t offset, uint32_t obj_size)
2067{
2068 /* FIXME: implement */
2069 return 0;
2070}
2071
2072void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
2073{
2074 /* FIXME: implement */
2075}
2076
2077
2078bool r600_card_posted(struct radeon_device *rdev)
2079{
2080 uint32_t reg;
2081
2082 /* first check CRTCs */
2083 reg = RREG32(D1CRTC_CONTROL) |
2084 RREG32(D2CRTC_CONTROL);
2085 if (reg & CRTC_EN)
2086 return true;
2087
2088 /* then check MEM_SIZE, in case the crtcs are off */
2089 if (RREG32(CONFIG_MEMSIZE))
2090 return true;
2091
2092 return false;
2093}
2094
fc30b8ef 2095int r600_startup(struct radeon_device *rdev)
3ce0a23d
JG		 2096{
2097 int r;
2098
779720a3
AD		 2099 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
2100 r = r600_init_microcode(rdev);
2101 if (r) {
2102 DRM_ERROR("Failed to load firmware!\n");
2103 return r;
2104 }
2105 }
2106
a3c1945a 2107 r600_mc_program(rdev);
1a029b76
JG		 2108 if (rdev->flags & RADEON_IS_AGP) {
2109 r600_agp_enable(rdev);
2110 } else {
2111 r = r600_pcie_gart_enable(rdev);
2112 if (r)
2113 return r;
2114 }
3ce0a23d 2115 r600_gpu_init(rdev);
c38c7b64
JG		 2116 r = r600_blit_init(rdev);
2117 if (r) {
2118 r600_blit_fini(rdev);
2119 rdev->asic->copy = NULL;
2120 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
2121 }
ff82f052
JG		 2122 /* pin copy shader into vram */
2123 if (rdev->r600_blit.shader_obj) {
2124 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
2125 if (unlikely(r != 0))
2126 return r;
2127 r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
2128 &rdev->r600_blit.shader_gpu_addr);
2129 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
7923c615 2130 if (r) {
ff82f052 2131 dev_err(rdev->dev, "(%d) pin blit object failed\n", r);
7923c615
AD		 2132 return r;
2133 }
2134 }
d8f60cfc 2135 /* Enable IRQ */
d8f60cfc
AD		 2136 r = r600_irq_init(rdev);
2137 if (r) {
2138 DRM_ERROR("radeon: IH init failed (%d).\n", r);
2139 radeon_irq_kms_fini(rdev);
2140 return r;
2141 }
2142 r600_irq_set(rdev);
2143
3ce0a23d
JG		 2144 r = radeon_ring_init(rdev, rdev->cp.ring_size);
2145 if (r)
2146 return r;
2147 r = r600_cp_load_microcode(rdev);
2148 if (r)
2149 return r;
2150 r = r600_cp_resume(rdev);
2151 if (r)
2152 return r;
81cc35bf
JG		 2153 /* write back buffer are not vital so don't worry about failure */
2154 r600_wb_enable(rdev);
3ce0a23d
JG		 2155 return 0;
2156}
2157
28d52043
DA		 2158void r600_vga_set_state(struct radeon_device *rdev, bool state)
2159{
2160 uint32_t temp;
2161
2162 temp = RREG32(CONFIG_CNTL);
2163 if (state == false) {
2164 temp &= ~(1<<0);
2165 temp |= (1<<1);
2166 } else {
2167 temp &= ~(1<<1);
2168 }
2169 WREG32(CONFIG_CNTL, temp);
2170}
2171
fc30b8ef
DA		 2172int r600_resume(struct radeon_device *rdev)
2173{
2174 int r;
2175
1a029b76
JG		 2176 /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
2177 * posting will perform necessary task to bring back GPU into good
2178 * shape.
2179 */
fc30b8ef 2180 /* post card */
e7d40b9a 2181 atom_asic_init(rdev->mode_info.atom_context);
fc30b8ef
DA		 2182 /* Initialize clocks */
2183 r = radeon_clocks_init(rdev);
2184 if (r) {
2185 return r;
2186 }
2187
2188 r = r600_startup(rdev);
2189 if (r) {
2190 DRM_ERROR("r600 startup failed on resume\n");
2191 return r;
2192 }
2193
62a8ea3f 2194 r = r600_ib_test(rdev);
fc30b8ef
DA		 2195 if (r) {
2196 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
2197 return r;
2198 }
38fd2c6f
RM		 2199
2200 r = r600_audio_init(rdev);
2201 if (r) {
2202 DRM_ERROR("radeon: audio resume failed\n");
2203 return r;
2204 }
2205
fc30b8ef
DA		 2206 return r;
2207}
2208
3ce0a23d
JG		 2209int r600_suspend(struct radeon_device *rdev)
2210{
4c788679
JG		 2211 int r;
2212
38fd2c6f 2213 r600_audio_fini(rdev);
3ce0a23d
JG		 2214 /* FIXME: we should wait for ring to be empty */
2215 r600_cp_stop(rdev);
bc1a631e 2216 rdev->cp.ready = false;
0c45249f 2217 r600_irq_suspend(rdev);
81cc35bf 2218 r600_wb_disable(rdev);
4aac0473 2219 r600_pcie_gart_disable(rdev);
bc1a631e 2220 /* unpin shaders bo */
30d2d9a5
JG		 2221 if (rdev->r600_blit.shader_obj) {
2222 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
2223 if (!r) {
2224 radeon_bo_unpin(rdev->r600_blit.shader_obj);
2225 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
2226 }
2227 }
3ce0a23d
JG		 2228 return 0;
2229}
2230
2231/* Plan is to move initialization in that function and use
2232 * helper function so that radeon_device_init pretty much
2233 * do nothing more than calling asic specific function. This
2234 * should also allow to remove a bunch of callback function
2235 * like vram_info.
2236 */
2237int r600_init(struct radeon_device *rdev)
771fe6b9 2238{
3ce0a23d 2239 int r;
771fe6b9 2240
3ce0a23d
JG		 2241 r = radeon_dummy_page_init(rdev);
2242 if (r)
2243 return r;
2244 if (r600_debugfs_mc_info_init(rdev)) {
2245 DRM_ERROR("Failed to register debugfs file for mc !\n");
2246 }
2247 /* This don't do much */
2248 r = radeon_gem_init(rdev);
2249 if (r)
2250 return r;
2251 /* Read BIOS */
2252 if (!radeon_get_bios(rdev)) {
2253 if (ASIC_IS_AVIVO(rdev))
2254 return -EINVAL;
2255 }
2256 /* Must be an ATOMBIOS */
e7d40b9a
JG		 2257 if (!rdev->is_atom_bios) {
2258 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
3ce0a23d 2259 return -EINVAL;
e7d40b9a 2260 }
3ce0a23d
JG		 2261 r = radeon_atombios_init(rdev);
2262 if (r)
2263 return r;
2264 /* Post card if necessary */
72542d77
DA		 2265 if (!r600_card_posted(rdev)) {
2266 if (!rdev->bios) {
2267 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2268 return -EINVAL;
2269 }
3ce0a23d
JG		 2270 DRM_INFO("GPU not posted. posting now...\n");
2271 atom_asic_init(rdev->mode_info.atom_context);
2272 }
2273 /* Initialize scratch registers */
2274 r600_scratch_init(rdev);
2275 /* Initialize surface registers */
2276 radeon_surface_init(rdev);
7433874e 2277 /* Initialize clocks */
5e6dde7e 2278 radeon_get_clock_info(rdev->ddev);
3ce0a23d
JG		 2279 r = radeon_clocks_init(rdev);
2280 if (r)
2281 return r;
7433874e
RM		 2282 /* Initialize power management */
2283 radeon_pm_init(rdev);
3ce0a23d
JG		 2284 /* Fence driver */
2285 r = radeon_fence_driver_init(rdev);
2286 if (r)
2287 return r;
700a0cc0
JG		 2288 if (rdev->flags & RADEON_IS_AGP) {
2289 r = radeon_agp_init(rdev);
2290 if (r)
2291 radeon_agp_disable(rdev);
2292 }
3ce0a23d 2293 r = r600_mc_init(rdev);
b574f251 2294 if (r)
3ce0a23d 2295 return r;
3ce0a23d 2296 /* Memory manager */
4c788679 2297 r = radeon_bo_init(rdev);
3ce0a23d
JG		 2298 if (r)
2299 return r;
d8f60cfc
AD		 2300
2301 r = radeon_irq_kms_init(rdev);
2302 if (r)
2303 return r;
2304
3ce0a23d
JG		 2305 rdev->cp.ring_obj = NULL;
2306 r600_ring_init(rdev, 1024 * 1024);
2307
d8f60cfc
AD		 2308 rdev->ih.ring_obj = NULL;
2309 r600_ih_ring_init(rdev, 64 * 1024);
3ce0a23d 2310
4aac0473
JG		 2311 r = r600_pcie_gart_init(rdev);
2312 if (r)
2313 return r;
2314
779720a3 2315 rdev->accel_working = true;
fc30b8ef 2316 r = r600_startup(rdev);
3ce0a23d 2317 if (r) {
655efd3d
JG		 2318 dev_err(rdev->dev, "disabling GPU acceleration\n");
2319 r600_cp_fini(rdev);
75c81298 2320 r600_wb_fini(rdev);
655efd3d
JG		 2321 r600_irq_fini(rdev);
2322 radeon_irq_kms_fini(rdev);
75c81298 2323 r600_pcie_gart_fini(rdev);
733289c2 2324 rdev->accel_working = false;
3ce0a23d 2325 }
733289c2
JG		 2326 if (rdev->accel_working) {
2327 r = radeon_ib_pool_init(rdev);
2328 if (r) {
db96380e 2329 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
733289c2 2330 rdev->accel_working = false;
db96380e
JG		 2331 } else {
2332 r = r600_ib_test(rdev);
2333 if (r) {
2334 dev_err(rdev->dev, "IB test failed (%d).\n", r);
2335 rdev->accel_working = false;
2336 }
733289c2 2337 }
3ce0a23d 2338 }
dafc3bd5
CK		 2339
2340 r = r600_audio_init(rdev);
2341 if (r)
2342 return r; /* TODO error handling */
3ce0a23d
JG		 2343 return 0;
2344}
2345
2346void r600_fini(struct radeon_device *rdev)
2347{
29fb52ca 2348 radeon_pm_fini(rdev);
dafc3bd5 2349 r600_audio_fini(rdev);
3ce0a23d 2350 r600_blit_fini(rdev);
655efd3d
JG		 2351 r600_cp_fini(rdev);
2352 r600_wb_fini(rdev);
d8f60cfc
AD		 2353 r600_irq_fini(rdev);
2354 radeon_irq_kms_fini(rdev);
4aac0473 2355 r600_pcie_gart_fini(rdev);
655efd3d 2356 radeon_agp_fini(rdev);
3ce0a23d
JG		 2357 radeon_gem_fini(rdev);
2358 radeon_fence_driver_fini(rdev);
2359 radeon_clocks_fini(rdev);
4c788679 2360 radeon_bo_fini(rdev);
e7d40b9a 2361 radeon_atombios_fini(rdev);
3ce0a23d
JG		 2362 kfree(rdev->bios);
2363 rdev->bios = NULL;
2364 radeon_dummy_page_fini(rdev);
2365}
2366
2367
2368/*
2369 * CS stuff
2370 */
2371void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
2372{
2373 /* FIXME: implement */
2374 radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
2375 radeon_ring_write(rdev, ib->gpu_addr & 0xFFFFFFFC);
2376 radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF);
2377 radeon_ring_write(rdev, ib->length_dw);
2378}
2379
2380int r600_ib_test(struct radeon_device *rdev)
2381{
2382 struct radeon_ib *ib;
2383 uint32_t scratch;
2384 uint32_t tmp = 0;
2385 unsigned i;
2386 int r;
2387
2388 r = radeon_scratch_get(rdev, &scratch);
2389 if (r) {
2390 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
2391 return r;
2392 }
2393 WREG32(scratch, 0xCAFEDEAD);
2394 r = radeon_ib_get(rdev, &ib);
2395 if (r) {
2396 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
2397 return r;
2398 }
2399 ib->ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
2400 ib->ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2401 ib->ptr[2] = 0xDEADBEEF;
2402 ib->ptr[3] = PACKET2(0);
2403 ib->ptr[4] = PACKET2(0);
2404 ib->ptr[5] = PACKET2(0);
2405 ib->ptr[6] = PACKET2(0);
2406 ib->ptr[7] = PACKET2(0);
2407 ib->ptr[8] = PACKET2(0);
2408 ib->ptr[9] = PACKET2(0);
2409 ib->ptr[10] = PACKET2(0);
2410 ib->ptr[11] = PACKET2(0);
2411 ib->ptr[12] = PACKET2(0);
2412 ib->ptr[13] = PACKET2(0);
2413 ib->ptr[14] = PACKET2(0);
2414 ib->ptr[15] = PACKET2(0);
2415 ib->length_dw = 16;
2416 r = radeon_ib_schedule(rdev, ib);
2417 if (r) {
2418 radeon_scratch_free(rdev, scratch);
2419 radeon_ib_free(rdev, &ib);
2420 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
2421 return r;
2422 }
2423 r = radeon_fence_wait(ib->fence, false);
2424 if (r) {
2425 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
2426 return r;
2427 }
2428 for (i = 0; i < rdev->usec_timeout; i++) {
2429 tmp = RREG32(scratch);
2430 if (tmp == 0xDEADBEEF)
2431 break;
2432 DRM_UDELAY(1);
2433 }
2434 if (i < rdev->usec_timeout) {
2435 DRM_INFO("ib test succeeded in %u usecs\n", i);
2436 } else {
2437 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
2438 scratch, tmp);
2439 r = -EINVAL;
2440 }
2441 radeon_scratch_free(rdev, scratch);
2442 radeon_ib_free(rdev, &ib);
771fe6b9
JG		 2443 return r;
2444}
2445
d8f60cfc
AD		 2446/*
2447 * Interrupts
2448 *
2449 * Interrupts use a ring buffer on r6xx/r7xx hardware. It works pretty
2450 * the same as the CP ring buffer, but in reverse. Rather than the CPU
2451 * writing to the ring and the GPU consuming, the GPU writes to the ring
2452 * and host consumes. As the host irq handler processes interrupts, it
2453 * increments the rptr. When the rptr catches up with the wptr, all the
2454 * current interrupts have been processed.
2455 */
2456
2457void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
2458{
2459 u32 rb_bufsz;
2460
2461 /* Align ring size */
2462 rb_bufsz = drm_order(ring_size / 4);
2463 ring_size = (1 << rb_bufsz) * 4;
2464 rdev->ih.ring_size = ring_size;
0c45249f
JG		 2465 rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
2466 rdev->ih.rptr = 0;
d8f60cfc
AD		 2467}
2468
0c45249f 2469static int r600_ih_ring_alloc(struct radeon_device *rdev)
d8f60cfc
AD		 2470{
2471 int r;
2472
d8f60cfc
AD		 2473 /* Allocate ring buffer */
2474 if (rdev->ih.ring_obj == NULL) {
4c788679
JG		 2475 r = radeon_bo_create(rdev, NULL, rdev->ih.ring_size,
2476 true,
2477 RADEON_GEM_DOMAIN_GTT,
2478 &rdev->ih.ring_obj);
d8f60cfc
AD		 2479 if (r) {
2480 DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r);
2481 return r;
2482 }
4c788679
JG		 2483 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2484 if (unlikely(r != 0))
2485 return r;
2486 r = radeon_bo_pin(rdev->ih.ring_obj,
2487 RADEON_GEM_DOMAIN_GTT,
2488 &rdev->ih.gpu_addr);
d8f60cfc 2489 if (r) {
4c788679 2490 radeon_bo_unreserve(rdev->ih.ring_obj);
d8f60cfc
AD		 2491 DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r);
2492 return r;
2493 }
4c788679
JG		 2494 r = radeon_bo_kmap(rdev->ih.ring_obj,
2495 (void **)&rdev->ih.ring);
2496 radeon_bo_unreserve(rdev->ih.ring_obj);
d8f60cfc
AD		 2497 if (r) {
2498 DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r);
2499 return r;
2500 }
2501 }
d8f60cfc
AD		 2502 return 0;
2503}
2504
2505static void r600_ih_ring_fini(struct radeon_device *rdev)
2506{
4c788679 2507 int r;
d8f60cfc 2508 if (rdev->ih.ring_obj) {
4c788679
JG		 2509 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2510 if (likely(r == 0)) {
2511 radeon_bo_kunmap(rdev->ih.ring_obj);
2512 radeon_bo_unpin(rdev->ih.ring_obj);
2513 radeon_bo_unreserve(rdev->ih.ring_obj);
2514 }
2515 radeon_bo_unref(&rdev->ih.ring_obj);
d8f60cfc
AD		 2516 rdev->ih.ring = NULL;
2517 rdev->ih.ring_obj = NULL;
2518 }
2519}
2520
45f9a39b 2521void r600_rlc_stop(struct radeon_device *rdev)
d8f60cfc
AD		 2522{
2523
45f9a39b
AD		 2524 if ((rdev->family >= CHIP_RV770) &&
2525 (rdev->family <= CHIP_RV740)) {
d8f60cfc
AD		 2526 /* r7xx asics need to soft reset RLC before halting */
2527 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
2528 RREG32(SRBM_SOFT_RESET);
2529 udelay(15000);
2530 WREG32(SRBM_SOFT_RESET, 0);
2531 RREG32(SRBM_SOFT_RESET);
2532 }
2533
2534 WREG32(RLC_CNTL, 0);
2535}
2536
2537static void r600_rlc_start(struct radeon_device *rdev)
2538{
2539 WREG32(RLC_CNTL, RLC_ENABLE);
2540}
2541
2542static int r600_rlc_init(struct radeon_device *rdev)
2543{
2544 u32 i;
2545 const __be32 *fw_data;
2546
2547 if (!rdev->rlc_fw)
2548 return -EINVAL;
2549
2550 r600_rlc_stop(rdev);
2551
2552 WREG32(RLC_HB_BASE, 0);
2553 WREG32(RLC_HB_CNTL, 0);
2554 WREG32(RLC_HB_RPTR, 0);
2555 WREG32(RLC_HB_WPTR, 0);
2556 WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
2557 WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
2558 WREG32(RLC_MC_CNTL, 0);
2559 WREG32(RLC_UCODE_CNTL, 0);
2560
2561 fw_data = (const __be32 *)rdev->rlc_fw->data;
45f9a39b
AD		 2562 if (rdev->family >= CHIP_CEDAR) {
2563 for (i = 0; i < EVERGREEN_RLC_UCODE_SIZE; i++) {
2564 WREG32(RLC_UCODE_ADDR, i);
2565 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2566 }
2567 } else if (rdev->family >= CHIP_RV770) {
d8f60cfc
AD		 2568 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) {
2569 WREG32(RLC_UCODE_ADDR, i);
2570 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2571 }
2572 } else {
2573 for (i = 0; i < RLC_UCODE_SIZE; i++) {
2574 WREG32(RLC_UCODE_ADDR, i);
2575 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2576 }
2577 }
2578 WREG32(RLC_UCODE_ADDR, 0);
2579
2580 r600_rlc_start(rdev);
2581
2582 return 0;
2583}
2584
2585static void r600_enable_interrupts(struct radeon_device *rdev)
2586{
2587 u32 ih_cntl = RREG32(IH_CNTL);
2588 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2589
2590 ih_cntl |= ENABLE_INTR;
2591 ih_rb_cntl |= IH_RB_ENABLE;
2592 WREG32(IH_CNTL, ih_cntl);
2593 WREG32(IH_RB_CNTL, ih_rb_cntl);
2594 rdev->ih.enabled = true;
2595}
2596
45f9a39b 2597void r600_disable_interrupts(struct radeon_device *rdev)
d8f60cfc
AD		 2598{
2599 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2600 u32 ih_cntl = RREG32(IH_CNTL);
2601
2602 ih_rb_cntl &= ~IH_RB_ENABLE;
2603 ih_cntl &= ~ENABLE_INTR;
2604 WREG32(IH_RB_CNTL, ih_rb_cntl);
2605 WREG32(IH_CNTL, ih_cntl);
2606 /* set rptr, wptr to 0 */
2607 WREG32(IH_RB_RPTR, 0);
2608 WREG32(IH_RB_WPTR, 0);
2609 rdev->ih.enabled = false;
2610 rdev->ih.wptr = 0;
2611 rdev->ih.rptr = 0;
2612}
2613
e0df1ac5
AD		 2614static void r600_disable_interrupt_state(struct radeon_device *rdev)
2615{
2616 u32 tmp;
2617
2618 WREG32(CP_INT_CNTL, 0);
2619 WREG32(GRBM_INT_CNTL, 0);
2620 WREG32(DxMODE_INT_MASK, 0);
2621 if (ASIC_IS_DCE3(rdev)) {
2622 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0);
2623 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0);
2624 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2625 WREG32(DC_HPD1_INT_CONTROL, tmp);
2626 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2627 WREG32(DC_HPD2_INT_CONTROL, tmp);
2628 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2629 WREG32(DC_HPD3_INT_CONTROL, tmp);
2630 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2631 WREG32(DC_HPD4_INT_CONTROL, tmp);
2632 if (ASIC_IS_DCE32(rdev)) {
2633 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
5898b1f3 2634 WREG32(DC_HPD5_INT_CONTROL, tmp);
e0df1ac5 2635 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
5898b1f3 2636 WREG32(DC_HPD6_INT_CONTROL, tmp);
e0df1ac5
AD		 2637 }
2638 } else {
2639 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2640 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2641 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
5898b1f3 2642 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
e0df1ac5 2643 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
5898b1f3 2644 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
e0df1ac5 2645 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
5898b1f3 2646 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
e0df1ac5
AD		 2647 }
2648}
2649
d8f60cfc
AD		 2650int r600_irq_init(struct radeon_device *rdev)
2651{
2652 int ret = 0;
2653 int rb_bufsz;
2654 u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
2655
2656 /* allocate ring */
0c45249f 2657 ret = r600_ih_ring_alloc(rdev);
d8f60cfc
AD		 2658 if (ret)
2659 return ret;
2660
2661 /* disable irqs */
2662 r600_disable_interrupts(rdev);
2663
2664 /* init rlc */
2665 ret = r600_rlc_init(rdev);
2666 if (ret) {
2667 r600_ih_ring_fini(rdev);
2668 return ret;
2669 }
2670
2671 /* setup interrupt control */
2672 /* set dummy read address to ring address */
2673 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
2674 interrupt_cntl = RREG32(INTERRUPT_CNTL);
2675 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
2676 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
2677 */
2678 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
2679 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
2680 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
2681 WREG32(INTERRUPT_CNTL, interrupt_cntl);
2682
2683 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
2684 rb_bufsz = drm_order(rdev->ih.ring_size / 4);
2685
2686 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
2687 IH_WPTR_OVERFLOW_CLEAR |
2688 (rb_bufsz << 1));
2689 /* WPTR writeback, not yet */
2690 /*ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;*/
2691 WREG32(IH_RB_WPTR_ADDR_LO, 0);
2692 WREG32(IH_RB_WPTR_ADDR_HI, 0);
2693
2694 WREG32(IH_RB_CNTL, ih_rb_cntl);
2695
2696 /* set rptr, wptr to 0 */
2697 WREG32(IH_RB_RPTR, 0);
2698 WREG32(IH_RB_WPTR, 0);
2699
2700 /* Default settings for IH_CNTL (disabled at first) */
2701 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10);
2702 /* RPTR_REARM only works if msi's are enabled */
2703 if (rdev->msi_enabled)
2704 ih_cntl |= RPTR_REARM;
2705
2706#ifdef __BIG_ENDIAN
2707 ih_cntl |= IH_MC_SWAP(IH_MC_SWAP_32BIT);
2708#endif
2709 WREG32(IH_CNTL, ih_cntl);
2710
2711 /* force the active interrupt state to all disabled */
45f9a39b
AD		 2712 if (rdev->family >= CHIP_CEDAR)
2713 evergreen_disable_interrupt_state(rdev);
2714 else
2715 r600_disable_interrupt_state(rdev);
d8f60cfc
AD		 2716
2717 /* enable irqs */
2718 r600_enable_interrupts(rdev);
2719
2720 return ret;
2721}
2722
0c45249f 2723void r600_irq_suspend(struct radeon_device *rdev)
d8f60cfc 2724{
45f9a39b 2725 r600_irq_disable(rdev);
d8f60cfc 2726 r600_rlc_stop(rdev);
0c45249f
JG		 2727}
2728
2729void r600_irq_fini(struct radeon_device *rdev)
2730{
2731 r600_irq_suspend(rdev);
d8f60cfc
AD		 2732 r600_ih_ring_fini(rdev);
2733}
2734
2735int r600_irq_set(struct radeon_device *rdev)
2736{
e0df1ac5
AD		 2737 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
2738 u32 mode_int = 0;
2739 u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
2031f77c 2740 u32 grbm_int_cntl = 0;
f2594933 2741 u32 hdmi1, hdmi2;
d8f60cfc 2742
003e69f9
JG		 2743 if (!rdev->irq.installed) {
2744 WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
2745 return -EINVAL;
2746 }
d8f60cfc 2747 /* don't enable anything if the ih is disabled */
79c2bbc5
JG		 2748 if (!rdev->ih.enabled) {
2749 r600_disable_interrupts(rdev);
2750 /* force the active interrupt state to all disabled */
2751 r600_disable_interrupt_state(rdev);
d8f60cfc 2752 return 0;
79c2bbc5 2753 }
d8f60cfc 2754
f2594933 2755 hdmi1 = RREG32(R600_HDMI_BLOCK1 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
e0df1ac5 2756 if (ASIC_IS_DCE3(rdev)) {
f2594933 2757 hdmi2 = RREG32(R600_HDMI_BLOCK3 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
e0df1ac5
AD		 2758 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2759 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2760 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2761 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
2762 if (ASIC_IS_DCE32(rdev)) {
2763 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
2764 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
2765 }
2766 } else {
f2594933 2767 hdmi2 = RREG32(R600_HDMI_BLOCK2 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
e0df1ac5
AD		 2768 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2769 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2770 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2771 }
2772
d8f60cfc
AD		 2773 if (rdev->irq.sw_int) {
2774 DRM_DEBUG("r600_irq_set: sw int\n");
2775 cp_int_cntl |= RB_INT_ENABLE;
2776 }
2777 if (rdev->irq.crtc_vblank_int[0]) {
2778 DRM_DEBUG("r600_irq_set: vblank 0\n");
2779 mode_int |= D1MODE_VBLANK_INT_MASK;
2780 }
2781 if (rdev->irq.crtc_vblank_int[1]) {
2782 DRM_DEBUG("r600_irq_set: vblank 1\n");
2783 mode_int |= D2MODE_VBLANK_INT_MASK;
2784 }
e0df1ac5
AD		 2785 if (rdev->irq.hpd[0]) {
2786 DRM_DEBUG("r600_irq_set: hpd 1\n");
2787 hpd1 |= DC_HPDx_INT_EN;
2788 }
2789 if (rdev->irq.hpd[1]) {
2790 DRM_DEBUG("r600_irq_set: hpd 2\n");
2791 hpd2 |= DC_HPDx_INT_EN;
2792 }
2793 if (rdev->irq.hpd[2]) {
2794 DRM_DEBUG("r600_irq_set: hpd 3\n");
2795 hpd3 |= DC_HPDx_INT_EN;
2796 }
2797 if (rdev->irq.hpd[3]) {
2798 DRM_DEBUG("r600_irq_set: hpd 4\n");
2799 hpd4 |= DC_HPDx_INT_EN;
2800 }
2801 if (rdev->irq.hpd[4]) {
2802 DRM_DEBUG("r600_irq_set: hpd 5\n");
2803 hpd5 |= DC_HPDx_INT_EN;
2804 }
2805 if (rdev->irq.hpd[5]) {
2806 DRM_DEBUG("r600_irq_set: hpd 6\n");
2807 hpd6 |= DC_HPDx_INT_EN;
2808 }
f2594933
CK		 2809 if (rdev->irq.hdmi[0]) {
2810 DRM_DEBUG("r600_irq_set: hdmi 1\n");
2811 hdmi1 |= R600_HDMI_INT_EN;
2812 }
2813 if (rdev->irq.hdmi[1]) {
2814 DRM_DEBUG("r600_irq_set: hdmi 2\n");
2815 hdmi2 |= R600_HDMI_INT_EN;
2816 }
2031f77c
AD		 2817 if (rdev->irq.gui_idle) {
2818 DRM_DEBUG("gui idle\n");
2819 grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
2820 }
d8f60cfc
AD		 2821
2822 WREG32(CP_INT_CNTL, cp_int_cntl);
2823 WREG32(DxMODE_INT_MASK, mode_int);
2031f77c 2824 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
f2594933 2825 WREG32(R600_HDMI_BLOCK1 + R600_HDMI_CNTL, hdmi1);
e0df1ac5 2826 if (ASIC_IS_DCE3(rdev)) {
f2594933 2827 WREG32(R600_HDMI_BLOCK3 + R600_HDMI_CNTL, hdmi2);
e0df1ac5
AD		 2828 WREG32(DC_HPD1_INT_CONTROL, hpd1);
2829 WREG32(DC_HPD2_INT_CONTROL, hpd2);
2830 WREG32(DC_HPD3_INT_CONTROL, hpd3);
2831 WREG32(DC_HPD4_INT_CONTROL, hpd4);
2832 if (ASIC_IS_DCE32(rdev)) {
2833 WREG32(DC_HPD5_INT_CONTROL, hpd5);
2834 WREG32(DC_HPD6_INT_CONTROL, hpd6);
2835 }
2836 } else {
f2594933 2837 WREG32(R600_HDMI_BLOCK2 + R600_HDMI_CNTL, hdmi2);
e0df1ac5
AD		 2838 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
2839 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
2840 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3);
2841 }
d8f60cfc
AD		 2842
2843 return 0;
2844}
2845
e0df1ac5
AD		 2846static inline void r600_irq_ack(struct radeon_device *rdev,
2847 u32 *disp_int,
2848 u32 *disp_int_cont,
2849 u32 *disp_int_cont2)
d8f60cfc 2850{
e0df1ac5
AD		 2851 u32 tmp;
2852
2853 if (ASIC_IS_DCE3(rdev)) {
2854 *disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
2855 *disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);
2856 *disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);
2857 } else {
2858 *disp_int = RREG32(DISP_INTERRUPT_STATUS);
2859 *disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
2860 *disp_int_cont2 = 0;
2861 }
d8f60cfc 2862
e0df1ac5 2863 if (*disp_int & LB_D1_VBLANK_INTERRUPT)
d8f60cfc 2864 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
e0df1ac5 2865 if (*disp_int & LB_D1_VLINE_INTERRUPT)
d8f60cfc 2866 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
e0df1ac5 2867 if (*disp_int & LB_D2_VBLANK_INTERRUPT)
d8f60cfc 2868 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
e0df1ac5 2869 if (*disp_int & LB_D2_VLINE_INTERRUPT)
d8f60cfc 2870 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
e0df1ac5
AD		 2871 if (*disp_int & DC_HPD1_INTERRUPT) {
2872 if (ASIC_IS_DCE3(rdev)) {
2873 tmp = RREG32(DC_HPD1_INT_CONTROL);
2874 tmp |= DC_HPDx_INT_ACK;
2875 WREG32(DC_HPD1_INT_CONTROL, tmp);
2876 } else {
2877 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
2878 tmp |= DC_HPDx_INT_ACK;
2879 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
2880 }
2881 }
2882 if (*disp_int & DC_HPD2_INTERRUPT) {
2883 if (ASIC_IS_DCE3(rdev)) {
2884 tmp = RREG32(DC_HPD2_INT_CONTROL);
2885 tmp |= DC_HPDx_INT_ACK;
2886 WREG32(DC_HPD2_INT_CONTROL, tmp);
2887 } else {
2888 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
2889 tmp |= DC_HPDx_INT_ACK;
2890 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
2891 }
2892 }
2893 if (*disp_int_cont & DC_HPD3_INTERRUPT) {
2894 if (ASIC_IS_DCE3(rdev)) {
2895 tmp = RREG32(DC_HPD3_INT_CONTROL);
2896 tmp |= DC_HPDx_INT_ACK;
2897 WREG32(DC_HPD3_INT_CONTROL, tmp);
2898 } else {
2899 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
2900 tmp |= DC_HPDx_INT_ACK;
2901 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
2902 }
2903 }
2904 if (*disp_int_cont & DC_HPD4_INTERRUPT) {
2905 tmp = RREG32(DC_HPD4_INT_CONTROL);
2906 tmp |= DC_HPDx_INT_ACK;
2907 WREG32(DC_HPD4_INT_CONTROL, tmp);
2908 }
2909 if (ASIC_IS_DCE32(rdev)) {
2910 if (*disp_int_cont2 & DC_HPD5_INTERRUPT) {
2911 tmp = RREG32(DC_HPD5_INT_CONTROL);
2912 tmp |= DC_HPDx_INT_ACK;
2913 WREG32(DC_HPD5_INT_CONTROL, tmp);
2914 }
2915 if (*disp_int_cont2 & DC_HPD6_INTERRUPT) {
2916 tmp = RREG32(DC_HPD5_INT_CONTROL);
2917 tmp |= DC_HPDx_INT_ACK;
2918 WREG32(DC_HPD6_INT_CONTROL, tmp);
2919 }
2920 }
f2594933
CK		 2921 if (RREG32(R600_HDMI_BLOCK1 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
2922 WREG32_P(R600_HDMI_BLOCK1 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
2923 }
2924 if (ASIC_IS_DCE3(rdev)) {
2925 if (RREG32(R600_HDMI_BLOCK3 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
2926 WREG32_P(R600_HDMI_BLOCK3 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
2927 }
2928 } else {
2929 if (RREG32(R600_HDMI_BLOCK2 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
2930 WREG32_P(R600_HDMI_BLOCK2 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
2931 }
2932 }
d8f60cfc
AD		 2933}
2934
2935void r600_irq_disable(struct radeon_device *rdev)
2936{
e0df1ac5 2937 u32 disp_int, disp_int_cont, disp_int_cont2;
d8f60cfc
AD		 2938
2939 r600_disable_interrupts(rdev);
2940 /* Wait and acknowledge irq */
2941 mdelay(1);
e0df1ac5
AD		 2942 r600_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2);
2943 r600_disable_interrupt_state(rdev);
d8f60cfc
AD		 2944}
2945
2946static inline u32 r600_get_ih_wptr(struct radeon_device *rdev)
2947{
2948 u32 wptr, tmp;
3ce0a23d 2949
d8f60cfc
AD		 2950 /* XXX use writeback */
2951 wptr = RREG32(IH_RB_WPTR);
3ce0a23d 2952
d8f60cfc 2953 if (wptr & RB_OVERFLOW) {
7924e5eb
JG		 2954 /* When a ring buffer overflow happen start parsing interrupt
2955 * from the last not overwritten vector (wptr + 16). Hopefully
2956 * this should allow us to catchup.
2957 */
2958 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
2959 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
2960 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
d8f60cfc
AD		 2961 tmp = RREG32(IH_RB_CNTL);
2962 tmp |= IH_WPTR_OVERFLOW_CLEAR;
2963 WREG32(IH_RB_CNTL, tmp);
2964 }
0c45249f 2965 return (wptr & rdev->ih.ptr_mask);
d8f60cfc 2966}
3ce0a23d 2967
d8f60cfc
AD		 2968/* r600 IV Ring
2969 * Each IV ring entry is 128 bits:
2970 * [7:0] - interrupt source id
2971 * [31:8] - reserved
2972 * [59:32] - interrupt source data
2973 * [127:60] - reserved
2974 *
2975 * The basic interrupt vector entries
2976 * are decoded as follows:
2977 * src_id src_data description
2978 * 1 0 D1 Vblank
2979 * 1 1 D1 Vline
2980 * 5 0 D2 Vblank
2981 * 5 1 D2 Vline
2982 * 19 0 FP Hot plug detection A
2983 * 19 1 FP Hot plug detection B
2984 * 19 2 DAC A auto-detection
2985 * 19 3 DAC B auto-detection
f2594933
CK		 2986 * 21 4 HDMI block A
2987 * 21 5 HDMI block B
d8f60cfc
AD		 2988 * 176 - CP_INT RB
2989 * 177 - CP_INT IB1
2990 * 178 - CP_INT IB2
2991 * 181 - EOP Interrupt
2992 * 233 - GUI Idle
2993 *
2994 * Note, these are based on r600 and may need to be
2995 * adjusted or added to on newer asics
2996 */
2997
2998int r600_irq_process(struct radeon_device *rdev)
2999{
3000 u32 wptr = r600_get_ih_wptr(rdev);
3001 u32 rptr = rdev->ih.rptr;
3002 u32 src_id, src_data;
e0df1ac5 3003 u32 ring_index, disp_int, disp_int_cont, disp_int_cont2;
d8f60cfc 3004 unsigned long flags;
d4877cf2 3005 bool queue_hotplug = false;
d8f60cfc
AD		 3006
3007 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
79c2bbc5
JG		 3008 if (!rdev->ih.enabled)
3009 return IRQ_NONE;
d8f60cfc
AD		 3010
3011 spin_lock_irqsave(&rdev->ih.lock, flags);
3012
3013 if (rptr == wptr) {
3014 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3015 return IRQ_NONE;
3016 }
3017 if (rdev->shutdown) {
3018 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3019 return IRQ_NONE;
3020 }
3021
3022restart_ih:
3023 /* display interrupts */
e0df1ac5 3024 r600_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2);
d8f60cfc
AD		 3025
3026 rdev->ih.wptr = wptr;
3027 while (rptr != wptr) {
3028 /* wptr/rptr are in bytes! */
3029 ring_index = rptr / 4;
3030 src_id = rdev->ih.ring[ring_index] & 0xff;
3031 src_data = rdev->ih.ring[ring_index + 1] & 0xfffffff;
3032
3033 switch (src_id) {
3034 case 1: /* D1 vblank/vline */
3035 switch (src_data) {
3036 case 0: /* D1 vblank */
3037 if (disp_int & LB_D1_VBLANK_INTERRUPT) {
3038 drm_handle_vblank(rdev->ddev, 0);
839461d3 3039 rdev->pm.vblank_sync = true;
73a6d3fc 3040 wake_up(&rdev->irq.vblank_queue);
d8f60cfc
AD		 3041 disp_int &= ~LB_D1_VBLANK_INTERRUPT;
3042 DRM_DEBUG("IH: D1 vblank\n");
3043 }
3044 break;
3045 case 1: /* D1 vline */
3046 if (disp_int & LB_D1_VLINE_INTERRUPT) {
3047 disp_int &= ~LB_D1_VLINE_INTERRUPT;
3048 DRM_DEBUG("IH: D1 vline\n");
3049 }
3050 break;
3051 default:
b042589c 3052 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
d8f60cfc
AD		 3053 break;
3054 }
3055 break;
3056 case 5: /* D2 vblank/vline */
3057 switch (src_data) {
3058 case 0: /* D2 vblank */
3059 if (disp_int & LB_D2_VBLANK_INTERRUPT) {
3060 drm_handle_vblank(rdev->ddev, 1);
839461d3 3061 rdev->pm.vblank_sync = true;
73a6d3fc 3062 wake_up(&rdev->irq.vblank_queue);
d8f60cfc
AD		 3063 disp_int &= ~LB_D2_VBLANK_INTERRUPT;
3064 DRM_DEBUG("IH: D2 vblank\n");
3065 }
3066 break;
3067 case 1: /* D1 vline */
3068 if (disp_int & LB_D2_VLINE_INTERRUPT) {
3069 disp_int &= ~LB_D2_VLINE_INTERRUPT;
3070 DRM_DEBUG("IH: D2 vline\n");
3071 }
3072 break;
3073 default:
b042589c 3074 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
d8f60cfc
AD		 3075 break;
3076 }
3077 break;
e0df1ac5
AD		 3078 case 19: /* HPD/DAC hotplug */
3079 switch (src_data) {
3080 case 0:
3081 if (disp_int & DC_HPD1_INTERRUPT) {
3082 disp_int &= ~DC_HPD1_INTERRUPT;
d4877cf2
AD		 3083 queue_hotplug = true;
3084 DRM_DEBUG("IH: HPD1\n");
e0df1ac5
AD		 3085 }
3086 break;
3087 case 1:
3088 if (disp_int & DC_HPD2_INTERRUPT) {
3089 disp_int &= ~DC_HPD2_INTERRUPT;
d4877cf2
AD		 3090 queue_hotplug = true;
3091 DRM_DEBUG("IH: HPD2\n");
e0df1ac5
AD		 3092 }
3093 break;
3094 case 4:
3095 if (disp_int_cont & DC_HPD3_INTERRUPT) {
3096 disp_int_cont &= ~DC_HPD3_INTERRUPT;
d4877cf2
AD		 3097 queue_hotplug = true;
3098 DRM_DEBUG("IH: HPD3\n");
e0df1ac5
AD		 3099 }
3100 break;
3101 case 5:
3102 if (disp_int_cont & DC_HPD4_INTERRUPT) {
3103 disp_int_cont &= ~DC_HPD4_INTERRUPT;
d4877cf2
AD		 3104 queue_hotplug = true;
3105 DRM_DEBUG("IH: HPD4\n");
e0df1ac5
AD		 3106 }
3107 break;
3108 case 10:
3109 if (disp_int_cont2 & DC_HPD5_INTERRUPT) {
5898b1f3 3110 disp_int_cont2 &= ~DC_HPD5_INTERRUPT;
d4877cf2
AD		 3111 queue_hotplug = true;
3112 DRM_DEBUG("IH: HPD5\n");
e0df1ac5
AD		 3113 }
3114 break;
3115 case 12:
3116 if (disp_int_cont2 & DC_HPD6_INTERRUPT) {
5898b1f3 3117 disp_int_cont2 &= ~DC_HPD6_INTERRUPT;
d4877cf2
AD		 3118 queue_hotplug = true;
3119 DRM_DEBUG("IH: HPD6\n");
e0df1ac5
AD		 3120 }
3121 break;
3122 default:
b042589c 3123 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
e0df1ac5
AD		 3124 break;
3125 }
3126 break;
f2594933
CK		 3127 case 21: /* HDMI */
3128 DRM_DEBUG("IH: HDMI: 0x%x\n", src_data);
3129 r600_audio_schedule_polling(rdev);
3130 break;
d8f60cfc
AD		 3131 case 176: /* CP_INT in ring buffer */
3132 case 177: /* CP_INT in IB1 */
3133 case 178: /* CP_INT in IB2 */
3134 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
3135 radeon_fence_process(rdev);
3136 break;
3137 case 181: /* CP EOP event */
3138 DRM_DEBUG("IH: CP EOP\n");
3139 break;
2031f77c
AD		 3140 case 233: /* GUI IDLE */
3141 DRM_DEBUG("IH: CP EOP\n");
3142 rdev->pm.gui_idle = true;
3143 wake_up(&rdev->irq.idle_queue);
3144 break;
d8f60cfc 3145 default:
b042589c 3146 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
d8f60cfc
AD		 3147 break;
3148 }
3149
3150 /* wptr/rptr are in bytes! */
0c45249f
JG		 3151 rptr += 16;
3152 rptr &= rdev->ih.ptr_mask;
d8f60cfc
AD		 3153 }
3154 /* make sure wptr hasn't changed while processing */
3155 wptr = r600_get_ih_wptr(rdev);
3156 if (wptr != rdev->ih.wptr)
3157 goto restart_ih;
d4877cf2
AD		 3158 if (queue_hotplug)
3159 queue_work(rdev->wq, &rdev->hotplug_work);
d8f60cfc
AD		 3160 rdev->ih.rptr = rptr;
3161 WREG32(IH_RB_RPTR, rdev->ih.rptr);
3162 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3163 return IRQ_HANDLED;
3164}
3ce0a23d
JG		 3165
3166/*
3167 * Debugfs info
3168 */
3169#if defined(CONFIG_DEBUG_FS)
3170
3171static int r600_debugfs_cp_ring_info(struct seq_file *m, void *data)
771fe6b9 3172{
3ce0a23d
JG		 3173 struct drm_info_node *node = (struct drm_info_node *) m->private;
3174 struct drm_device *dev = node->minor->dev;
3175 struct radeon_device *rdev = dev->dev_private;
3ce0a23d
JG		 3176 unsigned count, i, j;
3177
3178 radeon_ring_free_size(rdev);
d6840766 3179 count = (rdev->cp.ring_size / 4) - rdev->cp.ring_free_dw;
3ce0a23d 3180 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(CP_STAT));
d6840766
RM		 3181 seq_printf(m, "CP_RB_WPTR 0x%08x\n", RREG32(CP_RB_WPTR));
3182 seq_printf(m, "CP_RB_RPTR 0x%08x\n", RREG32(CP_RB_RPTR));
3183 seq_printf(m, "driver's copy of the CP_RB_WPTR 0x%08x\n", rdev->cp.wptr);
3184 seq_printf(m, "driver's copy of the CP_RB_RPTR 0x%08x\n", rdev->cp.rptr);
3ce0a23d
JG		 3185 seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
3186 seq_printf(m, "%u dwords in ring\n", count);
d6840766 3187 i = rdev->cp.rptr;
3ce0a23d 3188 for (j = 0; j <= count; j++) {
3ce0a23d 3189 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
d6840766 3190 i = (i + 1) & rdev->cp.ptr_mask;
3ce0a23d
JG		 3191 }
3192 return 0;
3193}
3194
3195static int r600_debugfs_mc_info(struct seq_file *m, void *data)
3196{
3197 struct drm_info_node *node = (struct drm_info_node *) m->private;
3198 struct drm_device *dev = node->minor->dev;
3199 struct radeon_device *rdev = dev->dev_private;
3200
3201 DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
3202 DREG32_SYS(m, rdev, VM_L2_STATUS);
3203 return 0;
3204}
3205
3206static struct drm_info_list r600_mc_info_list[] = {
3207 {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
3208 {"r600_ring_info", r600_debugfs_cp_ring_info, 0, NULL},
3209};
3210#endif
3211
3212int r600_debugfs_mc_info_init(struct radeon_device *rdev)
3213{
3214#if defined(CONFIG_DEBUG_FS)
3215 return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
3216#else
3217 return 0;
3218#endif
771fe6b9 3219}
062b389c
JG		 3220
3221/**
3222 * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl
3223 * rdev: radeon device structure
3224 * bo: buffer object struct which userspace is waiting for idle
3225 *
3226 * Some R6XX/R7XX doesn't seems to take into account HDP flush performed
3227 * through ring buffer, this leads to corruption in rendering, see
3228 * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we
3229 * directly perform HDP flush by writing register through MMIO.
3230 */
3231void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
3232{
3233 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
3234}
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