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drm/radeon/kms: enable writeback (v2)
[net-next-2.6.git] / drivers / gpu / drm / radeon / r600.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
5a0e3ad6 28#include <linux/slab.h>
3ce0a23d
JG		 29#include <linux/seq_file.h>
30#include <linux/firmware.h>
31#include <linux/platform_device.h>
771fe6b9 32#include "drmP.h"
3ce0a23d 33#include "radeon_drm.h"
771fe6b9 34#include "radeon.h"
e6990375 35#include "radeon_asic.h"
3ce0a23d 36#include "radeon_mode.h"
3ce0a23d 37#include "r600d.h"
3ce0a23d 38#include "atom.h"
d39c3b89 39#include "avivod.h"
771fe6b9 40
3ce0a23d
JG		 41#define PFP_UCODE_SIZE 576
42#define PM4_UCODE_SIZE 1792
d8f60cfc 43#define RLC_UCODE_SIZE 768
3ce0a23d
JG		 44#define R700_PFP_UCODE_SIZE 848
45#define R700_PM4_UCODE_SIZE 1360
d8f60cfc 46#define R700_RLC_UCODE_SIZE 1024
fe251e2f
AD		 47#define EVERGREEN_PFP_UCODE_SIZE 1120
48#define EVERGREEN_PM4_UCODE_SIZE 1376
45f9a39b 49#define EVERGREEN_RLC_UCODE_SIZE 768
3ce0a23d
JG		 50
51/* Firmware Names */
52MODULE_FIRMWARE("radeon/R600_pfp.bin");
53MODULE_FIRMWARE("radeon/R600_me.bin");
54MODULE_FIRMWARE("radeon/RV610_pfp.bin");
55MODULE_FIRMWARE("radeon/RV610_me.bin");
56MODULE_FIRMWARE("radeon/RV630_pfp.bin");
57MODULE_FIRMWARE("radeon/RV630_me.bin");
58MODULE_FIRMWARE("radeon/RV620_pfp.bin");
59MODULE_FIRMWARE("radeon/RV620_me.bin");
60MODULE_FIRMWARE("radeon/RV635_pfp.bin");
61MODULE_FIRMWARE("radeon/RV635_me.bin");
62MODULE_FIRMWARE("radeon/RV670_pfp.bin");
63MODULE_FIRMWARE("radeon/RV670_me.bin");
64MODULE_FIRMWARE("radeon/RS780_pfp.bin");
65MODULE_FIRMWARE("radeon/RS780_me.bin");
66MODULE_FIRMWARE("radeon/RV770_pfp.bin");
67MODULE_FIRMWARE("radeon/RV770_me.bin");
68MODULE_FIRMWARE("radeon/RV730_pfp.bin");
69MODULE_FIRMWARE("radeon/RV730_me.bin");
70MODULE_FIRMWARE("radeon/RV710_pfp.bin");
71MODULE_FIRMWARE("radeon/RV710_me.bin");
d8f60cfc
AD		 72MODULE_FIRMWARE("radeon/R600_rlc.bin");
73MODULE_FIRMWARE("radeon/R700_rlc.bin");
fe251e2f
AD		 74MODULE_FIRMWARE("radeon/CEDAR_pfp.bin");
75MODULE_FIRMWARE("radeon/CEDAR_me.bin");
45f9a39b 76MODULE_FIRMWARE("radeon/CEDAR_rlc.bin");
fe251e2f
AD		 77MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin");
78MODULE_FIRMWARE("radeon/REDWOOD_me.bin");
45f9a39b 79MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin");
fe251e2f
AD		 80MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin");
81MODULE_FIRMWARE("radeon/JUNIPER_me.bin");
45f9a39b 82MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin");
a7433742 83MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin");
fe251e2f 84MODULE_FIRMWARE("radeon/CYPRESS_me.bin");
45f9a39b 85MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin");
3ce0a23d
JG		 86
87int r600_debugfs_mc_info_init(struct radeon_device *rdev);
771fe6b9 88
1a029b76 89/* r600,rv610,rv630,rv620,rv635,rv670 */
771fe6b9
JG		 90int r600_mc_wait_for_idle(struct radeon_device *rdev);
91void r600_gpu_init(struct radeon_device *rdev);
3ce0a23d 92void r600_fini(struct radeon_device *rdev);
45f9a39b 93void r600_irq_disable(struct radeon_device *rdev);
771fe6b9 94
21a8122a
AD		 95/* get temperature in millidegrees */
96u32 rv6xx_get_temp(struct radeon_device *rdev)
97{
98 u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >>
99 ASIC_T_SHIFT;
100 u32 actual_temp = 0;
101
102 if ((temp >> 7) & 1)
103 actual_temp = 0;
104 else
105 actual_temp = (temp >> 1) & 0xff;
106
107 return actual_temp * 1000;
108}
109
ce8f5370 110void r600_pm_get_dynpm_state(struct radeon_device *rdev)
a48b9b4e
AD		 111{
112 int i;
113
ce8f5370
AD		 114 rdev->pm.dynpm_can_upclock = true;
115 rdev->pm.dynpm_can_downclock = true;
a48b9b4e
AD		 116
117 /* power state array is low to high, default is first */
118 if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) {
119 int min_power_state_index = 0;
120
121 if (rdev->pm.num_power_states > 2)
122 min_power_state_index = 1;
123
ce8f5370
AD		 124 switch (rdev->pm.dynpm_planned_action) {
125 case DYNPM_ACTION_MINIMUM:
a48b9b4e
AD		 126 rdev->pm.requested_power_state_index = min_power_state_index;
127 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 128 rdev->pm.dynpm_can_downclock = false;
a48b9b4e 129 break;
ce8f5370 130 case DYNPM_ACTION_DOWNCLOCK:
a48b9b4e
AD		 131 if (rdev->pm.current_power_state_index == min_power_state_index) {
132 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
ce8f5370 133 rdev->pm.dynpm_can_downclock = false;
a48b9b4e
AD		 134 } else {
135 if (rdev->pm.active_crtc_count > 1) {
136 for (i = 0; i < rdev->pm.num_power_states; i++) {
d7311171 137 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
a48b9b4e
AD		 138 continue;
139 else if (i >= rdev->pm.current_power_state_index) {
140 rdev->pm.requested_power_state_index =
141 rdev->pm.current_power_state_index;
142 break;
143 } else {
144 rdev->pm.requested_power_state_index = i;
145 break;
146 }
147 }
773c3fa3
AD		 148 } else {
149 if (rdev->pm.current_power_state_index == 0)
150 rdev->pm.requested_power_state_index =
151 rdev->pm.num_power_states - 1;
152 else
153 rdev->pm.requested_power_state_index =
154 rdev->pm.current_power_state_index - 1;
155 }
a48b9b4e
AD		 156 }
157 rdev->pm.requested_clock_mode_index = 0;
d7311171
AD		 158 /* don't use the power state if crtcs are active and no display flag is set */
159 if ((rdev->pm.active_crtc_count > 0) &&
160 (rdev->pm.power_state[rdev->pm.requested_power_state_index].
161 clock_info[rdev->pm.requested_clock_mode_index].flags &
162 RADEON_PM_MODE_NO_DISPLAY)) {
163 rdev->pm.requested_power_state_index++;
164 }
a48b9b4e 165 break;
ce8f5370 166 case DYNPM_ACTION_UPCLOCK:
a48b9b4e
AD		 167 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
168 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
ce8f5370 169 rdev->pm.dynpm_can_upclock = false;
a48b9b4e
AD		 170 } else {
171 if (rdev->pm.active_crtc_count > 1) {
172 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
d7311171 173 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
a48b9b4e
AD		 174 continue;
175 else if (i <= rdev->pm.current_power_state_index) {
176 rdev->pm.requested_power_state_index =
177 rdev->pm.current_power_state_index;
178 break;
179 } else {
180 rdev->pm.requested_power_state_index = i;
181 break;
182 }
183 }
184 } else
185 rdev->pm.requested_power_state_index =
186 rdev->pm.current_power_state_index + 1;
187 }
188 rdev->pm.requested_clock_mode_index = 0;
189 break;
ce8f5370 190 case DYNPM_ACTION_DEFAULT:
58e21dff
AD		 191 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
192 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 193 rdev->pm.dynpm_can_upclock = false;
58e21dff 194 break;
ce8f5370 195 case DYNPM_ACTION_NONE:
a48b9b4e
AD		 196 default:
197 DRM_ERROR("Requested mode for not defined action\n");
198 return;
199 }
200 } else {
201 /* XXX select a power state based on AC/DC, single/dualhead, etc. */
202 /* for now just select the first power state and switch between clock modes */
203 /* power state array is low to high, default is first (0) */
204 if (rdev->pm.active_crtc_count > 1) {
205 rdev->pm.requested_power_state_index = -1;
206 /* start at 1 as we don't want the default mode */
207 for (i = 1; i < rdev->pm.num_power_states; i++) {
d7311171 208 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
a48b9b4e
AD		 209 continue;
210 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) ||
211 (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) {
212 rdev->pm.requested_power_state_index = i;
213 break;
214 }
215 }
216 /* if nothing selected, grab the default state. */
217 if (rdev->pm.requested_power_state_index == -1)
218 rdev->pm.requested_power_state_index = 0;
219 } else
220 rdev->pm.requested_power_state_index = 1;
221
ce8f5370
AD		 222 switch (rdev->pm.dynpm_planned_action) {
223 case DYNPM_ACTION_MINIMUM:
a48b9b4e 224 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 225 rdev->pm.dynpm_can_downclock = false;
a48b9b4e 226 break;
ce8f5370 227 case DYNPM_ACTION_DOWNCLOCK:
a48b9b4e
AD		 228 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
229 if (rdev->pm.current_clock_mode_index == 0) {
230 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 231 rdev->pm.dynpm_can_downclock = false;
a48b9b4e
AD		 232 } else
233 rdev->pm.requested_clock_mode_index =
234 rdev->pm.current_clock_mode_index - 1;
235 } else {
236 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 237 rdev->pm.dynpm_can_downclock = false;
a48b9b4e 238 }
d7311171
AD		 239 /* don't use the power state if crtcs are active and no display flag is set */
240 if ((rdev->pm.active_crtc_count > 0) &&
241 (rdev->pm.power_state[rdev->pm.requested_power_state_index].
242 clock_info[rdev->pm.requested_clock_mode_index].flags &
243 RADEON_PM_MODE_NO_DISPLAY)) {
244 rdev->pm.requested_clock_mode_index++;
245 }
a48b9b4e 246 break;
ce8f5370 247 case DYNPM_ACTION_UPCLOCK:
a48b9b4e
AD		 248 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
249 if (rdev->pm.current_clock_mode_index ==
250 (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) {
251 rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index;
ce8f5370 252 rdev->pm.dynpm_can_upclock = false;
a48b9b4e
AD		 253 } else
254 rdev->pm.requested_clock_mode_index =
255 rdev->pm.current_clock_mode_index + 1;
256 } else {
257 rdev->pm.requested_clock_mode_index =
258 rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1;
ce8f5370 259 rdev->pm.dynpm_can_upclock = false;
a48b9b4e
AD		 260 }
261 break;
ce8f5370 262 case DYNPM_ACTION_DEFAULT:
58e21dff
AD		 263 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
264 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 265 rdev->pm.dynpm_can_upclock = false;
58e21dff 266 break;
ce8f5370 267 case DYNPM_ACTION_NONE:
a48b9b4e
AD		 268 default:
269 DRM_ERROR("Requested mode for not defined action\n");
270 return;
271 }
272 }
273
d9fdaafb 274 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
ce8a3eb2
AD		 275 rdev->pm.power_state[rdev->pm.requested_power_state_index].
276 clock_info[rdev->pm.requested_clock_mode_index].sclk,
277 rdev->pm.power_state[rdev->pm.requested_power_state_index].
278 clock_info[rdev->pm.requested_clock_mode_index].mclk,
279 rdev->pm.power_state[rdev->pm.requested_power_state_index].
280 pcie_lanes);
a48b9b4e
AD		 281}
282
ce8f5370
AD		 283static int r600_pm_get_type_index(struct radeon_device *rdev,
284 enum radeon_pm_state_type ps_type,
285 int instance)
bae6b562 286{
ce8f5370
AD		 287 int i;
288 int found_instance = -1;
bae6b562 289
ce8f5370
AD		 290 for (i = 0; i < rdev->pm.num_power_states; i++) {
291 if (rdev->pm.power_state[i].type == ps_type) {
292 found_instance++;
293 if (found_instance == instance)
294 return i;
a424816f 295 }
ce8f5370
AD		 296 }
297 /* return default if no match */
298 return rdev->pm.default_power_state_index;
299}
300
301void rs780_pm_init_profile(struct radeon_device *rdev)
302{
303 if (rdev->pm.num_power_states == 2) {
304 /* default */
305 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
306 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
307 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
308 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
309 /* low sh */
310 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
311 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
312 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
313 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 314 /* mid sh */
315 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
316 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
317 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
318 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 319 /* high sh */
320 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
321 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
322 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
323 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
324 /* low mh */
325 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
326 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
327 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
328 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 329 /* mid mh */
330 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
331 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
332 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
333 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 334 /* high mh */
335 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
336 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1;
337 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
338 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
339 } else if (rdev->pm.num_power_states == 3) {
340 /* default */
341 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
342 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
343 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
344 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
345 /* low sh */
346 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
347 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
348 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
349 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 350 /* mid sh */
351 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
352 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
353 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
354 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 355 /* high sh */
356 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
357 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2;
358 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
359 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
360 /* low mh */
361 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1;
362 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1;
363 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
364 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 365 /* mid mh */
366 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1;
367 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1;
368 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
369 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 370 /* high mh */
371 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1;
372 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
373 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
374 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
375 } else {
376 /* default */
377 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
378 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
379 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
380 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
381 /* low sh */
382 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2;
383 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2;
384 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
385 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 386 /* mid sh */
387 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2;
388 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2;
389 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
390 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 391 /* high sh */
392 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2;
393 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3;
394 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
395 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
396 /* low mh */
397 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
398 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
399 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
400 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 401 /* mid mh */
402 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
403 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
404 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
405 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 406 /* high mh */
407 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
408 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3;
409 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
410 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
411 }
412}
bae6b562 413
ce8f5370
AD		 414void r600_pm_init_profile(struct radeon_device *rdev)
415{
416 if (rdev->family == CHIP_R600) {
417 /* XXX */
418 /* default */
419 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
420 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
421 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
4bff5171 422 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 423 /* low sh */
424 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
425 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
426 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
4bff5171 427 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 428 /* mid sh */
429 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
430 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
431 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
432 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 433 /* high sh */
434 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
435 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
436 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
4bff5171 437 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 438 /* low mh */
439 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
440 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
441 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
4bff5171 442 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 443 /* mid mh */
444 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
445 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
446 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
447 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 448 /* high mh */
449 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
450 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
451 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
4bff5171 452 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 453 } else {
454 if (rdev->pm.num_power_states < 4) {
455 /* default */
456 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
457 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
458 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
459 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
460 /* low sh */
4bff5171
AD		 461 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
462 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
ce8f5370 463 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
c9e75b21
AD		 464 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
465 /* mid sh */
466 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
467 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
468 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
469 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
ce8f5370 470 /* high sh */
4bff5171
AD		 471 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
472 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
ce8f5370
AD		 473 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
474 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
475 /* low mh */
4bff5171
AD		 476 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
477 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2;
ce8f5370 478 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
c9e75b21
AD		 479 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
480 /* low mh */
481 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
482 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2;
483 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
484 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
ce8f5370 485 /* high mh */
4bff5171
AD		 486 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
487 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
ce8f5370
AD		 488 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
489 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
490 } else {
491 /* default */
492 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
493 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
494 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
495 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
496 /* low sh */
4bff5171
AD		 497 if (rdev->flags & RADEON_IS_MOBILITY) {
498 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx =
499 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
500 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx =
501 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
502 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
c9e75b21 503 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
4bff5171
AD		 504 } else {
505 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx =
506 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
507 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx =
508 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
509 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
c9e75b21
AD		 510 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
511 }
512 /* mid sh */
513 if (rdev->flags & RADEON_IS_MOBILITY) {
514 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx =
515 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
516 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx =
517 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
518 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
519 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
520 } else {
521 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx =
522 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
523 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx =
524 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
525 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
526 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
4bff5171 527 }
ce8f5370 528 /* high sh */
4bff5171
AD		 529 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx =
530 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
531 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx =
532 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
ce8f5370
AD		 533 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
534 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
535 /* low mh */
4bff5171
AD		 536 if (rdev->flags & RADEON_IS_MOBILITY) {
537 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx =
538 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
539 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx =
540 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
541 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
c9e75b21 542 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
4bff5171
AD		 543 } else {
544 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx =
545 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
546 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx =
547 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
548 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
c9e75b21
AD		 549 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
550 }
551 /* mid mh */
552 if (rdev->flags & RADEON_IS_MOBILITY) {
553 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx =
554 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
555 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx =
556 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
557 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
558 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
559 } else {
560 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx =
561 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
562 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx =
563 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
564 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
565 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
4bff5171 566 }
ce8f5370 567 /* high mh */
4bff5171
AD		 568 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx =
569 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
570 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx =
571 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
ce8f5370
AD		 572 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
573 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
574 }
575 }
bae6b562
AD		 576}
577
49e02b73
AD		 578void r600_pm_misc(struct radeon_device *rdev)
579{
a081a9d6
RM		 580 int req_ps_idx = rdev->pm.requested_power_state_index;
581 int req_cm_idx = rdev->pm.requested_clock_mode_index;
582 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
583 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
7ac9aa5a 584
4d60173f
AD		 585 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
586 if (voltage->voltage != rdev->pm.current_vddc) {
587 radeon_atom_set_voltage(rdev, voltage->voltage);
588 rdev->pm.current_vddc = voltage->voltage;
d9fdaafb 589 DRM_DEBUG_DRIVER("Setting: v: %d\n", voltage->voltage);
4d60173f
AD		 590 }
591 }
49e02b73
AD		 592}
593
def9ba9c
AD		 594bool r600_gui_idle(struct radeon_device *rdev)
595{
596 if (RREG32(GRBM_STATUS) & GUI_ACTIVE)
597 return false;
598 else
599 return true;
600}
601
e0df1ac5
AD		 602/* hpd for digital panel detect/disconnect */
603bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
604{
605 bool connected = false;
606
607 if (ASIC_IS_DCE3(rdev)) {
608 switch (hpd) {
609 case RADEON_HPD_1:
610 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
611 connected = true;
612 break;
613 case RADEON_HPD_2:
614 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
615 connected = true;
616 break;
617 case RADEON_HPD_3:
618 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
619 connected = true;
620 break;
621 case RADEON_HPD_4:
622 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
623 connected = true;
624 break;
625 /* DCE 3.2 */
626 case RADEON_HPD_5:
627 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
628 connected = true;
629 break;
630 case RADEON_HPD_6:
631 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
632 connected = true;
633 break;
634 default:
635 break;
636 }
637 } else {
638 switch (hpd) {
639 case RADEON_HPD_1:
640 if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
641 connected = true;
642 break;
643 case RADEON_HPD_2:
644 if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
645 connected = true;
646 break;
647 case RADEON_HPD_3:
648 if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
649 connected = true;
650 break;
651 default:
652 break;
653 }
654 }
655 return connected;
656}
657
658void r600_hpd_set_polarity(struct radeon_device *rdev,
429770b3 659 enum radeon_hpd_id hpd)
e0df1ac5
AD		 660{
661 u32 tmp;
662 bool connected = r600_hpd_sense(rdev, hpd);
663
664 if (ASIC_IS_DCE3(rdev)) {
665 switch (hpd) {
666 case RADEON_HPD_1:
667 tmp = RREG32(DC_HPD1_INT_CONTROL);
668 if (connected)
669 tmp &= ~DC_HPDx_INT_POLARITY;
670 else
671 tmp |= DC_HPDx_INT_POLARITY;
672 WREG32(DC_HPD1_INT_CONTROL, tmp);
673 break;
674 case RADEON_HPD_2:
675 tmp = RREG32(DC_HPD2_INT_CONTROL);
676 if (connected)
677 tmp &= ~DC_HPDx_INT_POLARITY;
678 else
679 tmp |= DC_HPDx_INT_POLARITY;
680 WREG32(DC_HPD2_INT_CONTROL, tmp);
681 break;
682 case RADEON_HPD_3:
683 tmp = RREG32(DC_HPD3_INT_CONTROL);
684 if (connected)
685 tmp &= ~DC_HPDx_INT_POLARITY;
686 else
687 tmp |= DC_HPDx_INT_POLARITY;
688 WREG32(DC_HPD3_INT_CONTROL, tmp);
689 break;
690 case RADEON_HPD_4:
691 tmp = RREG32(DC_HPD4_INT_CONTROL);
692 if (connected)
693 tmp &= ~DC_HPDx_INT_POLARITY;
694 else
695 tmp |= DC_HPDx_INT_POLARITY;
696 WREG32(DC_HPD4_INT_CONTROL, tmp);
697 break;
698 case RADEON_HPD_5:
699 tmp = RREG32(DC_HPD5_INT_CONTROL);
700 if (connected)
701 tmp &= ~DC_HPDx_INT_POLARITY;
702 else
703 tmp |= DC_HPDx_INT_POLARITY;
704 WREG32(DC_HPD5_INT_CONTROL, tmp);
705 break;
706 /* DCE 3.2 */
707 case RADEON_HPD_6:
708 tmp = RREG32(DC_HPD6_INT_CONTROL);
709 if (connected)
710 tmp &= ~DC_HPDx_INT_POLARITY;
711 else
712 tmp |= DC_HPDx_INT_POLARITY;
713 WREG32(DC_HPD6_INT_CONTROL, tmp);
714 break;
715 default:
716 break;
717 }
718 } else {
719 switch (hpd) {
720 case RADEON_HPD_1:
721 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
722 if (connected)
723 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
724 else
725 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
726 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
727 break;
728 case RADEON_HPD_2:
729 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
730 if (connected)
731 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
732 else
733 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
734 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
735 break;
736 case RADEON_HPD_3:
737 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
738 if (connected)
739 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
740 else
741 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
742 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
743 break;
744 default:
745 break;
746 }
747 }
748}
749
750void r600_hpd_init(struct radeon_device *rdev)
751{
752 struct drm_device *dev = rdev->ddev;
753 struct drm_connector *connector;
754
755 if (ASIC_IS_DCE3(rdev)) {
756 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
757 if (ASIC_IS_DCE32(rdev))
758 tmp |= DC_HPDx_EN;
759
760 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
761 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
762 switch (radeon_connector->hpd.hpd) {
763 case RADEON_HPD_1:
764 WREG32(DC_HPD1_CONTROL, tmp);
765 rdev->irq.hpd[0] = true;
766 break;
767 case RADEON_HPD_2:
768 WREG32(DC_HPD2_CONTROL, tmp);
769 rdev->irq.hpd[1] = true;
770 break;
771 case RADEON_HPD_3:
772 WREG32(DC_HPD3_CONTROL, tmp);
773 rdev->irq.hpd[2] = true;
774 break;
775 case RADEON_HPD_4:
776 WREG32(DC_HPD4_CONTROL, tmp);
777 rdev->irq.hpd[3] = true;
778 break;
779 /* DCE 3.2 */
780 case RADEON_HPD_5:
781 WREG32(DC_HPD5_CONTROL, tmp);
782 rdev->irq.hpd[4] = true;
783 break;
784 case RADEON_HPD_6:
785 WREG32(DC_HPD6_CONTROL, tmp);
786 rdev->irq.hpd[5] = true;
787 break;
788 default:
789 break;
790 }
791 }
792 } else {
793 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
794 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
795 switch (radeon_connector->hpd.hpd) {
796 case RADEON_HPD_1:
797 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);
798 rdev->irq.hpd[0] = true;
799 break;
800 case RADEON_HPD_2:
801 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);
802 rdev->irq.hpd[1] = true;
803 break;
804 case RADEON_HPD_3:
805 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);
806 rdev->irq.hpd[2] = true;
807 break;
808 default:
809 break;
810 }
811 }
812 }
003e69f9
JG		 813 if (rdev->irq.installed)
814 r600_irq_set(rdev);
e0df1ac5
AD		 815}
816
817void r600_hpd_fini(struct radeon_device *rdev)
818{
819 struct drm_device *dev = rdev->ddev;
820 struct drm_connector *connector;
821
822 if (ASIC_IS_DCE3(rdev)) {
823 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
824 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
825 switch (radeon_connector->hpd.hpd) {
826 case RADEON_HPD_1:
827 WREG32(DC_HPD1_CONTROL, 0);
828 rdev->irq.hpd[0] = false;
829 break;
830 case RADEON_HPD_2:
831 WREG32(DC_HPD2_CONTROL, 0);
832 rdev->irq.hpd[1] = false;
833 break;
834 case RADEON_HPD_3:
835 WREG32(DC_HPD3_CONTROL, 0);
836 rdev->irq.hpd[2] = false;
837 break;
838 case RADEON_HPD_4:
839 WREG32(DC_HPD4_CONTROL, 0);
840 rdev->irq.hpd[3] = false;
841 break;
842 /* DCE 3.2 */
843 case RADEON_HPD_5:
844 WREG32(DC_HPD5_CONTROL, 0);
845 rdev->irq.hpd[4] = false;
846 break;
847 case RADEON_HPD_6:
848 WREG32(DC_HPD6_CONTROL, 0);
849 rdev->irq.hpd[5] = false;
850 break;
851 default:
852 break;
853 }
854 }
855 } else {
856 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
857 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
858 switch (radeon_connector->hpd.hpd) {
859 case RADEON_HPD_1:
860 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);
861 rdev->irq.hpd[0] = false;
862 break;
863 case RADEON_HPD_2:
864 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);
865 rdev->irq.hpd[1] = false;
866 break;
867 case RADEON_HPD_3:
868 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);
869 rdev->irq.hpd[2] = false;
870 break;
871 default:
872 break;
873 }
874 }
875 }
876}
877
771fe6b9 878/*
3ce0a23d 879 * R600 PCIE GART
771fe6b9 880 */
3ce0a23d
JG		 881void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
882{
883 unsigned i;
884 u32 tmp;
885
2e98f10a 886 /* flush hdp cache so updates hit vram */
812d0469
AD		 887 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740)) {
888 void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
889 u32 tmp;
890
891 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read
892 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL
893 */
894 WREG32(HDP_DEBUG1, 0);
895 tmp = readl((void __iomem *)ptr);
896 } else
897 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
2e98f10a 898
3ce0a23d
JG		 899 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
900 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
901 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
902 for (i = 0; i < rdev->usec_timeout; i++) {
903 /* read MC_STATUS */
904 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
905 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
906 if (tmp == 2) {
907 printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
908 return;
909 }
910 if (tmp) {
911 return;
912 }
913 udelay(1);
914 }
915}
916
4aac0473 917int r600_pcie_gart_init(struct radeon_device *rdev)
3ce0a23d 918{
4aac0473 919 int r;
3ce0a23d 920
4aac0473
JG		 921 if (rdev->gart.table.vram.robj) {
922 WARN(1, "R600 PCIE GART already initialized.\n");
923 return 0;
924 }
3ce0a23d
JG		 925 /* Initialize common gart structure */
926 r = radeon_gart_init(rdev);
4aac0473 927 if (r)
3ce0a23d 928 return r;
3ce0a23d 929 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
4aac0473
JG		 930 return radeon_gart_table_vram_alloc(rdev);
931}
932
933int r600_pcie_gart_enable(struct radeon_device *rdev)
934{
935 u32 tmp;
936 int r, i;
937
938 if (rdev->gart.table.vram.robj == NULL) {
939 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
940 return -EINVAL;
771fe6b9 941 }
4aac0473
JG		 942 r = radeon_gart_table_vram_pin(rdev);
943 if (r)
944 return r;
82568565 945 radeon_gart_restore(rdev);
bc1a631e 946
3ce0a23d
JG		 947 /* Setup L2 cache */
948 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
949 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
950 EFFECTIVE_L2_QUEUE_SIZE(7));
951 WREG32(VM_L2_CNTL2, 0);
952 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
953 /* Setup TLB control */
954 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
955 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
956 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
957 ENABLE_WAIT_L2_QUERY;
958 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
959 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
960 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
961 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
962 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
963 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
964 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
965 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
966 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
967 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
968 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
969 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
970 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
971 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
972 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
1a029b76 973 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
3ce0a23d
JG		 974 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
975 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
976 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
977 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
978 (u32)(rdev->dummy_page.addr >> 12));
979 for (i = 1; i < 7; i++)
980 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
771fe6b9 981
3ce0a23d
JG		 982 r600_pcie_gart_tlb_flush(rdev);
983 rdev->gart.ready = true;
771fe6b9
JG		 984 return 0;
985}
986
3ce0a23d 987void r600_pcie_gart_disable(struct radeon_device *rdev)
771fe6b9 988{
3ce0a23d 989 u32 tmp;
4c788679 990 int i, r;
771fe6b9 991
3ce0a23d
JG		 992 /* Disable all tables */
993 for (i = 0; i < 7; i++)
994 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
771fe6b9 995
3ce0a23d
JG		 996 /* Disable L2 cache */
997 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
998 EFFECTIVE_L2_QUEUE_SIZE(7));
999 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1000 /* Setup L1 TLB control */
1001 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1002 ENABLE_WAIT_L2_QUERY;
1003 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1004 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1005 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1006 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1007 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1008 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1009 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1010 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1011 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
1012 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
1013 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1014 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1015 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
1016 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
4aac0473 1017 if (rdev->gart.table.vram.robj) {
4c788679
JG		 1018 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
1019 if (likely(r == 0)) {
1020 radeon_bo_kunmap(rdev->gart.table.vram.robj);
1021 radeon_bo_unpin(rdev->gart.table.vram.robj);
1022 radeon_bo_unreserve(rdev->gart.table.vram.robj);
1023 }
4aac0473
JG		 1024 }
1025}
1026
1027void r600_pcie_gart_fini(struct radeon_device *rdev)
1028{
f9274562 1029 radeon_gart_fini(rdev);
4aac0473
JG		 1030 r600_pcie_gart_disable(rdev);
1031 radeon_gart_table_vram_free(rdev);
771fe6b9
JG		 1032}
1033
1a029b76
JG		 1034void r600_agp_enable(struct radeon_device *rdev)
1035{
1036 u32 tmp;
1037 int i;
1038
1039 /* Setup L2 cache */
1040 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1041 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1042 EFFECTIVE_L2_QUEUE_SIZE(7));
1043 WREG32(VM_L2_CNTL2, 0);
1044 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1045 /* Setup TLB control */
1046 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1047 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1048 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1049 ENABLE_WAIT_L2_QUERY;
1050 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1051 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1052 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
1053 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1054 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1055 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1056 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1057 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1058 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1059 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1060 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1061 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1062 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1063 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1064 for (i = 0; i < 7; i++)
1065 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1066}
1067
771fe6b9
JG		 1068int r600_mc_wait_for_idle(struct radeon_device *rdev)
1069{
3ce0a23d
JG		 1070 unsigned i;
1071 u32 tmp;
1072
1073 for (i = 0; i < rdev->usec_timeout; i++) {
1074 /* read MC_STATUS */
1075 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
1076 if (!tmp)
1077 return 0;
1078 udelay(1);
1079 }
1080 return -1;
771fe6b9
JG		 1081}
1082
a3c1945a 1083static void r600_mc_program(struct radeon_device *rdev)
771fe6b9 1084{
a3c1945a 1085 struct rv515_mc_save save;
3ce0a23d
JG		 1086 u32 tmp;
1087 int i, j;
771fe6b9 1088
3ce0a23d
JG		 1089 /* Initialize HDP */
1090 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1091 WREG32((0x2c14 + j), 0x00000000);
1092 WREG32((0x2c18 + j), 0x00000000);
1093 WREG32((0x2c1c + j), 0x00000000);
1094 WREG32((0x2c20 + j), 0x00000000);
1095 WREG32((0x2c24 + j), 0x00000000);
1096 }
1097 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
771fe6b9 1098
a3c1945a 1099 rv515_mc_stop(rdev, &save);
3ce0a23d 1100 if (r600_mc_wait_for_idle(rdev)) {
a3c1945a 1101 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
3ce0a23d 1102 }
a3c1945a 1103 /* Lockout access through VGA aperture (doesn't exist before R600) */
3ce0a23d 1104 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
3ce0a23d 1105 /* Update configuration */
1a029b76
JG		 1106 if (rdev->flags & RADEON_IS_AGP) {
1107 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1108 /* VRAM before AGP */
1109 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1110 rdev->mc.vram_start >> 12);
1111 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1112 rdev->mc.gtt_end >> 12);
1113 } else {
1114 /* VRAM after AGP */
1115 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1116 rdev->mc.gtt_start >> 12);
1117 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1118 rdev->mc.vram_end >> 12);
1119 }
1120 } else {
1121 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
1122 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
1123 }
3ce0a23d 1124 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
1a029b76 1125 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
3ce0a23d
JG		 1126 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1127 WREG32(MC_VM_FB_LOCATION, tmp);
1128 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1129 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
46fcd2b3 1130 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
3ce0a23d 1131 if (rdev->flags & RADEON_IS_AGP) {
1a029b76
JG		 1132 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
1133 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
3ce0a23d
JG		 1134 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1135 } else {
1136 WREG32(MC_VM_AGP_BASE, 0);
1137 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1138 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1139 }
3ce0a23d 1140 if (r600_mc_wait_for_idle(rdev)) {
a3c1945a 1141 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
3ce0a23d 1142 }
a3c1945a 1143 rv515_mc_resume(rdev, &save);
698443d9
DA		 1144 /* we need to own VRAM, so turn off the VGA renderer here
1145 * to stop it overwriting our objects */
d39c3b89 1146 rv515_vga_render_disable(rdev);
3ce0a23d
JG		 1147}
1148
d594e46a
JG		 1149/**
1150 * r600_vram_gtt_location - try to find VRAM & GTT location
1151 * @rdev: radeon device structure holding all necessary informations
1152 * @mc: memory controller structure holding memory informations
1153 *
1154 * Function will place try to place VRAM at same place as in CPU (PCI)
1155 * address space as some GPU seems to have issue when we reprogram at
1156 * different address space.
1157 *
1158 * If there is not enough space to fit the unvisible VRAM after the
1159 * aperture then we limit the VRAM size to the aperture.
1160 *
1161 * If we are using AGP then place VRAM adjacent to AGP aperture are we need
1162 * them to be in one from GPU point of view so that we can program GPU to
1163 * catch access outside them (weird GPU policy see ??).
1164 *
1165 * This function will never fails, worst case are limiting VRAM or GTT.
1166 *
1167 * Note: GTT start, end, size should be initialized before calling this
1168 * function on AGP platform.
1169 */
1170void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
1171{
1172 u64 size_bf, size_af;
1173
1174 if (mc->mc_vram_size > 0xE0000000) {
1175 /* leave room for at least 512M GTT */
1176 dev_warn(rdev->dev, "limiting VRAM\n");
1177 mc->real_vram_size = 0xE0000000;
1178 mc->mc_vram_size = 0xE0000000;
1179 }
1180 if (rdev->flags & RADEON_IS_AGP) {
1181 size_bf = mc->gtt_start;
1182 size_af = 0xFFFFFFFF - mc->gtt_end + 1;
1183 if (size_bf > size_af) {
1184 if (mc->mc_vram_size > size_bf) {
1185 dev_warn(rdev->dev, "limiting VRAM\n");
1186 mc->real_vram_size = size_bf;
1187 mc->mc_vram_size = size_bf;
1188 }
1189 mc->vram_start = mc->gtt_start - mc->mc_vram_size;
1190 } else {
1191 if (mc->mc_vram_size > size_af) {
1192 dev_warn(rdev->dev, "limiting VRAM\n");
1193 mc->real_vram_size = size_af;
1194 mc->mc_vram_size = size_af;
1195 }
1196 mc->vram_start = mc->gtt_end;
1197 }
1198 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
1199 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
1200 mc->mc_vram_size >> 20, mc->vram_start,
1201 mc->vram_end, mc->real_vram_size >> 20);
1202 } else {
1203 u64 base = 0;
1204 if (rdev->flags & RADEON_IS_IGP)
1205 base = (RREG32(MC_VM_FB_LOCATION) & 0xFFFF) << 24;
1206 radeon_vram_location(rdev, &rdev->mc, base);
8d369bb1 1207 rdev->mc.gtt_base_align = 0;
d594e46a
JG		 1208 radeon_gtt_location(rdev, mc);
1209 }
1210}
1211
3ce0a23d 1212int r600_mc_init(struct radeon_device *rdev)
771fe6b9 1213{
3ce0a23d 1214 u32 tmp;
5885b7a9 1215 int chansize, numchan;
771fe6b9 1216
3ce0a23d 1217 /* Get VRAM informations */
771fe6b9 1218 rdev->mc.vram_is_ddr = true;
3ce0a23d
JG		 1219 tmp = RREG32(RAMCFG);
1220 if (tmp & CHANSIZE_OVERRIDE) {
771fe6b9 1221 chansize = 16;
3ce0a23d 1222 } else if (tmp & CHANSIZE_MASK) {
771fe6b9
JG		 1223 chansize = 64;
1224 } else {
1225 chansize = 32;
1226 }
5885b7a9
AD		 1227 tmp = RREG32(CHMAP);
1228 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1229 case 0:
1230 default:
1231 numchan = 1;
1232 break;
1233 case 1:
1234 numchan = 2;
1235 break;
1236 case 2:
1237 numchan = 4;
1238 break;
1239 case 3:
1240 numchan = 8;
1241 break;
771fe6b9 1242 }
5885b7a9 1243 rdev->mc.vram_width = numchan * chansize;
3ce0a23d 1244 /* Could aper size report 0 ? */
01d73a69
JC		 1245 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
1246 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
3ce0a23d
JG		 1247 /* Setup GPU memory space */
1248 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
1249 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
51e5fcd3 1250 rdev->mc.visible_vram_size = rdev->mc.aper_size;
d594e46a 1251 r600_vram_gtt_location(rdev, &rdev->mc);
f47299c5 1252
f892034a
AD		 1253 if (rdev->flags & RADEON_IS_IGP) {
1254 rs690_pm_info(rdev);
06b6476d 1255 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
f892034a 1256 }
f47299c5 1257 radeon_update_bandwidth_info(rdev);
3ce0a23d 1258 return 0;
771fe6b9
JG		 1259}
1260
3ce0a23d
JG		 1261/* We doesn't check that the GPU really needs a reset we simply do the
1262 * reset, it's up to the caller to determine if the GPU needs one. We
1263 * might add an helper function to check that.
1264 */
1265int r600_gpu_soft_reset(struct radeon_device *rdev)
771fe6b9 1266{
a3c1945a 1267 struct rv515_mc_save save;
3ce0a23d
JG		 1268 u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) |
1269 S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) |
1270 S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) |
1271 S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) |
1272 S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) |
1273 S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) |
1274 S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) |
1275 S_008010_GUI_ACTIVE(1);
1276 u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) |
1277 S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) |
1278 S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) |
1279 S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) |
1280 S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) |
1281 S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) |
1282 S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) |
1283 S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1);
a3c1945a 1284 u32 tmp;
771fe6b9 1285
1a029b76
JG		 1286 dev_info(rdev->dev, "GPU softreset \n");
1287 dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n",
1288 RREG32(R_008010_GRBM_STATUS));
1289 dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n",
a3c1945a 1290 RREG32(R_008014_GRBM_STATUS2));
1a029b76
JG		 1291 dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n",
1292 RREG32(R_000E50_SRBM_STATUS));
a3c1945a
JG		 1293 rv515_mc_stop(rdev, &save);
1294 if (r600_mc_wait_for_idle(rdev)) {
1295 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1296 }
3ce0a23d 1297 /* Disable CP parsing/prefetching */
90aca4d2 1298 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
3ce0a23d
JG		 1299 /* Check if any of the rendering block is busy and reset it */
1300 if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) ||
1301 (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) {
a3c1945a 1302 tmp = S_008020_SOFT_RESET_CR(1) |
3ce0a23d
JG		 1303 S_008020_SOFT_RESET_DB(1) |
1304 S_008020_SOFT_RESET_CB(1) |
1305 S_008020_SOFT_RESET_PA(1) |
1306 S_008020_SOFT_RESET_SC(1) |
1307 S_008020_SOFT_RESET_SMX(1) |
1308 S_008020_SOFT_RESET_SPI(1) |
1309 S_008020_SOFT_RESET_SX(1) |
1310 S_008020_SOFT_RESET_SH(1) |
1311 S_008020_SOFT_RESET_TC(1) |
1312 S_008020_SOFT_RESET_TA(1) |
1313 S_008020_SOFT_RESET_VC(1) |
a3c1945a 1314 S_008020_SOFT_RESET_VGT(1);
1a029b76 1315 dev_info(rdev->dev, " R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
a3c1945a 1316 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
90aca4d2
JG		 1317 RREG32(R_008020_GRBM_SOFT_RESET);
1318 mdelay(15);
3ce0a23d 1319 WREG32(R_008020_GRBM_SOFT_RESET, 0);
3ce0a23d
JG		 1320 }
1321 /* Reset CP (we always reset CP) */
a3c1945a
JG		 1322 tmp = S_008020_SOFT_RESET_CP(1);
1323 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1324 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
90aca4d2
JG		 1325 RREG32(R_008020_GRBM_SOFT_RESET);
1326 mdelay(15);
3ce0a23d 1327 WREG32(R_008020_GRBM_SOFT_RESET, 0);
3ce0a23d 1328 /* Wait a little for things to settle down */
225758d8 1329 mdelay(1);
1a029b76
JG		 1330 dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n",
1331 RREG32(R_008010_GRBM_STATUS));
1332 dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n",
1333 RREG32(R_008014_GRBM_STATUS2));
1334 dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n",
1335 RREG32(R_000E50_SRBM_STATUS));
a3c1945a 1336 rv515_mc_resume(rdev, &save);
3ce0a23d
JG		 1337 return 0;
1338}
1339
225758d8
JG		 1340bool r600_gpu_is_lockup(struct radeon_device *rdev)
1341{
1342 u32 srbm_status;
1343 u32 grbm_status;
1344 u32 grbm_status2;
1345 int r;
1346
1347 srbm_status = RREG32(R_000E50_SRBM_STATUS);
1348 grbm_status = RREG32(R_008010_GRBM_STATUS);
1349 grbm_status2 = RREG32(R_008014_GRBM_STATUS2);
1350 if (!G_008010_GUI_ACTIVE(grbm_status)) {
1351 r100_gpu_lockup_update(&rdev->config.r300.lockup, &rdev->cp);
1352 return false;
1353 }
1354 /* force CP activities */
1355 r = radeon_ring_lock(rdev, 2);
1356 if (!r) {
1357 /* PACKET2 NOP */
1358 radeon_ring_write(rdev, 0x80000000);
1359 radeon_ring_write(rdev, 0x80000000);
1360 radeon_ring_unlock_commit(rdev);
1361 }
1362 rdev->cp.rptr = RREG32(R600_CP_RB_RPTR);
1363 return r100_gpu_cp_is_lockup(rdev, &rdev->config.r300.lockup, &rdev->cp);
1364}
1365
a2d07b74 1366int r600_asic_reset(struct radeon_device *rdev)
3ce0a23d
JG		 1367{
1368 return r600_gpu_soft_reset(rdev);
1369}
1370
1371static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
1372 u32 num_backends,
1373 u32 backend_disable_mask)
1374{
1375 u32 backend_map = 0;
1376 u32 enabled_backends_mask;
1377 u32 enabled_backends_count;
1378 u32 cur_pipe;
1379 u32 swizzle_pipe[R6XX_MAX_PIPES];
1380 u32 cur_backend;
1381 u32 i;
1382
1383 if (num_tile_pipes > R6XX_MAX_PIPES)
1384 num_tile_pipes = R6XX_MAX_PIPES;
1385 if (num_tile_pipes < 1)
1386 num_tile_pipes = 1;
1387 if (num_backends > R6XX_MAX_BACKENDS)
1388 num_backends = R6XX_MAX_BACKENDS;
1389 if (num_backends < 1)
1390 num_backends = 1;
1391
1392 enabled_backends_mask = 0;
1393 enabled_backends_count = 0;
1394 for (i = 0; i < R6XX_MAX_BACKENDS; ++i) {
1395 if (((backend_disable_mask >> i) & 1) == 0) {
1396 enabled_backends_mask |= (1 << i);
1397 ++enabled_backends_count;
1398 }
1399 if (enabled_backends_count == num_backends)
1400 break;
1401 }
1402
1403 if (enabled_backends_count == 0) {
1404 enabled_backends_mask = 1;
1405 enabled_backends_count = 1;
1406 }
1407
1408 if (enabled_backends_count != num_backends)
1409 num_backends = enabled_backends_count;
1410
1411 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES);
1412 switch (num_tile_pipes) {
1413 case 1:
1414 swizzle_pipe[0] = 0;
1415 break;
1416 case 2:
1417 swizzle_pipe[0] = 0;
1418 swizzle_pipe[1] = 1;
1419 break;
1420 case 3:
1421 swizzle_pipe[0] = 0;
1422 swizzle_pipe[1] = 1;
1423 swizzle_pipe[2] = 2;
1424 break;
1425 case 4:
1426 swizzle_pipe[0] = 0;
1427 swizzle_pipe[1] = 1;
1428 swizzle_pipe[2] = 2;
1429 swizzle_pipe[3] = 3;
1430 break;
1431 case 5:
1432 swizzle_pipe[0] = 0;
1433 swizzle_pipe[1] = 1;
1434 swizzle_pipe[2] = 2;
1435 swizzle_pipe[3] = 3;
1436 swizzle_pipe[4] = 4;
1437 break;
1438 case 6:
1439 swizzle_pipe[0] = 0;
1440 swizzle_pipe[1] = 2;
1441 swizzle_pipe[2] = 4;
1442 swizzle_pipe[3] = 5;
1443 swizzle_pipe[4] = 1;
1444 swizzle_pipe[5] = 3;
1445 break;
1446 case 7:
1447 swizzle_pipe[0] = 0;
1448 swizzle_pipe[1] = 2;
1449 swizzle_pipe[2] = 4;
1450 swizzle_pipe[3] = 6;
1451 swizzle_pipe[4] = 1;
1452 swizzle_pipe[5] = 3;
1453 swizzle_pipe[6] = 5;
1454 break;
1455 case 8:
1456 swizzle_pipe[0] = 0;
1457 swizzle_pipe[1] = 2;
1458 swizzle_pipe[2] = 4;
1459 swizzle_pipe[3] = 6;
1460 swizzle_pipe[4] = 1;
1461 swizzle_pipe[5] = 3;
1462 swizzle_pipe[6] = 5;
1463 swizzle_pipe[7] = 7;
1464 break;
1465 }
1466
1467 cur_backend = 0;
1468 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1469 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1470 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
1471
1472 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
1473
1474 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
1475 }
1476
1477 return backend_map;
1478}
1479
1480int r600_count_pipe_bits(uint32_t val)
1481{
1482 int i, ret = 0;
1483
1484 for (i = 0; i < 32; i++) {
1485 ret += val & 1;
1486 val >>= 1;
1487 }
1488 return ret;
771fe6b9
JG		 1489}
1490
3ce0a23d
JG		 1491void r600_gpu_init(struct radeon_device *rdev)
1492{
1493 u32 tiling_config;
1494 u32 ramcfg;
d03f5d59
AD		 1495 u32 backend_map;
1496 u32 cc_rb_backend_disable;
1497 u32 cc_gc_shader_pipe_config;
3ce0a23d
JG		 1498 u32 tmp;
1499 int i, j;
1500 u32 sq_config;
1501 u32 sq_gpr_resource_mgmt_1 = 0;
1502 u32 sq_gpr_resource_mgmt_2 = 0;
1503 u32 sq_thread_resource_mgmt = 0;
1504 u32 sq_stack_resource_mgmt_1 = 0;
1505 u32 sq_stack_resource_mgmt_2 = 0;
1506
1507 /* FIXME: implement */
1508 switch (rdev->family) {
1509 case CHIP_R600:
1510 rdev->config.r600.max_pipes = 4;
1511 rdev->config.r600.max_tile_pipes = 8;
1512 rdev->config.r600.max_simds = 4;
1513 rdev->config.r600.max_backends = 4;
1514 rdev->config.r600.max_gprs = 256;
1515 rdev->config.r600.max_threads = 192;
1516 rdev->config.r600.max_stack_entries = 256;
1517 rdev->config.r600.max_hw_contexts = 8;
1518 rdev->config.r600.max_gs_threads = 16;
1519 rdev->config.r600.sx_max_export_size = 128;
1520 rdev->config.r600.sx_max_export_pos_size = 16;
1521 rdev->config.r600.sx_max_export_smx_size = 128;
1522 rdev->config.r600.sq_num_cf_insts = 2;
1523 break;
1524 case CHIP_RV630:
1525 case CHIP_RV635:
1526 rdev->config.r600.max_pipes = 2;
1527 rdev->config.r600.max_tile_pipes = 2;
1528 rdev->config.r600.max_simds = 3;
1529 rdev->config.r600.max_backends = 1;
1530 rdev->config.r600.max_gprs = 128;
1531 rdev->config.r600.max_threads = 192;
1532 rdev->config.r600.max_stack_entries = 128;
1533 rdev->config.r600.max_hw_contexts = 8;
1534 rdev->config.r600.max_gs_threads = 4;
1535 rdev->config.r600.sx_max_export_size = 128;
1536 rdev->config.r600.sx_max_export_pos_size = 16;
1537 rdev->config.r600.sx_max_export_smx_size = 128;
1538 rdev->config.r600.sq_num_cf_insts = 2;
1539 break;
1540 case CHIP_RV610:
1541 case CHIP_RV620:
1542 case CHIP_RS780:
1543 case CHIP_RS880:
1544 rdev->config.r600.max_pipes = 1;
1545 rdev->config.r600.max_tile_pipes = 1;
1546 rdev->config.r600.max_simds = 2;
1547 rdev->config.r600.max_backends = 1;
1548 rdev->config.r600.max_gprs = 128;
1549 rdev->config.r600.max_threads = 192;
1550 rdev->config.r600.max_stack_entries = 128;
1551 rdev->config.r600.max_hw_contexts = 4;
1552 rdev->config.r600.max_gs_threads = 4;
1553 rdev->config.r600.sx_max_export_size = 128;
1554 rdev->config.r600.sx_max_export_pos_size = 16;
1555 rdev->config.r600.sx_max_export_smx_size = 128;
1556 rdev->config.r600.sq_num_cf_insts = 1;
1557 break;
1558 case CHIP_RV670:
1559 rdev->config.r600.max_pipes = 4;
1560 rdev->config.r600.max_tile_pipes = 4;
1561 rdev->config.r600.max_simds = 4;
1562 rdev->config.r600.max_backends = 4;
1563 rdev->config.r600.max_gprs = 192;
1564 rdev->config.r600.max_threads = 192;
1565 rdev->config.r600.max_stack_entries = 256;
1566 rdev->config.r600.max_hw_contexts = 8;
1567 rdev->config.r600.max_gs_threads = 16;
1568 rdev->config.r600.sx_max_export_size = 128;
1569 rdev->config.r600.sx_max_export_pos_size = 16;
1570 rdev->config.r600.sx_max_export_smx_size = 128;
1571 rdev->config.r600.sq_num_cf_insts = 2;
1572 break;
1573 default:
1574 break;
1575 }
1576
1577 /* Initialize HDP */
1578 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1579 WREG32((0x2c14 + j), 0x00000000);
1580 WREG32((0x2c18 + j), 0x00000000);
1581 WREG32((0x2c1c + j), 0x00000000);
1582 WREG32((0x2c20 + j), 0x00000000);
1583 WREG32((0x2c24 + j), 0x00000000);
1584 }
1585
1586 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1587
1588 /* Setup tiling */
1589 tiling_config = 0;
1590 ramcfg = RREG32(RAMCFG);
1591 switch (rdev->config.r600.max_tile_pipes) {
1592 case 1:
1593 tiling_config |= PIPE_TILING(0);
1594 break;
1595 case 2:
1596 tiling_config |= PIPE_TILING(1);
1597 break;
1598 case 4:
1599 tiling_config |= PIPE_TILING(2);
1600 break;
1601 case 8:
1602 tiling_config |= PIPE_TILING(3);
1603 break;
1604 default:
1605 break;
1606 }
d03f5d59 1607 rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes;
961fb597 1608 rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
3ce0a23d
JG		 1609 tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1610 tiling_config |= GROUP_SIZE(0);
961fb597 1611 rdev->config.r600.tiling_group_size = 256;
3ce0a23d
JG		 1612 tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
1613 if (tmp > 3) {
1614 tiling_config |= ROW_TILING(3);
1615 tiling_config |= SAMPLE_SPLIT(3);
1616 } else {
1617 tiling_config |= ROW_TILING(tmp);
1618 tiling_config |= SAMPLE_SPLIT(tmp);
1619 }
1620 tiling_config |= BANK_SWAPS(1);
d03f5d59
AD		 1621
1622 cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
1623 cc_rb_backend_disable |=
1624 BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MASK);
1625
1626 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
1627 cc_gc_shader_pipe_config |=
1628 INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK);
1629 cc_gc_shader_pipe_config |=
1630 INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK);
1631
1632 backend_map = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes,
1633 (R6XX_MAX_BACKENDS -
1634 r600_count_pipe_bits((cc_rb_backend_disable &
1635 R6XX_MAX_BACKENDS_MASK) >> 16)),
1636 (cc_rb_backend_disable >> 16));
e7aeeba6 1637 rdev->config.r600.tile_config = tiling_config;
d03f5d59 1638 tiling_config |= BACKEND_MAP(backend_map);
3ce0a23d
JG		 1639 WREG32(GB_TILING_CONFIG, tiling_config);
1640 WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
1641 WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
1642
3ce0a23d 1643 /* Setup pipes */
d03f5d59
AD		 1644 WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
1645 WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
f867c60d 1646 WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
3ce0a23d 1647
d03f5d59 1648 tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
3ce0a23d
JG		 1649 WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
1650 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
1651
1652 /* Setup some CP states */
1653 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
1654 WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
1655
1656 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
1657 SYNC_WALKER | SYNC_ALIGNER));
1658 /* Setup various GPU states */
1659 if (rdev->family == CHIP_RV670)
1660 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
1661
1662 tmp = RREG32(SX_DEBUG_1);
1663 tmp |= SMX_EVENT_RELEASE;
1664 if ((rdev->family > CHIP_R600))
1665 tmp |= ENABLE_NEW_SMX_ADDRESS;
1666 WREG32(SX_DEBUG_1, tmp);
1667
1668 if (((rdev->family) == CHIP_R600) ||
1669 ((rdev->family) == CHIP_RV630) ||
1670 ((rdev->family) == CHIP_RV610) ||
1671 ((rdev->family) == CHIP_RV620) ||
ee59f2b4
AD		 1672 ((rdev->family) == CHIP_RS780) ||
1673 ((rdev->family) == CHIP_RS880)) {
3ce0a23d
JG		 1674 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
1675 } else {
1676 WREG32(DB_DEBUG, 0);
1677 }
1678 WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
1679 DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
1680
1681 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1682 WREG32(VGT_NUM_INSTANCES, 0);
1683
1684 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
1685 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
1686
1687 tmp = RREG32(SQ_MS_FIFO_SIZES);
1688 if (((rdev->family) == CHIP_RV610) ||
1689 ((rdev->family) == CHIP_RV620) ||
ee59f2b4
AD		 1690 ((rdev->family) == CHIP_RS780) ||
1691 ((rdev->family) == CHIP_RS880)) {
3ce0a23d
JG		 1692 tmp = (CACHE_FIFO_SIZE(0xa) |
1693 FETCH_FIFO_HIWATER(0xa) |
1694 DONE_FIFO_HIWATER(0xe0) |
1695 ALU_UPDATE_FIFO_HIWATER(0x8));
1696 } else if (((rdev->family) == CHIP_R600) ||
1697 ((rdev->family) == CHIP_RV630)) {
1698 tmp &= ~DONE_FIFO_HIWATER(0xff);
1699 tmp |= DONE_FIFO_HIWATER(0x4);
1700 }
1701 WREG32(SQ_MS_FIFO_SIZES, tmp);
1702
1703 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1704 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
1705 */
1706 sq_config = RREG32(SQ_CONFIG);
1707 sq_config &= ~(PS_PRIO(3) |
1708 VS_PRIO(3) |
1709 GS_PRIO(3) |
1710 ES_PRIO(3));
1711 sq_config |= (DX9_CONSTS |
1712 VC_ENABLE |
1713 PS_PRIO(0) |
1714 VS_PRIO(1) |
1715 GS_PRIO(2) |
1716 ES_PRIO(3));
1717
1718 if ((rdev->family) == CHIP_R600) {
1719 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
1720 NUM_VS_GPRS(124) |
1721 NUM_CLAUSE_TEMP_GPRS(4));
1722 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
1723 NUM_ES_GPRS(0));
1724 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
1725 NUM_VS_THREADS(48) |
1726 NUM_GS_THREADS(4) |
1727 NUM_ES_THREADS(4));
1728 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
1729 NUM_VS_STACK_ENTRIES(128));
1730 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
1731 NUM_ES_STACK_ENTRIES(0));
1732 } else if (((rdev->family) == CHIP_RV610) ||
1733 ((rdev->family) == CHIP_RV620) ||
ee59f2b4
AD		 1734 ((rdev->family) == CHIP_RS780) ||
1735 ((rdev->family) == CHIP_RS880)) {
3ce0a23d
JG		 1736 /* no vertex cache */
1737 sq_config &= ~VC_ENABLE;
1738
1739 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1740 NUM_VS_GPRS(44) |
1741 NUM_CLAUSE_TEMP_GPRS(2));
1742 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1743 NUM_ES_GPRS(17));
1744 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1745 NUM_VS_THREADS(78) |
1746 NUM_GS_THREADS(4) |
1747 NUM_ES_THREADS(31));
1748 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1749 NUM_VS_STACK_ENTRIES(40));
1750 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1751 NUM_ES_STACK_ENTRIES(16));
1752 } else if (((rdev->family) == CHIP_RV630) ||
1753 ((rdev->family) == CHIP_RV635)) {
1754 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1755 NUM_VS_GPRS(44) |
1756 NUM_CLAUSE_TEMP_GPRS(2));
1757 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
1758 NUM_ES_GPRS(18));
1759 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1760 NUM_VS_THREADS(78) |
1761 NUM_GS_THREADS(4) |
1762 NUM_ES_THREADS(31));
1763 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1764 NUM_VS_STACK_ENTRIES(40));
1765 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1766 NUM_ES_STACK_ENTRIES(16));
1767 } else if ((rdev->family) == CHIP_RV670) {
1768 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1769 NUM_VS_GPRS(44) |
1770 NUM_CLAUSE_TEMP_GPRS(2));
1771 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1772 NUM_ES_GPRS(17));
1773 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1774 NUM_VS_THREADS(78) |
1775 NUM_GS_THREADS(4) |
1776 NUM_ES_THREADS(31));
1777 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
1778 NUM_VS_STACK_ENTRIES(64));
1779 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
1780 NUM_ES_STACK_ENTRIES(64));
1781 }
1782
1783 WREG32(SQ_CONFIG, sq_config);
1784 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
1785 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
1786 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1787 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1788 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1789
1790 if (((rdev->family) == CHIP_RV610) ||
1791 ((rdev->family) == CHIP_RV620) ||
ee59f2b4
AD		 1792 ((rdev->family) == CHIP_RS780) ||
1793 ((rdev->family) == CHIP_RS880)) {
3ce0a23d
JG		 1794 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
1795 } else {
1796 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
1797 }
1798
1799 /* More default values. 2D/3D driver should adjust as needed */
1800 WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
1801 S1_X(0x4) | S1_Y(0xc)));
1802 WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
1803 S1_X(0x2) | S1_Y(0x2) |
1804 S2_X(0xa) | S2_Y(0x6) |
1805 S3_X(0x6) | S3_Y(0xa)));
1806 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
1807 S1_X(0x4) | S1_Y(0xc) |
1808 S2_X(0x1) | S2_Y(0x6) |
1809 S3_X(0xa) | S3_Y(0xe)));
1810 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
1811 S5_X(0x0) | S5_Y(0x0) |
1812 S6_X(0xb) | S6_Y(0x4) |
1813 S7_X(0x7) | S7_Y(0x8)));
1814
1815 WREG32(VGT_STRMOUT_EN, 0);
1816 tmp = rdev->config.r600.max_pipes * 16;
1817 switch (rdev->family) {
1818 case CHIP_RV610:
3ce0a23d 1819 case CHIP_RV620:
ee59f2b4
AD		 1820 case CHIP_RS780:
1821 case CHIP_RS880:
3ce0a23d
JG		 1822 tmp += 32;
1823 break;
1824 case CHIP_RV670:
1825 tmp += 128;
1826 break;
1827 default:
1828 break;
1829 }
1830 if (tmp > 256) {
1831 tmp = 256;
1832 }
1833 WREG32(VGT_ES_PER_GS, 128);
1834 WREG32(VGT_GS_PER_ES, tmp);
1835 WREG32(VGT_GS_PER_VS, 2);
1836 WREG32(VGT_GS_VERTEX_REUSE, 16);
1837
1838 /* more default values. 2D/3D driver should adjust as needed */
1839 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1840 WREG32(VGT_STRMOUT_EN, 0);
1841 WREG32(SX_MISC, 0);
1842 WREG32(PA_SC_MODE_CNTL, 0);
1843 WREG32(PA_SC_AA_CONFIG, 0);
1844 WREG32(PA_SC_LINE_STIPPLE, 0);
1845 WREG32(SPI_INPUT_Z, 0);
1846 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
1847 WREG32(CB_COLOR7_FRAG, 0);
1848
1849 /* Clear render buffer base addresses */
1850 WREG32(CB_COLOR0_BASE, 0);
1851 WREG32(CB_COLOR1_BASE, 0);
1852 WREG32(CB_COLOR2_BASE, 0);
1853 WREG32(CB_COLOR3_BASE, 0);
1854 WREG32(CB_COLOR4_BASE, 0);
1855 WREG32(CB_COLOR5_BASE, 0);
1856 WREG32(CB_COLOR6_BASE, 0);
1857 WREG32(CB_COLOR7_BASE, 0);
1858 WREG32(CB_COLOR7_FRAG, 0);
1859
1860 switch (rdev->family) {
1861 case CHIP_RV610:
3ce0a23d 1862 case CHIP_RV620:
ee59f2b4
AD		 1863 case CHIP_RS780:
1864 case CHIP_RS880:
3ce0a23d
JG		 1865 tmp = TC_L2_SIZE(8);
1866 break;
1867 case CHIP_RV630:
1868 case CHIP_RV635:
1869 tmp = TC_L2_SIZE(4);
1870 break;
1871 case CHIP_R600:
1872 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
1873 break;
1874 default:
1875 tmp = TC_L2_SIZE(0);
1876 break;
1877 }
1878 WREG32(TC_CNTL, tmp);
1879
1880 tmp = RREG32(HDP_HOST_PATH_CNTL);
1881 WREG32(HDP_HOST_PATH_CNTL, tmp);
1882
1883 tmp = RREG32(ARB_POP);
1884 tmp |= ENABLE_TC128;
1885 WREG32(ARB_POP, tmp);
1886
1887 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1888 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
1889 NUM_CLIP_SEQ(3)));
1890 WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
1891}
1892
1893
771fe6b9
JG		 1894/*
1895 * Indirect registers accessor
1896 */
3ce0a23d
JG		 1897u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
1898{
1899 u32 r;
1900
1901 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1902 (void)RREG32(PCIE_PORT_INDEX);
1903 r = RREG32(PCIE_PORT_DATA);
1904 return r;
1905}
1906
1907void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1908{
1909 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1910 (void)RREG32(PCIE_PORT_INDEX);
1911 WREG32(PCIE_PORT_DATA, (v));
1912 (void)RREG32(PCIE_PORT_DATA);
1913}
1914
3ce0a23d
JG		 1915/*
1916 * CP & Ring
1917 */
1918void r600_cp_stop(struct radeon_device *rdev)
1919{
1920 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
724c80e1 1921 WREG32(SCRATCH_UMSK, 0);
3ce0a23d
JG		 1922}
1923
d8f60cfc 1924int r600_init_microcode(struct radeon_device *rdev)
3ce0a23d
JG		 1925{
1926 struct platform_device *pdev;
1927 const char *chip_name;
d8f60cfc
AD		 1928 const char *rlc_chip_name;
1929 size_t pfp_req_size, me_req_size, rlc_req_size;
3ce0a23d
JG		 1930 char fw_name[30];
1931 int err;
1932
1933 DRM_DEBUG("\n");
1934
1935 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
1936 err = IS_ERR(pdev);
1937 if (err) {
1938 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
1939 return -EINVAL;
1940 }
1941
1942 switch (rdev->family) {
d8f60cfc
AD		 1943 case CHIP_R600:
1944 chip_name = "R600";
1945 rlc_chip_name = "R600";
1946 break;
1947 case CHIP_RV610:
1948 chip_name = "RV610";
1949 rlc_chip_name = "R600";
1950 break;
1951 case CHIP_RV630:
1952 chip_name = "RV630";
1953 rlc_chip_name = "R600";
1954 break;
1955 case CHIP_RV620:
1956 chip_name = "RV620";
1957 rlc_chip_name = "R600";
1958 break;
1959 case CHIP_RV635:
1960 chip_name = "RV635";
1961 rlc_chip_name = "R600";
1962 break;
1963 case CHIP_RV670:
1964 chip_name = "RV670";
1965 rlc_chip_name = "R600";
1966 break;
3ce0a23d 1967 case CHIP_RS780:
d8f60cfc
AD		 1968 case CHIP_RS880:
1969 chip_name = "RS780";
1970 rlc_chip_name = "R600";
1971 break;
1972 case CHIP_RV770:
1973 chip_name = "RV770";
1974 rlc_chip_name = "R700";
1975 break;
3ce0a23d 1976 case CHIP_RV730:
d8f60cfc
AD		 1977 case CHIP_RV740:
1978 chip_name = "RV730";
1979 rlc_chip_name = "R700";
1980 break;
1981 case CHIP_RV710:
1982 chip_name = "RV710";
1983 rlc_chip_name = "R700";
1984 break;
fe251e2f
AD		 1985 case CHIP_CEDAR:
1986 chip_name = "CEDAR";
45f9a39b 1987 rlc_chip_name = "CEDAR";
fe251e2f
AD		 1988 break;
1989 case CHIP_REDWOOD:
1990 chip_name = "REDWOOD";
45f9a39b 1991 rlc_chip_name = "REDWOOD";
fe251e2f
AD		 1992 break;
1993 case CHIP_JUNIPER:
1994 chip_name = "JUNIPER";
45f9a39b 1995 rlc_chip_name = "JUNIPER";
fe251e2f
AD		 1996 break;
1997 case CHIP_CYPRESS:
1998 case CHIP_HEMLOCK:
1999 chip_name = "CYPRESS";
45f9a39b 2000 rlc_chip_name = "CYPRESS";
fe251e2f 2001 break;
3ce0a23d
JG		 2002 default: BUG();
2003 }
2004
fe251e2f
AD		 2005 if (rdev->family >= CHIP_CEDAR) {
2006 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
2007 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
45f9a39b 2008 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
fe251e2f 2009 } else if (rdev->family >= CHIP_RV770) {
3ce0a23d
JG		 2010 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
2011 me_req_size = R700_PM4_UCODE_SIZE * 4;
d8f60cfc 2012 rlc_req_size = R700_RLC_UCODE_SIZE * 4;
3ce0a23d
JG		 2013 } else {
2014 pfp_req_size = PFP_UCODE_SIZE * 4;
2015 me_req_size = PM4_UCODE_SIZE * 12;
d8f60cfc 2016 rlc_req_size = RLC_UCODE_SIZE * 4;
3ce0a23d
JG		 2017 }
2018
d8f60cfc 2019 DRM_INFO("Loading %s Microcode\n", chip_name);
3ce0a23d
JG		 2020
2021 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
2022 err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
2023 if (err)
2024 goto out;
2025 if (rdev->pfp_fw->size != pfp_req_size) {
2026 printk(KERN_ERR
2027 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2028 rdev->pfp_fw->size, fw_name);
2029 err = -EINVAL;
2030 goto out;
2031 }
2032
2033 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
2034 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
2035 if (err)
2036 goto out;
2037 if (rdev->me_fw->size != me_req_size) {
2038 printk(KERN_ERR
2039 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2040 rdev->me_fw->size, fw_name);
2041 err = -EINVAL;
2042 }
d8f60cfc
AD		 2043
2044 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
2045 err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
2046 if (err)
2047 goto out;
2048 if (rdev->rlc_fw->size != rlc_req_size) {
2049 printk(KERN_ERR
2050 "r600_rlc: Bogus length %zu in firmware \"%s\"\n",
2051 rdev->rlc_fw->size, fw_name);
2052 err = -EINVAL;
2053 }
2054
3ce0a23d
JG		 2055out:
2056 platform_device_unregister(pdev);
2057
2058 if (err) {
2059 if (err != -EINVAL)
2060 printk(KERN_ERR
2061 "r600_cp: Failed to load firmware \"%s\"\n",
2062 fw_name);
2063 release_firmware(rdev->pfp_fw);
2064 rdev->pfp_fw = NULL;
2065 release_firmware(rdev->me_fw);
2066 rdev->me_fw = NULL;
d8f60cfc
AD		 2067 release_firmware(rdev->rlc_fw);
2068 rdev->rlc_fw = NULL;
3ce0a23d
JG		 2069 }
2070 return err;
2071}
2072
2073static int r600_cp_load_microcode(struct radeon_device *rdev)
2074{
2075 const __be32 *fw_data;
2076 int i;
2077
2078 if (!rdev->me_fw || !rdev->pfp_fw)
2079 return -EINVAL;
2080
2081 r600_cp_stop(rdev);
2082
2083 WREG32(CP_RB_CNTL, RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
2084
2085 /* Reset cp */
2086 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2087 RREG32(GRBM_SOFT_RESET);
2088 mdelay(15);
2089 WREG32(GRBM_SOFT_RESET, 0);
2090
2091 WREG32(CP_ME_RAM_WADDR, 0);
2092
2093 fw_data = (const __be32 *)rdev->me_fw->data;
2094 WREG32(CP_ME_RAM_WADDR, 0);
2095 for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
2096 WREG32(CP_ME_RAM_DATA,
2097 be32_to_cpup(fw_data++));
2098
2099 fw_data = (const __be32 *)rdev->pfp_fw->data;
2100 WREG32(CP_PFP_UCODE_ADDR, 0);
2101 for (i = 0; i < PFP_UCODE_SIZE; i++)
2102 WREG32(CP_PFP_UCODE_DATA,
2103 be32_to_cpup(fw_data++));
2104
2105 WREG32(CP_PFP_UCODE_ADDR, 0);
2106 WREG32(CP_ME_RAM_WADDR, 0);
2107 WREG32(CP_ME_RAM_RADDR, 0);
2108 return 0;
2109}
2110
2111int r600_cp_start(struct radeon_device *rdev)
2112{
2113 int r;
2114 uint32_t cp_me;
2115
2116 r = radeon_ring_lock(rdev, 7);
2117 if (r) {
2118 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2119 return r;
2120 }
2121 radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
2122 radeon_ring_write(rdev, 0x1);
7e7b41d2 2123 if (rdev->family >= CHIP_RV770) {
3ce0a23d
JG		 2124 radeon_ring_write(rdev, 0x0);
2125 radeon_ring_write(rdev, rdev->config.rv770.max_hw_contexts - 1);
fe251e2f
AD		 2126 } else {
2127 radeon_ring_write(rdev, 0x3);
2128 radeon_ring_write(rdev, rdev->config.r600.max_hw_contexts - 1);
3ce0a23d
JG		 2129 }
2130 radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2131 radeon_ring_write(rdev, 0);
2132 radeon_ring_write(rdev, 0);
2133 radeon_ring_unlock_commit(rdev);
2134
2135 cp_me = 0xff;
2136 WREG32(R_0086D8_CP_ME_CNTL, cp_me);
2137 return 0;
2138}
2139
2140int r600_cp_resume(struct radeon_device *rdev)
2141{
2142 u32 tmp;
2143 u32 rb_bufsz;
2144 int r;
2145
2146 /* Reset cp */
2147 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2148 RREG32(GRBM_SOFT_RESET);
2149 mdelay(15);
2150 WREG32(GRBM_SOFT_RESET, 0);
2151
2152 /* Set ring buffer size */
2153 rb_bufsz = drm_order(rdev->cp.ring_size / 8);
724c80e1 2154 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
3ce0a23d 2155#ifdef __BIG_ENDIAN
d6f28938 2156 tmp |= BUF_SWAP_32BIT;
3ce0a23d 2157#endif
d6f28938 2158 WREG32(CP_RB_CNTL, tmp);
3ce0a23d
JG		 2159 WREG32(CP_SEM_WAIT_TIMER, 0x4);
2160
2161 /* Set the write pointer delay */
2162 WREG32(CP_RB_WPTR_DELAY, 0);
2163
2164 /* Initialize the ring buffer's read and write pointers */
3ce0a23d
JG		 2165 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
2166 WREG32(CP_RB_RPTR_WR, 0);
2167 WREG32(CP_RB_WPTR, 0);
724c80e1
AD		 2168
2169 /* set the wb address whether it's enabled or not */
2170 WREG32(CP_RB_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC);
2171 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
2172 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
2173
2174 if (rdev->wb.enabled)
2175 WREG32(SCRATCH_UMSK, 0xff);
2176 else {
2177 tmp |= RB_NO_UPDATE;
2178 WREG32(SCRATCH_UMSK, 0);
2179 }
2180
3ce0a23d
JG		 2181 mdelay(1);
2182 WREG32(CP_RB_CNTL, tmp);
2183
2184 WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
2185 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
2186
2187 rdev->cp.rptr = RREG32(CP_RB_RPTR);
2188 rdev->cp.wptr = RREG32(CP_RB_WPTR);
2189
2190 r600_cp_start(rdev);
2191 rdev->cp.ready = true;
2192 r = radeon_ring_test(rdev);
2193 if (r) {
2194 rdev->cp.ready = false;
2195 return r;
2196 }
2197 return 0;
2198}
2199
2200void r600_cp_commit(struct radeon_device *rdev)
2201{
2202 WREG32(CP_RB_WPTR, rdev->cp.wptr);
2203 (void)RREG32(CP_RB_WPTR);
2204}
2205
2206void r600_ring_init(struct radeon_device *rdev, unsigned ring_size)
2207{
2208 u32 rb_bufsz;
2209
2210 /* Align ring size */
2211 rb_bufsz = drm_order(ring_size / 8);
2212 ring_size = (1 << (rb_bufsz + 1)) * 4;
2213 rdev->cp.ring_size = ring_size;
2214 rdev->cp.align_mask = 16 - 1;
2215}
2216
655efd3d
JG		 2217void r600_cp_fini(struct radeon_device *rdev)
2218{
2219 r600_cp_stop(rdev);
2220 radeon_ring_fini(rdev);
2221}
2222
3ce0a23d
JG		 2223
2224/*
2225 * GPU scratch registers helpers function.
2226 */
2227void r600_scratch_init(struct radeon_device *rdev)
2228{
2229 int i;
2230
2231 rdev->scratch.num_reg = 7;
724c80e1 2232 rdev->scratch.reg_base = SCRATCH_REG0;
3ce0a23d
JG		 2233 for (i = 0; i < rdev->scratch.num_reg; i++) {
2234 rdev->scratch.free[i] = true;
724c80e1 2235 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
3ce0a23d
JG		 2236 }
2237}
2238
2239int r600_ring_test(struct radeon_device *rdev)
2240{
2241 uint32_t scratch;
2242 uint32_t tmp = 0;
2243 unsigned i;
2244 int r;
2245
2246 r = radeon_scratch_get(rdev, &scratch);
2247 if (r) {
2248 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
2249 return r;
2250 }
2251 WREG32(scratch, 0xCAFEDEAD);
2252 r = radeon_ring_lock(rdev, 3);
2253 if (r) {
2254 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2255 radeon_scratch_free(rdev, scratch);
2256 return r;
2257 }
2258 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2259 radeon_ring_write(rdev, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2260 radeon_ring_write(rdev, 0xDEADBEEF);
2261 radeon_ring_unlock_commit(rdev);
2262 for (i = 0; i < rdev->usec_timeout; i++) {
2263 tmp = RREG32(scratch);
2264 if (tmp == 0xDEADBEEF)
2265 break;
2266 DRM_UDELAY(1);
2267 }
2268 if (i < rdev->usec_timeout) {
2269 DRM_INFO("ring test succeeded in %d usecs\n", i);
2270 } else {
2271 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
2272 scratch, tmp);
2273 r = -EINVAL;
2274 }
2275 radeon_scratch_free(rdev, scratch);
2276 return r;
2277}
2278
3ce0a23d
JG		 2279void r600_fence_ring_emit(struct radeon_device *rdev,
2280 struct radeon_fence *fence)
2281{
d8f60cfc 2282 /* Also consider EVENT_WRITE_EOP. it handles the interrupts + timestamps + events */
44224c3f
AD		 2283
2284 radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0));
2285 radeon_ring_write(rdev, CACHE_FLUSH_AND_INV_EVENT);
2286 /* wait for 3D idle clean */
2287 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2288 radeon_ring_write(rdev, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2289 radeon_ring_write(rdev, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
3ce0a23d
JG		 2290 /* Emit fence sequence & fire IRQ */
2291 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2292 radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2293 radeon_ring_write(rdev, fence->seq);
d8f60cfc
AD		 2294 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
2295 radeon_ring_write(rdev, PACKET0(CP_INT_STATUS, 0));
2296 radeon_ring_write(rdev, RB_INT_STAT);
3ce0a23d
JG		 2297}
2298
3ce0a23d
JG		 2299int r600_copy_blit(struct radeon_device *rdev,
2300 uint64_t src_offset, uint64_t dst_offset,
2301 unsigned num_pages, struct radeon_fence *fence)
2302{
ff82f052
JG		 2303 int r;
2304
2305 mutex_lock(&rdev->r600_blit.mutex);
2306 rdev->r600_blit.vb_ib = NULL;
2307 r = r600_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE);
2308 if (r) {
2309 if (rdev->r600_blit.vb_ib)
2310 radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
2311 mutex_unlock(&rdev->r600_blit.mutex);
2312 return r;
2313 }
a77f1718 2314 r600_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE);
3ce0a23d 2315 r600_blit_done_copy(rdev, fence);
ff82f052 2316 mutex_unlock(&rdev->r600_blit.mutex);
3ce0a23d
JG		 2317 return 0;
2318}
2319
3ce0a23d
JG		 2320int r600_set_surface_reg(struct radeon_device *rdev, int reg,
2321 uint32_t tiling_flags, uint32_t pitch,
2322 uint32_t offset, uint32_t obj_size)
2323{
2324 /* FIXME: implement */
2325 return 0;
2326}
2327
2328void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
2329{
2330 /* FIXME: implement */
2331}
2332
2333
2334bool r600_card_posted(struct radeon_device *rdev)
2335{
2336 uint32_t reg;
2337
2338 /* first check CRTCs */
2339 reg = RREG32(D1CRTC_CONTROL) |
2340 RREG32(D2CRTC_CONTROL);
2341 if (reg & CRTC_EN)
2342 return true;
2343
2344 /* then check MEM_SIZE, in case the crtcs are off */
2345 if (RREG32(CONFIG_MEMSIZE))
2346 return true;
2347
2348 return false;
2349}
2350
fc30b8ef 2351int r600_startup(struct radeon_device *rdev)
3ce0a23d
JG		 2352{
2353 int r;
2354
779720a3
AD		 2355 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
2356 r = r600_init_microcode(rdev);
2357 if (r) {
2358 DRM_ERROR("Failed to load firmware!\n");
2359 return r;
2360 }
2361 }
2362
a3c1945a 2363 r600_mc_program(rdev);
1a029b76
JG		 2364 if (rdev->flags & RADEON_IS_AGP) {
2365 r600_agp_enable(rdev);
2366 } else {
2367 r = r600_pcie_gart_enable(rdev);
2368 if (r)
2369 return r;
2370 }
3ce0a23d 2371 r600_gpu_init(rdev);
c38c7b64
JG		 2372 r = r600_blit_init(rdev);
2373 if (r) {
2374 r600_blit_fini(rdev);
2375 rdev->asic->copy = NULL;
2376 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
2377 }
b70d6bb3 2378
724c80e1
AD		 2379 /* allocate wb buffer */
2380 r = radeon_wb_init(rdev);
2381 if (r)
2382 return r;
2383
d8f60cfc 2384 /* Enable IRQ */
d8f60cfc
AD		 2385 r = r600_irq_init(rdev);
2386 if (r) {
2387 DRM_ERROR("radeon: IH init failed (%d).\n", r);
2388 radeon_irq_kms_fini(rdev);
2389 return r;
2390 }
2391 r600_irq_set(rdev);
2392
3ce0a23d
JG		 2393 r = radeon_ring_init(rdev, rdev->cp.ring_size);
2394 if (r)
2395 return r;
2396 r = r600_cp_load_microcode(rdev);
2397 if (r)
2398 return r;
2399 r = r600_cp_resume(rdev);
2400 if (r)
2401 return r;
724c80e1 2402
3ce0a23d
JG		 2403 return 0;
2404}
2405
28d52043
DA		 2406void r600_vga_set_state(struct radeon_device *rdev, bool state)
2407{
2408 uint32_t temp;
2409
2410 temp = RREG32(CONFIG_CNTL);
2411 if (state == false) {
2412 temp &= ~(1<<0);
2413 temp |= (1<<1);
2414 } else {
2415 temp &= ~(1<<1);
2416 }
2417 WREG32(CONFIG_CNTL, temp);
2418}
2419
fc30b8ef
DA		 2420int r600_resume(struct radeon_device *rdev)
2421{
2422 int r;
2423
1a029b76
JG		 2424 /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
2425 * posting will perform necessary task to bring back GPU into good
2426 * shape.
2427 */
fc30b8ef 2428 /* post card */
e7d40b9a 2429 atom_asic_init(rdev->mode_info.atom_context);
fc30b8ef
DA		 2430
2431 r = r600_startup(rdev);
2432 if (r) {
2433 DRM_ERROR("r600 startup failed on resume\n");
2434 return r;
2435 }
2436
62a8ea3f 2437 r = r600_ib_test(rdev);
fc30b8ef
DA		 2438 if (r) {
2439 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
2440 return r;
2441 }
38fd2c6f
RM		 2442
2443 r = r600_audio_init(rdev);
2444 if (r) {
2445 DRM_ERROR("radeon: audio resume failed\n");
2446 return r;
2447 }
2448
fc30b8ef
DA		 2449 return r;
2450}
2451
3ce0a23d
JG		 2452int r600_suspend(struct radeon_device *rdev)
2453{
4c788679
JG		 2454 int r;
2455
38fd2c6f 2456 r600_audio_fini(rdev);
3ce0a23d
JG		 2457 /* FIXME: we should wait for ring to be empty */
2458 r600_cp_stop(rdev);
bc1a631e 2459 rdev->cp.ready = false;
0c45249f 2460 r600_irq_suspend(rdev);
724c80e1 2461 radeon_wb_disable(rdev);
4aac0473 2462 r600_pcie_gart_disable(rdev);
bc1a631e 2463 /* unpin shaders bo */
30d2d9a5
JG		 2464 if (rdev->r600_blit.shader_obj) {
2465 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
2466 if (!r) {
2467 radeon_bo_unpin(rdev->r600_blit.shader_obj);
2468 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
2469 }
2470 }
3ce0a23d
JG		 2471 return 0;
2472}
2473
2474/* Plan is to move initialization in that function and use
2475 * helper function so that radeon_device_init pretty much
2476 * do nothing more than calling asic specific function. This
2477 * should also allow to remove a bunch of callback function
2478 * like vram_info.
2479 */
2480int r600_init(struct radeon_device *rdev)
771fe6b9 2481{
3ce0a23d 2482 int r;
771fe6b9 2483
3ce0a23d
JG		 2484 r = radeon_dummy_page_init(rdev);
2485 if (r)
2486 return r;
2487 if (r600_debugfs_mc_info_init(rdev)) {
2488 DRM_ERROR("Failed to register debugfs file for mc !\n");
2489 }
2490 /* This don't do much */
2491 r = radeon_gem_init(rdev);
2492 if (r)
2493 return r;
2494 /* Read BIOS */
2495 if (!radeon_get_bios(rdev)) {
2496 if (ASIC_IS_AVIVO(rdev))
2497 return -EINVAL;
2498 }
2499 /* Must be an ATOMBIOS */
e7d40b9a
JG		 2500 if (!rdev->is_atom_bios) {
2501 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
3ce0a23d 2502 return -EINVAL;
e7d40b9a 2503 }
3ce0a23d
JG		 2504 r = radeon_atombios_init(rdev);
2505 if (r)
2506 return r;
2507 /* Post card if necessary */
72542d77
DA		 2508 if (!r600_card_posted(rdev)) {
2509 if (!rdev->bios) {
2510 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2511 return -EINVAL;
2512 }
3ce0a23d
JG		 2513 DRM_INFO("GPU not posted. posting now...\n");
2514 atom_asic_init(rdev->mode_info.atom_context);
2515 }
2516 /* Initialize scratch registers */
2517 r600_scratch_init(rdev);
2518 /* Initialize surface registers */
2519 radeon_surface_init(rdev);
7433874e 2520 /* Initialize clocks */
5e6dde7e 2521 radeon_get_clock_info(rdev->ddev);
3ce0a23d
JG		 2522 /* Fence driver */
2523 r = radeon_fence_driver_init(rdev);
2524 if (r)
2525 return r;
700a0cc0
JG		 2526 if (rdev->flags & RADEON_IS_AGP) {
2527 r = radeon_agp_init(rdev);
2528 if (r)
2529 radeon_agp_disable(rdev);
2530 }
3ce0a23d 2531 r = r600_mc_init(rdev);
b574f251 2532 if (r)
3ce0a23d 2533 return r;
3ce0a23d 2534 /* Memory manager */
4c788679 2535 r = radeon_bo_init(rdev);
3ce0a23d
JG		 2536 if (r)
2537 return r;
d8f60cfc
AD		 2538
2539 r = radeon_irq_kms_init(rdev);
2540 if (r)
2541 return r;
2542
3ce0a23d
JG		 2543 rdev->cp.ring_obj = NULL;
2544 r600_ring_init(rdev, 1024 * 1024);
2545
d8f60cfc
AD		 2546 rdev->ih.ring_obj = NULL;
2547 r600_ih_ring_init(rdev, 64 * 1024);
3ce0a23d 2548
4aac0473
JG		 2549 r = r600_pcie_gart_init(rdev);
2550 if (r)
2551 return r;
2552
779720a3 2553 rdev->accel_working = true;
fc30b8ef 2554 r = r600_startup(rdev);
3ce0a23d 2555 if (r) {
655efd3d
JG		 2556 dev_err(rdev->dev, "disabling GPU acceleration\n");
2557 r600_cp_fini(rdev);
655efd3d 2558 r600_irq_fini(rdev);
724c80e1 2559 radeon_wb_fini(rdev);
655efd3d 2560 radeon_irq_kms_fini(rdev);
75c81298 2561 r600_pcie_gart_fini(rdev);
733289c2 2562 rdev->accel_working = false;
3ce0a23d 2563 }
733289c2
JG		 2564 if (rdev->accel_working) {
2565 r = radeon_ib_pool_init(rdev);
2566 if (r) {
db96380e 2567 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
733289c2 2568 rdev->accel_working = false;
db96380e
JG		 2569 } else {
2570 r = r600_ib_test(rdev);
2571 if (r) {
2572 dev_err(rdev->dev, "IB test failed (%d).\n", r);
2573 rdev->accel_working = false;
2574 }
733289c2 2575 }
3ce0a23d 2576 }
dafc3bd5
CK		 2577
2578 r = r600_audio_init(rdev);
2579 if (r)
2580 return r; /* TODO error handling */
3ce0a23d
JG		 2581 return 0;
2582}
2583
2584void r600_fini(struct radeon_device *rdev)
2585{
dafc3bd5 2586 r600_audio_fini(rdev);
3ce0a23d 2587 r600_blit_fini(rdev);
655efd3d 2588 r600_cp_fini(rdev);
d8f60cfc 2589 r600_irq_fini(rdev);
724c80e1 2590 radeon_wb_fini(rdev);
d8f60cfc 2591 radeon_irq_kms_fini(rdev);
4aac0473 2592 r600_pcie_gart_fini(rdev);
655efd3d 2593 radeon_agp_fini(rdev);
3ce0a23d
JG		 2594 radeon_gem_fini(rdev);
2595 radeon_fence_driver_fini(rdev);
4c788679 2596 radeon_bo_fini(rdev);
e7d40b9a 2597 radeon_atombios_fini(rdev);
3ce0a23d
JG		 2598 kfree(rdev->bios);
2599 rdev->bios = NULL;
2600 radeon_dummy_page_fini(rdev);
2601}
2602
2603
2604/*
2605 * CS stuff
2606 */
2607void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
2608{
2609 /* FIXME: implement */
2610 radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
2611 radeon_ring_write(rdev, ib->gpu_addr & 0xFFFFFFFC);
2612 radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF);
2613 radeon_ring_write(rdev, ib->length_dw);
2614}
2615
2616int r600_ib_test(struct radeon_device *rdev)
2617{
2618 struct radeon_ib *ib;
2619 uint32_t scratch;
2620 uint32_t tmp = 0;
2621 unsigned i;
2622 int r;
2623
2624 r = radeon_scratch_get(rdev, &scratch);
2625 if (r) {
2626 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
2627 return r;
2628 }
2629 WREG32(scratch, 0xCAFEDEAD);
2630 r = radeon_ib_get(rdev, &ib);
2631 if (r) {
2632 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
2633 return r;
2634 }
2635 ib->ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
2636 ib->ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2637 ib->ptr[2] = 0xDEADBEEF;
2638 ib->ptr[3] = PACKET2(0);
2639 ib->ptr[4] = PACKET2(0);
2640 ib->ptr[5] = PACKET2(0);
2641 ib->ptr[6] = PACKET2(0);
2642 ib->ptr[7] = PACKET2(0);
2643 ib->ptr[8] = PACKET2(0);
2644 ib->ptr[9] = PACKET2(0);
2645 ib->ptr[10] = PACKET2(0);
2646 ib->ptr[11] = PACKET2(0);
2647 ib->ptr[12] = PACKET2(0);
2648 ib->ptr[13] = PACKET2(0);
2649 ib->ptr[14] = PACKET2(0);
2650 ib->ptr[15] = PACKET2(0);
2651 ib->length_dw = 16;
2652 r = radeon_ib_schedule(rdev, ib);
2653 if (r) {
2654 radeon_scratch_free(rdev, scratch);
2655 radeon_ib_free(rdev, &ib);
2656 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
2657 return r;
2658 }
2659 r = radeon_fence_wait(ib->fence, false);
2660 if (r) {
2661 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
2662 return r;
2663 }
2664 for (i = 0; i < rdev->usec_timeout; i++) {
2665 tmp = RREG32(scratch);
2666 if (tmp == 0xDEADBEEF)
2667 break;
2668 DRM_UDELAY(1);
2669 }
2670 if (i < rdev->usec_timeout) {
2671 DRM_INFO("ib test succeeded in %u usecs\n", i);
2672 } else {
4417d7f6 2673 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
3ce0a23d
JG		 2674 scratch, tmp);
2675 r = -EINVAL;
2676 }
2677 radeon_scratch_free(rdev, scratch);
2678 radeon_ib_free(rdev, &ib);
771fe6b9
JG		 2679 return r;
2680}
2681
d8f60cfc
AD		 2682/*
2683 * Interrupts
2684 *
2685 * Interrupts use a ring buffer on r6xx/r7xx hardware. It works pretty
2686 * the same as the CP ring buffer, but in reverse. Rather than the CPU
2687 * writing to the ring and the GPU consuming, the GPU writes to the ring
2688 * and host consumes. As the host irq handler processes interrupts, it
2689 * increments the rptr. When the rptr catches up with the wptr, all the
2690 * current interrupts have been processed.
2691 */
2692
2693void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
2694{
2695 u32 rb_bufsz;
2696
2697 /* Align ring size */
2698 rb_bufsz = drm_order(ring_size / 4);
2699 ring_size = (1 << rb_bufsz) * 4;
2700 rdev->ih.ring_size = ring_size;
0c45249f
JG		 2701 rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
2702 rdev->ih.rptr = 0;
d8f60cfc
AD		 2703}
2704
0c45249f 2705static int r600_ih_ring_alloc(struct radeon_device *rdev)
d8f60cfc
AD		 2706{
2707 int r;
2708
d8f60cfc
AD		 2709 /* Allocate ring buffer */
2710 if (rdev->ih.ring_obj == NULL) {
4c788679
JG		 2711 r = radeon_bo_create(rdev, NULL, rdev->ih.ring_size,
2712 true,
2713 RADEON_GEM_DOMAIN_GTT,
2714 &rdev->ih.ring_obj);
d8f60cfc
AD		 2715 if (r) {
2716 DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r);
2717 return r;
2718 }
4c788679
JG		 2719 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2720 if (unlikely(r != 0))
2721 return r;
2722 r = radeon_bo_pin(rdev->ih.ring_obj,
2723 RADEON_GEM_DOMAIN_GTT,
2724 &rdev->ih.gpu_addr);
d8f60cfc 2725 if (r) {
4c788679 2726 radeon_bo_unreserve(rdev->ih.ring_obj);
d8f60cfc
AD		 2727 DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r);
2728 return r;
2729 }
4c788679
JG		 2730 r = radeon_bo_kmap(rdev->ih.ring_obj,
2731 (void **)&rdev->ih.ring);
2732 radeon_bo_unreserve(rdev->ih.ring_obj);
d8f60cfc
AD		 2733 if (r) {
2734 DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r);
2735 return r;
2736 }
2737 }
d8f60cfc
AD		 2738 return 0;
2739}
2740
2741static void r600_ih_ring_fini(struct radeon_device *rdev)
2742{
4c788679 2743 int r;
d8f60cfc 2744 if (rdev->ih.ring_obj) {
4c788679
JG		 2745 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2746 if (likely(r == 0)) {
2747 radeon_bo_kunmap(rdev->ih.ring_obj);
2748 radeon_bo_unpin(rdev->ih.ring_obj);
2749 radeon_bo_unreserve(rdev->ih.ring_obj);
2750 }
2751 radeon_bo_unref(&rdev->ih.ring_obj);
d8f60cfc
AD		 2752 rdev->ih.ring = NULL;
2753 rdev->ih.ring_obj = NULL;
2754 }
2755}
2756
45f9a39b 2757void r600_rlc_stop(struct radeon_device *rdev)
d8f60cfc
AD		 2758{
2759
45f9a39b
AD		 2760 if ((rdev->family >= CHIP_RV770) &&
2761 (rdev->family <= CHIP_RV740)) {
d8f60cfc
AD		 2762 /* r7xx asics need to soft reset RLC before halting */
2763 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
2764 RREG32(SRBM_SOFT_RESET);
2765 udelay(15000);
2766 WREG32(SRBM_SOFT_RESET, 0);
2767 RREG32(SRBM_SOFT_RESET);
2768 }
2769
2770 WREG32(RLC_CNTL, 0);
2771}
2772
2773static void r600_rlc_start(struct radeon_device *rdev)
2774{
2775 WREG32(RLC_CNTL, RLC_ENABLE);
2776}
2777
2778static int r600_rlc_init(struct radeon_device *rdev)
2779{
2780 u32 i;
2781 const __be32 *fw_data;
2782
2783 if (!rdev->rlc_fw)
2784 return -EINVAL;
2785
2786 r600_rlc_stop(rdev);
2787
2788 WREG32(RLC_HB_BASE, 0);
2789 WREG32(RLC_HB_CNTL, 0);
2790 WREG32(RLC_HB_RPTR, 0);
2791 WREG32(RLC_HB_WPTR, 0);
2792 WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
2793 WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
2794 WREG32(RLC_MC_CNTL, 0);
2795 WREG32(RLC_UCODE_CNTL, 0);
2796
2797 fw_data = (const __be32 *)rdev->rlc_fw->data;
45f9a39b
AD		 2798 if (rdev->family >= CHIP_CEDAR) {
2799 for (i = 0; i < EVERGREEN_RLC_UCODE_SIZE; i++) {
2800 WREG32(RLC_UCODE_ADDR, i);
2801 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2802 }
2803 } else if (rdev->family >= CHIP_RV770) {
d8f60cfc
AD		 2804 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) {
2805 WREG32(RLC_UCODE_ADDR, i);
2806 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2807 }
2808 } else {
2809 for (i = 0; i < RLC_UCODE_SIZE; i++) {
2810 WREG32(RLC_UCODE_ADDR, i);
2811 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2812 }
2813 }
2814 WREG32(RLC_UCODE_ADDR, 0);
2815
2816 r600_rlc_start(rdev);
2817
2818 return 0;
2819}
2820
2821static void r600_enable_interrupts(struct radeon_device *rdev)
2822{
2823 u32 ih_cntl = RREG32(IH_CNTL);
2824 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2825
2826 ih_cntl |= ENABLE_INTR;
2827 ih_rb_cntl |= IH_RB_ENABLE;
2828 WREG32(IH_CNTL, ih_cntl);
2829 WREG32(IH_RB_CNTL, ih_rb_cntl);
2830 rdev->ih.enabled = true;
2831}
2832
45f9a39b 2833void r600_disable_interrupts(struct radeon_device *rdev)
d8f60cfc
AD		 2834{
2835 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2836 u32 ih_cntl = RREG32(IH_CNTL);
2837
2838 ih_rb_cntl &= ~IH_RB_ENABLE;
2839 ih_cntl &= ~ENABLE_INTR;
2840 WREG32(IH_RB_CNTL, ih_rb_cntl);
2841 WREG32(IH_CNTL, ih_cntl);
2842 /* set rptr, wptr to 0 */
2843 WREG32(IH_RB_RPTR, 0);
2844 WREG32(IH_RB_WPTR, 0);
2845 rdev->ih.enabled = false;
2846 rdev->ih.wptr = 0;
2847 rdev->ih.rptr = 0;
2848}
2849
e0df1ac5
AD		 2850static void r600_disable_interrupt_state(struct radeon_device *rdev)
2851{
2852 u32 tmp;
2853
2854 WREG32(CP_INT_CNTL, 0);
2855 WREG32(GRBM_INT_CNTL, 0);
2856 WREG32(DxMODE_INT_MASK, 0);
2857 if (ASIC_IS_DCE3(rdev)) {
2858 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0);
2859 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0);
2860 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2861 WREG32(DC_HPD1_INT_CONTROL, tmp);
2862 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2863 WREG32(DC_HPD2_INT_CONTROL, tmp);
2864 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2865 WREG32(DC_HPD3_INT_CONTROL, tmp);
2866 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2867 WREG32(DC_HPD4_INT_CONTROL, tmp);
2868 if (ASIC_IS_DCE32(rdev)) {
2869 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
5898b1f3 2870 WREG32(DC_HPD5_INT_CONTROL, tmp);
e0df1ac5 2871 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
5898b1f3 2872 WREG32(DC_HPD6_INT_CONTROL, tmp);
e0df1ac5
AD		 2873 }
2874 } else {
2875 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2876 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2877 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
5898b1f3 2878 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
e0df1ac5 2879 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
5898b1f3 2880 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
e0df1ac5 2881 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
5898b1f3 2882 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
e0df1ac5
AD		 2883 }
2884}
2885
d8f60cfc
AD		 2886int r600_irq_init(struct radeon_device *rdev)
2887{
2888 int ret = 0;
2889 int rb_bufsz;
2890 u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
2891
2892 /* allocate ring */
0c45249f 2893 ret = r600_ih_ring_alloc(rdev);
d8f60cfc
AD		 2894 if (ret)
2895 return ret;
2896
2897 /* disable irqs */
2898 r600_disable_interrupts(rdev);
2899
2900 /* init rlc */
2901 ret = r600_rlc_init(rdev);
2902 if (ret) {
2903 r600_ih_ring_fini(rdev);
2904 return ret;
2905 }
2906
2907 /* setup interrupt control */
2908 /* set dummy read address to ring address */
2909 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
2910 interrupt_cntl = RREG32(INTERRUPT_CNTL);
2911 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
2912 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
2913 */
2914 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
2915 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
2916 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
2917 WREG32(INTERRUPT_CNTL, interrupt_cntl);
2918
2919 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
2920 rb_bufsz = drm_order(rdev->ih.ring_size / 4);
2921
2922 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
2923 IH_WPTR_OVERFLOW_CLEAR |
2924 (rb_bufsz << 1));
724c80e1
AD		 2925
2926 if (rdev->wb.enabled)
2927 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;
2928
2929 /* set the writeback address whether it's enabled or not */
2930 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);
2931 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);
d8f60cfc
AD		 2932
2933 WREG32(IH_RB_CNTL, ih_rb_cntl);
2934
2935 /* set rptr, wptr to 0 */
2936 WREG32(IH_RB_RPTR, 0);
2937 WREG32(IH_RB_WPTR, 0);
2938
2939 /* Default settings for IH_CNTL (disabled at first) */
2940 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10);
2941 /* RPTR_REARM only works if msi's are enabled */
2942 if (rdev->msi_enabled)
2943 ih_cntl |= RPTR_REARM;
2944
2945#ifdef __BIG_ENDIAN
2946 ih_cntl |= IH_MC_SWAP(IH_MC_SWAP_32BIT);
2947#endif
2948 WREG32(IH_CNTL, ih_cntl);
2949
2950 /* force the active interrupt state to all disabled */
45f9a39b
AD		 2951 if (rdev->family >= CHIP_CEDAR)
2952 evergreen_disable_interrupt_state(rdev);
2953 else
2954 r600_disable_interrupt_state(rdev);
d8f60cfc
AD		 2955
2956 /* enable irqs */
2957 r600_enable_interrupts(rdev);
2958
2959 return ret;
2960}
2961
0c45249f 2962void r600_irq_suspend(struct radeon_device *rdev)
d8f60cfc 2963{
45f9a39b 2964 r600_irq_disable(rdev);
d8f60cfc 2965 r600_rlc_stop(rdev);
0c45249f
JG		 2966}
2967
2968void r600_irq_fini(struct radeon_device *rdev)
2969{
2970 r600_irq_suspend(rdev);
d8f60cfc
AD		 2971 r600_ih_ring_fini(rdev);
2972}
2973
2974int r600_irq_set(struct radeon_device *rdev)
2975{
e0df1ac5
AD		 2976 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
2977 u32 mode_int = 0;
2978 u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
2031f77c 2979 u32 grbm_int_cntl = 0;
f2594933 2980 u32 hdmi1, hdmi2;
d8f60cfc 2981
003e69f9
JG		 2982 if (!rdev->irq.installed) {
2983 WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
2984 return -EINVAL;
2985 }
d8f60cfc 2986 /* don't enable anything if the ih is disabled */
79c2bbc5
JG		 2987 if (!rdev->ih.enabled) {
2988 r600_disable_interrupts(rdev);
2989 /* force the active interrupt state to all disabled */
2990 r600_disable_interrupt_state(rdev);
d8f60cfc 2991 return 0;
79c2bbc5 2992 }
d8f60cfc 2993
f2594933 2994 hdmi1 = RREG32(R600_HDMI_BLOCK1 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
e0df1ac5 2995 if (ASIC_IS_DCE3(rdev)) {
f2594933 2996 hdmi2 = RREG32(R600_HDMI_BLOCK3 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
e0df1ac5
AD		 2997 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2998 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2999 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3000 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
3001 if (ASIC_IS_DCE32(rdev)) {
3002 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
3003 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
3004 }
3005 } else {
f2594933 3006 hdmi2 = RREG32(R600_HDMI_BLOCK2 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
e0df1ac5
AD		 3007 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3008 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3009 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3010 }
3011
d8f60cfc
AD		 3012 if (rdev->irq.sw_int) {
3013 DRM_DEBUG("r600_irq_set: sw int\n");
3014 cp_int_cntl |= RB_INT_ENABLE;
3015 }
3016 if (rdev->irq.crtc_vblank_int[0]) {
3017 DRM_DEBUG("r600_irq_set: vblank 0\n");
3018 mode_int |= D1MODE_VBLANK_INT_MASK;
3019 }
3020 if (rdev->irq.crtc_vblank_int[1]) {
3021 DRM_DEBUG("r600_irq_set: vblank 1\n");
3022 mode_int |= D2MODE_VBLANK_INT_MASK;
3023 }
e0df1ac5
AD		 3024 if (rdev->irq.hpd[0]) {
3025 DRM_DEBUG("r600_irq_set: hpd 1\n");
3026 hpd1 |= DC_HPDx_INT_EN;
3027 }
3028 if (rdev->irq.hpd[1]) {
3029 DRM_DEBUG("r600_irq_set: hpd 2\n");
3030 hpd2 |= DC_HPDx_INT_EN;
3031 }
3032 if (rdev->irq.hpd[2]) {
3033 DRM_DEBUG("r600_irq_set: hpd 3\n");
3034 hpd3 |= DC_HPDx_INT_EN;
3035 }
3036 if (rdev->irq.hpd[3]) {
3037 DRM_DEBUG("r600_irq_set: hpd 4\n");
3038 hpd4 |= DC_HPDx_INT_EN;
3039 }
3040 if (rdev->irq.hpd[4]) {
3041 DRM_DEBUG("r600_irq_set: hpd 5\n");
3042 hpd5 |= DC_HPDx_INT_EN;
3043 }
3044 if (rdev->irq.hpd[5]) {
3045 DRM_DEBUG("r600_irq_set: hpd 6\n");
3046 hpd6 |= DC_HPDx_INT_EN;
3047 }
f2594933
CK		 3048 if (rdev->irq.hdmi[0]) {
3049 DRM_DEBUG("r600_irq_set: hdmi 1\n");
3050 hdmi1 |= R600_HDMI_INT_EN;
3051 }
3052 if (rdev->irq.hdmi[1]) {
3053 DRM_DEBUG("r600_irq_set: hdmi 2\n");
3054 hdmi2 |= R600_HDMI_INT_EN;
3055 }
2031f77c
AD		 3056 if (rdev->irq.gui_idle) {
3057 DRM_DEBUG("gui idle\n");
3058 grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
3059 }
d8f60cfc
AD		 3060
3061 WREG32(CP_INT_CNTL, cp_int_cntl);
3062 WREG32(DxMODE_INT_MASK, mode_int);
2031f77c 3063 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
f2594933 3064 WREG32(R600_HDMI_BLOCK1 + R600_HDMI_CNTL, hdmi1);
e0df1ac5 3065 if (ASIC_IS_DCE3(rdev)) {
f2594933 3066 WREG32(R600_HDMI_BLOCK3 + R600_HDMI_CNTL, hdmi2);
e0df1ac5
AD		 3067 WREG32(DC_HPD1_INT_CONTROL, hpd1);
3068 WREG32(DC_HPD2_INT_CONTROL, hpd2);
3069 WREG32(DC_HPD3_INT_CONTROL, hpd3);
3070 WREG32(DC_HPD4_INT_CONTROL, hpd4);
3071 if (ASIC_IS_DCE32(rdev)) {
3072 WREG32(DC_HPD5_INT_CONTROL, hpd5);
3073 WREG32(DC_HPD6_INT_CONTROL, hpd6);
3074 }
3075 } else {
f2594933 3076 WREG32(R600_HDMI_BLOCK2 + R600_HDMI_CNTL, hdmi2);
e0df1ac5
AD		 3077 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
3078 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
3079 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3);
3080 }
d8f60cfc
AD		 3081
3082 return 0;
3083}
3084
e0df1ac5
AD		 3085static inline void r600_irq_ack(struct radeon_device *rdev,
3086 u32 *disp_int,
3087 u32 *disp_int_cont,
3088 u32 *disp_int_cont2)
d8f60cfc 3089{
e0df1ac5
AD		 3090 u32 tmp;
3091
3092 if (ASIC_IS_DCE3(rdev)) {
3093 *disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
3094 *disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);
3095 *disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);
3096 } else {
3097 *disp_int = RREG32(DISP_INTERRUPT_STATUS);
3098 *disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
3099 *disp_int_cont2 = 0;
3100 }
d8f60cfc 3101
e0df1ac5 3102 if (*disp_int & LB_D1_VBLANK_INTERRUPT)
d8f60cfc 3103 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
e0df1ac5 3104 if (*disp_int & LB_D1_VLINE_INTERRUPT)
d8f60cfc 3105 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
e0df1ac5 3106 if (*disp_int & LB_D2_VBLANK_INTERRUPT)
d8f60cfc 3107 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
e0df1ac5 3108 if (*disp_int & LB_D2_VLINE_INTERRUPT)
d8f60cfc 3109 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
e0df1ac5
AD		 3110 if (*disp_int & DC_HPD1_INTERRUPT) {
3111 if (ASIC_IS_DCE3(rdev)) {
3112 tmp = RREG32(DC_HPD1_INT_CONTROL);
3113 tmp |= DC_HPDx_INT_ACK;
3114 WREG32(DC_HPD1_INT_CONTROL, tmp);
3115 } else {
3116 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
3117 tmp |= DC_HPDx_INT_ACK;
3118 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
3119 }
3120 }
3121 if (*disp_int & DC_HPD2_INTERRUPT) {
3122 if (ASIC_IS_DCE3(rdev)) {
3123 tmp = RREG32(DC_HPD2_INT_CONTROL);
3124 tmp |= DC_HPDx_INT_ACK;
3125 WREG32(DC_HPD2_INT_CONTROL, tmp);
3126 } else {
3127 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
3128 tmp |= DC_HPDx_INT_ACK;
3129 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
3130 }
3131 }
3132 if (*disp_int_cont & DC_HPD3_INTERRUPT) {
3133 if (ASIC_IS_DCE3(rdev)) {
3134 tmp = RREG32(DC_HPD3_INT_CONTROL);
3135 tmp |= DC_HPDx_INT_ACK;
3136 WREG32(DC_HPD3_INT_CONTROL, tmp);
3137 } else {
3138 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
3139 tmp |= DC_HPDx_INT_ACK;
3140 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
3141 }
3142 }
3143 if (*disp_int_cont & DC_HPD4_INTERRUPT) {
3144 tmp = RREG32(DC_HPD4_INT_CONTROL);
3145 tmp |= DC_HPDx_INT_ACK;
3146 WREG32(DC_HPD4_INT_CONTROL, tmp);
3147 }
3148 if (ASIC_IS_DCE32(rdev)) {
3149 if (*disp_int_cont2 & DC_HPD5_INTERRUPT) {
3150 tmp = RREG32(DC_HPD5_INT_CONTROL);
3151 tmp |= DC_HPDx_INT_ACK;
3152 WREG32(DC_HPD5_INT_CONTROL, tmp);
3153 }
3154 if (*disp_int_cont2 & DC_HPD6_INTERRUPT) {
3155 tmp = RREG32(DC_HPD5_INT_CONTROL);
3156 tmp |= DC_HPDx_INT_ACK;
3157 WREG32(DC_HPD6_INT_CONTROL, tmp);
3158 }
3159 }
f2594933
CK		 3160 if (RREG32(R600_HDMI_BLOCK1 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
3161 WREG32_P(R600_HDMI_BLOCK1 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
3162 }
3163 if (ASIC_IS_DCE3(rdev)) {
3164 if (RREG32(R600_HDMI_BLOCK3 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
3165 WREG32_P(R600_HDMI_BLOCK3 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
3166 }
3167 } else {
3168 if (RREG32(R600_HDMI_BLOCK2 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
3169 WREG32_P(R600_HDMI_BLOCK2 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
3170 }
3171 }
d8f60cfc
AD		 3172}
3173
3174void r600_irq_disable(struct radeon_device *rdev)
3175{
e0df1ac5 3176 u32 disp_int, disp_int_cont, disp_int_cont2;
d8f60cfc
AD		 3177
3178 r600_disable_interrupts(rdev);
3179 /* Wait and acknowledge irq */
3180 mdelay(1);
e0df1ac5
AD		 3181 r600_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2);
3182 r600_disable_interrupt_state(rdev);
d8f60cfc
AD		 3183}
3184
3185static inline u32 r600_get_ih_wptr(struct radeon_device *rdev)
3186{
3187 u32 wptr, tmp;
3ce0a23d 3188
724c80e1
AD		 3189 if (rdev->wb.enabled)
3190 wptr = rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4];
3191 else
3192 wptr = RREG32(IH_RB_WPTR);
3ce0a23d 3193
d8f60cfc 3194 if (wptr & RB_OVERFLOW) {
7924e5eb
JG		 3195 /* When a ring buffer overflow happen start parsing interrupt
3196 * from the last not overwritten vector (wptr + 16). Hopefully
3197 * this should allow us to catchup.
3198 */
3199 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
3200 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
3201 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
d8f60cfc
AD		 3202 tmp = RREG32(IH_RB_CNTL);
3203 tmp |= IH_WPTR_OVERFLOW_CLEAR;
3204 WREG32(IH_RB_CNTL, tmp);
3205 }
0c45249f 3206 return (wptr & rdev->ih.ptr_mask);
d8f60cfc 3207}
3ce0a23d 3208
d8f60cfc
AD		 3209/* r600 IV Ring
3210 * Each IV ring entry is 128 bits:
3211 * [7:0] - interrupt source id
3212 * [31:8] - reserved
3213 * [59:32] - interrupt source data
3214 * [127:60] - reserved
3215 *
3216 * The basic interrupt vector entries
3217 * are decoded as follows:
3218 * src_id src_data description
3219 * 1 0 D1 Vblank
3220 * 1 1 D1 Vline
3221 * 5 0 D2 Vblank
3222 * 5 1 D2 Vline
3223 * 19 0 FP Hot plug detection A
3224 * 19 1 FP Hot plug detection B
3225 * 19 2 DAC A auto-detection
3226 * 19 3 DAC B auto-detection
f2594933
CK		 3227 * 21 4 HDMI block A
3228 * 21 5 HDMI block B
d8f60cfc
AD		 3229 * 176 - CP_INT RB
3230 * 177 - CP_INT IB1
3231 * 178 - CP_INT IB2
3232 * 181 - EOP Interrupt
3233 * 233 - GUI Idle
3234 *
3235 * Note, these are based on r600 and may need to be
3236 * adjusted or added to on newer asics
3237 */
3238
3239int r600_irq_process(struct radeon_device *rdev)
3240{
3241 u32 wptr = r600_get_ih_wptr(rdev);
3242 u32 rptr = rdev->ih.rptr;
3243 u32 src_id, src_data;
e0df1ac5 3244 u32 ring_index, disp_int, disp_int_cont, disp_int_cont2;
d8f60cfc 3245 unsigned long flags;
d4877cf2 3246 bool queue_hotplug = false;
d8f60cfc
AD		 3247
3248 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
79c2bbc5
JG		 3249 if (!rdev->ih.enabled)
3250 return IRQ_NONE;
d8f60cfc
AD		 3251
3252 spin_lock_irqsave(&rdev->ih.lock, flags);
3253
3254 if (rptr == wptr) {
3255 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3256 return IRQ_NONE;
3257 }
3258 if (rdev->shutdown) {
3259 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3260 return IRQ_NONE;
3261 }
3262
3263restart_ih:
3264 /* display interrupts */
e0df1ac5 3265 r600_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2);
d8f60cfc
AD		 3266
3267 rdev->ih.wptr = wptr;
3268 while (rptr != wptr) {
3269 /* wptr/rptr are in bytes! */
3270 ring_index = rptr / 4;
3271 src_id = rdev->ih.ring[ring_index] & 0xff;
3272 src_data = rdev->ih.ring[ring_index + 1] & 0xfffffff;
3273
3274 switch (src_id) {
3275 case 1: /* D1 vblank/vline */
3276 switch (src_data) {
3277 case 0: /* D1 vblank */
3278 if (disp_int & LB_D1_VBLANK_INTERRUPT) {
3279 drm_handle_vblank(rdev->ddev, 0);
839461d3 3280 rdev->pm.vblank_sync = true;
73a6d3fc 3281 wake_up(&rdev->irq.vblank_queue);
d8f60cfc
AD		 3282 disp_int &= ~LB_D1_VBLANK_INTERRUPT;
3283 DRM_DEBUG("IH: D1 vblank\n");
3284 }
3285 break;
3286 case 1: /* D1 vline */
3287 if (disp_int & LB_D1_VLINE_INTERRUPT) {
3288 disp_int &= ~LB_D1_VLINE_INTERRUPT;
3289 DRM_DEBUG("IH: D1 vline\n");
3290 }
3291 break;
3292 default:
b042589c 3293 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
d8f60cfc
AD		 3294 break;
3295 }
3296 break;
3297 case 5: /* D2 vblank/vline */
3298 switch (src_data) {
3299 case 0: /* D2 vblank */
3300 if (disp_int & LB_D2_VBLANK_INTERRUPT) {
3301 drm_handle_vblank(rdev->ddev, 1);
839461d3 3302 rdev->pm.vblank_sync = true;
73a6d3fc 3303 wake_up(&rdev->irq.vblank_queue);
d8f60cfc
AD		 3304 disp_int &= ~LB_D2_VBLANK_INTERRUPT;
3305 DRM_DEBUG("IH: D2 vblank\n");
3306 }
3307 break;
3308 case 1: /* D1 vline */
3309 if (disp_int & LB_D2_VLINE_INTERRUPT) {
3310 disp_int &= ~LB_D2_VLINE_INTERRUPT;
3311 DRM_DEBUG("IH: D2 vline\n");
3312 }
3313 break;
3314 default:
b042589c 3315 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
d8f60cfc
AD		 3316 break;
3317 }
3318 break;
e0df1ac5
AD		 3319 case 19: /* HPD/DAC hotplug */
3320 switch (src_data) {
3321 case 0:
3322 if (disp_int & DC_HPD1_INTERRUPT) {
3323 disp_int &= ~DC_HPD1_INTERRUPT;
d4877cf2
AD		 3324 queue_hotplug = true;
3325 DRM_DEBUG("IH: HPD1\n");
e0df1ac5
AD		 3326 }
3327 break;
3328 case 1:
3329 if (disp_int & DC_HPD2_INTERRUPT) {
3330 disp_int &= ~DC_HPD2_INTERRUPT;
d4877cf2
AD		 3331 queue_hotplug = true;
3332 DRM_DEBUG("IH: HPD2\n");
e0df1ac5
AD		 3333 }
3334 break;
3335 case 4:
3336 if (disp_int_cont & DC_HPD3_INTERRUPT) {
3337 disp_int_cont &= ~DC_HPD3_INTERRUPT;
d4877cf2
AD		 3338 queue_hotplug = true;
3339 DRM_DEBUG("IH: HPD3\n");
e0df1ac5
AD		 3340 }
3341 break;
3342 case 5:
3343 if (disp_int_cont & DC_HPD4_INTERRUPT) {
3344 disp_int_cont &= ~DC_HPD4_INTERRUPT;
d4877cf2
AD		 3345 queue_hotplug = true;
3346 DRM_DEBUG("IH: HPD4\n");
e0df1ac5
AD		 3347 }
3348 break;
3349 case 10:
3350 if (disp_int_cont2 & DC_HPD5_INTERRUPT) {
5898b1f3 3351 disp_int_cont2 &= ~DC_HPD5_INTERRUPT;
d4877cf2
AD		 3352 queue_hotplug = true;
3353 DRM_DEBUG("IH: HPD5\n");
e0df1ac5
AD		 3354 }
3355 break;
3356 case 12:
3357 if (disp_int_cont2 & DC_HPD6_INTERRUPT) {
5898b1f3 3358 disp_int_cont2 &= ~DC_HPD6_INTERRUPT;
d4877cf2
AD		 3359 queue_hotplug = true;
3360 DRM_DEBUG("IH: HPD6\n");
e0df1ac5
AD		 3361 }
3362 break;
3363 default:
b042589c 3364 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
e0df1ac5
AD		 3365 break;
3366 }
3367 break;
f2594933
CK		 3368 case 21: /* HDMI */
3369 DRM_DEBUG("IH: HDMI: 0x%x\n", src_data);
3370 r600_audio_schedule_polling(rdev);
3371 break;
d8f60cfc
AD		 3372 case 176: /* CP_INT in ring buffer */
3373 case 177: /* CP_INT in IB1 */
3374 case 178: /* CP_INT in IB2 */
3375 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
3376 radeon_fence_process(rdev);
3377 break;
3378 case 181: /* CP EOP event */
3379 DRM_DEBUG("IH: CP EOP\n");
3380 break;
2031f77c
AD		 3381 case 233: /* GUI IDLE */
3382 DRM_DEBUG("IH: CP EOP\n");
3383 rdev->pm.gui_idle = true;
3384 wake_up(&rdev->irq.idle_queue);
3385 break;
d8f60cfc 3386 default:
b042589c 3387 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
d8f60cfc
AD		 3388 break;
3389 }
3390
3391 /* wptr/rptr are in bytes! */
0c45249f
JG		 3392 rptr += 16;
3393 rptr &= rdev->ih.ptr_mask;
d8f60cfc
AD		 3394 }
3395 /* make sure wptr hasn't changed while processing */
3396 wptr = r600_get_ih_wptr(rdev);
3397 if (wptr != rdev->ih.wptr)
3398 goto restart_ih;
d4877cf2
AD		 3399 if (queue_hotplug)
3400 queue_work(rdev->wq, &rdev->hotplug_work);
d8f60cfc
AD		 3401 rdev->ih.rptr = rptr;
3402 WREG32(IH_RB_RPTR, rdev->ih.rptr);
3403 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3404 return IRQ_HANDLED;
3405}
3ce0a23d
JG		 3406
3407/*
3408 * Debugfs info
3409 */
3410#if defined(CONFIG_DEBUG_FS)
3411
3412static int r600_debugfs_cp_ring_info(struct seq_file *m, void *data)
771fe6b9 3413{
3ce0a23d
JG		 3414 struct drm_info_node *node = (struct drm_info_node *) m->private;
3415 struct drm_device *dev = node->minor->dev;
3416 struct radeon_device *rdev = dev->dev_private;
3ce0a23d
JG		 3417 unsigned count, i, j;
3418
3419 radeon_ring_free_size(rdev);
d6840766 3420 count = (rdev->cp.ring_size / 4) - rdev->cp.ring_free_dw;
3ce0a23d 3421 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(CP_STAT));
d6840766
RM		 3422 seq_printf(m, "CP_RB_WPTR 0x%08x\n", RREG32(CP_RB_WPTR));
3423 seq_printf(m, "CP_RB_RPTR 0x%08x\n", RREG32(CP_RB_RPTR));
3424 seq_printf(m, "driver's copy of the CP_RB_WPTR 0x%08x\n", rdev->cp.wptr);
3425 seq_printf(m, "driver's copy of the CP_RB_RPTR 0x%08x\n", rdev->cp.rptr);
3ce0a23d
JG		 3426 seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
3427 seq_printf(m, "%u dwords in ring\n", count);
d6840766 3428 i = rdev->cp.rptr;
3ce0a23d 3429 for (j = 0; j <= count; j++) {
3ce0a23d 3430 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
d6840766 3431 i = (i + 1) & rdev->cp.ptr_mask;
3ce0a23d
JG		 3432 }
3433 return 0;
3434}
3435
3436static int r600_debugfs_mc_info(struct seq_file *m, void *data)
3437{
3438 struct drm_info_node *node = (struct drm_info_node *) m->private;
3439 struct drm_device *dev = node->minor->dev;
3440 struct radeon_device *rdev = dev->dev_private;
3441
3442 DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
3443 DREG32_SYS(m, rdev, VM_L2_STATUS);
3444 return 0;
3445}
3446
3447static struct drm_info_list r600_mc_info_list[] = {
3448 {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
3449 {"r600_ring_info", r600_debugfs_cp_ring_info, 0, NULL},
3450};
3451#endif
3452
3453int r600_debugfs_mc_info_init(struct radeon_device *rdev)
3454{
3455#if defined(CONFIG_DEBUG_FS)
3456 return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
3457#else
3458 return 0;
3459#endif
771fe6b9 3460}
062b389c
JG		 3461
3462/**
3463 * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl
3464 * rdev: radeon device structure
3465 * bo: buffer object struct which userspace is waiting for idle
3466 *
3467 * Some R6XX/R7XX doesn't seems to take into account HDP flush performed
3468 * through ring buffer, this leads to corruption in rendering, see
3469 * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we
3470 * directly perform HDP flush by writing register through MMIO.
3471 */
3472void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
3473{
812d0469
AD		 3474 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read
3475 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL
3476 */
e488459a
AD		 3477 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
3478 rdev->vram_scratch.ptr) {
87cbf8f2 3479 void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
812d0469
AD		 3480 u32 tmp;
3481
3482 WREG32(HDP_DEBUG1, 0);
3483 tmp = readl((void __iomem *)ptr);
3484 } else
3485 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
062b389c 3486}
Clone of davem's net-next-2.6 tree